ADS124S08 Example C Code
1.0.0
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This header file contains all register map definitions for the ADS124S08 device family. More...
Go to the source code of this file.
Constants for ADS124S08 | |
#define | NUM_REGISTERS ((uint8_t) 18) |
#define | ADS124S08_FCLK 4096000 |
#define | ADS124S08_BITRES 24 |
#define | DATA_LENGTH 3 |
#define | COMMAND_LENGTH 2 |
#define | STATUS_LENGTH 1 |
#define | CRC_LENGTH 1 |
#define | RDATA_COMMAND_LENGTH 1 |
#define | DATA_MODE_NORMAL 0x00 |
#define | DATA_MODE_STATUS 0x01 |
#define | DATA_MODE_CRC 0x02 |
#define | INT_VREF 2.5 |
#define | DELAY_4TCLK (uint32_t) (1) |
#define | DELAY_4096TCLK (uint32_t) (4096.0 * 1000000 / ADS124S08_FCLK ) |
#define | DELAY_2p2MS (uint32_t) (0.0022 * 1000000 ) |
bool | converting |
Command byte definition | |
| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 || COMMAND | | |
#define | OPCODE_NOP ((uint8_t) 0x00) |
#define | OPCODE_WAKEUP ((uint8_t) 0x02) |
#define | OPCODE_POWERDOWN ((uint8_t) 0x04) |
#define | OPCODE_RESET ((uint8_t) 0x06) |
#define | OPCODE_START ((uint8_t) 0x08) |
#define | OPCODE_STOP ((uint8_t) 0x0A) |
#define | OPCODE_SYOCAL ((uint8_t) 0x16) |
#define | OPCODE_SYGCAL ((uint8_t) 0x17) |
#define | OPCODE_SFOCAL ((uint8_t) 0x19) |
#define | OPCODE_RDATA ((uint8_t) 0x12) |
#define | OPCODE_RREG ((uint8_t) 0x20) |
#define | OPCODE_WREG ((uint8_t) 0x40) |
#define | OPCODE_RWREG_MASK ((uint8_t) 0x1F) |
enum | readMode { DIRECT, COMMAND } |
Register definitions | |
#define | REG_ADDR_ID ((uint8_t) 0x00) |
#define | ID_DEFAULT ((uint8_t) 0x00) |
#define | ADS_124S08 0x00 |
#define | ADS_124S06 0x01 |
#define | ADS_114S08 0x04 |
#define | ADS_114S06 0x05 |
#define | REG_ADDR_STATUS ((uint8_t) 0x01) |
#define | STATUS_DEFAULT ((uint8_t) 0x80) |
#define | ADS_FL_POR_MASK 0x80 |
#define | ADS_nRDY_MASK 0x40 |
#define | ADS_FL_P_RAILP_MASK 0x20 |
#define | ADS_FL_P_RAILN_MASK 0x10 |
#define | ADS_FL_N_RAILP_MASK 0x08 |
#define | ADS_FL_N_RAILN_MASK 0x04 |
#define | ADS_FL_REF_L1_MASK 0x02 |
#define | ADS_FL_REF_L0_MASK 0x10 |
#define | REG_ADDR_INPMUX ((uint8_t) 0x02) |
#define | INPMUX_DEFAULT ((uint8_t) 0x01) |
#define | ADS_P_AIN0 0x00 |
#define | ADS_P_AIN1 0x10 |
#define | ADS_P_AIN2 0x20 |
#define | ADS_P_AIN3 0x30 |
#define | ADS_P_AIN4 0x40 |
#define | ADS_P_AIN5 0x50 |
#define | ADS_P_AIN6 0x60 |
#define | ADS_P_AIN7 0x70 |
#define | ADS_P_AIN8 0x80 |
#define | ADS_P_AIN9 0x90 |
#define | ADS_P_AIN10 0xA0 |
#define | ADS_P_AIN11 0xB0 |
#define | ADS_P_AINCOM 0xC0 |
#define | ADS_N_AIN0 0x00 |
#define | ADS_N_AIN1 0x01 |
#define | ADS_N_AIN2 0x02 |
#define | ADS_N_AIN3 0x03 |
#define | ADS_N_AIN4 0x04 |
#define | ADS_N_AIN5 0x05 |
#define | ADS_N_AIN6 0x06 |
#define | ADS_N_AIN7 0x07 |
#define | ADS_N_AIN8 0x08 |
#define | ADS_N_AIN9 0x09 |
#define | ADS_N_AIN10 0x0A |
#define | ADS_N_AIN11 0x0B |
#define | ADS_N_AINCOM 0x0C |
#define | REG_ADDR_PGA ((uint8_t) 0x03) |
#define | PGA_DEFAULT ((uint8_t) 0x00) |
#define | ADS_DELAY_14 0x00 |
#define | ADS_DELAY_25 0x20 |
#define | ADS_DELAY_64 0x40 |
#define | ADS_DELAY_256 0x60 |
#define | ADS_DELAY_1024 0x80 |
#define | ADS_DELAY_2048 0xA0 |
#define | ADS_DELAY_4096 0xC0 |
#define | ADS_DELAY_1 0xE0 |
#define | ADS_PGA_BYPASS 0x00 |
#define | ADS_PGA_ENABLED 0x08 |
#define | ADS_GAIN_1 0x00 |
#define | ADS_GAIN_2 0x01 |
#define | ADS_GAIN_4 0x02 |
#define | ADS_GAIN_8 0x03 |
#define | ADS_GAIN_16 0x04 |
#define | ADS_GAIN_32 0x05 |
#define | ADS_GAIN_64 0x06 |
#define | ADS_GAIN_128 0x07 |
#define | ADS_GAIN_MASK 0x07 |
#define | REG_ADDR_DATARATE ((uint8_t) 0x04) |
#define | DATARATE_DEFAULT ((uint8_t) 0x14) |
#define | ADS_GLOBALCHOP 0x80 |
#define | ADS_CLKSEL_EXT 0x40 |
#define | ADS_CONVMODE_SS 0x20 |
#define | ADS_CONVMODE_CONT 0x00 |
#define | ADS_FILTERTYPE_LL 0x10 |
#define | ADS_DR_2_5 0x00 |
#define | ADS_DR_5 0x01 |
#define | ADS_DR_10 0x02 |
#define | ADS_DR_16 0x03 |
#define | ADS_DR_20 0x04 |
#define | ADS_DR_50 0x05 |
#define | ADS_DR_60 0x06 |
#define | ADS_DR_100 0x07 |
#define | ADS_DR_200 0x08 |
#define | ADS_DR_400 0x09 |
#define | ADS_DR_800 0x0A |
#define | ADS_DR_1000 0x0B |
#define | ADS_DR_2000 0x0C |
#define | ADS_DR_4000 0x0D |
#define | REG_ADDR_REF ((uint8_t) 0x05) |
#define | REF_DEFAULT ((uint8_t) 0x10) |
#define | ADS_FLAG_REF_DISABLE 0x00 |
#define | ADS_FLAG_REF_EN_L0 0x40 |
#define | ADS_FLAG_REF_EN_BOTH 0x80 |
#define | ADS_FLAG_REF_EN_10M 0xC0 |
#define | ADS_REFP_BYP_DISABLE 0x20 |
#define | ADS_REFP_BYP_ENABLE 0x00 |
#define | ADS_REFN_BYP_DISABLE 0x10 |
#define | ADS_REFN_BYP_ENABLE 0x00 |
#define | ADS_REFSEL_P0 0x00 |
#define | ADS_REFSEL_P1 0x04 |
#define | ADS_REFSEL_INT 0x08 |
#define | ADS_REFINT_OFF 0x00 |
#define | ADS_REFINT_ON_PDWN 0x01 |
#define | ADS_REFINT_ON_ALWAYS 0x02 |
#define | REG_ADDR_IDACMAG ((uint8_t) 0x06) |
#define | IDACMAG_DEFAULT ((uint8_t) 0x00) |
#define | ADS_FLAG_RAIL_ENABLE 0x80 |
#define | ADS_FLAG_RAIL_DISABLE 0x00 |
#define | ADS_PSW_OPEN 0x00 |
#define | ADS_PSW_CLOSED 0x40 |
#define | ADS_IDACMAG_OFF 0x00 |
#define | ADS_IDACMAG_10 0x01 |
#define | ADS_IDACMAG_50 0x02 |
#define | ADS_IDACMAG_100 0x03 |
#define | ADS_IDACMAG_250 0x04 |
#define | ADS_IDACMAG_500 0x05 |
#define | ADS_IDACMAG_750 0x06 |
#define | ADS_IDACMAG_1000 0x07 |
#define | ADS_IDACMAG_1500 0x08 |
#define | ADS_IDACMAG_2000 0x09 |
#define | REG_ADDR_IDACMUX ((uint8_t) 0x07) |
#define | IDACMUX_DEFAULT ((uint8_t) 0xFF) |
#define | ADS_IDAC2_A0 0x00 |
#define | ADS_IDAC2_A1 0x10 |
#define | ADS_IDAC2_A2 0x20 |
#define | ADS_IDAC2_A3 0x30 |
#define | ADS_IDAC2_A4 0x40 |
#define | ADS_IDAC2_A5 0x50 |
#define | ADS_IDAC2_A6 0x60 |
#define | ADS_IDAC2_A7 0x70 |
#define | ADS_IDAC2_A8 0x80 |
#define | ADS_IDAC2_A9 0x90 |
#define | ADS_IDAC2_A10 0xA0 |
#define | ADS_IDAC2_A11 0xB0 |
#define | ADS_IDAC2_AINCOM 0xC0 |
#define | ADS_IDAC2_OFF 0xF0 |
#define | ADS_IDAC1_A0 0x00 |
#define | ADS_IDAC1_A1 0x01 |
#define | ADS_IDAC1_A2 0x02 |
#define | ADS_IDAC1_A3 0x03 |
#define | ADS_IDAC1_A4 0x04 |
#define | ADS_IDAC1_A5 0x05 |
#define | ADS_IDAC1_A6 0x06 |
#define | ADS_IDAC1_A7 0x07 |
#define | ADS_IDAC1_A8 0x08 |
#define | ADS_IDAC1_A9 0x09 |
#define | ADS_IDAC1_A10 0x0A |
#define | ADS_IDAC1_A11 0x0B |
#define | ADS_IDAC1_AINCOM 0x0C |
#define | ADS_IDAC1_OFF 0x0F |
#define | REG_ADDR_VBIAS ((uint8_t) 0x08) |
#define | VBIAS_DEFAULT ((uint8_t) 0x00) |
#define | ADS_VBIAS_LVL_DIV2 0x00 |
#define | ADS_VBIAS_LVL_DIV12 0x80 |
#define | ADS_VB_AINC 0x40 |
#define | ADS_VB_AIN5 0x20 |
#define | ADS_VB_AIN4 0x10 |
#define | ADS_VB_AIN3 0x08 |
#define | ADS_VB_AIN2 0x04 |
#define | ADS_VB_AIN1 0x02 |
#define | ADS_VB_AIN0 0x01 |
#define | REG_ADDR_SYS ((uint8_t) 0x09) |
#define | SYS_DEFAULT ((uint8_t) 0x10) |
#define | ADS_SYS_MON_OFF 0x00 |
#define | ADS_SYS_MON_SHORT 0x20 |
#define | ADS_SYS_MON_TEMP 0x40 |
#define | ADS_SYS_MON_ADIV4 0x60 |
#define | ADS_SYS_MON_DDIV4 0x80 |
#define | ADS_SYS_MON_BCS_2 0xA0 |
#define | ADS_SYS_MON_BCS_1 0xC0 |
#define | ADS_SYS_MON_BCS_10 0xE0 |
#define | ADS_CALSAMPLE_1 0x00 |
#define | ADS_CALSAMPLE_4 0x08 |
#define | ADS_CALSAMPLE_8 0x10 |
#define | ADS_CALSAMPLE_16 0x18 |
#define | ADS_TIMEOUT_DISABLE 0x00 |
#define | ADS_TIMEOUT_ENABLE 0x04 |
#define | ADS_CRC_DISABLE 0x00 |
#define | ADS_CRC_ENABLE 0x02 |
#define | ADS_CRC_MASK 0x02 |
#define | ADS_SENDSTATUS_DISABLE 0x00 |
#define | ADS_SENDSTATUS_ENABLE 0x01 |
#define | ADS_SENDSTATUS_MASK 0x01 |
#define | REG_ADDR_OFCAL0 ((uint8_t) 0x0A) |
#define | OFCAL0_DEFAULT ((uint8_t) 0x00) |
#define | REG_ADDR_OFCAL1 ((uint8_t) 0x0B) |
#define | OFCAL1_DEFAULT ((uint8_t) 0x00) |
#define | REG_ADDR_OFCAL2 ((uint8_t) 0x0C) |
#define | OFCAL2_DEFAULT ((uint8_t) 0x00) |
#define | REG_ADDR_FSCAL0 ((uint8_t) 0x0D) |
#define | FSCAL0_DEFAULT ((uint8_t) 0x00) |
#define | REG_ADDR_FSCAL1 ((uint8_t) 0x0E) |
#define | FSCAL1_DEFAULT ((uint8_t) 0x00) |
#define | REG_ADDR_FSCAL2 ((uint8_t) 0x0F) |
#define | FSCAL2_DEFAULT ((uint8_t) 0x40) |
#define | REG_ADDR_GPIODAT ((uint8_t) 0x10) |
#define | GPIODAT_DEFAULT ((uint8_t) 0x00) |
#define | ADS_GPIO0_DIR_INPUT 0x10 |
#define | ADS_GPIO1_DIR_INPUT 0x20 |
#define | ADS_GPIO2_DIR_INPUT 0x40 |
#define | ADS_GPIO3_DIR_INPUT 0x80 |
#define | REG_ADDR_GPIOCON ((uint8_t) 0x11) |
#define | GPIOCON_DEFAULT ((uint8_t) 0x00) |
#define | ADS_GPIO0_CFG_GPIO 0x01 |
#define | ADS_GPIO1_CFG_GPIO 0x02 |
#define | ADS_GPIO2_CFG_GPIO 0x04 |
#define | ADS_GPIO3_CFG_GPIO 0x08 |
#define | IS_SENDSTAT_SET ((bool) (getRegisterValue(REG_ADDR_SYS) & ADS_SENDSTATUS_MASK)) |
#define | IS_CRC_SET ((bool) (getRegisterValue(REG_ADDR_SYS) & ADS_CRC_MASK)) |
bool | adcStartupRoutine (SPI_Handle spiHdl) |
adcStartupRoutine() Startup function to be called before communicating with the ADC More... | |
int32_t | readConvertedData (SPI_Handle spiHdl, uint8_t status[], readMode mode) |
readConvertedData() Sends the read command and retrieves STATUS (if enabled) and data NOTE: Call this function after /DRDY goes low and specify the the number of bytes to read and the starting position of data More... | |
uint8_t | readSingleRegister (SPI_Handle spiHdl, uint8_t address) |
readSingleRegister() Reads contents of a single register at the specified address More... | |
void | readMultipleRegisters (SPI_Handle spiHdl, uint8_t startAddress, uint8_t count) |
readMultipleRegisters() Reads a group of registers starting at the specified address NOTE: Use getRegisterValue() to retrieve the read values More... | |
void | sendCommand (SPI_Handle spiHdl, uint8_t op_code) |
sendCommand() Sends the specified SPI command to the ADC More... | |
void | startConversions (SPI_Handle spiHdl) |
startConversions() Wakes the device from power-down and starts continuous conversions by setting START pin high or sending START Command More... | |
void | stopConversions (SPI_Handle spiHdl) |
stopConversions() Stops continuous conversions by setting START pin low or sending STOP Command More... | |
void | writeSingleRegister (SPI_Handle spiHdl, uint8_t address, uint8_t data) |
writeSingleRegister() Write data to a single register at the specified address More... | |
void | writeMultipleRegisters (SPI_Handle spiHdl, uint8_t startAddress, uint8_t count, uint8_t regData[]) |
writeMultipleRegisters() Write data to a group of registers NOTES: Use getRegisterValue() to retrieve the written values. Registers should be re-read after a write operation to ensure proper configuration. More... | |
void | resetADC (SPI_Handle spiHdl) |
resetADC() Resets ADC by setting RESET pin low or sending RESET Command More... | |
uint8_t | getRegisterValue (uint8_t address) |
getRegisterValue() Getter function to access the registerMap array outside of this module More... | |
void | restoreRegisterDefaults (void) |
restoreRegisterDefaults() Updates the registerMap[] array to its default values NOTES: If the MCU keeps a copy of the ADC register settings in memory, then it is important to ensure that these values remain in sync with the actual hardware settings. In order to help facilitate this, this function should be called after powering up or resetting the device (either by hardware pin control or SPI software command). Reading back all of the registers after resetting the device will accomplish the same result. More... | |
This header file contains all register map definitions for the ADS124S08 device family.
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#define ADS124S08_BITRES 24 |
#define ADS124S08_FCLK 4096000 |
#define ADS_114S06 0x05 |
#define ADS_114S08 0x04 |
#define ADS_124S06 0x01 |
#define ADS_124S08 0x00 |
#define ADS_CALSAMPLE_1 0x00 |
#define ADS_CALSAMPLE_16 0x18 |
#define ADS_CALSAMPLE_4 0x08 |
#define ADS_CALSAMPLE_8 0x10 |
#define ADS_CLKSEL_EXT 0x40 |
#define ADS_CONVMODE_CONT 0x00 |
#define ADS_CONVMODE_SS 0x20 |
#define ADS_CRC_DISABLE 0x00 |
#define ADS_CRC_ENABLE 0x02 |
#define ADS_CRC_MASK 0x02 |
#define ADS_DELAY_1 0xE0 |
#define ADS_DELAY_1024 0x80 |
#define ADS_DELAY_14 0x00 |
#define ADS_DELAY_2048 0xA0 |
#define ADS_DELAY_25 0x20 |
#define ADS_DELAY_256 0x60 |
#define ADS_DELAY_4096 0xC0 |
#define ADS_DELAY_64 0x40 |
#define ADS_DR_10 0x02 |
#define ADS_DR_100 0x07 |
#define ADS_DR_1000 0x0B |
#define ADS_DR_16 0x03 |
#define ADS_DR_20 0x04 |
#define ADS_DR_200 0x08 |
#define ADS_DR_2000 0x0C |
#define ADS_DR_2_5 0x00 |
#define ADS_DR_400 0x09 |
#define ADS_DR_4000 0x0D |
#define ADS_DR_5 0x01 |
#define ADS_DR_50 0x05 |
#define ADS_DR_60 0x06 |
#define ADS_DR_800 0x0A |
#define ADS_FILTERTYPE_LL 0x10 |
#define ADS_FL_N_RAILN_MASK 0x04 |
#define ADS_FL_N_RAILP_MASK 0x08 |
#define ADS_FL_P_RAILN_MASK 0x10 |
#define ADS_FL_P_RAILP_MASK 0x20 |
#define ADS_FL_POR_MASK 0x80 |
#define ADS_FL_REF_L0_MASK 0x10 |
#define ADS_FL_REF_L1_MASK 0x02 |
#define ADS_FLAG_RAIL_DISABLE 0x00 |
#define ADS_FLAG_RAIL_ENABLE 0x80 |
#define ADS_FLAG_REF_DISABLE 0x00 |
#define ADS_FLAG_REF_EN_10M 0xC0 |
#define ADS_FLAG_REF_EN_BOTH 0x80 |
#define ADS_FLAG_REF_EN_L0 0x40 |
#define ADS_GAIN_1 0x00 |
#define ADS_GAIN_128 0x07 |
#define ADS_GAIN_16 0x04 |
#define ADS_GAIN_2 0x01 |
#define ADS_GAIN_32 0x05 |
#define ADS_GAIN_4 0x02 |
#define ADS_GAIN_64 0x06 |
#define ADS_GAIN_8 0x03 |
#define ADS_GAIN_MASK 0x07 |
#define ADS_GLOBALCHOP 0x80 |
#define ADS_GPIO0_CFG_GPIO 0x01 |
#define ADS_GPIO0_DIR_INPUT 0x10 |
#define ADS_GPIO1_CFG_GPIO 0x02 |
#define ADS_GPIO1_DIR_INPUT 0x20 |
#define ADS_GPIO2_CFG_GPIO 0x04 |
#define ADS_GPIO2_DIR_INPUT 0x40 |
#define ADS_GPIO3_CFG_GPIO 0x08 |
#define ADS_GPIO3_DIR_INPUT 0x80 |
#define ADS_IDAC1_A0 0x00 |
#define ADS_IDAC1_A1 0x01 |
#define ADS_IDAC1_A10 0x0A |
#define ADS_IDAC1_A11 0x0B |
#define ADS_IDAC1_A2 0x02 |
#define ADS_IDAC1_A3 0x03 |
#define ADS_IDAC1_A4 0x04 |
#define ADS_IDAC1_A5 0x05 |
#define ADS_IDAC1_A6 0x06 |
#define ADS_IDAC1_A7 0x07 |
#define ADS_IDAC1_A8 0x08 |
#define ADS_IDAC1_A9 0x09 |
#define ADS_IDAC1_AINCOM 0x0C |
#define ADS_IDAC1_OFF 0x0F |
#define ADS_IDAC2_A0 0x00 |
#define ADS_IDAC2_A1 0x10 |
#define ADS_IDAC2_A10 0xA0 |
#define ADS_IDAC2_A11 0xB0 |
#define ADS_IDAC2_A2 0x20 |
#define ADS_IDAC2_A3 0x30 |
#define ADS_IDAC2_A4 0x40 |
#define ADS_IDAC2_A5 0x50 |
#define ADS_IDAC2_A6 0x60 |
#define ADS_IDAC2_A7 0x70 |
#define ADS_IDAC2_A8 0x80 |
#define ADS_IDAC2_A9 0x90 |
#define ADS_IDAC2_AINCOM 0xC0 |
#define ADS_IDAC2_OFF 0xF0 |
#define ADS_IDACMAG_10 0x01 |
#define ADS_IDACMAG_100 0x03 |
#define ADS_IDACMAG_1000 0x07 |
#define ADS_IDACMAG_1500 0x08 |
#define ADS_IDACMAG_2000 0x09 |
#define ADS_IDACMAG_250 0x04 |
#define ADS_IDACMAG_50 0x02 |
#define ADS_IDACMAG_500 0x05 |
#define ADS_IDACMAG_750 0x06 |
#define ADS_IDACMAG_OFF 0x00 |
#define ADS_N_AIN0 0x00 |
#define ADS_N_AIN1 0x01 |
#define ADS_N_AIN10 0x0A |
#define ADS_N_AIN11 0x0B |
#define ADS_N_AIN2 0x02 |
#define ADS_N_AIN3 0x03 |
#define ADS_N_AIN4 0x04 |
#define ADS_N_AIN5 0x05 |
#define ADS_N_AIN6 0x06 |
#define ADS_N_AIN7 0x07 |
#define ADS_N_AIN8 0x08 |
#define ADS_N_AIN9 0x09 |
#define ADS_N_AINCOM 0x0C |
#define ADS_nRDY_MASK 0x40 |
#define ADS_P_AIN0 0x00 |
#define ADS_P_AIN1 0x10 |
#define ADS_P_AIN10 0xA0 |
#define ADS_P_AIN11 0xB0 |
#define ADS_P_AIN2 0x20 |
#define ADS_P_AIN3 0x30 |
#define ADS_P_AIN4 0x40 |
#define ADS_P_AIN5 0x50 |
#define ADS_P_AIN6 0x60 |
#define ADS_P_AIN7 0x70 |
#define ADS_P_AIN8 0x80 |
#define ADS_P_AIN9 0x90 |
#define ADS_P_AINCOM 0xC0 |
#define ADS_PGA_BYPASS 0x00 |
#define ADS_PGA_ENABLED 0x08 |
#define ADS_PSW_CLOSED 0x40 |
#define ADS_PSW_OPEN 0x00 |
#define ADS_REFINT_OFF 0x00 |
#define ADS_REFINT_ON_ALWAYS 0x02 |
#define ADS_REFINT_ON_PDWN 0x01 |
#define ADS_REFN_BYP_DISABLE 0x10 |
#define ADS_REFN_BYP_ENABLE 0x00 |
#define ADS_REFP_BYP_DISABLE 0x20 |
#define ADS_REFP_BYP_ENABLE 0x00 |
#define ADS_REFSEL_INT 0x08 |
#define ADS_REFSEL_P0 0x00 |
#define ADS_REFSEL_P1 0x04 |
#define ADS_SENDSTATUS_DISABLE 0x00 |
#define ADS_SENDSTATUS_ENABLE 0x01 |
#define ADS_SENDSTATUS_MASK 0x01 |
#define ADS_SYS_MON_ADIV4 0x60 |
#define ADS_SYS_MON_BCS_1 0xC0 |
#define ADS_SYS_MON_BCS_10 0xE0 |
#define ADS_SYS_MON_BCS_2 0xA0 |
#define ADS_SYS_MON_DDIV4 0x80 |
#define ADS_SYS_MON_OFF 0x00 |
#define ADS_SYS_MON_SHORT 0x20 |
#define ADS_SYS_MON_TEMP 0x40 |
#define ADS_TIMEOUT_DISABLE 0x00 |
#define ADS_TIMEOUT_ENABLE 0x04 |
#define ADS_VB_AIN0 0x01 |
#define ADS_VB_AIN1 0x02 |
#define ADS_VB_AIN2 0x04 |
#define ADS_VB_AIN3 0x08 |
#define ADS_VB_AIN4 0x10 |
#define ADS_VB_AIN5 0x20 |
#define ADS_VB_AINC 0x40 |
#define ADS_VBIAS_LVL_DIV12 0x80 |
#define ADS_VBIAS_LVL_DIV2 0x00 |
#define COMMAND_LENGTH 2 |
#define CRC_LENGTH 1 |
#define DATA_LENGTH 3 |
#define DATA_MODE_CRC 0x02 |
#define DATA_MODE_NORMAL 0x00 |
#define DATA_MODE_STATUS 0x01 |
#define DATARATE_DEFAULT ((uint8_t) 0x14) |
DATARATE default (reset) value
#define DELAY_2p2MS (uint32_t) (0.0022 * 1000000 ) |
#define DELAY_4096TCLK (uint32_t) (4096.0 * 1000000 / ADS124S08_FCLK ) |
#define DELAY_4TCLK (uint32_t) (1) |
#define FSCAL0_DEFAULT ((uint8_t) 0x00) |
FSCAL0 default (reset) value
#define FSCAL1_DEFAULT ((uint8_t) 0x00) |
FSCAL1 default (reset) value
#define FSCAL2_DEFAULT ((uint8_t) 0x40) |
FSCAL2 default (reset) value
#define GPIOCON_DEFAULT ((uint8_t) 0x00) |
GPIOCON default (reset) value
#define GPIODAT_DEFAULT ((uint8_t) 0x00) |
GPIODAT default (reset) value
#define ID_DEFAULT ((uint8_t) 0x00) |
ID default (reset) value
#define IDACMAG_DEFAULT ((uint8_t) 0x00) |
IDACMAG default (reset) value
#define IDACMUX_DEFAULT ((uint8_t) 0xFF) |
IDACMUX default (reset) value
#define INPMUX_DEFAULT ((uint8_t) 0x01) |
INPMUX default (reset) value
#define INT_VREF 2.5 |
#define IS_CRC_SET ((bool) (getRegisterValue(REG_ADDR_SYS) & ADS_CRC_MASK)) |
#define IS_SENDSTAT_SET ((bool) (getRegisterValue(REG_ADDR_SYS) & ADS_SENDSTATUS_MASK)) |
Register bit checking macros... Return true if register bit is set (since last read or write).
#define NUM_REGISTERS ((uint8_t) 18) |
#define OFCAL0_DEFAULT ((uint8_t) 0x00) |
OFCAL0 default (reset) value
#define OFCAL1_DEFAULT ((uint8_t) 0x00) |
OFCAL1 default (reset) value
#define OFCAL2_DEFAULT ((uint8_t) 0x00) |
OFCAL2 default (reset) value
#define OPCODE_NOP ((uint8_t) 0x00) |
#define OPCODE_POWERDOWN ((uint8_t) 0x04) |
#define OPCODE_RDATA ((uint8_t) 0x12) |
#define OPCODE_RESET ((uint8_t) 0x06) |
#define OPCODE_RREG ((uint8_t) 0x20) |
#define OPCODE_RWREG_MASK ((uint8_t) 0x1F) |
#define OPCODE_SFOCAL ((uint8_t) 0x19) |
#define OPCODE_START ((uint8_t) 0x08) |
#define OPCODE_STOP ((uint8_t) 0x0A) |
#define OPCODE_SYGCAL ((uint8_t) 0x17) |
#define OPCODE_SYOCAL ((uint8_t) 0x16) |
#define OPCODE_WAKEUP ((uint8_t) 0x02) |
#define OPCODE_WREG ((uint8_t) 0x40) |
#define PGA_DEFAULT ((uint8_t) 0x00) |
PGA default (reset) value
#define RDATA_COMMAND_LENGTH 1 |
#define REF_DEFAULT ((uint8_t) 0x10) |
REF default (reset) value
#define REG_ADDR_DATARATE ((uint8_t) 0x04) |
#define REG_ADDR_FSCAL0 ((uint8_t) 0x0D) |
#define REG_ADDR_FSCAL1 ((uint8_t) 0x0E) |
#define REG_ADDR_FSCAL2 ((uint8_t) 0x0F) |
#define REG_ADDR_GPIOCON ((uint8_t) 0x11) |
#define REG_ADDR_GPIODAT ((uint8_t) 0x10) |
#define REG_ADDR_ID ((uint8_t) 0x00) |
#define REG_ADDR_IDACMAG ((uint8_t) 0x06) |
#define REG_ADDR_IDACMUX ((uint8_t) 0x07) |
#define REG_ADDR_INPMUX ((uint8_t) 0x02) |
#define REG_ADDR_OFCAL0 ((uint8_t) 0x0A) |
#define REG_ADDR_OFCAL1 ((uint8_t) 0x0B) |
#define REG_ADDR_OFCAL2 ((uint8_t) 0x0C) |
#define REG_ADDR_PGA ((uint8_t) 0x03) |
#define REG_ADDR_REF ((uint8_t) 0x05) |
#define REG_ADDR_STATUS ((uint8_t) 0x01) |
STATUS register address
#define REG_ADDR_SYS ((uint8_t) 0x09) |
#define REG_ADDR_VBIAS ((uint8_t) 0x08) |
#define STATUS_DEFAULT ((uint8_t) 0x80) |
STATUS default (reset) value
#define STATUS_LENGTH 1 |
#define SYS_DEFAULT ((uint8_t) 0x10) |
SYS default (reset) value
#define VBIAS_DEFAULT ((uint8_t) 0x00) |
VBIAS default (reset) value
enum readMode |
bool adcStartupRoutine | ( | SPI_Handle | spiHdl | ) |
adcStartupRoutine() Startup function to be called before communicating with the ADC
[in] | *spiHdl | SPI_Handle pointer for TI Drivers |
uint8_t getRegisterValue | ( | uint8_t | address | ) |
getRegisterValue() Getter function to access the registerMap array outside of this module
[in] | address | The 8-bit register address |
int32_t readConvertedData | ( | SPI_Handle | spiHdl, |
uint8_t | status[], | ||
readMode | mode | ||
) |
readConvertedData() Sends the read command and retrieves STATUS (if enabled) and data NOTE: Call this function after /DRDY goes low and specify the the number of bytes to read and the starting position of data
[in] | spiHdl | SPI_Handle from TI Drivers |
[in] | status[] | Pointer to location where STATUS byte will be stored |
[in] | mode | Direct or Command read mode |
void readMultipleRegisters | ( | SPI_Handle | spiHdl, |
uint8_t | startAddress, | ||
uint8_t | count | ||
) |
readMultipleRegisters() Reads a group of registers starting at the specified address NOTE: Use getRegisterValue() to retrieve the read values
[in] | spiHdl | SPI_Handle from TI Drivers |
[in] | startAddress | Register address to start reading |
[in] | count | Number of registers to read |
uint8_t readSingleRegister | ( | SPI_Handle | spiHdl, |
uint8_t | address | ||
) |
readSingleRegister() Reads contents of a single register at the specified address
[in] | spiHdl | SPI_Handle from TI Drivers |
[in] | address | Address of the register to be read |
void resetADC | ( | SPI_Handle | spiHdl | ) |
resetADC() Resets ADC by setting RESET pin low or sending RESET Command
[in] | spiHdl | SPI_Handle from TI Drivers |
void restoreRegisterDefaults | ( | void | ) |
restoreRegisterDefaults() Updates the registerMap[] array to its default values NOTES: If the MCU keeps a copy of the ADC register settings in memory, then it is important to ensure that these values remain in sync with the actual hardware settings. In order to help facilitate this, this function should be called after powering up or resetting the device (either by hardware pin control or SPI software command). Reading back all of the registers after resetting the device will accomplish the same result.
void sendCommand | ( | SPI_Handle | spiHdl, |
uint8_t | op_code | ||
) |
sendCommand() Sends the specified SPI command to the ADC
[in] | spiHdl | SPI_Handle from TI Drivers |
[in] | op_code | SPI command byte |
void startConversions | ( | SPI_Handle | spiHdl | ) |
startConversions() Wakes the device from power-down and starts continuous conversions by setting START pin high or sending START Command
[in] | spiHdl | SPI_Handle from TI Drivers |
void stopConversions | ( | SPI_Handle | spiHdl | ) |
stopConversions() Stops continuous conversions by setting START pin low or sending STOP Command
[in] | spiHdl | SPI_Handle from TI Drivers |
void writeMultipleRegisters | ( | SPI_Handle | spiHdl, |
uint8_t | startAddress, | ||
uint8_t | count, | ||
uint8_t | regData[] | ||
) |
writeMultipleRegisters() Write data to a group of registers NOTES: Use getRegisterValue() to retrieve the written values. Registers should be re-read after a write operation to ensure proper configuration.
[in] | spiHdl | SPI_Handle from TI Drivers |
[in] | startAddress | Register address to start writing |
[in] | count | Number of registers to write |
[in] | regData | Array that holds the data to write, where element zero is the data to write to the starting address. |
void writeSingleRegister | ( | SPI_Handle | spiHdl, |
uint8_t | address, | ||
uint8_t | data | ||
) |
writeSingleRegister() Write data to a single register at the specified address
[in] | spiHdl | SPI_Handle from TI Drivers |
[in] | address | Register address to write |
[in] | data | 8-bit data to write |
bool converting |