ADS124S08 Example C Code  1.0.0
ads124s08.h
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1 
39 #ifndef ADS124S08_H_
40 #define ADS124S08_H_
41 
42 #include <stdbool.h>
43 #include <stdint.h>
44 #include <string.h>
45 #include "hal.h"
46 
47 //extern SPI_Handle spiHdl;
48 /********************************************************************************/
53 #define NUM_REGISTERS ((uint8_t) 18)
54 
55 #define ADS124S08_FCLK 4096000 // Standard internal clock frequency. Change value for external clock.
56 #define ADS124S08_BITRES 24 // ADS124S0x ADC resolution. Change to '16' if using ADS114S0x.
57 
58 // Lengths of conversion data components
59 // Variable data depending on device used
60 #define DATA_LENGTH 3 // Conversion data total bytes for ADS124S0x. Change to '2' if using ADS114S0x.
61 
62 // Fixed data for all device variants
63 #define COMMAND_LENGTH 2 // Register read and write standard command length.
64 #define STATUS_LENGTH 1 // Status length in bytes.
65 #define CRC_LENGTH 1 // CRC length in bytes.
66 #define RDATA_COMMAND_LENGTH 1 // Number of bytes for command if RDATA is used as opposed to reading conversion data directly.
67 
68 // Flag to signal that we are in the process of collecting data
69 extern bool converting;
70 #define DATA_MODE_NORMAL 0x00
71 #define DATA_MODE_STATUS 0x01
72 #define DATA_MODE_CRC 0x02
73 
74 #define INT_VREF 2.5
75 
76 
77 //#define START_PIN_CONTROLLED // Conversion START/STOP functions are pin controlled through the START/SYNC pin
78 //#define RESET_PIN_CONTROLLED // Device RESET is controlled by the RESET pin
79 
80 //Fixed timing delays
81 #define DELAY_4TCLK (uint32_t) (1) // 1usec ~= (4.0 /ADS124S08_FCLK) which is the minimum required low time for RESET or START/SYNC.
82 #define DELAY_4096TCLK (uint32_t) (4096.0 * 1000000 / ADS124S08_FCLK ) // Minimum delay time following a RESET condition before beginning communication.
83 #define DELAY_2p2MS (uint32_t) (0.0022 * 1000000 ) // Minimum delay following device power-up prior to communication or device operation.
84 
85 
86 /********************************************************************************/
96  // SPI Control Commands
97  #define OPCODE_NOP ((uint8_t) 0x00)
98  #define OPCODE_WAKEUP ((uint8_t) 0x02)
99  #define OPCODE_POWERDOWN ((uint8_t) 0x04)
100  #define OPCODE_RESET ((uint8_t) 0x06)
101  #define OPCODE_START ((uint8_t) 0x08)
102  #define OPCODE_STOP ((uint8_t) 0x0A)
103 
104  //SPI Calibration Commands
105  #define OPCODE_SYOCAL ((uint8_t) 0x16)
106  #define OPCODE_SYGCAL ((uint8_t) 0x17)
107  #define OPCODE_SFOCAL ((uint8_t) 0x19)
108 
109  // SPI Data Read Command
110  #define OPCODE_RDATA ((uint8_t) 0x12)
111 
112  // SPI Register Read and Write Commands
113  #define OPCODE_RREG ((uint8_t) 0x20)
114  #define OPCODE_WREG ((uint8_t) 0x40)
115  #define OPCODE_RWREG_MASK ((uint8_t) 0x1F)
116 
117  /* Read mode enum */
118  typedef enum {
121  } readMode;
122 
123 /********************************************************************************/
128 /* ADS124S08 Register 0x0 (ID) Definition
129  *| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
130  *-----------------------------------------------------------------------------------------------
131  *| RESERVED[4:0] | DEV_ID[2:0] |
132  *-----------------------------------------------------------------------------------------------
133  *
134  */
135  // ID register address
136  #define REG_ADDR_ID ((uint8_t) 0x00)
137 
139  #define ID_DEFAULT ((uint8_t) 0x00)
140 
141  // Define DEV_ID
142  #define ADS_124S08 0x00
143  #define ADS_124S06 0x01
144  #define ADS_114S08 0x04
145  #define ADS_114S06 0x05
146 
147 
148 /* ADS124S08 Register 0x1 (STATUS) Definition
149  *| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
150  *------------------------------------------------------------------------------------------------
151  *| FL_POR | nRDY | FL_P_RAILP| FL_P_RAILN| FL_N_RAILP| FL_N_RAILN| FL_REF_L1 | FL_REF_L0 |
152  *------------------------------------------------------------------------------------------------
153  */
155  #define REG_ADDR_STATUS ((uint8_t) 0x01)
156 
158  #define STATUS_DEFAULT ((uint8_t) 0x80)
159 
160  #define ADS_FL_POR_MASK 0x80
161  #define ADS_nRDY_MASK 0x40
162  #define ADS_FL_P_RAILP_MASK 0x20
163  #define ADS_FL_P_RAILN_MASK 0x10
164  #define ADS_FL_N_RAILP_MASK 0x08
165  #define ADS_FL_N_RAILN_MASK 0x04
166  #define ADS_FL_REF_L1_MASK 0x02
167  #define ADS_FL_REF_L0_MASK 0x10
168 
169 
170 /* ADS124S08 Register 0x2 (INPMUX) Definition
171  *| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
172  *------------------------------------------------------------------------------------------------
173  *| MUXP[3:0] | MUXN[3:0] |
174  *------------------------------------------------------------------------------------------------
175  */
176  // INPMUX register address
177  #define REG_ADDR_INPMUX ((uint8_t) 0x02)
178 
180  #define INPMUX_DEFAULT ((uint8_t) 0x01)
181 
182  // Define the ADC positive input channels (MUXP)
183  #define ADS_P_AIN0 0x00
184  #define ADS_P_AIN1 0x10
185  #define ADS_P_AIN2 0x20
186  #define ADS_P_AIN3 0x30
187  #define ADS_P_AIN4 0x40
188  #define ADS_P_AIN5 0x50
189  #define ADS_P_AIN6 0x60
190  #define ADS_P_AIN7 0x70
191  #define ADS_P_AIN8 0x80
192  #define ADS_P_AIN9 0x90
193  #define ADS_P_AIN10 0xA0
194  #define ADS_P_AIN11 0xB0
195  #define ADS_P_AINCOM 0xC0
196 
197  // Define the ADC negative input channels (MUXN)
198  #define ADS_N_AIN0 0x00
199  #define ADS_N_AIN1 0x01
200  #define ADS_N_AIN2 0x02
201  #define ADS_N_AIN3 0x03
202  #define ADS_N_AIN4 0x04
203  #define ADS_N_AIN5 0x05
204  #define ADS_N_AIN6 0x06
205  #define ADS_N_AIN7 0x07
206  #define ADS_N_AIN8 0x08
207  #define ADS_N_AIN9 0x09
208  #define ADS_N_AIN10 0x0A
209  #define ADS_N_AIN11 0x0B
210  #define ADS_N_AINCOM 0x0C
211 
212 
213 /* ADS124S08 Register 0x3 (PGA) Definition
214  *| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
215  *-----------------------------------------------------------------------------------------------
216  *| DELAY[2:0] | PGA_EN[1:0] | GAIN[2:0] |
217  *-----------------------------------------------------------------------------------------------
218  */
219  // PGA register address
220  #define REG_ADDR_PGA ((uint8_t) 0x03)
221 
223  #define PGA_DEFAULT ((uint8_t) 0x00)
224 
225  // Define conversion delay in tmod clock periods
226  #define ADS_DELAY_14 0x00
227  #define ADS_DELAY_25 0x20
228  #define ADS_DELAY_64 0x40
229  #define ADS_DELAY_256 0x60
230  #define ADS_DELAY_1024 0x80
231  #define ADS_DELAY_2048 0xA0
232  #define ADS_DELAY_4096 0xC0
233  #define ADS_DELAY_1 0xE0
234 
235  // Define PGA control
236  #define ADS_PGA_BYPASS 0x00
237  #define ADS_PGA_ENABLED 0x08
238 
239  // Define Gain
240  #define ADS_GAIN_1 0x00
241  #define ADS_GAIN_2 0x01
242  #define ADS_GAIN_4 0x02
243  #define ADS_GAIN_8 0x03
244  #define ADS_GAIN_16 0x04
245  #define ADS_GAIN_32 0x05
246  #define ADS_GAIN_64 0x06
247  #define ADS_GAIN_128 0x07
248  #define ADS_GAIN_MASK 0x07
249 
250 
251 /* ADS124S08 Register 0x4 (DATARATE) Definition
252  *| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
253  *-----------------------------------------------------------------------------------------------
254  *| G_CHOP | CLK | MODE | FILTER | DR[3:0] |
255  *-----------------------------------------------------------------------------------------------
256  */
257  // DATARATE register address
258  #define REG_ADDR_DATARATE ((uint8_t) 0x04)
259 
261  #define DATARATE_DEFAULT ((uint8_t) 0x14)
262 
263  #define ADS_GLOBALCHOP 0x80
264  #define ADS_CLKSEL_EXT 0x40
265  #define ADS_CONVMODE_SS 0x20
266  #define ADS_CONVMODE_CONT 0x00
267  #define ADS_FILTERTYPE_LL 0x10
268 
269  // Define the data rate */
270  #define ADS_DR_2_5 0x00
271  #define ADS_DR_5 0x01
272  #define ADS_DR_10 0x02
273  #define ADS_DR_16 0x03
274  #define ADS_DR_20 0x04
275  #define ADS_DR_50 0x05
276  #define ADS_DR_60 0x06
277  #define ADS_DR_100 0x07
278  #define ADS_DR_200 0x08
279  #define ADS_DR_400 0x09
280  #define ADS_DR_800 0x0A
281  #define ADS_DR_1000 0x0B
282  #define ADS_DR_2000 0x0C
283  #define ADS_DR_4000 0x0D
284 
285 
286 /* ADS124S08 Register 0x5 (REF) Definition
287  *| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
288  *-----------------------------------------------------------------------------------------------
289  *| FL_REF_EN[1:0] | nREFP_BUF | nREFN_BUF | REFSEL[1:0] | REFCON[1:0] |
290  *-----------------------------------------------------------------------------------------------
291  */
292  // REF register address
293  #define REG_ADDR_REF ((uint8_t) 0x05)
294 
296  #define REF_DEFAULT ((uint8_t) 0x10)
297 
298  #define ADS_FLAG_REF_DISABLE 0x00
299  #define ADS_FLAG_REF_EN_L0 0x40
300  #define ADS_FLAG_REF_EN_BOTH 0x80
301  #define ADS_FLAG_REF_EN_10M 0xC0
302  #define ADS_REFP_BYP_DISABLE 0x20
303  #define ADS_REFP_BYP_ENABLE 0x00
304  #define ADS_REFN_BYP_DISABLE 0x10
305  #define ADS_REFN_BYP_ENABLE 0x00
306  #define ADS_REFSEL_P0 0x00
307  #define ADS_REFSEL_P1 0x04
308  #define ADS_REFSEL_INT 0x08
309  #define ADS_REFINT_OFF 0x00
310  #define ADS_REFINT_ON_PDWN 0x01
311  #define ADS_REFINT_ON_ALWAYS 0x02
312 
313 
314 /* ADS124S08 Register 0x6 (IDACMAG) Definition
315  *| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
316  *-----------------------------------------------------------------------------------------------
317  *|FL_RAIL_EN| PSW | 0 | 0 | IMAG[3:0] |
318  *-----------------------------------------------------------------------------------------------
319  */
320  // IDACMAG register address
321  #define REG_ADDR_IDACMAG ((uint8_t) 0x06)
322 
324  #define IDACMAG_DEFAULT ((uint8_t) 0x00)
325 
326  #define ADS_FLAG_RAIL_ENABLE 0x80
327  #define ADS_FLAG_RAIL_DISABLE 0x00
328  #define ADS_PSW_OPEN 0x00
329  #define ADS_PSW_CLOSED 0x40
330  #define ADS_IDACMAG_OFF 0x00
331  #define ADS_IDACMAG_10 0x01
332  #define ADS_IDACMAG_50 0x02
333  #define ADS_IDACMAG_100 0x03
334  #define ADS_IDACMAG_250 0x04
335  #define ADS_IDACMAG_500 0x05
336  #define ADS_IDACMAG_750 0x06
337  #define ADS_IDACMAG_1000 0x07
338  #define ADS_IDACMAG_1500 0x08
339  #define ADS_IDACMAG_2000 0x09
340 
341 
342 /* ADS124S08 Register 0x7 (IDACMUX) Definition
343  *| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
344  *-----------------------------------------------------------------------------------------------
345  *| I2MUX[3:0] | I1MUX[3:0] |
346  *-----------------------------------------------------------------------------------------------
347  */
348  // IDACMUX register address
349  #define REG_ADDR_IDACMUX ((uint8_t) 0x07)
350 
352  #define IDACMUX_DEFAULT ((uint8_t) 0xFF)
353 
354  // Define IDAC2 Output
355  #define ADS_IDAC2_A0 0x00
356  #define ADS_IDAC2_A1 0x10
357  #define ADS_IDAC2_A2 0x20
358  #define ADS_IDAC2_A3 0x30
359  #define ADS_IDAC2_A4 0x40
360  #define ADS_IDAC2_A5 0x50
361  #define ADS_IDAC2_A6 0x60
362  #define ADS_IDAC2_A7 0x70
363  #define ADS_IDAC2_A8 0x80
364  #define ADS_IDAC2_A9 0x90
365  #define ADS_IDAC2_A10 0xA0
366  #define ADS_IDAC2_A11 0xB0
367  #define ADS_IDAC2_AINCOM 0xC0
368  #define ADS_IDAC2_OFF 0xF0
369 
370  // Define IDAC1 Output
371  #define ADS_IDAC1_A0 0x00
372  #define ADS_IDAC1_A1 0x01
373  #define ADS_IDAC1_A2 0x02
374  #define ADS_IDAC1_A3 0x03
375  #define ADS_IDAC1_A4 0x04
376  #define ADS_IDAC1_A5 0x05
377  #define ADS_IDAC1_A6 0x06
378  #define ADS_IDAC1_A7 0x07
379  #define ADS_IDAC1_A8 0x08
380  #define ADS_IDAC1_A9 0x09
381  #define ADS_IDAC1_A10 0x0A
382  #define ADS_IDAC1_A11 0x0B
383  #define ADS_IDAC1_AINCOM 0x0C
384  #define ADS_IDAC1_OFF 0x0F
385 
386 
387 /* ADS124S08 Register 0x8 (VBIAS) Definition
388  *| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
389  *-----------------------------------------------------------------------------------------------
390  *| VB_LEVEL | VB_AINC | VB_AIN5 | VB_AIN4 | VB_AIN3 | VB_AIN2 | VB_AIN1 | VB_AIN0 |
391  *-----------------------------------------------------------------------------------------------
392  */
393  // VBIAS register address
394  #define REG_ADDR_VBIAS ((uint8_t) 0x08)
395 
397  #define VBIAS_DEFAULT ((uint8_t) 0x00)
398 
399  #define ADS_VBIAS_LVL_DIV2 0x00
400  #define ADS_VBIAS_LVL_DIV12 0x80
401 
402  // Define VBIAS here
403  #define ADS_VB_AINC 0x40
404  #define ADS_VB_AIN5 0x20
405  #define ADS_VB_AIN4 0x10
406  #define ADS_VB_AIN3 0x08
407  #define ADS_VB_AIN2 0x04
408  #define ADS_VB_AIN1 0x02
409  #define ADS_VB_AIN0 0x01
410 
411 
412 /* ADS124S08 Register 0x9 (SYS) Definition
413  *| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
414  *-----------------------------------------------------------------------------------------------
415  *| SYS_MON[2:0] | CAL_SAMP[1:0] | TIMEOUT | CRC | SENDSTAT |
416  *-----------------------------------------------------------------------------------------------
417  */
418  // SYS register address
419  #define REG_ADDR_SYS ((uint8_t) 0x09)
420 
422  #define SYS_DEFAULT ((uint8_t) 0x10)
423 
424  #define ADS_SYS_MON_OFF 0x00
425  #define ADS_SYS_MON_SHORT 0x20
426  #define ADS_SYS_MON_TEMP 0x40
427  #define ADS_SYS_MON_ADIV4 0x60
428  #define ADS_SYS_MON_DDIV4 0x80
429  #define ADS_SYS_MON_BCS_2 0xA0
430  #define ADS_SYS_MON_BCS_1 0xC0
431  #define ADS_SYS_MON_BCS_10 0xE0
432  #define ADS_CALSAMPLE_1 0x00
433  #define ADS_CALSAMPLE_4 0x08
434  #define ADS_CALSAMPLE_8 0x10
435  #define ADS_CALSAMPLE_16 0x18
436  #define ADS_TIMEOUT_DISABLE 0x00
437  #define ADS_TIMEOUT_ENABLE 0x04
438  #define ADS_CRC_DISABLE 0x00
439  #define ADS_CRC_ENABLE 0x02
440  #define ADS_CRC_MASK 0x02
441  #define ADS_SENDSTATUS_DISABLE 0x00
442  #define ADS_SENDSTATUS_ENABLE 0x01
443  #define ADS_SENDSTATUS_MASK 0x01
444 
445 /* ADS124S08 Register 0xA (OFCAL0) Definition
446  *| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
447  *-----------------------------------------------------------------------------------------------
448  *| OFC[7:0] |
449  *-----------------------------------------------------------------------------------------------
450  */
451  // OFCAL0 register address
452  #define REG_ADDR_OFCAL0 ((uint8_t) 0x0A)
453 
455  #define OFCAL0_DEFAULT ((uint8_t) 0x00)
456 
457 
458 
459 /* ADS124S08 Register 0xB (OFCAL1) Definition
460  *| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
461  *-----------------------------------------------------------------------------------------------
462  *| OFC[15:8] |
463  *-----------------------------------------------------------------------------------------------
464  */
465  // OFCAL1 register address
466  #define REG_ADDR_OFCAL1 ((uint8_t) 0x0B)
467 
469  #define OFCAL1_DEFAULT ((uint8_t) 0x00)
470 
471 
472 /* ADS124S08 Register 0xC (OFCAL2) Definition
473  *| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
474  *-----------------------------------------------------------------------------------------------
475  *| OFC[23:16] |
476  *-----------------------------------------------------------------------------------------------
477  */
478  // OFCAL2 register address
479  #define REG_ADDR_OFCAL2 ((uint8_t) 0x0C)
480 
482  #define OFCAL2_DEFAULT ((uint8_t) 0x00)
483 
484 
485 /* ADS124S08 Register 0xD (FSCAL0) Definition
486  *| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
487  *-----------------------------------------------------------------------------------------------
488  *| FSC[7:0] |
489  *-----------------------------------------------------------------------------------------------
490  */
491  // FSCAL0 register address
492  #define REG_ADDR_FSCAL0 ((uint8_t) 0x0D)
493 
495  #define FSCAL0_DEFAULT ((uint8_t) 0x00)
496 
497 
498 /* ADS124S08 Register 0xE (FSCAL1) Definition
499  *| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
500  *-----------------------------------------------------------------------------------------------
501  *| FSC[15:8] |
502  *-----------------------------------------------------------------------------------------------
503  */
504  // FSCAL1 register address
505  #define REG_ADDR_FSCAL1 ((uint8_t) 0x0E)
506 
508  #define FSCAL1_DEFAULT ((uint8_t) 0x00)
509 
510 
511 /* ADS124S08 Register 0xF (FSCAL2) Definition
512  *| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
513  *-----------------------------------------------------------------------------------------------
514  *| FSC[23:16] |
515  *-----------------------------------------------------------------------------------------------
516  */
517  // FSCAL2 register address
518  #define REG_ADDR_FSCAL2 ((uint8_t) 0x0F)
519 
521  #define FSCAL2_DEFAULT ((uint8_t) 0x40)
522 
523 
524 /* ADS124S08 Register 0x10 (GPIODAT) Definition
525  *| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
526  *-----------------------------------------------------------------------------------------------
527  *| DIR[3:0] | DAT[3:0] |
528  *-----------------------------------------------------------------------------------------------
529  */
530  // GPIODAT register address
531  #define REG_ADDR_GPIODAT ((uint8_t) 0x10)
532 
534  #define GPIODAT_DEFAULT ((uint8_t) 0x00)
535 
536  // Define GPIO direction (0-Output; 1-Input) here
537  #define ADS_GPIO0_DIR_INPUT 0x10
538  #define ADS_GPIO1_DIR_INPUT 0x20
539  #define ADS_GPIO2_DIR_INPUT 0x40
540  #define ADS_GPIO3_DIR_INPUT 0x80
541 
542 
543 /* ADS124S08 Register 0x11 (GPIOCON) Definition
544  *| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
545  *-----------------------------------------------------------------------------------------------
546  *| 0 | 0 | 0 | 0 | CON[3:0] |
547  *-----------------------------------------------------------------------------------------------
548  */
549  // GPIOCON register address
550  #define REG_ADDR_GPIOCON ((uint8_t) 0x11)
551 
553  #define GPIOCON_DEFAULT ((uint8_t) 0x00)
554 
555  // Define GPIO configuration (0-Analog Input; 1-GPIO) here
556  #define ADS_GPIO0_CFG_GPIO 0x01
557  #define ADS_GPIO1_CFG_GPIO 0x02
558  #define ADS_GPIO2_CFG_GPIO 0x04
559  #define ADS_GPIO3_CFG_GPIO 0x08
560 
561 
562 
563 //*****************************************************************************
564 //
565 // Function Prototypes
566 //
567 //*****************************************************************************
568 
569 bool adcStartupRoutine( SPI_Handle spiHdl );
570 int32_t readConvertedData( SPI_Handle spiHdl, uint8_t status[], readMode mode );
571 uint8_t readSingleRegister( SPI_Handle spiHdl, uint8_t address );
572 void readMultipleRegisters( SPI_Handle spiHdl, uint8_t startAddress, uint8_t count );
573 void sendCommand( SPI_Handle spiHdl, uint8_t op_code );
574 void startConversions( SPI_Handle spiHdl );
575 void stopConversions( SPI_Handle spiHdl );
576 void writeSingleRegister( SPI_Handle spiHdl, uint8_t address, uint8_t data );
577 void writeMultipleRegisters( SPI_Handle spiHdl, uint8_t startAddress, uint8_t count, uint8_t regData[] );
578 void resetADC( SPI_Handle spiHdl );
579 
580 // Internal variable getters
581 uint8_t getRegisterValue( uint8_t address );
582 
583 // Internal variable setters
584 void restoreRegisterDefaults( void) ;
585 
586 //*****************************************************************************
587 //
588 // Macros
589 //
590 //*****************************************************************************
591 
595 #define IS_SENDSTAT_SET ((bool) (getRegisterValue(REG_ADDR_SYS) & ADS_SENDSTATUS_MASK))
596 #define IS_CRC_SET ((bool) (getRegisterValue(REG_ADDR_SYS) & ADS_CRC_MASK))
597 
598 
599 
600 #endif // ADS124S08_H_
Definition: ads124s08.h:119
void writeMultipleRegisters(SPI_Handle spiHdl, uint8_t startAddress, uint8_t count, uint8_t regData[])
writeMultipleRegisters() Write data to a group of registers NOTES: Use getRegisterValue() to retrieve...
Definition: ads124s08.c:232
bool adcStartupRoutine(SPI_Handle spiHdl)
adcStartupRoutine() Startup function to be called before communicating with the ADC ...
Definition: ads124s08.c:88
Example of a hardware abstraction layer.
void restoreRegisterDefaults(void)
restoreRegisterDefaults() Updates the registerMap[] array to its default values NOTES: If the MCU kee...
Definition: ads124s08.c:466
bool converting
uint8_t getRegisterValue(uint8_t address)
getRegisterValue() Getter function to access the registerMap array outside of this module ...
Definition: ads124s08.c:72
void stopConversions(SPI_Handle spiHdl)
stopConversions() Stops continuous conversions by setting START pin low or sending STOP Command ...
Definition: ads124s08.c:317
void readMultipleRegisters(SPI_Handle spiHdl, uint8_t startAddress, uint8_t count)
readMultipleRegisters() Reads a group of registers starting at the specified address NOTE: Use getReg...
Definition: ads124s08.c:169
uint8_t readSingleRegister(SPI_Handle spiHdl, uint8_t address)
readSingleRegister() Reads contents of a single register at the specified address ...
Definition: ads124s08.c:139
void resetADC(SPI_Handle spiHdl)
resetADC() Resets ADC by setting RESET pin low or sending RESET Command
Definition: ads124s08.c:336
void sendCommand(SPI_Handle spiHdl, uint8_t op_code)
sendCommand() Sends the specified SPI command to the ADC
Definition: ads124s08.c:265
int32_t readConvertedData(SPI_Handle spiHdl, uint8_t status[], readMode mode)
readConvertedData() Sends the read command and retrieves STATUS (if enabled) and data NOTE: Call this...
Definition: ads124s08.c:364
void writeSingleRegister(SPI_Handle spiHdl, uint8_t address, uint8_t data)
writeSingleRegister() Write data to a single register at the specified address
Definition: ads124s08.c:201
void startConversions(SPI_Handle spiHdl)
startConversions() Wakes the device from power-down and starts continuous conversions by setting STAR...
Definition: ads124s08.c:295
readMode
Definition: ads124s08.h:118
Definition: ads124s08.h:120
SPI_Handle spiHdl