ADS1282 Example C Code  1.0.0
ads1282.h
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1 
38 #ifndef ADS1282_H_
39 #define ADS1282_H_
40 
41 // Standard libraries
42 #include <assert.h>
43 #include <stdbool.h>
44 #include <stdint.h>
45 
46 // Custom libraries
47 #include "hal.h"
48 
49 
50 //*****************************************************************************
51 //
52 // Constants
53 //
54 //*****************************************************************************
55 
57 #define NUM_REGISTERS ((uint8_t) 11)
58 
60 #define HIGH ((bool) true)
61 
63 #define LOW ((bool) false)
64 
72 #define DELAY_T_DLY ((uint32_t) 6 * (4096000/FCLK_FREQ_HZ))
73 
74 
75 //*****************************************************************************
76 //
77 // Commands
78 //
79 //*****************************************************************************
80 
81 #define OPCODE_NOP ((uint8_t) 0x00)
82 #define OPCODE_WAKEUP ((uint8_t) 0x00) // Use 0x00 or 0x01
83 #define OPCODE_STANDBY ((uint8_t) 0x03) // Use 0x02 or 0x03
84 #define OPCODE_SYNC ((uint8_t) 0x05) // Use 0x04 or 0x05
85 #define OPCODE_RESET ((uint8_t) 0x07) // Use 0x06 or 0x07
86 #define OPCODE_RDATAC ((uint8_t) 0x10)
87 #define OPCODE_SDATAC ((uint8_t) 0x11)
88 #define OPCODE_RDATA ((uint8_t) 0x12)
89 #define OPCODE_RREG ((uint8_t) 0x20) // OR'd with register address
90 #define OPCODE_WREG ((uint8_t) 0x40) // OR'd with register address
91 #define OPCODE_REG_ADDR_MASK ((uint8_t) 0x1F) // Location of address bits in RREG/WREG commands (1st byte)
92 #define OPCODE_REG_COUNT_MASK ((uint8_t) 0x1F) // Location of count bits in RREG/WREG commands (2nd byte)
93 #define OPCODE_OFSCAL ((uint8_t) 0x60)
94 #define OPCODE_GANCAL ((uint8_t) 0x61)
95 
96  /* Read mode enum */
97 typedef enum { DIRECT, COMMAND } readMode;
98 
99 
100 //*****************************************************************************
101 //
102 // Function Prototypes
103 //
104 //*****************************************************************************
105 
106 void adcStartupRoutine(void);
107 uint8_t readSingleRegister(const uint8_t address);
108 void readMultipleRegisters(const uint8_t startAddress, const uint8_t count);
109 void writeSingleRegister(const uint8_t address, const uint8_t data);
110 void writeMultipleRegisters(const uint8_t startAddress, const uint8_t count, const uint8_t regData[]);
111 int32_t readData(void);
112 void sendCommand(const uint8_t op_code);
113 
114 // Getters...
115 uint8_t getRegisterValue(const uint8_t address);
116 
117 // Internal Use Functions...
118 // NOTE: Avoid calling these functions in the application code except when absolutely needed
119 // as these functions affect the internal state variables in the ads1282.c module.
120 void _restoreRegisterDefaults(void);
121 
122 
123 //*****************************************************************************
124 //
125 // Register macros
126 //
127 //*****************************************************************************
128 
129 #define FILTR_SETTING ((uint8_t) (getRegisterValue(CONFIG0_ADDRESS) & CONFIG0_FILTR_MASK))
130 #define FILTR_BYPASSED ((bool) (FILTR_SETTING == CONFIG0_FILTR_MODMODE))
131 #define FILTR_SINC_ONLY ((bool) (FILTR_SETTING == CONFIG0_FILTR_SINC))
132 
133 
134 //*****************************************************************************
135 //
136 // Register definitions
137 //
138 //*****************************************************************************
139 
140 /* Register 0x00 (ID) definition
141  * ---------------------------------------------------------------------------------
142  * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
143  * ---------------------------------------------------------------------------------
144  * | ID[3:0] | 0 |
145  * ---------------------------------------------------------------------------------
146  */
147 
148  /* ID register */
149  #define ID_ADDRESS ((uint8_t) 0x00)
150  #define ID_RESET_MASK ((uint8_t) 0x0F) // Only lower nibble is determinate after rest
151  #define ID_DEFAULT ((uint8_t) 0x00)
152 
153  /* Factory-programmed identification bits (read-only) */
154  #define ID_ID_MASK ((uint8_t) 0xF0)
155 
156 
157 /* Register 0x01 (CONFIG0) definition
158 * ---------------------------------------------------------------------------------
159 * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
160 * ---------------------------------------------------------------------------------
161 * | SYNC | 1 | DR[2:0] | PHASE | FILTR[0:1] |
162 * ---------------------------------------------------------------------------------
163 */
164 
165  /* CONFIG0 register */
166  #define CONFIG0_ADDRESS ((uint8_t) 0x01)
167  #define CONFIG0_DEFAULT ((uint8_t) 0x52)
168 
169  /* Synchronization mode */
170  #define CONFIG0_SYNC_MASK ((uint8_t) 0x80)
171  #define CONFIG0_SYNC_PULSE ((uint8_t) 0x00 << 7) // default
172  #define CONFIG0_SYNC_CONTINUOUS ((uint8_t) 0x01 << 7)
173 
174  /* Data Rate Select */
175  // NOTE: Specified data rates valid only in FIR filter mode with nominal 4.096 MHz FCLK
176  #define CONFIG0_DR_MASK ((uint8_t) 0x38)
177  #define CONFIG0_DR_250SPS ((uint8_t) 0x00 << 3)
178  #define CONFIG0_DR_500SPS ((uint8_t) 0x01 << 3)
179  #define CONFIG0_DR_1000SPS ((uint8_t) 0x02 << 3) // default
180  #define CONFIG0_DR_2000SPS ((uint8_t) 0x03 << 3)
181  #define CONFIG0_DR_4000SPS ((uint8_t) 0x04 << 3)
182 
183  /* FIR Phase Response */
184  #define CONFIG0_PHASE_MASK ((uint8_t) 0x04)
185  #define CONFIG0_PHASE_LINEAR ((uint8_t) 0x00 << 2) // default
186  #define CONFIG0_PHASE_MINIMUM ((uint8_t) 0x01 << 2)
187 
188  /* Digital Filter Select */
189  #define CONFIG0_FILTR_MASK ((uint8_t) 0x03)
190  #define CONFIG0_FILTR_MODMODE ((uint8_t) 0x00 << 0)
191  #define CONFIG0_FILTR_SINC ((uint8_t) 0x01 << 0)
192  #define CONFIG0_FILTR_SINC_LPF ((uint8_t) 0x02 << 0) // default
193  #define CONFIG0_FILTR_SINC_LPF_HPF ((uint8_t) 0x03 << 0)
194 
195 
196 /* Register 0x02 (CONFIG1) definition
197 * ---------------------------------------------------------------------------------
198 * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
199 * ---------------------------------------------------------------------------------
200 * | 0 | MUX[2:0] | CHOP | PGA[3:0] |
201 * ---------------------------------------------------------------------------------
202 */
203 
204  /* CONFIG1 register */
205  #define CONFIG1_ADDRESS ((uint8_t) 0x02)
206  #define CONFIG1_DEFAULT ((uint8_t) 0x08)
207 
208  /* MUX Select */
209  #define CONFIG1_MUX_MASK ((uint8_t) 0x70)
210  #define CONFIG1_MUX_AINP1_AINN1 ((uint8_t) 0x00 << 4) // default
211  #define CONFIG1_MUX_AINP2_AINN2 ((uint8_t) 0x01 << 4)
212  #define CONFIG1_MUX_INT_400OHM_SHORT ((uint8_t) 0x02 << 4)
213  #define CONFIG1_MUX_AINX1_AINX2 ((uint8_t) 0x03 << 4)
214  #define CONFIG1_MUX_EXT_SHORT_AINN2 ((uint8_t) 0x04 << 4)
215 
216  /* PGA Chopping Enable */
217  #define CONFIG1_CHOP_MASK ((uint8_t) 0x08)
218  #define CONFIG1_CHOP_DISABLED ((uint8_t) 0x00 << 3)
219  #define CONFIG1_CHOP_ENDABLED ((uint8_t) 0x01 << 3) // default
220 
221  /* PGA Gain Select */
222  #define CONFIG1_PGA_MASK ((uint8_t) 0x07)
223  #define CONFIG1_PGA_1 ((uint8_t) 0x00 << 0)
224  #define CONFIG1_PGA_2 ((uint8_t) 0x01 << 0)
225  #define CONFIG1_PGA_4 ((uint8_t) 0x02 << 0)
226  #define CONFIG1_PGA_8 ((uint8_t) 0x03 << 0)
227  #define CONFIG1_PGA_16 ((uint8_t) 0x04 << 0)
228  #define CONFIG1_PGA_32 ((uint8_t) 0x05 << 0)
229  #define CONFIG1_PGA_64 ((uint8_t) 0x06 << 0)
230 
231 
232 /* Register 0x03 (HPF0) definition
233 * ---------------------------------------------------------------------------------
234 * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
235 * ---------------------------------------------------------------------------------
236 * | HP[07:00] |
237 * ---------------------------------------------------------------------------------
238 */
239 
240  /* HPF0 register */
241  #define HPF0_ADDRESS ((uint8_t) 0x03)
242  #define HPF0_DEFAULT ((uint8_t) 0x32)
243 
244 
245 /* Register 0x04 (HPF1) definition
246 * ---------------------------------------------------------------------------------
247 * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
248 * ---------------------------------------------------------------------------------
249 * | HP[15:08] |
250 * ---------------------------------------------------------------------------------
251 */
252 
253  /* HPF1 register */
254  #define HPF1_ADDRESS ((uint8_t) 0x04)
255  #define HPF1_DEFAULT ((uint8_t) 0x03)
256 
257 
258 /* Register 0x05 (OFC0) definition
259 * ---------------------------------------------------------------------------------
260 * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
261 * ---------------------------------------------------------------------------------
262 * | OC[07:00] |
263 * ---------------------------------------------------------------------------------
264 */
265 
266  /* OFC0 register */
267  #define OFC0_ADDRESS ((uint8_t) 0x05)
268  #define OFC0_DEFAULT ((uint8_t) 0x00)
269 
270 
271 /* Register 0x06 (OFC1) definition
272 * ---------------------------------------------------------------------------------
273 * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
274 * ---------------------------------------------------------------------------------
275 * | OC[15:08] |
276 * ---------------------------------------------------------------------------------
277 */
278 
279  /* OFC1 register */
280  #define OFC1_ADDRESS ((uint8_t) 0x06)
281  #define OFC1_DEFAULT ((uint8_t) 0x00)
282 
283 
284 /* Register 0x07 (OFC2) definition
285 * ---------------------------------------------------------------------------------
286 * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
287 * ---------------------------------------------------------------------------------
288 * | OC[23:16] |
289 * ---------------------------------------------------------------------------------
290 */
291 
292  /* OFC2 register */
293  #define OFC2_ADDRESS ((uint8_t) 0x07)
294  #define OFC2_DEFAULT ((uint8_t) 0x00)
295 
296 
297 /* Register 0x08 (FSC0) definition
298 * ---------------------------------------------------------------------------------
299 * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
300 * ---------------------------------------------------------------------------------
301 * | FSC[07:00] |
302 * ---------------------------------------------------------------------------------
303 */
304 
305  /* FSC0 register */
306  #define FSC0_ADDRESS ((uint8_t) 0x08)
307  #define FSC0_DEFAULT ((uint8_t) 0x00)
308 
309 
310 /* Register 0x09 (FSC1) definition
311 * ---------------------------------------------------------------------------------
312 * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
313 * ---------------------------------------------------------------------------------
314 * | FSC[15:08] |
315 * ---------------------------------------------------------------------------------
316 */
317 
318  /* FSC1 register */
319  #define FSC1_ADDRESS ((uint8_t) 0x09)
320  #define FSC1_DEFAULT ((uint8_t) 0x00)
321 
322 
323 /* Register 0x0A (FSC2) definition
324 * ---------------------------------------------------------------------------------
325 * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
326 * ---------------------------------------------------------------------------------
327 * | FSC[23:16] |
328 * ---------------------------------------------------------------------------------
329 */
330 
331  /* FSC2 register */
332  #define FSC2_ADDRESS ((uint8_t) 0x0A)
333  #define FSC2_DEFAULT ((uint8_t) 0x40)
334 
335 
336 #endif /* ADS1282_H_ */
Definition: ads1282.h:97
void adcStartupRoutine(void)
Definition: ads1282.c:104
Hardware abstraction layer (HAL) descriptor.
void _restoreRegisterDefaults(void)
Definition: ads1282.c:409
Definition: ads1282.h:97
void readMultipleRegisters(const uint8_t startAddress, const uint8_t count)
Definition: ads1282.c:179
void writeSingleRegister(const uint8_t address, const uint8_t data)
Definition: ads1282.c:219
uint8_t readSingleRegister(const uint8_t address)
Definition: ads1282.c:140
void writeMultipleRegisters(const uint8_t startAddress, const uint8_t count, const uint8_t regData[])
Definition: ads1282.c:261
int32_t readData(void)
Definition: ads1282.c:375
void sendCommand(const uint8_t op_code)
Definition: ads1282.c:305
uint8_t getRegisterValue(const uint8_t address)
Definition: ads1282.c:84
readMode
Definition: ads1282.h:97