57 #define NUM_REGISTERS ((uint8_t) 11) 60 #define HIGH ((bool) true) 63 #define LOW ((bool) false) 72 #define DELAY_T_DLY ((uint32_t) 6 * (4096000/FCLK_FREQ_HZ)) 81 #define OPCODE_NOP ((uint8_t) 0x00) 82 #define OPCODE_WAKEUP ((uint8_t) 0x00) // Use 0x00 or 0x01 83 #define OPCODE_STANDBY ((uint8_t) 0x03) // Use 0x02 or 0x03 84 #define OPCODE_SYNC ((uint8_t) 0x05) // Use 0x04 or 0x05 85 #define OPCODE_RESET ((uint8_t) 0x07) // Use 0x06 or 0x07 86 #define OPCODE_RDATAC ((uint8_t) 0x10) 87 #define OPCODE_SDATAC ((uint8_t) 0x11) 88 #define OPCODE_RDATA ((uint8_t) 0x12) 89 #define OPCODE_RREG ((uint8_t) 0x20) // OR'd with register address 90 #define OPCODE_WREG ((uint8_t) 0x40) // OR'd with register address 91 #define OPCODE_REG_ADDR_MASK ((uint8_t) 0x1F) // Location of address bits in RREG/WREG commands (1st byte) 92 #define OPCODE_REG_COUNT_MASK ((uint8_t) 0x1F) // Location of count bits in RREG/WREG commands (2nd byte) 93 #define OPCODE_OFSCAL ((uint8_t) 0x60) 94 #define OPCODE_GANCAL ((uint8_t) 0x61) 129 #define FILTR_SETTING ((uint8_t) (getRegisterValue(CONFIG0_ADDRESS) & CONFIG0_FILTR_MASK)) 130 #define FILTR_BYPASSED ((bool) (FILTR_SETTING == CONFIG0_FILTR_MODMODE)) 131 #define FILTR_SINC_ONLY ((bool) (FILTR_SETTING == CONFIG0_FILTR_SINC)) 149 #define ID_ADDRESS ((uint8_t) 0x00) 150 #define ID_RESET_MASK ((uint8_t) 0x0F) // Only lower nibble is determinate after rest 151 #define ID_DEFAULT ((uint8_t) 0x00) 154 #define ID_ID_MASK ((uint8_t) 0xF0) 166 #define CONFIG0_ADDRESS ((uint8_t) 0x01) 167 #define CONFIG0_DEFAULT ((uint8_t) 0x52) 170 #define CONFIG0_SYNC_MASK ((uint8_t) 0x80) 171 #define CONFIG0_SYNC_PULSE ((uint8_t) 0x00 << 7) // default 172 #define CONFIG0_SYNC_CONTINUOUS ((uint8_t) 0x01 << 7) 176 #define CONFIG0_DR_MASK ((uint8_t) 0x38) 177 #define CONFIG0_DR_250SPS ((uint8_t) 0x00 << 3) 178 #define CONFIG0_DR_500SPS ((uint8_t) 0x01 << 3) 179 #define CONFIG0_DR_1000SPS ((uint8_t) 0x02 << 3) // default 180 #define CONFIG0_DR_2000SPS ((uint8_t) 0x03 << 3) 181 #define CONFIG0_DR_4000SPS ((uint8_t) 0x04 << 3) 184 #define CONFIG0_PHASE_MASK ((uint8_t) 0x04) 185 #define CONFIG0_PHASE_LINEAR ((uint8_t) 0x00 << 2) // default 186 #define CONFIG0_PHASE_MINIMUM ((uint8_t) 0x01 << 2) 189 #define CONFIG0_FILTR_MASK ((uint8_t) 0x03) 190 #define CONFIG0_FILTR_MODMODE ((uint8_t) 0x00 << 0) 191 #define CONFIG0_FILTR_SINC ((uint8_t) 0x01 << 0) 192 #define CONFIG0_FILTR_SINC_LPF ((uint8_t) 0x02 << 0) // default 193 #define CONFIG0_FILTR_SINC_LPF_HPF ((uint8_t) 0x03 << 0) 205 #define CONFIG1_ADDRESS ((uint8_t) 0x02) 206 #define CONFIG1_DEFAULT ((uint8_t) 0x08) 209 #define CONFIG1_MUX_MASK ((uint8_t) 0x70) 210 #define CONFIG1_MUX_AINP1_AINN1 ((uint8_t) 0x00 << 4) // default 211 #define CONFIG1_MUX_AINP2_AINN2 ((uint8_t) 0x01 << 4) 212 #define CONFIG1_MUX_INT_400OHM_SHORT ((uint8_t) 0x02 << 4) 213 #define CONFIG1_MUX_AINX1_AINX2 ((uint8_t) 0x03 << 4) 214 #define CONFIG1_MUX_EXT_SHORT_AINN2 ((uint8_t) 0x04 << 4) 217 #define CONFIG1_CHOP_MASK ((uint8_t) 0x08) 218 #define CONFIG1_CHOP_DISABLED ((uint8_t) 0x00 << 3) 219 #define CONFIG1_CHOP_ENDABLED ((uint8_t) 0x01 << 3) // default 222 #define CONFIG1_PGA_MASK ((uint8_t) 0x07) 223 #define CONFIG1_PGA_1 ((uint8_t) 0x00 << 0) 224 #define CONFIG1_PGA_2 ((uint8_t) 0x01 << 0) 225 #define CONFIG1_PGA_4 ((uint8_t) 0x02 << 0) 226 #define CONFIG1_PGA_8 ((uint8_t) 0x03 << 0) 227 #define CONFIG1_PGA_16 ((uint8_t) 0x04 << 0) 228 #define CONFIG1_PGA_32 ((uint8_t) 0x05 << 0) 229 #define CONFIG1_PGA_64 ((uint8_t) 0x06 << 0) 241 #define HPF0_ADDRESS ((uint8_t) 0x03) 242 #define HPF0_DEFAULT ((uint8_t) 0x32) 254 #define HPF1_ADDRESS ((uint8_t) 0x04) 255 #define HPF1_DEFAULT ((uint8_t) 0x03) 267 #define OFC0_ADDRESS ((uint8_t) 0x05) 268 #define OFC0_DEFAULT ((uint8_t) 0x00) 280 #define OFC1_ADDRESS ((uint8_t) 0x06) 281 #define OFC1_DEFAULT ((uint8_t) 0x00) 293 #define OFC2_ADDRESS ((uint8_t) 0x07) 294 #define OFC2_DEFAULT ((uint8_t) 0x00) 306 #define FSC0_ADDRESS ((uint8_t) 0x08) 307 #define FSC0_DEFAULT ((uint8_t) 0x00) 319 #define FSC1_ADDRESS ((uint8_t) 0x09) 320 #define FSC1_DEFAULT ((uint8_t) 0x00) 332 #define FSC2_ADDRESS ((uint8_t) 0x0A) 333 #define FSC2_DEFAULT ((uint8_t) 0x40)
void adcStartupRoutine(void)
Definition: ads1282.c:104
Hardware abstraction layer (HAL) descriptor.
void _restoreRegisterDefaults(void)
Definition: ads1282.c:409
void readMultipleRegisters(const uint8_t startAddress, const uint8_t count)
Definition: ads1282.c:179
void writeSingleRegister(const uint8_t address, const uint8_t data)
Definition: ads1282.c:219
uint8_t readSingleRegister(const uint8_t address)
Definition: ads1282.c:140
void writeMultipleRegisters(const uint8_t startAddress, const uint8_t count, const uint8_t regData[])
Definition: ads1282.c:261
int32_t readData(void)
Definition: ads1282.c:375
void sendCommand(const uint8_t op_code)
Definition: ads1282.c:305
uint8_t getRegisterValue(const uint8_t address)
Definition: ads1282.c:84
readMode
Definition: ads1282.h:97