70 #define ASYNC_SLAVE_MODE 73 #define WORD_LENGTH_BITS ((uint8_t) 24) 74 #define WORD_LENGTH_24BIT 115 uint16_t
calculateCRC(
const uint8_t dataBytes[], uint8_t numberBytes, uint16_t initialValue);
119 int32_t
signExtend(
const uint8_t dataBytes[]);
129 #define OPCODE_NULL ((uint16_t) 0x0000) 130 #define OPCODE_RESET ((uint16_t) 0x0011) 131 #define OPCODE_STANDBY ((uint16_t) 0x0022) 132 #define OPCODE_WAKEUP ((uint16_t) 0x0033) 133 #define OPCODE_LOCK ((uint16_t) 0x0555) 134 #define OPCODE_UNLOCK ((uint16_t) 0x0655) 135 #define OPCODE_RREG ((uint16_t) 0x2000) 136 #define OPCODE_WREG ((uint16_t) 0x4000) 149 #define NUM_REGISTERS ((uint8_t) 21) 161 #define ID_MSB_ADDRESS ((uint8_t) 0x00) 164 #define ID_MSB_NU_CH_MASK ((uint8_t) 0xFF) 167 #define ID_MSB_NU_CH_2 ((uint8_t) 0x02) 168 #define ID_MSB_NU_CH_4 ((uint8_t) 0x04) 181 #define ID_LSB_ADDRESS ((uint8_t) 0x01) 184 #define ID_LSB_REV_ID_MASK ((uint8_t) 0xFF) 197 #define STAT_1_ADDRESS ((uint8_t) 0x02) 200 #define STAT_1_DEFAULT ((uint8_t) 0x00) 203 #define STAT_1_F_OPC_MASK ((uint8_t) 0x40) 204 #define STAT_1_F_SPI_MASK ((uint8_t) 0x20) 205 #define STAT_1_F_ADCIN_MASK ((uint8_t) 0x10) 206 #define STAT_1_F_WDT_MASK ((uint8_t) 0x08) 207 #define STAT_1_F_RESYNC_MASK ((uint8_t) 0x04) 208 #define STAT_1_F_DRDY_MASK ((uint8_t) 0x02) 209 #define STAT_1_F_CHECK_MASK ((uint8_t) 0x01) 222 #define STAT_P_ADDRESS ((uint8_t) 0x03) 225 #define STAT_P_DEFAULT ((uint8_t) 0x00) 228 #define STAT_P_F_IN4P_MASK ((uint8_t) 0x08) 229 #define STAT_P_F_IN3P_MASK ((uint8_t) 0x04) 230 #define STAT_P_F_IN2P_MASK ((uint8_t) 0x02) 231 #define STAT_P_F_IN1P_MASK ((uint8_t) 0x01) 244 #define STAT_N_ADDRESS ((uint8_t) 0x04) 247 #define STAT_N_DEFAULT ((uint8_t) 0x00) 250 #define STAT_N_F_IN4N_MASK ((uint8_t) 0x08) 251 #define STAT_N_F_IN3N_MASK ((uint8_t) 0x04) 252 #define STAT_N_F_IN2N_MASK ((uint8_t) 0x02) 253 #define STAT_N_F_IN1N_MASK ((uint8_t) 0x01) 266 #define STAT_S_ADDRESS ((uint8_t) 0x05) 269 #define STAT_S_DEFAULT ((uint8_t) 0x00) 272 #define STAT_S_F_STARTUP_MASK ((uint8_t) 0x04) 273 #define STAT_S_F_CS_MASK ((uint8_t) 0x02) 274 #define STAT_S_F_FRAME_MASK ((uint8_t) 0x01) 287 #define ERROR_CNT_ADDRESS ((uint8_t) 0x06) 290 #define ERROR_CNT_DEFAULT ((uint8_t) 0x00) 293 #define ERROR_CNT_ER_MASK ((uint8_t) 0xFF) 306 #define STAT_M2_ADDRESS ((uint8_t) 0x07) 309 #define STAT_M2_DEFAULT ((uint8_t) 0x00) 310 #define STAT_M2_DEFAULT_MASK ((uint8_t) 0xC0) 313 #define STAT_M2_M2PIN_MASK ((uint8_t) 0x30) 314 #define STAT_M2_M1PIN_MASK ((uint8_t) 0x0C) 315 #define STAT_M2_M0PIN_MASK ((uint8_t) 0x03) 318 #define STAT_M2_M2PIN_M2_HAMMING_OFF ((uint8_t) 0x00) 319 #define STAT_M2_M2PIN_M2_HAMMING_ON ((uint8_t) 0x10) 320 #define STAT_M2_M2PIN_M2_NC ((uint8_t) 0x20) 323 #define STAT_M2_M1PIN_M1_24BIT ((uint8_t) 0x00) 324 #define STAT_M2_M1PIN_M1_32BIT ((uint8_t) 0x04) 325 #define STAT_M2_M1PIN_M1_16BIT ((uint8_t) 0x08) 328 #define STAT_M2_M0PIN_M0_SYNC_MASTER ((uint8_t) 0x00) 329 #define STAT_M2_M0PIN_M0_ASYNC_SLAVE ((uint8_t) 0x01) 330 #define STAT_M2_M0PIN_M0_SYNC_SLAVE ((uint8_t) 0x02) 373 #define A_SYS_CFG_ADDRESS ((uint8_t) 0x0B) 376 #define A_SYS_CFG_DEFAULT ((uint8_t) 0x60) 379 #define A_SYS_CFG_VNCPEN_MASK ((uint8_t) 0x80) 380 #define A_SYS_CFG_HRM_MASK ((uint8_t) 0x40) 381 #define A_SYS_CFG_VREF_4V_MASK ((uint8_t) 0x10) 382 #define A_SYS_CFG_INT_REFEN_MASK ((uint8_t) 0x08) 383 #define A_SYS_CFG_COMP_TH_MASK ((uint8_t) 0x07) 386 #define A_SYS_CFG_COMP_TH_HIGH_95_LOW_5 ((uint8_t) 0x00) 387 #define A_SYS_CFG_COMP_TH_HIGH_92p5_LOW_7p5 ((uint8_t) 0x01) 388 #define A_SYS_CFG_COMP_TH_HIGH_90_LOW_10 ((uint8_t) 0x02) 389 #define A_SYS_CFG_COMP_TH_HIGH_87p5_LOW_12p5 ((uint8_t) 0x03) 390 #define A_SYS_CFG_COMP_TH_HIGH_85_LOW_15 ((uint8_t) 0x04) 391 #define A_SYS_CFG_COMP_TH_HIGH_80_LOW_20 ((uint8_t) 0x05) 392 #define A_SYS_CFG_COMP_TH_HIGH_75_LOW_25 ((uint8_t) 0x06) 393 #define A_SYS_CFG_COMP_TH_HIGH_70_LOW_30 ((uint8_t) 0x07) 406 #define D_SYS_CFG_ADDRESS ((uint8_t) 0x0C) 409 #define D_SYS_CFG_DEFAULT ((uint8_t) 0x3C) 412 #define D_SYS_CFG_WDT_EN_MASK ((uint8_t) 0x80) 413 #define D_SYS_CFG_CRC_MODE_MASK ((uint8_t) 0x40) 414 #define D_SYS_CFG_DNDLY_MASK ((uint8_t) 0x30) 415 #define D_SYS_CFG_HIZDLY_MASK ((uint8_t) 0x0C) 416 #define D_SYS_CFG_FIXED_MASK ((uint8_t) 0x02) 417 #define D_SYS_CFG_CRC_EN_MASK ((uint8_t) 0x01) 420 #define D_SYS_CFG_DNDLY_6ns ((uint8_t) 0x00) 421 #define D_SYS_CFG_DNDLY_8ns ((uint8_t) 0x10) 422 #define D_SYS_CFG_DNDLY_10ns ((uint8_t) 0x20) 423 #define D_SYS_CFG_DNDLY_12ns ((uint8_t) 0x30) 426 #define D_SYS_CFG_HIZDLY_6ns ((uint8_t) 0x00) 427 #define D_SYS_CFG_HIZDLY_8ns ((uint8_t) 0x04) 428 #define D_SYS_CFG_HIZDLY_10ns ((uint8_t) 0x08) 429 #define D_SYS_CFG_HIZDLY_12ns ((uint8_t) 0x0C) 442 #define CLK1_ADDRESS ((uint8_t) 0x0D) 445 #define CLK1_DEFAULT ((uint8_t) 0x08) 448 #define CLK1_CLKSRC_MASK ((uint8_t) 0x80) 449 #define CLK1_CLK_DIV_MASK ((uint8_t) 0x0E) 452 #define CLK1_CLK_DIV_2 ((uint8_t) 0x02) 453 #define CLK1_CLK_DIV_4 ((uint8_t) 0x04) 454 #define CLK1_CLK_DIV_6 ((uint8_t) 0x06) 455 #define CLK1_CLK_DIV_8 ((uint8_t) 0x08) 456 #define CLK1_CLK_DIV_10 ((uint8_t) 0x0A) 457 #define CLK1_CLK_DIV_12 ((uint8_t) 0x0C) 458 #define CLK1_CLK_DIV_14 ((uint8_t) 0x0E) 471 #define CLK2_ADDRESS ((uint8_t) 0x0E) 474 #define CLK2_DEFAULT ((uint8_t) 0x86) 477 #define CLK2_ICLK_DIV_MASK ((uint8_t) 0xE0) 478 #define CLK2_OSR_MASK ((uint8_t) 0x0F) 481 #define CLK2_ICLK_DIV_2 ((uint8_t) 0x20) 482 #define CLK2_ICLK_DIV_4 ((uint8_t) 0x40) 483 #define CLK2_ICLK_DIV_6 ((uint8_t) 0x60) 484 #define CLK2_ICLK_DIV_8 ((uint8_t) 0x80) 485 #define CLK2_ICLK_DIV_10 ((uint8_t) 0xA0) 486 #define CLK2_ICLK_DIV_12 ((uint8_t) 0xC0) 487 #define CLK2_ICLK_DIV_14 ((uint8_t) 0xE0) 490 #define CLK2_OSR_4096 ((uint8_t) 0x00) 491 #define CLK2_OSR_2048 ((uint8_t) 0x01) 492 #define CLK2_OSR_1024 ((uint8_t) 0x02) 493 #define CLK2_OSR_800 ((uint8_t) 0x03) 494 #define CLK2_OSR_768 ((uint8_t) 0x04) 495 #define CLK2_OSR_512 ((uint8_t) 0x05) 496 #define CLK2_OSR_400 ((uint8_t) 0x06) 497 #define CLK2_OSR_384 ((uint8_t) 0x07) 498 #define CLK2_OSR_256 ((uint8_t) 0x08) 499 #define CLK2_OSR_200 ((uint8_t) 0x09) 500 #define CLK2_OSR_192 ((uint8_t) 0x0A) 501 #define CLK2_OSR_128 ((uint8_t) 0x0B) 502 #define CLK2_OSR_96 ((uint8_t) 0x0C) 503 #define CLK2_OSR_64 ((uint8_t) 0x0D) 504 #define CLK2_OSR_48 ((uint8_t) 0x0E) 505 #define CLK2_OSR_32 ((uint8_t) 0x0F) 518 #define ADC_ENA_ADDRESS ((uint8_t) 0x0F) 521 #define ADC_ENA_DEFAULT ((uint8_t) 0x00) 524 #define ADC_ENA_ENA_MASK ((uint8_t) 0x0F) 527 #define ADC_ENA_ENA_ALL_CH_PWDN ((uint8_t) 0x00) 528 #define ADC_ENA_ENA_ALL_CH_PWUP ((uint8_t) 0x0F) 551 #define ADC1_ADDRESS ((uint8_t) 0x11) 554 #define ADC1_DEFAULT ((uint8_t) 0x00) 557 #define ADC1_GAIN1_MASK ((uint8_t) 0x07) 560 #define ADC1_GAIN1_1 ((uint8_t) 0x00) 561 #define ADC1_GAIN1_2 ((uint8_t) 0x01) 562 #define ADC1_GAIN1_4 ((uint8_t) 0x02) 563 #define ADC1_GAIN1_8 ((uint8_t) 0x03) 564 #define ADC1_GAIN1_16 ((uint8_t) 0x04) 577 #define ADC2_ADDRESS ((uint8_t) 0x12) 580 #define ADC2_DEFAULT ((uint8_t) 0x00) 583 #define ADC2_GAIN2_MASK ((uint8_t) 0x07) 586 #define ADC2_GAIN2_1 ((uint8_t) 0x00) 587 #define ADC2_GAIN2_2 ((uint8_t) 0x01) 588 #define ADC2_GAIN2_4 ((uint8_t) 0x02) 589 #define ADC2_GAIN2_8 ((uint8_t) 0x03) 590 #define ADC2_GAIN2_16 ((uint8_t) 0x04) 603 #define ADC3_ADDRESS ((uint8_t) 0x13) 606 #define ADC3_DEFAULT ((uint8_t) 0x00) 609 #define ADC3_GAIN3_MASK ((uint8_t) 0x07) 612 #define ADC3_GAIN3_1 ((uint8_t) 0x00) 613 #define ADC3_GAIN3_2 ((uint8_t) 0x01) 614 #define ADC3_GAIN3_4 ((uint8_t) 0x02) 615 #define ADC3_GAIN3_8 ((uint8_t) 0x03) 616 #define ADC3_GAIN3_16 ((uint8_t) 0x04) 629 #define ADC4_ADDRESS ((uint8_t) 0x14) 632 #define ADC4_DEFAULT ((uint8_t) 0x00) 635 #define ADC4_GAIN4_MASK ((uint8_t) 0x07) 638 #define ADC4_GAIN4_1 ((uint8_t) 0x00) 639 #define ADC4_GAIN4_2 ((uint8_t) 0x01) 640 #define ADC4_GAIN4_4 ((uint8_t) 0x02) 641 #define ADC4_GAIN4_8 ((uint8_t) 0x03) 642 #define ADC4_GAIN4_16 ((uint8_t) 0x04) 656 #define CRC_EN ((bool) (getRegisterValue(D_SYS_CFG_ADDRESS) & D_SYS_CFG_CRC_EN_MASK)) 657 #define CRC_MODE ((bool) (getRegisterValue(D_SYS_CFG_ADDRESS) & D_SYS_CFG_CRC_MODE_MASK)) 658 #define FIXED ((bool) (getRegisterValue(D_SYS_CFG_ADDRESS) & D_SYS_CFG_FIXED_MASK)) Definition: ads131a04.h:88
int32_t signExtend(const uint8_t dataBytes[])
Definition: ads131a04.c:701
uint16_t calculateCRC(const uint8_t dataBytes[], uint8_t numberBytes, uint16_t initialValue)
Definition: ads131a04.c:566
int32_t channel4
Definition: ads131a04.h:93
bool readData(adc_data_struct *dataStruct)
Definition: ads131a04.c:346
void restoreRegisterDefaults(void)
Definition: ads131a04.c:659
uint8_t getRegisterValue(uint8_t address)
Definition: ads131a04.c:115
uint16_t crc
Definition: ads131a04.h:95
uint16_t response
Definition: ads131a04.h:94
int32_t channel3
Definition: ads131a04.h:92
bool lockRegisters(void)
Definition: ads131a04.c:490
uint16_t sendCommand(uint16_t opcode)
Definition: ads131a04.c:440
int32_t channel1
Definition: ads131a04.h:90
void adcStartup(void)
Definition: ads131a04.c:139
uint8_t readSingleRegister(uint8_t address)
Definition: ads131a04.c:234
int32_t channel2
Definition: ads131a04.h:91
void writeSingleRegister(uint8_t address, uint8_t data)
Definition: ads131a04.c:283
bool unlockRegisters(void)
Definition: ads131a04.c:524