ADS131A04 Example C Code
1.0.0
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Data Structures | |
struct | adc_data_struct |
Macros | |
#define | SET_FIXED |
#define | ASYNC_SLAVE_MODE |
#define | WORD_LENGTH_BITS ((uint8_t) 24) |
#define | WORD_LENGTH_24BIT |
#define | OPCODE_NULL ((uint16_t) 0x0000) |
#define | OPCODE_RESET ((uint16_t) 0x0011) |
#define | OPCODE_STANDBY ((uint16_t) 0x0022) |
#define | OPCODE_WAKEUP ((uint16_t) 0x0033) |
#define | OPCODE_LOCK ((uint16_t) 0x0555) |
#define | OPCODE_UNLOCK ((uint16_t) 0x0655) |
#define | OPCODE_RREG ((uint16_t) 0x2000) |
#define | OPCODE_WREG ((uint16_t) 0x4000) |
#define | NUM_REGISTERS ((uint8_t) 21) |
#define | ID_MSB_ADDRESS ((uint8_t) 0x00) |
#define | ID_MSB_NU_CH_MASK ((uint8_t) 0xFF) |
#define | ID_MSB_NU_CH_2 ((uint8_t) 0x02) |
#define | ID_MSB_NU_CH_4 ((uint8_t) 0x04) |
#define | ID_LSB_ADDRESS ((uint8_t) 0x01) |
#define | ID_LSB_REV_ID_MASK ((uint8_t) 0xFF) |
#define | STAT_1_ADDRESS ((uint8_t) 0x02) |
#define | STAT_1_DEFAULT ((uint8_t) 0x00) |
#define | STAT_1_F_OPC_MASK ((uint8_t) 0x40) |
#define | STAT_1_F_SPI_MASK ((uint8_t) 0x20) |
#define | STAT_1_F_ADCIN_MASK ((uint8_t) 0x10) |
#define | STAT_1_F_WDT_MASK ((uint8_t) 0x08) |
#define | STAT_1_F_RESYNC_MASK ((uint8_t) 0x04) |
#define | STAT_1_F_DRDY_MASK ((uint8_t) 0x02) |
#define | STAT_1_F_CHECK_MASK ((uint8_t) 0x01) |
#define | STAT_P_ADDRESS ((uint8_t) 0x03) |
#define | STAT_P_DEFAULT ((uint8_t) 0x00) |
#define | STAT_P_F_IN4P_MASK ((uint8_t) 0x08) |
#define | STAT_P_F_IN3P_MASK ((uint8_t) 0x04) |
#define | STAT_P_F_IN2P_MASK ((uint8_t) 0x02) |
#define | STAT_P_F_IN1P_MASK ((uint8_t) 0x01) |
#define | STAT_N_ADDRESS ((uint8_t) 0x04) |
#define | STAT_N_DEFAULT ((uint8_t) 0x00) |
#define | STAT_N_F_IN4N_MASK ((uint8_t) 0x08) |
#define | STAT_N_F_IN3N_MASK ((uint8_t) 0x04) |
#define | STAT_N_F_IN2N_MASK ((uint8_t) 0x02) |
#define | STAT_N_F_IN1N_MASK ((uint8_t) 0x01) |
#define | STAT_S_ADDRESS ((uint8_t) 0x05) |
#define | STAT_S_DEFAULT ((uint8_t) 0x00) |
#define | STAT_S_F_STARTUP_MASK ((uint8_t) 0x04) |
#define | STAT_S_F_CS_MASK ((uint8_t) 0x02) |
#define | STAT_S_F_FRAME_MASK ((uint8_t) 0x01) |
#define | ERROR_CNT_ADDRESS ((uint8_t) 0x06) |
#define | ERROR_CNT_DEFAULT ((uint8_t) 0x00) |
#define | ERROR_CNT_ER_MASK ((uint8_t) 0xFF) |
#define | STAT_M2_ADDRESS ((uint8_t) 0x07) |
#define | STAT_M2_DEFAULT ((uint8_t) 0x00) |
#define | STAT_M2_DEFAULT_MASK ((uint8_t) 0xC0) |
#define | STAT_M2_M2PIN_MASK ((uint8_t) 0x30) |
#define | STAT_M2_M1PIN_MASK ((uint8_t) 0x0C) |
#define | STAT_M2_M0PIN_MASK ((uint8_t) 0x03) |
#define | STAT_M2_M2PIN_M2_HAMMING_OFF ((uint8_t) 0x00) |
#define | STAT_M2_M2PIN_M2_HAMMING_ON ((uint8_t) 0x10) |
#define | STAT_M2_M2PIN_M2_NC ((uint8_t) 0x20) |
#define | STAT_M2_M1PIN_M1_24BIT ((uint8_t) 0x00) |
#define | STAT_M2_M1PIN_M1_32BIT ((uint8_t) 0x04) |
#define | STAT_M2_M1PIN_M1_16BIT ((uint8_t) 0x08) |
#define | STAT_M2_M0PIN_M0_SYNC_MASTER ((uint8_t) 0x00) |
#define | STAT_M2_M0PIN_M0_ASYNC_SLAVE ((uint8_t) 0x01) |
#define | STAT_M2_M0PIN_M0_SYNC_SLAVE ((uint8_t) 0x02) |
#define | A_SYS_CFG_ADDRESS ((uint8_t) 0x0B) |
#define | A_SYS_CFG_DEFAULT ((uint8_t) 0x60) |
#define | A_SYS_CFG_VNCPEN_MASK ((uint8_t) 0x80) |
#define | A_SYS_CFG_HRM_MASK ((uint8_t) 0x40) |
#define | A_SYS_CFG_VREF_4V_MASK ((uint8_t) 0x10) |
#define | A_SYS_CFG_INT_REFEN_MASK ((uint8_t) 0x08) |
#define | A_SYS_CFG_COMP_TH_MASK ((uint8_t) 0x07) |
#define | A_SYS_CFG_COMP_TH_HIGH_95_LOW_5 ((uint8_t) 0x00) |
#define | A_SYS_CFG_COMP_TH_HIGH_92p5_LOW_7p5 ((uint8_t) 0x01) |
#define | A_SYS_CFG_COMP_TH_HIGH_90_LOW_10 ((uint8_t) 0x02) |
#define | A_SYS_CFG_COMP_TH_HIGH_87p5_LOW_12p5 ((uint8_t) 0x03) |
#define | A_SYS_CFG_COMP_TH_HIGH_85_LOW_15 ((uint8_t) 0x04) |
#define | A_SYS_CFG_COMP_TH_HIGH_80_LOW_20 ((uint8_t) 0x05) |
#define | A_SYS_CFG_COMP_TH_HIGH_75_LOW_25 ((uint8_t) 0x06) |
#define | A_SYS_CFG_COMP_TH_HIGH_70_LOW_30 ((uint8_t) 0x07) |
#define | D_SYS_CFG_ADDRESS ((uint8_t) 0x0C) |
#define | D_SYS_CFG_DEFAULT ((uint8_t) 0x3C) |
#define | D_SYS_CFG_WDT_EN_MASK ((uint8_t) 0x80) |
#define | D_SYS_CFG_CRC_MODE_MASK ((uint8_t) 0x40) |
#define | D_SYS_CFG_DNDLY_MASK ((uint8_t) 0x30) |
#define | D_SYS_CFG_HIZDLY_MASK ((uint8_t) 0x0C) |
#define | D_SYS_CFG_FIXED_MASK ((uint8_t) 0x02) |
#define | D_SYS_CFG_CRC_EN_MASK ((uint8_t) 0x01) |
#define | D_SYS_CFG_DNDLY_6ns ((uint8_t) 0x00) |
#define | D_SYS_CFG_DNDLY_8ns ((uint8_t) 0x10) |
#define | D_SYS_CFG_DNDLY_10ns ((uint8_t) 0x20) |
#define | D_SYS_CFG_DNDLY_12ns ((uint8_t) 0x30) |
#define | D_SYS_CFG_HIZDLY_6ns ((uint8_t) 0x00) |
#define | D_SYS_CFG_HIZDLY_8ns ((uint8_t) 0x04) |
#define | D_SYS_CFG_HIZDLY_10ns ((uint8_t) 0x08) |
#define | D_SYS_CFG_HIZDLY_12ns ((uint8_t) 0x0C) |
#define | CLK1_ADDRESS ((uint8_t) 0x0D) |
#define | CLK1_DEFAULT ((uint8_t) 0x08) |
#define | CLK1_CLKSRC_MASK ((uint8_t) 0x80) |
#define | CLK1_CLK_DIV_MASK ((uint8_t) 0x0E) |
#define | CLK1_CLK_DIV_2 ((uint8_t) 0x02) |
#define | CLK1_CLK_DIV_4 ((uint8_t) 0x04) |
#define | CLK1_CLK_DIV_6 ((uint8_t) 0x06) |
#define | CLK1_CLK_DIV_8 ((uint8_t) 0x08) |
#define | CLK1_CLK_DIV_10 ((uint8_t) 0x0A) |
#define | CLK1_CLK_DIV_12 ((uint8_t) 0x0C) |
#define | CLK1_CLK_DIV_14 ((uint8_t) 0x0E) |
#define | CLK2_ADDRESS ((uint8_t) 0x0E) |
#define | CLK2_DEFAULT ((uint8_t) 0x86) |
#define | CLK2_ICLK_DIV_MASK ((uint8_t) 0xE0) |
#define | CLK2_OSR_MASK ((uint8_t) 0x0F) |
#define | CLK2_ICLK_DIV_2 ((uint8_t) 0x20) |
#define | CLK2_ICLK_DIV_4 ((uint8_t) 0x40) |
#define | CLK2_ICLK_DIV_6 ((uint8_t) 0x60) |
#define | CLK2_ICLK_DIV_8 ((uint8_t) 0x80) |
#define | CLK2_ICLK_DIV_10 ((uint8_t) 0xA0) |
#define | CLK2_ICLK_DIV_12 ((uint8_t) 0xC0) |
#define | CLK2_ICLK_DIV_14 ((uint8_t) 0xE0) |
#define | CLK2_OSR_4096 ((uint8_t) 0x00) |
#define | CLK2_OSR_2048 ((uint8_t) 0x01) |
#define | CLK2_OSR_1024 ((uint8_t) 0x02) |
#define | CLK2_OSR_800 ((uint8_t) 0x03) |
#define | CLK2_OSR_768 ((uint8_t) 0x04) |
#define | CLK2_OSR_512 ((uint8_t) 0x05) |
#define | CLK2_OSR_400 ((uint8_t) 0x06) |
#define | CLK2_OSR_384 ((uint8_t) 0x07) |
#define | CLK2_OSR_256 ((uint8_t) 0x08) |
#define | CLK2_OSR_200 ((uint8_t) 0x09) |
#define | CLK2_OSR_192 ((uint8_t) 0x0A) |
#define | CLK2_OSR_128 ((uint8_t) 0x0B) |
#define | CLK2_OSR_96 ((uint8_t) 0x0C) |
#define | CLK2_OSR_64 ((uint8_t) 0x0D) |
#define | CLK2_OSR_48 ((uint8_t) 0x0E) |
#define | CLK2_OSR_32 ((uint8_t) 0x0F) |
#define | ADC_ENA_ADDRESS ((uint8_t) 0x0F) |
#define | ADC_ENA_DEFAULT ((uint8_t) 0x00) |
#define | ADC_ENA_ENA_MASK ((uint8_t) 0x0F) |
#define | ADC_ENA_ENA_ALL_CH_PWDN ((uint8_t) 0x00) |
#define | ADC_ENA_ENA_ALL_CH_PWUP ((uint8_t) 0x0F) |
#define | ADC1_ADDRESS ((uint8_t) 0x11) |
#define | ADC1_DEFAULT ((uint8_t) 0x00) |
#define | ADC1_GAIN1_MASK ((uint8_t) 0x07) |
#define | ADC1_GAIN1_1 ((uint8_t) 0x00) |
#define | ADC1_GAIN1_2 ((uint8_t) 0x01) |
#define | ADC1_GAIN1_4 ((uint8_t) 0x02) |
#define | ADC1_GAIN1_8 ((uint8_t) 0x03) |
#define | ADC1_GAIN1_16 ((uint8_t) 0x04) |
#define | ADC2_ADDRESS ((uint8_t) 0x12) |
#define | ADC2_DEFAULT ((uint8_t) 0x00) |
#define | ADC2_GAIN2_MASK ((uint8_t) 0x07) |
#define | ADC2_GAIN2_1 ((uint8_t) 0x00) |
#define | ADC2_GAIN2_2 ((uint8_t) 0x01) |
#define | ADC2_GAIN2_4 ((uint8_t) 0x02) |
#define | ADC2_GAIN2_8 ((uint8_t) 0x03) |
#define | ADC2_GAIN2_16 ((uint8_t) 0x04) |
#define | ADC3_ADDRESS ((uint8_t) 0x13) |
#define | ADC3_DEFAULT ((uint8_t) 0x00) |
#define | ADC3_GAIN3_MASK ((uint8_t) 0x07) |
#define | ADC3_GAIN3_1 ((uint8_t) 0x00) |
#define | ADC3_GAIN3_2 ((uint8_t) 0x01) |
#define | ADC3_GAIN3_4 ((uint8_t) 0x02) |
#define | ADC3_GAIN3_8 ((uint8_t) 0x03) |
#define | ADC3_GAIN3_16 ((uint8_t) 0x04) |
#define | ADC4_ADDRESS ((uint8_t) 0x14) |
#define | ADC4_DEFAULT ((uint8_t) 0x00) |
#define | ADC4_GAIN4_MASK ((uint8_t) 0x07) |
#define | ADC4_GAIN4_1 ((uint8_t) 0x00) |
#define | ADC4_GAIN4_2 ((uint8_t) 0x01) |
#define | ADC4_GAIN4_4 ((uint8_t) 0x02) |
#define | ADC4_GAIN4_8 ((uint8_t) 0x03) |
#define | ADC4_GAIN4_16 ((uint8_t) 0x04) |
#define | CRC_EN ((bool) (getRegisterValue(D_SYS_CFG_ADDRESS) & D_SYS_CFG_CRC_EN_MASK)) |
#define | CRC_MODE ((bool) (getRegisterValue(D_SYS_CFG_ADDRESS) & D_SYS_CFG_CRC_MODE_MASK)) |
#define | FIXED ((bool) (getRegisterValue(D_SYS_CFG_ADDRESS) & D_SYS_CFG_FIXED_MASK)) |
Functions | |
uint8_t | getRegisterValue (uint8_t address) |
void | adcStartup (void) |
uint8_t | readSingleRegister (uint8_t address) |
void | writeSingleRegister (uint8_t address, uint8_t data) |
bool | readData (adc_data_struct *dataStruct) |
uint16_t | sendCommand (uint16_t opcode) |
bool | lockRegisters (void) |
bool | unlockRegisters (void) |
uint16_t | calculateCRC (const uint8_t dataBytes[], uint8_t numberBytes, uint16_t initialValue) |
void | restoreRegisterDefaults (void) |
int32_t | signExtend (const uint8_t dataBytes[]) |
#define A_SYS_CFG_ADDRESS ((uint8_t) 0x0B) |
#define A_SYS_CFG_COMP_TH_HIGH_70_LOW_30 ((uint8_t) 0x07) |
#define A_SYS_CFG_COMP_TH_HIGH_75_LOW_25 ((uint8_t) 0x06) |
#define A_SYS_CFG_COMP_TH_HIGH_80_LOW_20 ((uint8_t) 0x05) |
#define A_SYS_CFG_COMP_TH_HIGH_85_LOW_15 ((uint8_t) 0x04) |
#define A_SYS_CFG_COMP_TH_HIGH_87p5_LOW_12p5 ((uint8_t) 0x03) |
#define A_SYS_CFG_COMP_TH_HIGH_90_LOW_10 ((uint8_t) 0x02) |
#define A_SYS_CFG_COMP_TH_HIGH_92p5_LOW_7p5 ((uint8_t) 0x01) |
#define A_SYS_CFG_COMP_TH_HIGH_95_LOW_5 ((uint8_t) 0x00) |
#define A_SYS_CFG_COMP_TH_MASK ((uint8_t) 0x07) |
#define A_SYS_CFG_DEFAULT ((uint8_t) 0x60) |
#define A_SYS_CFG_HRM_MASK ((uint8_t) 0x40) |
#define A_SYS_CFG_INT_REFEN_MASK ((uint8_t) 0x08) |
#define A_SYS_CFG_VNCPEN_MASK ((uint8_t) 0x80) |
#define A_SYS_CFG_VREF_4V_MASK ((uint8_t) 0x10) |
#define ADC1_ADDRESS ((uint8_t) 0x11) |
#define ADC1_DEFAULT ((uint8_t) 0x00) |
#define ADC1_GAIN1_1 ((uint8_t) 0x00) |
#define ADC1_GAIN1_16 ((uint8_t) 0x04) |
#define ADC1_GAIN1_2 ((uint8_t) 0x01) |
#define ADC1_GAIN1_4 ((uint8_t) 0x02) |
#define ADC1_GAIN1_8 ((uint8_t) 0x03) |
#define ADC1_GAIN1_MASK ((uint8_t) 0x07) |
#define ADC2_ADDRESS ((uint8_t) 0x12) |
#define ADC2_DEFAULT ((uint8_t) 0x00) |
#define ADC2_GAIN2_1 ((uint8_t) 0x00) |
#define ADC2_GAIN2_16 ((uint8_t) 0x04) |
#define ADC2_GAIN2_2 ((uint8_t) 0x01) |
#define ADC2_GAIN2_4 ((uint8_t) 0x02) |
#define ADC2_GAIN2_8 ((uint8_t) 0x03) |
#define ADC2_GAIN2_MASK ((uint8_t) 0x07) |
#define ADC3_ADDRESS ((uint8_t) 0x13) |
#define ADC3_DEFAULT ((uint8_t) 0x00) |
#define ADC3_GAIN3_1 ((uint8_t) 0x00) |
#define ADC3_GAIN3_16 ((uint8_t) 0x04) |
#define ADC3_GAIN3_2 ((uint8_t) 0x01) |
#define ADC3_GAIN3_4 ((uint8_t) 0x02) |
#define ADC3_GAIN3_8 ((uint8_t) 0x03) |
#define ADC3_GAIN3_MASK ((uint8_t) 0x07) |
#define ADC4_ADDRESS ((uint8_t) 0x14) |
#define ADC4_DEFAULT ((uint8_t) 0x00) |
#define ADC4_GAIN4_1 ((uint8_t) 0x00) |
#define ADC4_GAIN4_16 ((uint8_t) 0x04) |
#define ADC4_GAIN4_2 ((uint8_t) 0x01) |
#define ADC4_GAIN4_4 ((uint8_t) 0x02) |
#define ADC4_GAIN4_8 ((uint8_t) 0x03) |
#define ADC4_GAIN4_MASK ((uint8_t) 0x07) |
#define ADC_ENA_ADDRESS ((uint8_t) 0x0F) |
#define ADC_ENA_DEFAULT ((uint8_t) 0x00) |
#define ADC_ENA_ENA_ALL_CH_PWDN ((uint8_t) 0x00) |
#define ADC_ENA_ENA_ALL_CH_PWUP ((uint8_t) 0x0F) |
#define ADC_ENA_ENA_MASK ((uint8_t) 0x0F) |
#define ASYNC_SLAVE_MODE |
#define CLK1_ADDRESS ((uint8_t) 0x0D) |
#define CLK1_CLK_DIV_10 ((uint8_t) 0x0A) |
#define CLK1_CLK_DIV_12 ((uint8_t) 0x0C) |
#define CLK1_CLK_DIV_14 ((uint8_t) 0x0E) |
#define CLK1_CLK_DIV_2 ((uint8_t) 0x02) |
#define CLK1_CLK_DIV_4 ((uint8_t) 0x04) |
#define CLK1_CLK_DIV_6 ((uint8_t) 0x06) |
#define CLK1_CLK_DIV_8 ((uint8_t) 0x08) |
#define CLK1_CLK_DIV_MASK ((uint8_t) 0x0E) |
#define CLK1_CLKSRC_MASK ((uint8_t) 0x80) |
#define CLK1_DEFAULT ((uint8_t) 0x08) |
#define CLK2_ADDRESS ((uint8_t) 0x0E) |
#define CLK2_DEFAULT ((uint8_t) 0x86) |
#define CLK2_ICLK_DIV_10 ((uint8_t) 0xA0) |
#define CLK2_ICLK_DIV_12 ((uint8_t) 0xC0) |
#define CLK2_ICLK_DIV_14 ((uint8_t) 0xE0) |
#define CLK2_ICLK_DIV_2 ((uint8_t) 0x20) |
#define CLK2_ICLK_DIV_4 ((uint8_t) 0x40) |
#define CLK2_ICLK_DIV_6 ((uint8_t) 0x60) |
#define CLK2_ICLK_DIV_8 ((uint8_t) 0x80) |
#define CLK2_ICLK_DIV_MASK ((uint8_t) 0xE0) |
#define CLK2_OSR_1024 ((uint8_t) 0x02) |
#define CLK2_OSR_128 ((uint8_t) 0x0B) |
#define CLK2_OSR_192 ((uint8_t) 0x0A) |
#define CLK2_OSR_200 ((uint8_t) 0x09) |
#define CLK2_OSR_2048 ((uint8_t) 0x01) |
#define CLK2_OSR_256 ((uint8_t) 0x08) |
#define CLK2_OSR_32 ((uint8_t) 0x0F) |
#define CLK2_OSR_384 ((uint8_t) 0x07) |
#define CLK2_OSR_400 ((uint8_t) 0x06) |
#define CLK2_OSR_4096 ((uint8_t) 0x00) |
#define CLK2_OSR_48 ((uint8_t) 0x0E) |
#define CLK2_OSR_512 ((uint8_t) 0x05) |
#define CLK2_OSR_64 ((uint8_t) 0x0D) |
#define CLK2_OSR_768 ((uint8_t) 0x04) |
#define CLK2_OSR_800 ((uint8_t) 0x03) |
#define CLK2_OSR_96 ((uint8_t) 0x0C) |
#define CLK2_OSR_MASK ((uint8_t) 0x0F) |
#define CRC_EN ((bool) (getRegisterValue(D_SYS_CFG_ADDRESS) & D_SYS_CFG_CRC_EN_MASK)) |
#define CRC_MODE ((bool) (getRegisterValue(D_SYS_CFG_ADDRESS) & D_SYS_CFG_CRC_MODE_MASK)) |
#define D_SYS_CFG_ADDRESS ((uint8_t) 0x0C) |
#define D_SYS_CFG_CRC_EN_MASK ((uint8_t) 0x01) |
#define D_SYS_CFG_CRC_MODE_MASK ((uint8_t) 0x40) |
#define D_SYS_CFG_DEFAULT ((uint8_t) 0x3C) |
#define D_SYS_CFG_DNDLY_10ns ((uint8_t) 0x20) |
#define D_SYS_CFG_DNDLY_12ns ((uint8_t) 0x30) |
#define D_SYS_CFG_DNDLY_6ns ((uint8_t) 0x00) |
#define D_SYS_CFG_DNDLY_8ns ((uint8_t) 0x10) |
#define D_SYS_CFG_DNDLY_MASK ((uint8_t) 0x30) |
#define D_SYS_CFG_FIXED_MASK ((uint8_t) 0x02) |
#define D_SYS_CFG_HIZDLY_10ns ((uint8_t) 0x08) |
#define D_SYS_CFG_HIZDLY_12ns ((uint8_t) 0x0C) |
#define D_SYS_CFG_HIZDLY_6ns ((uint8_t) 0x00) |
#define D_SYS_CFG_HIZDLY_8ns ((uint8_t) 0x04) |
#define D_SYS_CFG_HIZDLY_MASK ((uint8_t) 0x0C) |
#define D_SYS_CFG_WDT_EN_MASK ((uint8_t) 0x80) |
#define ERROR_CNT_ADDRESS ((uint8_t) 0x06) |
#define ERROR_CNT_DEFAULT ((uint8_t) 0x00) |
#define ERROR_CNT_ER_MASK ((uint8_t) 0xFF) |
#define FIXED ((bool) (getRegisterValue(D_SYS_CFG_ADDRESS) & D_SYS_CFG_FIXED_MASK)) |
#define ID_LSB_ADDRESS ((uint8_t) 0x01) |
#define ID_LSB_REV_ID_MASK ((uint8_t) 0xFF) |
#define ID_MSB_ADDRESS ((uint8_t) 0x00) |
#define ID_MSB_NU_CH_2 ((uint8_t) 0x02) |
#define ID_MSB_NU_CH_4 ((uint8_t) 0x04) |
#define ID_MSB_NU_CH_MASK ((uint8_t) 0xFF) |
#define NUM_REGISTERS ((uint8_t) 21) |
#define OPCODE_LOCK ((uint16_t) 0x0555) |
#define OPCODE_NULL ((uint16_t) 0x0000) |
#define OPCODE_RESET ((uint16_t) 0x0011) |
#define OPCODE_RREG ((uint16_t) 0x2000) |
#define OPCODE_STANDBY ((uint16_t) 0x0022) |
#define OPCODE_UNLOCK ((uint16_t) 0x0655) |
#define OPCODE_WAKEUP ((uint16_t) 0x0033) |
#define OPCODE_WREG ((uint16_t) 0x4000) |
#define SET_FIXED |
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#define STAT_1_ADDRESS ((uint8_t) 0x02) |
#define STAT_1_DEFAULT ((uint8_t) 0x00) |
#define STAT_1_F_ADCIN_MASK ((uint8_t) 0x10) |
#define STAT_1_F_CHECK_MASK ((uint8_t) 0x01) |
#define STAT_1_F_DRDY_MASK ((uint8_t) 0x02) |
#define STAT_1_F_OPC_MASK ((uint8_t) 0x40) |
#define STAT_1_F_RESYNC_MASK ((uint8_t) 0x04) |
#define STAT_1_F_SPI_MASK ((uint8_t) 0x20) |
#define STAT_1_F_WDT_MASK ((uint8_t) 0x08) |
#define STAT_M2_ADDRESS ((uint8_t) 0x07) |
#define STAT_M2_DEFAULT ((uint8_t) 0x00) |
#define STAT_M2_DEFAULT_MASK ((uint8_t) 0xC0) |
#define STAT_M2_M0PIN_M0_ASYNC_SLAVE ((uint8_t) 0x01) |
#define STAT_M2_M0PIN_M0_SYNC_MASTER ((uint8_t) 0x00) |
#define STAT_M2_M0PIN_M0_SYNC_SLAVE ((uint8_t) 0x02) |
#define STAT_M2_M0PIN_MASK ((uint8_t) 0x03) |
#define STAT_M2_M1PIN_M1_16BIT ((uint8_t) 0x08) |
#define STAT_M2_M1PIN_M1_24BIT ((uint8_t) 0x00) |
#define STAT_M2_M1PIN_M1_32BIT ((uint8_t) 0x04) |
#define STAT_M2_M1PIN_MASK ((uint8_t) 0x0C) |
#define STAT_M2_M2PIN_M2_HAMMING_OFF ((uint8_t) 0x00) |
#define STAT_M2_M2PIN_M2_HAMMING_ON ((uint8_t) 0x10) |
#define STAT_M2_M2PIN_M2_NC ((uint8_t) 0x20) |
#define STAT_M2_M2PIN_MASK ((uint8_t) 0x30) |
#define STAT_N_ADDRESS ((uint8_t) 0x04) |
#define STAT_N_DEFAULT ((uint8_t) 0x00) |
#define STAT_N_F_IN1N_MASK ((uint8_t) 0x01) |
#define STAT_N_F_IN2N_MASK ((uint8_t) 0x02) |
#define STAT_N_F_IN3N_MASK ((uint8_t) 0x04) |
#define STAT_N_F_IN4N_MASK ((uint8_t) 0x08) |
#define STAT_P_ADDRESS ((uint8_t) 0x03) |
#define STAT_P_DEFAULT ((uint8_t) 0x00) |
#define STAT_P_F_IN1P_MASK ((uint8_t) 0x01) |
#define STAT_P_F_IN2P_MASK ((uint8_t) 0x02) |
#define STAT_P_F_IN3P_MASK ((uint8_t) 0x04) |
#define STAT_P_F_IN4P_MASK ((uint8_t) 0x08) |
#define STAT_S_ADDRESS ((uint8_t) 0x05) |
#define STAT_S_DEFAULT ((uint8_t) 0x00) |
#define STAT_S_F_CS_MASK ((uint8_t) 0x02) |
#define STAT_S_F_FRAME_MASK ((uint8_t) 0x01) |
#define STAT_S_F_STARTUP_MASK ((uint8_t) 0x04) |
#define WORD_LENGTH_24BIT |
#define WORD_LENGTH_BITS ((uint8_t) 24) |
void adcStartup | ( | void | ) |
Example start up sequence for the ADS131A04.
Before calling this function, the device must be powered, the SPI/GPIO pins of the MCU must have already been configured, and (if applicable) the external clock source should be provided to CLKIN.
NOTE: You may want to modify this function to configure the ADC's initial register settings to your application's requirements.
uint16_t calculateCRC | ( | const uint8_t | dataBytes[], |
uint8_t | numberBytes, | ||
uint16_t | initialValue | ||
) |
Calculates the 16-bit CRC for the selected CRC polynomial.
dataBytes[] | pointer to first element in the data byte array |
numberBytes | length of data byte array to include in the CRC calculation |
initialValue | the seed value (or partial crc calculation), use 0xFFFF when beginning a new CRC computation |
NOTE: This calculation is shown as an example and has not been optimized for speed.
uint8_t getRegisterValue | ( | uint8_t | address | ) |
Getter function to access registerMap array from outside of this module.
NOTE: The internal registerMap arrays stores the last known register value, since the last read or write operation to that register. This function does not communicate with the device to retrieve the current register value. For the most up-to-date register data or reading the value of a hardware controlled register, it is recommend to use readSingleRegister() to read the device register.
address | is the 8-bit address of the register value to recall. |
bool lockRegisters | ( | void | ) |
Sends the LOCK command and then verifies that registers are locked.
bool readData | ( | adc_data_struct * | dataStruct | ) |
Read ADC data
dataStruct | pointer to data structure where results from reading data will be placed |
NOTE: This is currently the only function in this example that verifies if the CRC word on DOUT is correct.
uint8_t readSingleRegister | ( | uint8_t | address | ) |
Reads the contents of a single register at the specified address.
address | is the 8-bit address of the register to read. |
void restoreRegisterDefaults | ( | void | ) |
Updates the registerMap[] array to its default values.
NOTES:
uint16_t sendCommand | ( | uint16_t | opcode | ) |
Sends the specified SPI command to the ADC (NULL, RESET, STANDBY, or WAKEUP).
opcode | 16-bit SPI command. |
NOTE: Other ADC commands have their own dedicated functions to support additional functionality. This function will raise an assert if used with one of these commands (RREG, WREG, WREGS, LOCK,or UNLOCK).
int32_t signExtend | ( | const uint8_t | dataBytes[] | ) |
Internal function used by readData() to convert ADC data from multiple unsigned bytes into a single signed 32-bit word.
dataBytes | is a pointer to uint8_t[] where the first element is the MSB. |
bool unlockRegisters | ( | void | ) |
Sends the UNLOCK command and then verifies that registers are unlocked
void writeSingleRegister | ( | uint8_t | address, |
uint8_t | data | ||
) |
Writes data to a single register.
This command will be ignored if device registers are locked.
NOTE: This functions also performs a NULL command frame after the register write command to verify the new register value.
address | is the address of the register to write to. |
data | is the value to write. |