ADS131A04 Example C Code  1.0.0
ads131a04.h
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1 
35 #ifndef ADS131A04_H_
36 #define ADS131A04_H_
37 
38 
39 // Standard libraries
40 #include <assert.h>
41 #include <stdint.h>
42 #include <stdbool.h>
43 
44 // Custom libraries
45 #include "hal.h"
46 
47 
48 //
49 // Configure Register settings - NOTE: These values can be change, but FIXED mode is recommended!
50 //
51 
52  // Fixed SPI Frame Mode - NOTE: Dynamic frame mode requires additional logic
53  // (not provided in this example code) to prevent the F_SPI error flag.
54  #define SET_FIXED
55 
56  // CRC Enable - NOTE: In this example enabling CRC will increase the amount
57  // of time it takes the MCU to construct and send an SPI frame!
58  //#define SET_CRC_EN
59 
60  // CRC Mode - Selects which SPI words get included in the CRC computation
61  //#define SET_CRC_MODE
62 
63 
64 //
65 // Pin settings - NOTE: These values are NOT configurable in this example!
66 // This example code is only targeted at asynchronous slave mode with hamming validation turned off.
67 //
68 
69  // M0 -> Tied to IOVDD
70  #define ASYNC_SLAVE_MODE
71 
72  // M1 -> Tied to GND
73  #define WORD_LENGTH_BITS ((uint8_t) 24)
74  #define WORD_LENGTH_24BIT
75  //#define WORD_LENGTH_16BIT
76  //#define WORD_LENGTH_32BIT
77 
78  // M2 -> Tied to GND
79  //#define HAMMING_ENABLED
80 
81 
82 //****************************************************************************
83 //
84 // Channel data structure
85 //
86 //****************************************************************************
87 
88 typedef struct
89 {
90  int32_t channel1;
91  int32_t channel2;
92  int32_t channel3;
93  int32_t channel4;
94  uint16_t response;
95  uint16_t crc;
96 
98 
99 
100 
101 //**********************************************************************************
102 //
103 // Function prototypes
104 //
105 //**********************************************************************************
106 
107 uint8_t getRegisterValue(uint8_t address);
108 void adcStartup(void);
109 uint8_t readSingleRegister(uint8_t address);
110 void writeSingleRegister(uint8_t address, uint8_t data);
111 bool readData(adc_data_struct *dataStruct);
112 uint16_t sendCommand(uint16_t opcode);
113 bool lockRegisters(void);
114 bool unlockRegisters(void);
115 uint16_t calculateCRC(const uint8_t dataBytes[], uint8_t numberBytes, uint16_t initialValue);
116 
117 // Helper functions
118 void restoreRegisterDefaults(void);
119 int32_t signExtend(const uint8_t dataBytes[]);
120 
121 
122 
123 //**********************************************************************************
124 //
125 // Device commands
126 //
127 //**********************************************************************************
128 
129 #define OPCODE_NULL ((uint16_t) 0x0000)
130 #define OPCODE_RESET ((uint16_t) 0x0011)
131 #define OPCODE_STANDBY ((uint16_t) 0x0022)
132 #define OPCODE_WAKEUP ((uint16_t) 0x0033)
133 #define OPCODE_LOCK ((uint16_t) 0x0555)
134 #define OPCODE_UNLOCK ((uint16_t) 0x0655)
135 #define OPCODE_RREG ((uint16_t) 0x2000)
136 #define OPCODE_WREG ((uint16_t) 0x4000)
137 
138 // NOTE: The following command(s) are not implemented in this example...
139 //#define OPCODE_WREGS ((uint16_t) 0x6000)
140 
141 
142 
143 //**********************************************************************************
144 //
145 // Register definitions
146 //
147 //**********************************************************************************
148 
149 #define NUM_REGISTERS ((uint8_t) 21)
150 
151 
152 /* Register 0x00 (ID_MSB) definition
153  * -------------------------------------------------------------------------------------------------
154  * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
155  * -------------------------------------------------------------------------------------------------
156  * | NU_CH[7:0] |
157  * -------------------------------------------------------------------------------------------------
158  */
159 
160  /* ID_MSB register address */
161  #define ID_MSB_ADDRESS ((uint8_t) 0x00)
162 
163  /* ID_MSB register field masks */
164  #define ID_MSB_NU_CH_MASK ((uint8_t) 0xFF)
165 
166  /* NU_CH field values */
167  #define ID_MSB_NU_CH_2 ((uint8_t) 0x02)
168  #define ID_MSB_NU_CH_4 ((uint8_t) 0x04)
169 
170 
171 
172 /* Register 0x01 (ID_LSB) definition
173  * -------------------------------------------------------------------------------------------------
174  * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
175  * -------------------------------------------------------------------------------------------------
176  * | REV_ID[7:0] |
177  * -------------------------------------------------------------------------------------------------
178  */
179 
180  /* ID_LSB register address */
181  #define ID_LSB_ADDRESS ((uint8_t) 0x01)
182 
183  /* ID_LSB register field masks */
184  #define ID_LSB_REV_ID_MASK ((uint8_t) 0xFF)
185 
186 
187 
188 /* Register 0x02 (STAT_1) definition
189  * -------------------------------------------------------------------------------------------------
190  * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
191  * -------------------------------------------------------------------------------------------------
192  * | 0 | F_OPC | F_SPI | F_ADCIN | F_WDT | F_RESYNC | F_DRDY | F_CHECK |
193  * -------------------------------------------------------------------------------------------------
194  */
195 
196  /* STAT_1 register address */
197  #define STAT_1_ADDRESS ((uint8_t) 0x02)
198 
199  /* STAT_1 default (reset) value */
200  #define STAT_1_DEFAULT ((uint8_t) 0x00)
201 
202  /* STAT_1 register field masks */
203  #define STAT_1_F_OPC_MASK ((uint8_t) 0x40)
204  #define STAT_1_F_SPI_MASK ((uint8_t) 0x20)
205  #define STAT_1_F_ADCIN_MASK ((uint8_t) 0x10)
206  #define STAT_1_F_WDT_MASK ((uint8_t) 0x08)
207  #define STAT_1_F_RESYNC_MASK ((uint8_t) 0x04)
208  #define STAT_1_F_DRDY_MASK ((uint8_t) 0x02)
209  #define STAT_1_F_CHECK_MASK ((uint8_t) 0x01)
210 
211 
212 
213 /* Register 0x03 (STAT_P) definition
214  * -------------------------------------------------------------------------------------------------
215  * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
216  * -------------------------------------------------------------------------------------------------
217  * | 0 | 0 | 0 | 0 | F_IN4P | F_IN3P | F_IN2P | F_IN1P |
218  * -------------------------------------------------------------------------------------------------
219  */
220 
221  /* STAT_P register address */
222  #define STAT_P_ADDRESS ((uint8_t) 0x03)
223 
224  /* STAT_P default (reset) value */
225  #define STAT_P_DEFAULT ((uint8_t) 0x00)
226 
227  /* STAT_P register field masks */
228  #define STAT_P_F_IN4P_MASK ((uint8_t) 0x08)
229  #define STAT_P_F_IN3P_MASK ((uint8_t) 0x04)
230  #define STAT_P_F_IN2P_MASK ((uint8_t) 0x02)
231  #define STAT_P_F_IN1P_MASK ((uint8_t) 0x01)
232 
233 
234 
235 /* Register 0x04 (STAT_N) definition
236  * -------------------------------------------------------------------------------------------------
237  * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
238  * -------------------------------------------------------------------------------------------------
239  * | 0 | 0 | 0 | 0 | F_IN4N | F_IN3N | F_IN2N | F_IN1N |
240  * -------------------------------------------------------------------------------------------------
241  */
242 
243  /* STAT_N register address */
244  #define STAT_N_ADDRESS ((uint8_t) 0x04)
245 
246  /* STAT_N default (reset) value */
247  #define STAT_N_DEFAULT ((uint8_t) 0x00)
248 
249  /* STAT_N register field masks */
250  #define STAT_N_F_IN4N_MASK ((uint8_t) 0x08)
251  #define STAT_N_F_IN3N_MASK ((uint8_t) 0x04)
252  #define STAT_N_F_IN2N_MASK ((uint8_t) 0x02)
253  #define STAT_N_F_IN1N_MASK ((uint8_t) 0x01)
254 
255 
256 
257 /* Register 0x05 (STAT_S) definition
258  * -------------------------------------------------------------------------------------------------
259  * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
260  * -------------------------------------------------------------------------------------------------
261  * | 0 | 0 | 0 | 0 | 0 | F_STARTUP | F_CS | F_FRAME |
262  * -------------------------------------------------------------------------------------------------
263  */
264 
265  /* STAT_S register address */
266  #define STAT_S_ADDRESS ((uint8_t) 0x05)
267 
268  /* STAT_S default (reset) value */
269  #define STAT_S_DEFAULT ((uint8_t) 0x00)
270 
271  /* STAT_S register field masks */
272  #define STAT_S_F_STARTUP_MASK ((uint8_t) 0x04)
273  #define STAT_S_F_CS_MASK ((uint8_t) 0x02)
274  #define STAT_S_F_FRAME_MASK ((uint8_t) 0x01)
275 
276 
277 
278 /* Register 0x06 (ERROR_CNT) definition
279  * -------------------------------------------------------------------------------------------------
280  * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
281  * -------------------------------------------------------------------------------------------------
282  * | ER[7:0] |
283  * -------------------------------------------------------------------------------------------------
284  */
285 
286  /* ERROR_CNT register address */
287  #define ERROR_CNT_ADDRESS ((uint8_t) 0x06)
288 
289  /* ERROR_CNT default (reset) value */
290  #define ERROR_CNT_DEFAULT ((uint8_t) 0x00)
291 
292  /* ERROR_CNT register field masks */
293  #define ERROR_CNT_ER_MASK ((uint8_t) 0xFF)
294 
295 
296 
297 /* Register 0x07 (STAT_M2) definition
298  * -------------------------------------------------------------------------------------------------
299  * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
300  * -------------------------------------------------------------------------------------------------
301  * | 0 | 0 | M2PIN[1:0] | M1PIN[1:0] | M0PIN[1:0] |
302  * -------------------------------------------------------------------------------------------------
303  */
304 
305  /* STAT_M2 register address */
306  #define STAT_M2_ADDRESS ((uint8_t) 0x07)
307 
308  /* STAT_M2 default (reset) value */
309  #define STAT_M2_DEFAULT ((uint8_t) 0x00)
310  #define STAT_M2_DEFAULT_MASK ((uint8_t) 0xC0)
311 
312  /* STAT_M2 register field masks */
313  #define STAT_M2_M2PIN_MASK ((uint8_t) 0x30)
314  #define STAT_M2_M1PIN_MASK ((uint8_t) 0x0C)
315  #define STAT_M2_M0PIN_MASK ((uint8_t) 0x03)
316 
317  /* M2PIN field values */
318  #define STAT_M2_M2PIN_M2_HAMMING_OFF ((uint8_t) 0x00)
319  #define STAT_M2_M2PIN_M2_HAMMING_ON ((uint8_t) 0x10)
320  #define STAT_M2_M2PIN_M2_NC ((uint8_t) 0x20)
321 
322  /* M1PIN field values */
323  #define STAT_M2_M1PIN_M1_24BIT ((uint8_t) 0x00)
324  #define STAT_M2_M1PIN_M1_32BIT ((uint8_t) 0x04)
325  #define STAT_M2_M1PIN_M1_16BIT ((uint8_t) 0x08)
326 
327  /* M0PIN field values */
328  #define STAT_M2_M0PIN_M0_SYNC_MASTER ((uint8_t) 0x00)
329  #define STAT_M2_M0PIN_M0_ASYNC_SLAVE ((uint8_t) 0x01)
330  #define STAT_M2_M0PIN_M0_SYNC_SLAVE ((uint8_t) 0x02)
331 
332 
333 
334 /* Register 0x08 (RESERVED0) definition
335  * -------------------------------------------------------------------------------------------------
336  * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
337  * -------------------------------------------------------------------------------------------------
338  * | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
339  * -------------------------------------------------------------------------------------------------
340  */
341 
342 
343 
344 /* Register 0x09 (RESERVED1) definition
345  * -------------------------------------------------------------------------------------------------
346  * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
347  * -------------------------------------------------------------------------------------------------
348  * | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
349  * -------------------------------------------------------------------------------------------------
350  */
351 
352 
353 
354 /* Register 0x0A (RESERVED2) definition
355  * -------------------------------------------------------------------------------------------------
356  * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
357  * -------------------------------------------------------------------------------------------------
358  * | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
359  * -------------------------------------------------------------------------------------------------
360  */
361 
362 
363 
364 /* Register 0x0B (A_SYS_CFG) definition
365  * -------------------------------------------------------------------------------------------------
366  * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
367  * -------------------------------------------------------------------------------------------------
368  * | VNCPEN | HRM | 0 | VREF_4V | INT_REFEN | COMP_TH[2:0] |
369  * -------------------------------------------------------------------------------------------------
370  */
371 
372  /* A_SYS_CFG register address */
373  #define A_SYS_CFG_ADDRESS ((uint8_t) 0x0B)
374 
375  /* A_SYS_CFG default (reset) value */
376  #define A_SYS_CFG_DEFAULT ((uint8_t) 0x60)
377 
378  /* A_SYS_CFG register field masks */
379  #define A_SYS_CFG_VNCPEN_MASK ((uint8_t) 0x80)
380  #define A_SYS_CFG_HRM_MASK ((uint8_t) 0x40)
381  #define A_SYS_CFG_VREF_4V_MASK ((uint8_t) 0x10)
382  #define A_SYS_CFG_INT_REFEN_MASK ((uint8_t) 0x08)
383  #define A_SYS_CFG_COMP_TH_MASK ((uint8_t) 0x07)
384 
385  /* COMP_TH field values */
386  #define A_SYS_CFG_COMP_TH_HIGH_95_LOW_5 ((uint8_t) 0x00)
387  #define A_SYS_CFG_COMP_TH_HIGH_92p5_LOW_7p5 ((uint8_t) 0x01)
388  #define A_SYS_CFG_COMP_TH_HIGH_90_LOW_10 ((uint8_t) 0x02)
389  #define A_SYS_CFG_COMP_TH_HIGH_87p5_LOW_12p5 ((uint8_t) 0x03)
390  #define A_SYS_CFG_COMP_TH_HIGH_85_LOW_15 ((uint8_t) 0x04)
391  #define A_SYS_CFG_COMP_TH_HIGH_80_LOW_20 ((uint8_t) 0x05)
392  #define A_SYS_CFG_COMP_TH_HIGH_75_LOW_25 ((uint8_t) 0x06)
393  #define A_SYS_CFG_COMP_TH_HIGH_70_LOW_30 ((uint8_t) 0x07)
394 
395 
396 
397 /* Register 0x0C (D_SYS_CFG) definition
398  * -------------------------------------------------------------------------------------------------
399  * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
400  * -------------------------------------------------------------------------------------------------
401  * | WDT_EN | CRC_MODE | DNDLY[1:0] | HIZDLY[1:0] | FIXED | CRC_EN |
402  * -------------------------------------------------------------------------------------------------
403  */
404 
405  /* D_SYS_CFG register address */
406  #define D_SYS_CFG_ADDRESS ((uint8_t) 0x0C)
407 
408  /* D_SYS_CFG default (reset) value */
409  #define D_SYS_CFG_DEFAULT ((uint8_t) 0x3C)
410 
411  /* D_SYS_CFG register field masks */
412  #define D_SYS_CFG_WDT_EN_MASK ((uint8_t) 0x80)
413  #define D_SYS_CFG_CRC_MODE_MASK ((uint8_t) 0x40)
414  #define D_SYS_CFG_DNDLY_MASK ((uint8_t) 0x30)
415  #define D_SYS_CFG_HIZDLY_MASK ((uint8_t) 0x0C)
416  #define D_SYS_CFG_FIXED_MASK ((uint8_t) 0x02)
417  #define D_SYS_CFG_CRC_EN_MASK ((uint8_t) 0x01)
418 
419  /* DNDLY field values */
420  #define D_SYS_CFG_DNDLY_6ns ((uint8_t) 0x00)
421  #define D_SYS_CFG_DNDLY_8ns ((uint8_t) 0x10)
422  #define D_SYS_CFG_DNDLY_10ns ((uint8_t) 0x20)
423  #define D_SYS_CFG_DNDLY_12ns ((uint8_t) 0x30)
424 
425  /* HIZDLY field values */
426  #define D_SYS_CFG_HIZDLY_6ns ((uint8_t) 0x00)
427  #define D_SYS_CFG_HIZDLY_8ns ((uint8_t) 0x04)
428  #define D_SYS_CFG_HIZDLY_10ns ((uint8_t) 0x08)
429  #define D_SYS_CFG_HIZDLY_12ns ((uint8_t) 0x0C)
430 
431 
432 
433 /* Register 0x0D (CLK1) definition
434  * -------------------------------------------------------------------------------------------------
435  * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
436  * -------------------------------------------------------------------------------------------------
437  * | CLKSRC | 0 | 0 | 0 | CLK_DIV[2:0] | 0 |
438  * -------------------------------------------------------------------------------------------------
439  */
440 
441  /* CLK1 register address */
442  #define CLK1_ADDRESS ((uint8_t) 0x0D)
443 
444  /* CLK1 default (reset) value */
445  #define CLK1_DEFAULT ((uint8_t) 0x08)
446 
447  /* CLK1 register field masks */
448  #define CLK1_CLKSRC_MASK ((uint8_t) 0x80)
449  #define CLK1_CLK_DIV_MASK ((uint8_t) 0x0E)
450 
451  /* CLK_DIV field values */
452  #define CLK1_CLK_DIV_2 ((uint8_t) 0x02)
453  #define CLK1_CLK_DIV_4 ((uint8_t) 0x04)
454  #define CLK1_CLK_DIV_6 ((uint8_t) 0x06)
455  #define CLK1_CLK_DIV_8 ((uint8_t) 0x08)
456  #define CLK1_CLK_DIV_10 ((uint8_t) 0x0A)
457  #define CLK1_CLK_DIV_12 ((uint8_t) 0x0C)
458  #define CLK1_CLK_DIV_14 ((uint8_t) 0x0E)
459 
460 
461 
462 /* Register 0x0E (CLK2) definition
463  * -------------------------------------------------------------------------------------------------
464  * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
465  * -------------------------------------------------------------------------------------------------
466  * | ICLK_DIV[2:0] | 0 | OSR[3:0] |
467  * -------------------------------------------------------------------------------------------------
468  */
469 
470  /* CLK2 register address */
471  #define CLK2_ADDRESS ((uint8_t) 0x0E)
472 
473  /* CLK2 default (reset) value */
474  #define CLK2_DEFAULT ((uint8_t) 0x86)
475 
476  /* CLK2 register field masks */
477  #define CLK2_ICLK_DIV_MASK ((uint8_t) 0xE0)
478  #define CLK2_OSR_MASK ((uint8_t) 0x0F)
479 
480  /* ICLK_DIV field values */
481  #define CLK2_ICLK_DIV_2 ((uint8_t) 0x20)
482  #define CLK2_ICLK_DIV_4 ((uint8_t) 0x40)
483  #define CLK2_ICLK_DIV_6 ((uint8_t) 0x60)
484  #define CLK2_ICLK_DIV_8 ((uint8_t) 0x80)
485  #define CLK2_ICLK_DIV_10 ((uint8_t) 0xA0)
486  #define CLK2_ICLK_DIV_12 ((uint8_t) 0xC0)
487  #define CLK2_ICLK_DIV_14 ((uint8_t) 0xE0)
488 
489  /* OSR field values */
490  #define CLK2_OSR_4096 ((uint8_t) 0x00)
491  #define CLK2_OSR_2048 ((uint8_t) 0x01)
492  #define CLK2_OSR_1024 ((uint8_t) 0x02)
493  #define CLK2_OSR_800 ((uint8_t) 0x03)
494  #define CLK2_OSR_768 ((uint8_t) 0x04)
495  #define CLK2_OSR_512 ((uint8_t) 0x05)
496  #define CLK2_OSR_400 ((uint8_t) 0x06)
497  #define CLK2_OSR_384 ((uint8_t) 0x07)
498  #define CLK2_OSR_256 ((uint8_t) 0x08)
499  #define CLK2_OSR_200 ((uint8_t) 0x09)
500  #define CLK2_OSR_192 ((uint8_t) 0x0A)
501  #define CLK2_OSR_128 ((uint8_t) 0x0B)
502  #define CLK2_OSR_96 ((uint8_t) 0x0C)
503  #define CLK2_OSR_64 ((uint8_t) 0x0D)
504  #define CLK2_OSR_48 ((uint8_t) 0x0E)
505  #define CLK2_OSR_32 ((uint8_t) 0x0F)
506 
507 
508 
509 /* Register 0x0F (ADC_ENA) definition
510  * -------------------------------------------------------------------------------------------------
511  * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
512  * -------------------------------------------------------------------------------------------------
513  * | 0 | 0 | 0 | 0 | ENA[3:0] |
514  * -------------------------------------------------------------------------------------------------
515  */
516 
517  /* ADC_ENA register address */
518  #define ADC_ENA_ADDRESS ((uint8_t) 0x0F)
519 
520  /* ADC_ENA default (reset) value */
521  #define ADC_ENA_DEFAULT ((uint8_t) 0x00)
522 
523  /* ADC_ENA register field masks */
524  #define ADC_ENA_ENA_MASK ((uint8_t) 0x0F)
525 
526  /* ENA field values */
527  #define ADC_ENA_ENA_ALL_CH_PWDN ((uint8_t) 0x00)
528  #define ADC_ENA_ENA_ALL_CH_PWUP ((uint8_t) 0x0F)
529 
530 
531 
532 /* Register 0x10 (RESERVED3) definition
533  * -------------------------------------------------------------------------------------------------
534  * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
535  * -------------------------------------------------------------------------------------------------
536  * | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
537  * -------------------------------------------------------------------------------------------------
538  */
539 
540 
541 
542 /* Register 0x11 (ADC1) definition
543  * -------------------------------------------------------------------------------------------------
544  * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
545  * -------------------------------------------------------------------------------------------------
546  * | 0 | 0 | 0 | 0 | 0 | GAIN1[2:0] |
547  * -------------------------------------------------------------------------------------------------
548  */
549 
550  /* ADC1 register address */
551  #define ADC1_ADDRESS ((uint8_t) 0x11)
552 
553  /* ADC1 default (reset) value */
554  #define ADC1_DEFAULT ((uint8_t) 0x00)
555 
556  /* ADC1 register field masks */
557  #define ADC1_GAIN1_MASK ((uint8_t) 0x07)
558 
559  /* GAIN1 field values */
560  #define ADC1_GAIN1_1 ((uint8_t) 0x00)
561  #define ADC1_GAIN1_2 ((uint8_t) 0x01)
562  #define ADC1_GAIN1_4 ((uint8_t) 0x02)
563  #define ADC1_GAIN1_8 ((uint8_t) 0x03)
564  #define ADC1_GAIN1_16 ((uint8_t) 0x04)
565 
566 
567 
568 /* Register 0x12 (ADC2) definition
569  * -------------------------------------------------------------------------------------------------
570  * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
571  * -------------------------------------------------------------------------------------------------
572  * | 0 | 0 | 0 | 0 | 0 | GAIN2[2:0] |
573  * -------------------------------------------------------------------------------------------------
574  */
575 
576  /* ADC2 register address */
577  #define ADC2_ADDRESS ((uint8_t) 0x12)
578 
579  /* ADC2 default (reset) value */
580  #define ADC2_DEFAULT ((uint8_t) 0x00)
581 
582  /* ADC2 register field masks */
583  #define ADC2_GAIN2_MASK ((uint8_t) 0x07)
584 
585  /* GAIN2 field values */
586  #define ADC2_GAIN2_1 ((uint8_t) 0x00)
587  #define ADC2_GAIN2_2 ((uint8_t) 0x01)
588  #define ADC2_GAIN2_4 ((uint8_t) 0x02)
589  #define ADC2_GAIN2_8 ((uint8_t) 0x03)
590  #define ADC2_GAIN2_16 ((uint8_t) 0x04)
591 
592 
593 
594 /* Register 0x13 (ADC3) definition
595  * -------------------------------------------------------------------------------------------------
596  * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
597  * -------------------------------------------------------------------------------------------------
598  * | 0 | 0 | 0 | 0 | 0 | GAIN3[2:0] |
599  * -------------------------------------------------------------------------------------------------
600  */
601 
602  /* ADC3 register address */
603  #define ADC3_ADDRESS ((uint8_t) 0x13)
604 
605  /* ADC3 default (reset) value */
606  #define ADC3_DEFAULT ((uint8_t) 0x00)
607 
608  /* ADC3 register field masks */
609  #define ADC3_GAIN3_MASK ((uint8_t) 0x07)
610 
611  /* GAIN3 field values */
612  #define ADC3_GAIN3_1 ((uint8_t) 0x00)
613  #define ADC3_GAIN3_2 ((uint8_t) 0x01)
614  #define ADC3_GAIN3_4 ((uint8_t) 0x02)
615  #define ADC3_GAIN3_8 ((uint8_t) 0x03)
616  #define ADC3_GAIN3_16 ((uint8_t) 0x04)
617 
618 
619 
620 /* Register 0x14 (ADC4) definition
621  * -------------------------------------------------------------------------------------------------
622  * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
623  * -------------------------------------------------------------------------------------------------
624  * | 0 | 0 | 0 | 0 | 0 | GAIN4[2:0] |
625  * -------------------------------------------------------------------------------------------------
626  */
627 
628  /* ADC4 register address */
629  #define ADC4_ADDRESS ((uint8_t) 0x14)
630 
631  /* ADC4 default (reset) value */
632  #define ADC4_DEFAULT ((uint8_t) 0x00)
633 
634  /* ADC4 register field masks */
635  #define ADC4_GAIN4_MASK ((uint8_t) 0x07)
636 
637  /* GAIN4 field values */
638  #define ADC4_GAIN4_1 ((uint8_t) 0x00)
639  #define ADC4_GAIN4_2 ((uint8_t) 0x01)
640  #define ADC4_GAIN4_4 ((uint8_t) 0x02)
641  #define ADC4_GAIN4_8 ((uint8_t) 0x03)
642  #define ADC4_GAIN4_16 ((uint8_t) 0x04)
643 
644 
645 
646 //****************************************************************************
647 //
648 // Register settings macros
649 //
650 //****************************************************************************
651 
652 // NOTE: These macros can be used in logical expressions for checking known register values.
653 // These macros will take on the value from the last register read/write operation, or the
654 // default register value if no register operations have occurred or the device is reset.
655 
656 #define CRC_EN ((bool) (getRegisterValue(D_SYS_CFG_ADDRESS) & D_SYS_CFG_CRC_EN_MASK))
657 #define CRC_MODE ((bool) (getRegisterValue(D_SYS_CFG_ADDRESS) & D_SYS_CFG_CRC_MODE_MASK))
658 #define FIXED ((bool) (getRegisterValue(D_SYS_CFG_ADDRESS) & D_SYS_CFG_FIXED_MASK))
659 
660 
661 
662 #endif /* ADS131A04_H_ */
Definition: ads131a04.h:88
int32_t signExtend(const uint8_t dataBytes[])
Definition: ads131a04.c:701
uint16_t calculateCRC(const uint8_t dataBytes[], uint8_t numberBytes, uint16_t initialValue)
Definition: ads131a04.c:566
int32_t channel4
Definition: ads131a04.h:93
bool readData(adc_data_struct *dataStruct)
Definition: ads131a04.c:346
void restoreRegisterDefaults(void)
Definition: ads131a04.c:659
uint8_t getRegisterValue(uint8_t address)
Definition: ads131a04.c:115
uint16_t crc
Definition: ads131a04.h:95
uint16_t response
Definition: ads131a04.h:94
int32_t channel3
Definition: ads131a04.h:92
bool lockRegisters(void)
Definition: ads131a04.c:490
uint16_t sendCommand(uint16_t opcode)
Definition: ads131a04.c:440
int32_t channel1
Definition: ads131a04.h:90
void adcStartup(void)
Definition: ads131a04.c:139
uint8_t readSingleRegister(uint8_t address)
Definition: ads131a04.c:234
int32_t channel2
Definition: ads131a04.h:91
void writeSingleRegister(uint8_t address, uint8_t data)
Definition: ads131a04.c:283
bool unlockRegisters(void)
Definition: ads131a04.c:524