PDK API Guide for AM64x
csl_mdio.h
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1 
63 #ifndef CSL_MDIO_V5_H
64 #define CSL_MDIO_V5_H
65 
66 #ifdef __cplusplus
67 extern "C" {
68 #endif
69 
70 
71 #include <ti/csl/soc.h>
72 #include <ti/csl/csl.h>
73 #include <ti/csl/cslr_mdio.h>
74 
75 
84 #include <string.h>
85 #include <stdbool.h>
86 #include <ti/csl/cslr.h>
87 #include <ti/csl/hw_types.h>
88 #include <ti/csl/csl_mdio_def.h>
89 
90 typedef volatile CSL_MdioRegs *CSL_mdioHandle;
91 
132  CSL_mdioHandle hMdioRegs,
133  CSL_MDIO_VERSION* mdioVersionInfo
134 );
135 
136 
167 uint16_t CSL_MDIO_getClkDivVal(
168  CSL_mdioHandle hMdioRegs
169 );
170 
171 
211  CSL_mdioHandle hMdioRegs,
212  uint16_t clkDivVal
213 );
214 
252  CSL_mdioHandle hMdioRegs
253 );
254 
285  CSL_mdioHandle hMdioRegs
286 );
287 
321  CSL_mdioHandle hMdioRegs
322 );
323 
367 uint32_t CSL_MDIO_isPhyAlive(
368  CSL_mdioHandle hMdioRegs,
369  uint32_t phyAddr
370 );
371 
372 
415 uint32_t CSL_MDIO_isPhyLinked(
416  CSL_mdioHandle hMdioRegs,
417  uint32_t phyAddr
418 );
419 
467  CSL_mdioHandle hMdioRegs,
468  uint32_t index
469 );
470 
471 
510  CSL_mdioHandle hMdioRegs,
511  uint32_t index
512 );
513 
527 uint32_t CSL_MDIO_phyRegRead(uint32_t baseAddr,
528  uint32_t phyAddr,
529  uint32_t regNum,
530  uint16_t *pData);
531 
544 void CSL_MDIO_phyRegWrite(uint32_t baseAddr, uint32_t phyAddr, uint32_t regNum, uint16_t wrVal);
545 
561 uint32_t CSL_MDIO_phyLinkStatus(uint32_t baseAddr, uint32_t phyAddr);
562 
582  CSL_mdioHandle hMdioRegs,
583  Uint32 index,
584  Uint32 phyAddr
585 );
586 
602  CSL_mdioHandle hMdioRegs,
603  Uint32 index,
604  Uint32 phyAddr
605 );
606 
639  CSL_mdioHandle hMdioRegs
640 );
641 
674  CSL_mdioHandle hMdioRegs
675 );
676 
708  CSL_mdioHandle hMdioRegs
709 );
710 
742  CSL_mdioHandle hMdioRegs
743 );
744 
745 
760 uint32_t CSL_MDIO_phyRegRead2(CSL_mdioHandle hMdioRegs,
761  uint32_t userGroup,
762  uint32_t phyAddr,
763  uint32_t regNum,
764  uint16_t *pData);
765 
779 void CSL_MDIO_phyRegWrite2(CSL_mdioHandle hMdioRegs, uint32_t userGroup, uint32_t phyAddr, uint32_t regNum, uint16_t wrVal);
780 
793  uint32_t clause45EnableMask);
794 
808 
829  uint32_t userGroup,
830  uint32_t phyAddr,
831  uint32_t mmdNum,
832  uint32_t regAddr,
833  uint16_t wrVal);
834 
855  uint32_t userGroup,
856  uint32_t phyAddr,
857  uint32_t mmdNum,
858  uint32_t regAddr);
859 
879  uint32_t userGroup,
880  uint32_t phyAddr,
881  uint32_t regAddr,
882  uint16_t wrVal);
883 
903  uint32_t userGroup,
904  uint32_t phyAddr,
905  uint32_t regAddr);
906 
924 int32_t CSL_MDIO_phyGetRegReadVal(CSL_mdioHandle hMdioRegs,
925  uint32_t userGroup,
926  uint16_t *pData);
927 
942  uint32_t userGroup);
943 
959 uint32_t CSL_MDIO_phyLinkStatus2(CSL_mdioHandle hMdioRegs, uint32_t phyAddr);
960 
978 
995 
1009 
1010 
1011 
1028  Uint32 index);
1029 
1047 
1064 
1078 
1092 void CSL_MDIO_setPollIPG(CSL_mdioHandle hMdioRegs,
1093  uint8_t ipgVal);
1094 
1109 uint8_t CSL_MDIO_getPollIPG(CSL_mdioHandle hMdioRegs);
1110 
1128  uint32_t pollEnableMask);
1129 
1144 uint32_t CSL_MDIO_getPollEnableMask(CSL_mdioHandle hMdioRegs);
1145 
1149 #ifdef __cplusplus
1150 }
1151 #endif
1152 
1153 #endif /* CSL_MDIO_V5_H */
uint16_t index
Definition: tisci_rm_proxy.h:153
uint32_t CSL_MDIO_phyRegRead(uint32_t baseAddr, uint32_t phyAddr, uint32_t regNum, uint16_t *pData)
void CSL_MDIO_disableFaultDetect(CSL_mdioHandle hMdioRegs)
uint32_t CSL_MDIO_phyLinkStatus2(CSL_mdioHandle hMdioRegs, uint32_t phyAddr)
This API reads the link status of all PHY connected to this MDIO. The bit corresponding to the PHY ad...
uint32_t CSL_MDIO_isPhyLinked(CSL_mdioHandle hMdioRegs, uint32_t phyAddr)
uint16_t CSL_MDIO_getClkDivVal(CSL_mdioHandle hMdioRegs)
uint32_t CSL_MDIO_isStateMachineEnabled(CSL_mdioHandle hMdioRegs)
uint32_t CSL_MDIO_phyLinkStatus(uint32_t baseAddr, uint32_t phyAddr)
This API reads the link status of all PHY connected to this MDIO. The bit corresponding to the PHY ad...
uint32_t CSL_MDIO_isStateChangeModeEnabled(CSL_mdioHandle hMdioRegs)
Checks if the State Change Mode is enabled or not.
void CSL_MDIO_disableStateChangeMode(CSL_mdioHandle hMdioRegs)
This function disables the MDIO State Change Mode.
uint32_t CSL_MDIO_isStatusChangeModeInterruptEnabled(CSL_mdioHandle hMdioRegs)
Check if the MDIO link interrupt (MDIO_LINKINT) is enabled.
void CSL_MDIO_phyRegWrite(uint32_t baseAddr, uint32_t phyAddr, uint32_t regNum, uint16_t wrVal)
This API writes a PHY register using MDIO.
void CSL_MDIO_enableLinkStatusChangeInterrupt(CSL_mdioHandle hMdioRegs, Uint32 index, Uint32 phyAddr)
Enable MDIO link interrupt (MDIO_LINKINT) for PHY monitoring.
void CSL_MDIO_disableLinkStatusChangeInterrupt(CSL_mdioHandle hMdioRegs, Uint32 index, Uint32 phyAddr)
Disable MDIO link interrupt (MDIO_LINKINT) for PHY monitoring.
volatile CSL_MdioRegs * CSL_mdioHandle
Definition: csl_mdio.h:90
uint32_t CSL_MDIO_getClause45EnableMask(CSL_mdioHandle hMdioRegs)
Get Clause-45 enable mask. Each bit in the mask is associated with a PHY address, i....
void CSL_MDIO_enableStateChangeMode(CSL_mdioHandle hMdioRegs)
This function enables the MDIO State Change Mode.
int32_t CSL_MDIO_phyInitiateRegReadC22(CSL_mdioHandle hMdioRegs, uint32_t userGroup, uint32_t phyAddr, uint32_t regAddr)
Initiate a non-blocking register read transaction with PHY using Clause-22 frame. The user should cal...
uint32_t CSL_MDIO_isUnmaskedLinkStatusChangeIntSet(CSL_mdioHandle hMdioRegs, uint32_t index)
void CSL_MDIO_clearUnmaskedLinkStatusChangeInt(CSL_mdioHandle hMdioRegs, uint32_t index)
uint32_t CSL_MDIO_phyRegRead2(CSL_mdioHandle hMdioRegs, uint32_t userGroup, uint32_t phyAddr, uint32_t regNum, uint16_t *pData)
int32_t CSL_MDIO_phyGetRegReadVal(CSL_mdioHandle hMdioRegs, uint32_t userGroup, uint16_t *pData)
Get the value read from a PHY register from a transaction previously initiated through either CSL_MDI...
void CSL_MDIO_setPollIPG(CSL_mdioHandle hMdioRegs, uint8_t ipgVal)
Set Polling Inter Packet Gap value.
void CSL_MDIO_enableStatusChangeModeInterrupt(CSL_mdioHandle hMdioRegs)
Enable MDIO link interrupt (MDIO_LINKINT)
uint8_t CSL_MDIO_getPollIPG(CSL_mdioHandle hMdioRegs)
Get Polling Inter Packet Gap value.
void CSL_MDIO_getVersionInfo(CSL_mdioHandle hMdioRegs, CSL_MDIO_VERSION *mdioVersionInfo)
void CSL_MDIO_enableStateMachine(CSL_mdioHandle hMdioRegs)
uint32_t CSL_MDIO_isPhyRegAccessComplete(CSL_mdioHandle hMdioRegs, uint32_t userGroup)
Check if there is a transaction going on in MDIO.
void CSL_MDIO_setPollEnableMask(CSL_mdioHandle hMdioRegs, uint32_t pollEnableMask)
Set poll enable mask.
uint32_t CSL_MDIO_getPollEnableMask(CSL_mdioHandle hMdioRegs)
Get poll enable mask.
int32_t CSL_MDIO_phyInitiateRegReadC45(CSL_mdioHandle hMdioRegs, uint32_t userGroup, uint32_t phyAddr, uint32_t mmdNum, uint32_t regAddr)
Initiate a non-blocking register read transaction with PHY using Clause-45 frame. The user should cal...
void CSL_MDIO_enablePreamble(CSL_mdioHandle hMdioRegs)
void CSL_MDIO_disableStatusChangeModeInterrupt(CSL_mdioHandle hMdioRegs)
Disable MDIO link interrupt (MDIO_LINKINT)
int32_t CSL_MDIO_phyRegInitiateWriteC22(CSL_mdioHandle hMdioRegs, uint32_t userGroup, uint32_t phyAddr, uint32_t regAddr, uint16_t wrVal)
Initiate a non-blocking write transaction with PHY using Clause-22 frame. The user should call CSL_MD...
void CSL_MDIO_phyRegWrite2(CSL_mdioHandle hMdioRegs, uint32_t userGroup, uint32_t phyAddr, uint32_t regNum, uint16_t wrVal)
This API writes a PHY register using MDIO.
void CSL_MDIO_disablePreamble(CSL_mdioHandle hMdioRegs)
int32_t CSL_MDIO_phyInitiateRegWriteC45(CSL_mdioHandle hMdioRegs, uint32_t userGroup, uint32_t phyAddr, uint32_t mmdNum, uint32_t regAddr, uint16_t wrVal)
Initiate a non-blocking write transaction with PHY using Clause-45 frame. The user should call CSL_MD...
void CSL_MDIO_enableFaultDetect(CSL_mdioHandle hMdioRegs)
Uint32 CSL_MDIO_getLinkStatusChangePhyAddr(CSL_mdioHandle hMdioRegs, Uint32 index)
Get the PHY address being monitored.
void CSL_MDIO_disableStateMachine(CSL_mdioHandle hMdioRegs)
uint32_t CSL_MDIO_isPhyAlive(CSL_mdioHandle hMdioRegs, uint32_t phyAddr)
void CSL_MDIO_setClkDivVal(CSL_mdioHandle hMdioRegs, uint16_t clkDivVal)
void CSL_MDIO_setClause45EnableMask(CSL_mdioHandle hMdioRegs, uint32_t clause45EnableMask)
Set Clause-45 enable mask. Each bit in the mask is associated with a PHY address, i....