5.6.7.1. AM64x Peripheral Interrupt Source Descriptions

5.6.7.1.1. Introduction

This chapter provides information on peripheral interrupt source IDs that are permitted in the am64x SoC. The interrupt source IDs represent outputs from SoC peripherals capable of generating an egress interrupt or event signal. The System Firmware interrupt management TISCI message APIs take interrupt source IDs as input to set and release interrupt routes between source peripherals and destination host processors.

5.6.7.1.2. Event-Based Interrupt Source IDs

Device Name Device ID Interrupt Source Name Interrupt Source Index
AM64X_DEV_DMASS0_RINGACC_0 33 Ring events 20 to 31
AM64X_DEV_DMASS0_RINGACC_0 33 Ring global error event 32
AM64X_DEV_DMASS0_INTAGGR_0 28 DMASS0_INTAGGR_0 mapped timermgr_evt events 0 to 1023
AM64X_DEV_DMASS0_INTAGGR_0 28 DMASS0_INTAGGR_0 mapped pktdma_tx_chan_error events 4096 to 4137
AM64X_DEV_DMASS0_INTAGGR_0 28 DMASS0_INTAGGR_0 mapped pktdma_tx_flow_completion events 4608 to 4719
AM64X_DEV_DMASS0_INTAGGR_0 28 DMASS0_INTAGGR_0 mapped pktdma_rx_chan_error events 5120 to 5148
AM64X_DEV_DMASS0_INTAGGR_0 28 DMASS0_INTAGGR_0 mapped pktdma_rx_flow_completion events 5632 to 5807
AM64X_DEV_DMASS0_INTAGGR_0 28 DMASS0_INTAGGR_0 mapped pktdma_rx_flow_starvation events 6144 to 6319
AM64X_DEV_DMASS0_INTAGGR_0 28 DMASS0_INTAGGR_0 mapped pktdma_rx_flow_firewall events 6656 to 6831
AM64X_DEV_DMASS0_INTAGGR_0 28 DMASS0_INTAGGR_0 mapped bcdma_chan_error events 8192 to 8219
AM64X_DEV_DMASS0_INTAGGR_0 28 DMASS0_INTAGGR_0 mapped bcdma_chan_data_completion events 8704 to 8731
AM64X_DEV_DMASS0_INTAGGR_0 28 DMASS0_INTAGGR_0 mapped bcdma_chan_ring_completion events 9216 to 9243
AM64X_DEV_DMASS0_INTAGGR_0 28 DMASS0_INTAGGR_0 mapped bcdma_tx_chan_error events 9728 to 9747
AM64X_DEV_DMASS0_INTAGGR_0 28 DMASS0_INTAGGR_0 mapped bcdma_tx_chan_data_completion events 10240 to 10259
AM64X_DEV_DMASS0_INTAGGR_0 28 DMASS0_INTAGGR_0 mapped bcdma_tx_chan_ring_completion events 10752 to 10771
AM64X_DEV_DMASS0_INTAGGR_0 28 DMASS0_INTAGGR_0 mapped bcdma_rx_chan_error events 11264 to 11283
AM64X_DEV_DMASS0_INTAGGR_0 28 DMASS0_INTAGGR_0 mapped bcdma_rx_chan_data_completion events 11776 to 11795
AM64X_DEV_DMASS0_INTAGGR_0 28 DMASS0_INTAGGR_0 mapped bcdma_rx_chan_ring_completion events 12288 to 12307

5.6.7.1.3. Non-Event Interrupt Source IDs

Device Name Device ID Interrupt Source Design Name Interrupt Source Index
AM64X_DEV_CPSW0 13 cpts_comp 0 0
AM64X_DEV_CPSW0 13 cpts_genf0 0 1
AM64X_DEV_CPSW0 13 cpts_genf1 0 2
AM64X_DEV_CPSW0 13 cpts_sync 0 3
AM64X_DEV_CPTS0 84 cpts_comp 0 0
AM64X_DEV_CPTS0 84 cpts_genf0 0 1
AM64X_DEV_CPTS0 84 cpts_genf1 0 2
AM64X_DEV_CPTS0 84 cpts_genf2 0 3
AM64X_DEV_CPTS0 84 cpts_genf3 0 4
AM64X_DEV_CPTS0 84 cpts_genf4 0 5
AM64X_DEV_CPTS0 84 cpts_genf5 0 6
AM64X_DEV_CPTS0 84 cpts_sync 0 7
AM64X_DEV_EPWM0 86 epwm_synco_o 0 0
AM64X_DEV_EPWM3 89 epwm_synco_o 0 0
AM64X_DEV_EPWM6 92 epwm_synco_o 0 0
AM64X_DEV_GPIO0 77 gpio 0 to 89 0 to 89
AM64X_DEV_GPIO0 77 gpio_bank 0 to 8 90 to 98
AM64X_DEV_GPIO1 78 gpio 0 to 89 0 to 89
AM64X_DEV_GPIO1 78 gpio_bank 0 to 8 90 to 98
AM64X_DEV_GTC0 61 gtc_push_event 0 0
AM64X_DEV_MCU_GPIO0 79 gpio 0 to 29 0 to 29
AM64X_DEV_MCU_GPIO0 79 gpio_bank 0 to 1 30 to 31
AM64X_DEV_PCIE0 114 pcie_cpts_comp 0 0
AM64X_DEV_PCIE0 114 pcie_cpts_genf0 0 1
AM64X_DEV_PCIE0 114 pcie_cpts_hw1_push 0 2
AM64X_DEV_PCIE0 114 pcie_cpts_sync 0 3
AM64X_DEV_PCIE0 114 pcie_ptm_valid_pulse 0 4
AM64X_DEV_PRU_ICSSG0 81 pr1_edc0_sync0_out 0 0
AM64X_DEV_PRU_ICSSG0 81 pr1_edc0_sync1_out 0 1
AM64X_DEV_PRU_ICSSG0 81 pr1_edc1_sync0_out 0 2
AM64X_DEV_PRU_ICSSG0 81 pr1_edc1_sync1_out 0 3
AM64X_DEV_PRU_ICSSG0 81 pr1_host_intr_req 0 to 7 4 to 11
AM64X_DEV_PRU_ICSSG0 81 pr1_iep0_cmp_intr_req 0 to 15 12 to 27
AM64X_DEV_PRU_ICSSG0 81 pr1_iep1_cmp_intr_req 0 to 15 28 to 43
AM64X_DEV_PRU_ICSSG1 82 pr1_edc0_sync0_out 0 0
AM64X_DEV_PRU_ICSSG1 82 pr1_edc0_sync1_out 0 1
AM64X_DEV_PRU_ICSSG1 82 pr1_edc1_sync0_out 0 2
AM64X_DEV_PRU_ICSSG1 82 pr1_edc1_sync1_out 0 3
AM64X_DEV_PRU_ICSSG1 82 pr1_host_intr_req 0 to 7 4 to 11
AM64X_DEV_PRU_ICSSG1 82 pr1_iep0_cmp_intr_req 0 to 15 12 to 27
AM64X_DEV_PRU_ICSSG1 82 pr1_iep1_cmp_intr_req 0 to 15 28 to 43
AM64X_DEV_TIMER0 36 timer_pwm 0 0
AM64X_DEV_TIMER1 37 timer_pwm 0 0
AM64X_DEV_TIMER2 38 timer_pwm 0 0