42 #ifndef CSL_CPGMAC_SL_V5_H_ 43 #define CSL_CPGMAC_SL_V5_H_ 50 #include <ti/csl/soc.h> 51 #include <ti/csl/csl.h> 52 #include <ti/csl/cslr_xge_cpsw.h> 90 #define CSL_CPGMAC_SL_MACCONTROL_FULLDUPLEX_EN (1 << 0u) 93 #define CSL_CPGMAC_SL_MACCONTROL_LOOPBACK_EN (1 << 1u) 96 #define CSL_CPGMAC_SL_MACCONTROL_RX_FLOW_EN (1 << 3u) 99 #define CSL_CPGMAC_SL_MACCONTROL_TX_FLOW_EN (1 << 4u) 102 #define CSL_CPGMAC_SL_MACCONTROL_GMII_EN (1 << 5u) 105 #define CSL_CPGMAC_SL_MACCONTROL_TX_PACE_EN (1 << 6u) 108 #define CSL_CPGMAC_SL_MACCONTROL_GIG_EN (1 << 7u) 111 #define CSL_CPGMAC_SL_MACCONTROL_TX_SHORT_GAP_EN (1 << 10u) 114 #define CSL_CPGMAC_SL_MACCONTROL_CMD_IDLE_EN (1 << 11u) 117 #define CSL_CPGMAC_SL_MACCONTROL_CASTAGNOLI_CRC (1 << 12u) 120 #define CSL_CPGMAC_SL_MACCONTROL_IFCTL_A_EN (1 << 15u) 123 #define CSL_CPGMAC_SL_MACCONTROL_IFCTL_B_EN (1 << 16u) 126 #define CSL_CPGMAC_SL_MACCONTROL_GIG_FORCE_EN (1 << 17u) 129 #define CSL_CPGMAC_SL_MACCONTROL_EXT_EN (1 << 18u) 132 #define CSL_CPGMAC_SL_MACCONTROL_EXT_EN_RX_FLOW (1 << 19u) 135 #define CSL_CPGMAC_SL_MACCONTROL_EXT_EN_TX_FLOW (1 << 20u) 138 #define CSL_CPGMAC_SL_MACCONTROL_RX_CEF_EN (1 << 22u) 141 #define CSL_CPGMAC_SL_MACCONTROL_RX_CSF_EN (1 << 23u) 144 #define CSL_CPGMAC_SL_MACCONTROL_RX_CMF_EN (1 << 24u) 267 (CSL_Xge_cpswRegs *hCpswRegs,
305 (CSL_Xge_cpswRegs *hCpswRegs,
343 (CSL_Xge_cpswRegs *hCpswRegs,
389 (CSL_Xge_cpswRegs *hCpswRegs,
427 (CSL_Xge_cpswRegs *hCpswRegs,
464 (CSL_Xge_cpswRegs *hCpswRegs,
510 (CSL_Xge_cpswRegs *hCpswRegs,
548 (CSL_Xge_cpswRegs *hCpswRegs,
586 (CSL_Xge_cpswRegs *hCpswRegs,
632 (CSL_Xge_cpswRegs *hCpswRegs,
670 (CSL_Xge_cpswRegs *hCpswRegs,
708 (CSL_Xge_cpswRegs *hCpswRegs,
755 (CSL_Xge_cpswRegs *hCpswRegs,
793 (CSL_Xge_cpswRegs *hCpswRegs,
831 (CSL_Xge_cpswRegs *hCpswRegs,
877 (CSL_Xge_cpswRegs *hCpswRegs,
915 (CSL_Xge_cpswRegs *hCpswRegs,
953 (CSL_Xge_cpswRegs *hCpswRegs,
999 (CSL_Xge_cpswRegs *hCpswRegs,
1037 (CSL_Xge_cpswRegs *hCpswRegs,
1075 (CSL_Xge_cpswRegs *hCpswRegs,
1123 (CSL_Xge_cpswRegs *hCpswRegs,
1161 (CSL_Xge_cpswRegs *hCpswRegs,
1199 (CSL_Xge_cpswRegs *hCpswRegs,
1247 (CSL_Xge_cpswRegs *hCpswRegs,
1285 (CSL_Xge_cpswRegs *hCpswRegs,
1323 (CSL_Xge_cpswRegs *hCpswRegs,
1368 (CSL_Xge_cpswRegs *hCpswRegs,
1406 (CSL_Xge_cpswRegs *hCpswRegs,
1444 (CSL_Xge_cpswRegs *hCpswRegs,
1491 (CSL_Xge_cpswRegs *hCpswRegs,
1529 (CSL_Xge_cpswRegs *hCpswRegs,
1567 (CSL_Xge_cpswRegs *hCpswRegs,
1613 (CSL_Xge_cpswRegs *hCpswRegs,
1651 (CSL_Xge_cpswRegs *hCpswRegs,
1689 (CSL_Xge_cpswRegs *hCpswRegs,
1735 (CSL_Xge_cpswRegs *hCpswRegs,
1773 (CSL_Xge_cpswRegs *hCpswRegs,
1811 (CSL_Xge_cpswRegs *hCpswRegs,
1859 (CSL_Xge_cpswRegs *hCpswRegs,
1897 (CSL_Xge_cpswRegs *hCpswRegs,
1935 (CSL_Xge_cpswRegs *hCpswRegs,
1983 (CSL_Xge_cpswRegs *hCpswRegs,
2021 (CSL_Xge_cpswRegs *hCpswRegs,
2059 (CSL_Xge_cpswRegs *hCpswRegs,
2107 (CSL_Xge_cpswRegs *hCpswRegs,
2145 (CSL_Xge_cpswRegs *hCpswRegs,
2183 (CSL_Xge_cpswRegs *hCpswRegs,
2232 (CSL_Xge_cpswRegs *hCpswRegs,
2270 (CSL_Xge_cpswRegs *hCpswRegs,
2308 (CSL_Xge_cpswRegs *hCpswRegs,
2356 (CSL_Xge_cpswRegs *hCpswRegs,
2394 (CSL_Xge_cpswRegs *hCpswRegs,
2432 (CSL_Xge_cpswRegs *hCpswRegs,
2480 (CSL_Xge_cpswRegs *hCpswRegs,
2518 (CSL_Xge_cpswRegs *hCpswRegs,
2556 (CSL_Xge_cpswRegs *hCpswRegs,
2594 (CSL_Xge_cpswRegs *hCpswRegs,
2638 (CSL_Xge_cpswRegs *hCpswRegs,
2640 Uint32 macControlRegVal
2686 (CSL_Xge_cpswRegs *hCpswRegs,
2725 (CSL_Xge_cpswRegs *hCpswRegs,
2768 (CSL_Xge_cpswRegs *hCpswRegs,
2807 (CSL_Xge_cpswRegs *hCpswRegs,
2849 (CSL_Xge_cpswRegs *hCpswRegs,
2890 (CSL_Xge_cpswRegs *hCpswRegs,
2932 (CSL_Xge_cpswRegs *hCpswRegs,
2972 (CSL_Xge_cpswRegs *hCpswRegs,
3010 (CSL_Xge_cpswRegs *hCpswRegs,
3050 (CSL_Xge_cpswRegs *hCpswRegs,
3088 (CSL_Xge_cpswRegs *hCpswRegs,
3130 (CSL_Xge_cpswRegs *hCpswRegs,
3132 Uint32* pEmulFreeBit,
3133 Uint32* pEmulSoftBit
3175 (CSL_Xge_cpswRegs *hCpswRegs,
3226 (CSL_Xge_cpswRegs *hCpswRegs,
3228 Uint32* pMacRxPriMap
3276 (CSL_Xge_cpswRegs *hCpswRegs,
3278 Uint32* pMacRxPriMap
Uint32 CSL_CPGMAC_SL_isGigForceModeEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_resetMac(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_enableRxCSF(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_isRxCSFEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 idle
Definition: csl_cpgmac_sl.h:209
void CSL_CPGMAC_SL_enableRxCMF(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableRxCEF(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 macTxIdle
Definition: csl_cpgmac_sl.h:203
void CSL_CPGMAC_SL_enableRxCEF(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_getRxPauseTimerReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_enableTxShortGapLimit(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_enableTxFlowControl(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_enableTxShortGap(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 extFullDuplexEnabled
Definition: csl_cpgmac_sl.h:181
void CSL_CPGMAC_SL_enableGMII(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_setTxPauseTimerReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 txPauseTimer)
Uint32 CSL_CPGMAC_SL_isExtControlEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableGigabit(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_isTxShortGapEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableTxShortGapLimit(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableLoopback(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableIFCTLA(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableFullDuplex(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_isExtTxFlowEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_setRxMaxLen(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 rxMaxLen)
Uint32 CSL_CPGMAC_SL_isIFCTLBEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableExtControl(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 txPfcFlowAct
Definition: csl_cpgmac_sl.h:195
void CSL_CPGMAC_SL_enableFullDuplex(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_setMacRxPriMapReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pMacRxPriMap)
Uint32 CSL_CPGMAC_SL_setTxGap(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 txGap)
Uint32 rxPfcFlowAct
Definition: csl_cpgmac_sl.h:193
Holds the Sliver submodule's version info.
Definition: csl_cpgmac_sl.h:150
void CSL_CPGMAC_SL_getInterVLANCfg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 routeIndex, CSL_CPSW_INTERVLANCFG *pInterVLANCfg)
Uint32 rtlVer
Definition: csl_cpgmac_sl.h:158
void CSL_CPGMAC_SL_getMacRxPriMapReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pMacRxPriMap)
Holds the Enet_Pn_FIFO_Status register contents.
Definition: csl_cpsw.h:1651
void CSL_CPGMAC_SL_disableTxFlowControl(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableIFCTLB(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableGMII(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_isExtRxFlowEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_enableGigabit(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_isTxShortGapLimitEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_enableIFCTLB(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_isTxPaceEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_isRxCEFEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Holds MAC status register contents.
Definition: csl_cpgmac_sl.h:168
void CSL_CPGMAC_SL_enableIdleMode(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_enableCastagnoliCRC(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_clearMacStatusTorf(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_enableTxPace(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 extRxFlowEnabled
Definition: csl_cpgmac_sl.h:187
void CSL_CPGMAC_SL_enableExtTxFlow(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_getTxPauseTimerReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 torfPri
Definition: csl_cpgmac_sl.h:199
void CSL_CPGMAC_SL_getMacStatusReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPGMAC_SL_MACSTATUS *pMacStatus)
Uint32 CSL_CPGMAC_SL_getRxMaxLen(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_enableExtRxFlow(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Holds the Port intervlan configuration info.
Definition: csl_cpsw.h:1615
Uint32 extTxFlowEnabled
Definition: csl_cpgmac_sl.h:191
void CSL_CPGMAC_SL_enableGigForceMode(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_isMACResetDone(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_isRxCMFEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 majorVer
Definition: csl_cpgmac_sl.h:155
void CSL_CPGMAC_SL_disableRxCSF(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 preemptMacIdle
Definition: csl_cpgmac_sl.h:207
Uint32 CSL_CPGMAC_SL_isIFCTLAEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 extGigabitEnabled
Definition: csl_cpgmac_sl.h:183
Uint32 CSL_CPGMAC_SL_isGMIIEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_enableExtControl(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_isTxFlowControlEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableRxFlowControl(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_enableIFCTLA(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableCastagnoliCRC(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableTxShortGap(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_setMacControlReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 macControlRegVal)
Uint32 CSL_CPGMAC_SL_isIdleModeEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 txFlowActive
Definition: csl_cpgmac_sl.h:175
void CSL_CPGMAC_SL_enableRxFlowControl(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_getEmulControlReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pEmulFreeBit, Uint32 *pEmulSoftBit)
void CSL_CPGMAC_SL_setEmulControlReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 emulFreeBit, Uint32 emulSoftBit)
void CSL_CPGMAC_SL_disableRxCMF(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_enableLoopback(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableGigForceMode(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_clearMacStatusTorfPri(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_isGigabitEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 torf
Definition: csl_cpgmac_sl.h:201
Uint32 CSL_CPGMAC_SL_isFullDuplexEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableExtTxFlow(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableIdleMode(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_getMacControlReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_isCastagnoliCRCEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_isLoopbackModeEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 id
Definition: csl_cpgmac_sl.h:161
void CSL_CPGMAC_SL_setInterVLANCfg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 routeIndex, CSL_CPSW_INTERVLANCFG *pInterVLANCfg)
Uint32 rxFlowActive
Definition: csl_cpgmac_sl.h:179
Uint32 CSL_CPGMAC_SL_getTxGap(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 expressMacIdle
Definition: csl_cpgmac_sl.h:205
void CSL_CPGMAC_SL_getFifoStatus(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPGMAC_SL_FIFOSTATUS *pFifoStatus)
Uint32 CSL_CPGMAC_SL_isRxFlowControlEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableExtRxFlow(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 minorVer
Definition: csl_cpgmac_sl.h:152
void CSL_CPGMAC_SL_disableTxPace(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_setRxPauseTimerReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 rxPauseTimer)