50 #ifndef ti_osal_CacheP__include 51 #define ti_osal_CacheP__include 71 #define OSAL_CACHEP_COHERENT ((uint32_t) 0U) 73 #define OSAL_CACHEP_NOT_COHERENT ((uint32_t) 1U) void CacheP_fenceDma2Cpu(uintptr_t addr, uint32_t size, Osal_CacheP_isCoherent isCoherent)
Function to call before reading the memory to CPU after DMA operations.
uint32_t Osal_CacheP_isCoherent
This enumerator defines the cache coherent types.
Definition: CacheP.h:69
void CacheP_fenceCpu2Dma(uintptr_t addr, uint32_t size, Osal_CacheP_isCoherent isCoherent)
Function to call before handing over the memory buffer to DMA from CPU.
void CacheP_wbInv(const void *addr, int32_t size)
Function to write back and invalidate cache lines.
void CacheP_wb(const void *addr, int32_t size)
Function to write back cache lines.
void CacheP_Inv(const void *addr, int32_t size)
Function to invalidate cache lines.
uint64_t addr
Definition: csl_bcdma.h:1291
uint16_t size
Definition: tisci_boardcfg.h:112