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PDK API Guide for AM64x
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Go to the documentation of this file. 41 #ifndef SCICLIENT_FMWMSGPARAMS_H_ 42 #define SCICLIENT_FMWMSGPARAMS_H_ 49 #include <ti/csl/soc.h> 60 #define TISCI_PARAM_UNDEF (0xFFFFFFFFU) 70 #define SCICLIENT_FIRMWARE_ABI_MAJOR (3U) 75 #define SCICLIENT_FIRMWARE_ABI_MINOR (1U) 85 #define SCICLIENT_CONTEXT_R5_0_SEC_0 (0U) 87 #define SCICLIENT_CONTEXT_R5_0_NONSEC_0 (1U) 89 #define SCICLIENT_CONTEXT_R5_0_SEC_1 (2U) 91 #define SCICLIENT_CONTEXT_R5_0_NONSEC_1 (3U) 93 #define SCICLIENT_CONTEXT_A53_SEC_0 (4U) 95 #define SCICLIENT_CONTEXT_A53_NONSEC_0 (5U) 97 #define SCICLIENT_CONTEXT_A53_NONSEC_1 (6U) 99 #define SCICLIENT_CONTEXT_A53_NONSEC_2 (7U) 101 #define SCICLIENT_CONTEXT_M4_NONSEC_0 (8U) 103 #define SCICLIENT_CONTEXT_R5_1_SEC_0 (9U) 105 #define SCICLIENT_CONTEXT_R5_1_NONSEC_0 (10U) 107 #define SCICLIENT_CONTEXT_R5_1_SEC_1 (11U) 109 #define SCICLIENT_CONTEXT_R5_1_NONSEC_1 (12U) 111 #define SCICLIENT_CONTEXT_ICSSG_NONSEC_0 (13U) 113 #define SCICLIENT_CONTEXT_M4_SEC_0 (14U) 116 #define SCICLIENT_CONTEXT_MAX_NUM (15U) 127 #define SCICLIENT_PROCID_A53_CL0_C0 (0x20U) 129 #define SCICLIENT_PROCID_A53_CL0_C1 (0x21U) 131 #define SCICLIENT_PROCID_R5_CL0_C0 (0x01U) 133 #define SCICLIENT_PROCID_R5_CL0_C1 (0x02U) 135 #define SCICLIENT_PROCID_R5_CL1_C0 (0x06U) 137 #define SCICLIENT_PROCID_R5_CL1_C1 (0x07U) 139 #define SCICLIENT_PROCID_MCU_M4FSS0_C0 (0x18U) 145 #define TISCI_MSG_VALUE_RM_NULL_RING_TYPE (0xFFFFu) 146 #define TISCI_MSG_VALUE_RM_NULL_RING_INDEX (0xFFFFFFFFu) 147 #define TISCI_MSG_VALUE_RM_NULL_RING_ADDR (0xFFFFFFFFu) 148 #define TISCI_MSG_VALUE_RM_NULL_RING_COUNT (0xFFFFFFFFu) 154 #define TISCI_MSG_VALUE_RM_NULL_RING_MODE (0xFFu) 155 #define TISCI_MSG_VALUE_RM_NULL_RING_SIZE (0xFFu) 156 #define TISCI_MSG_VALUE_RM_NULL_ORDER_ID (0xFFu) 157 #define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_TYPE (0xFFu) 158 #define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_INDEX (0xFFFFFFFFu) 167 #include <ti/drv/sciclient/soc/sysfw/include/am64x/tisci_devices.h> 176 #include <ti/drv/sciclient/soc/sysfw/include/am64x/tisci_clocks.h> 186 #define TISCI_RINGACC0_OES_IRQ_SRC_IDX_START (20U) 187 #define TISCI_RINGACC0_EOES_IRQ_SRC_IDX_START (32U) 188 #define TISCI_TIMERMGR_OES_IRQ_SRC_IDX_START (0U) 189 #define TISCI_PKTDMA0_TX_EOES_IRQ_SRC_IDX_START (4096U) 190 #define TISCI_PKTDMA0_TX_FLOW_OES_IRQ_SRC_IDX_START (4608U) 191 #define TISCI_PKTDMA0_RX_EOES_IRQ_SRC_IDX_START (5120U) 192 #define TISCI_PKTDMA0_RX_FLOW_OES_IRQ_SRC_IDX_START (5632U) 193 #define TISCI_PKTDMA0_RX_FLOW_SOES_IRQ_SRC_IDX_START (6144U) 194 #define TISCI_PKTDMA0_RX_FLOW_FOES_IRQ_SRC_IDX_START (6656U) 195 #define TISCI_BCDMA0_BC_EOES_IRQ_SRC_IDX_START (8192U) 196 #define TISCI_BCDMA0_BC_DC_OES_IRQ_SRC_IDX_START (8704U) 197 #define TISCI_BCDMA0_BC_RC_OES_IRQ_SRC_IDX_START (9216U) 198 #define TISCI_BCDMA0_TX_EOES_IRQ_SRC_IDX_START (9728U) 199 #define TISCI_BCDMA0_TX_DC_OES_IRQ_SRC_IDX_START (10240U) 200 #define TISCI_BCDMA0_TX_RC_OES_IRQ_SRC_IDX_START (10752U) 201 #define TISCI_BCDMA0_RX_EOES_IRQ_SRC_IDX_START (11264U) 202 #define TISCI_BCDMA0_RX_DC_OES_IRQ_SRC_IDX_START (11776U) 203 #define TISCI_BCDMA0_RX_RC_OES_IRQ_SRC_IDX_START (12288U) 213 #define SCICLIENT_DEV_MCU_R5FSS0_CORE0 (TISCI_DEV_R5FSS0_CORE0) 214 #define SCICLIENT_DEV_MCU_R5FSS0_CORE1 (TISCI_DEV_R5FSS0_CORE1) 223 #define SCICLIENT_DEV_MCU_R5FSS0_CORE0_PROCID \ 224 (SCICLIENT_PROCID_R5_CL0_C0) 225 #define SCICLIENT_DEV_MCU_R5FSS0_CORE1_PROCID \ 226 (SCICLIENT_PROCID_R5_CL0_C1) 230 #define SCICLIENT_ALLOWED_BOARDCFG_BASE_START (CSL_MSRAM_256K0_RAM_BASE) 232 #define SCICLIENT_ALLOWED_BOARDCFG_BASE_END (CSL_MSRAM_256K0_RAM_BASE + CSL_MSRAM_256K0_RAM_SIZE * 8UL)