PDK API Guide for AM64x
csl_cpsw_ss.h
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1 
42 #ifndef CSL_CPSW_SS_V5_0_H_
43 #define CSL_CPSW_SS_V5_0_H_
44 
45 #ifdef __cplusplus
46 extern "C" {
47 #endif
48 
49 #include <stdbool.h>
50 #include <ti/csl/soc.h>
51 #include <ti/csl/csl.h>
52 #include <ti/csl/cslr_xge_cpsw_ss_s.h>
53 
61 typedef enum
62 {
65 
69 
74 typedef struct {
76  Uint32 minorVer;
77 
79  Uint32 majorVer;
80 
82  Uint32 rtlVer;
83 
85  Uint32 id;
87 
92 typedef struct {
94  Uint32 scheme;
96  Uint32 bu;
98  Uint32 function;
100  Uint32 rtlVer;
104  Uint32 custom;
108 
113 typedef struct {
121 
126 typedef struct {
128  Uint32 link;
130  Uint32 speed;
132  Uint32 fullDuplex;
178 void CSL_CPSW_SS_getVersionInfo (CSL_Xge_cpsw_ss_sRegs * hCpswSsRegs,
179  CSL_CPSW_SS_VERSION* versionInfo
180 );
181 
200 void CSL_CPSW_SS_INTD_getVersionInfo(CSL_cpswRegs_INTD * hCpswIntDRegs,
201  CSL_CPSW_SS_INTD_VERSION* versionInfo);
202 
225 Uint32 CSL_CPSW_SS_INTD_getEOIVector(CSL_cpswRegs_INTD * hCpswIntDRegs);
226 
249 void CSL_CPSW_SS_INTD_setEOIVector(CSL_cpswRegs_INTD * hCpswIntDRegs,
250  Uint32 eoiVector);
251 
273 Uint32 CSL_CPSW_SS_INTD_getEOIIntrVector(CSL_cpswRegs_INTD * hCpswIntDRegs);
274 
295 Uint32 CSL_CPSW_SS_INTD_getIntrVectorOutPulse(CSL_cpswRegs_INTD * hCpswIntDRegs);
296 
313 void CSL_CPSW_SS_INTD_setEnableIntrCPSWEventInterrupt(CSL_cpswRegs_INTD * hCpswIntDRegs,
314  Uint32 enable);
315 
332 Uint32 CSL_CPSW_SS_INTD_getEnableIntrCPSWEventInterrupt(CSL_cpswRegs_INTD * hCpswIntDRegs);
333 
351 void CSL_CPSW_SS_INTD_setClearIntrCPSWEventInterrupt(CSL_cpswRegs_INTD * hCpswIntDRegs);
352 
370 void CSL_CPSW_SS_INTD_getStatusIntr(CSL_cpswRegs_INTD * hCpswIntDRegs,
371  CSL_CPSW_SS_INTD_INTRSTATUS *intrStatus);
372 
389 void CSL_CPSW_SS_INTD_setEnableIntrMdioInterrupt(CSL_cpswRegs_INTD * hCpswIntDRegs,
390  Uint32 enable);
391 
408 Uint32 CSL_CPSW_SS_INTD_getEnableIntrMdioInterrupt(CSL_cpswRegs_INTD * hCpswIntDRegs);
409 
427 void CSL_CPSW_SS_INTD_setClearIntrMdioInterrupt(CSL_cpswRegs_INTD * hCpswIntDRegs);
428 
445 void CSL_CPSW_SS_INTD_setEnableIntrStatInterrupt(CSL_cpswRegs_INTD * hCpswIntDRegs,
446  Uint32 enable);
447 
464 Uint32 CSL_CPSW_SS_INTD_getEnableIntrStatInterrupt(CSL_cpswRegs_INTD * hCpswIntDRegs);
465 
483 void CSL_CPSW_SS_INTD_setClearIntrStatInterrupt(CSL_cpswRegs_INTD * hCpswIntDRegs);
484 
502 void CSL_CPSW_SS_setSGMIIMode(CSL_Xge_cpsw_ss_sRegs * hCpswSsRegs,
503  Uint32 macPortNum,
504  CSL_SGMII_MODE sgmiiModeId);
505 
523 void CSL_CPSW_SS_getRGMIIStatus(CSL_Xge_cpsw_ss_sRegs * hCpswSsRegs,
524  Uint32 macPortNum,
525  CSL_CPSW_SS_RGMIISTATUS *pRgmiiStatus);
526 
543 Uint32 CSL_CPSW_SS_getSerdesResetIsolation(CSL_Xge_cpsw_ss_sRegs * hCpswSsRegs);
544 
561 void CSL_CPSW_SS_setSerdesResetIsolation(CSL_Xge_cpsw_ss_sRegs * hCpswSsRegs,
562  Uint32 resetIso);
563 
580 Uint32 CSL_CPSW_SS_getQSGMIIControlRdCd(CSL_Xge_cpsw_ss_sRegs * hCpswSsRegs,
581  Uint32 qsgmiiId);
582 
600 void CSL_CPSW_SS_setQSGMIIControlRdCd(CSL_Xge_cpsw_ss_sRegs * hCpswSsRegs,
601  Uint32 qsgmiiId,
602  Uint32 qsgmiiControlRdCd);
603 
620 Uint32 CSL_CPSW_SS_getQSGMIIStatusRxSync(CSL_Xge_cpsw_ss_sRegs * hCpswSsRegs,
621  Uint32 qsgmiiId);
622 
639 Uint32 CSL_CPSW_SS_getXGMIILinkStatus(CSL_Xge_cpsw_ss_sRegs * hCpswSsRegs,
640  Uint32 xgmiiId);
641 
658 Uint32 CSL_CPSW_SS_getSGMIILinkStatus(CSL_Xge_cpsw_ss_sRegs * hCpswSsRegs,
659  Uint32 sgmiiId);
660 
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676 
677 
678 #ifdef __cplusplus
679 }
680 #endif
681 
682 #endif
683 
Definition: csl_cpsw_ss.h:67
void CSL_CPSW_SS_setSerdesResetIsolation(CSL_Xge_cpsw_ss_sRegs *hCpswSsRegs, Uint32 resetIso)
Uint32 CSL_CPSW_SS_getQSGMIIStatusRxSync(CSL_Xge_cpsw_ss_sRegs *hCpswSsRegs, Uint32 qsgmiiId)
void CSL_CPSW_SS_INTD_setEOIVector(CSL_cpswRegs_INTD *hCpswIntDRegs, Uint32 eoiVector)
Uint32 CSL_CPSW_SS_INTD_getEnableIntrCPSWEventInterrupt(CSL_cpswRegs_INTD *hCpswIntDRegs)
Uint32 scheme
Definition: csl_cpsw_ss.h:94
void CSL_CPSW_SS_INTD_getStatusIntr(CSL_cpswRegs_INTD *hCpswIntDRegs, CSL_CPSW_SS_INTD_INTRSTATUS *intrStatus)
Uint32 majorRevision
Definition: csl_cpsw_ss.h:102
Uint32 fullDuplex
Definition: csl_cpsw_ss.h:132
Uint32 bu
Definition: csl_cpsw_ss.h:96
Uint32 custom
Definition: csl_cpsw_ss.h:104
void CSL_CPSW_SS_INTD_setEnableIntrCPSWEventInterrupt(CSL_cpswRegs_INTD *hCpswIntDRegs, Uint32 enable)
Uint32 mdioInterruptActive
Definition: csl_cpsw_ss.h:117
Uint32 majorVer
Definition: csl_cpsw_ss.h:79
Uint32 speed
Definition: csl_cpsw_ss.h:130
void CSL_CPSW_SS_getVersionInfo(CSL_Xge_cpsw_ss_sRegs *hCpswSsRegs, CSL_CPSW_SS_VERSION *versionInfo)
Holds the CPSW_SS INTD version info.
Definition: csl_cpsw_ss.h:92
void CSL_CPSW_SS_INTD_setClearIntrStatInterrupt(CSL_cpswRegs_INTD *hCpswIntDRegs)
void CSL_CPSW_SS_INTD_setClearIntrMdioInterrupt(CSL_cpswRegs_INTD *hCpswIntDRegs)
Holds the CPSW_SS RGMII STATUS.
Definition: csl_cpsw_ss.h:126
Uint32 CSL_CPSW_SS_getQSGMIIControlRdCd(CSL_Xge_cpsw_ss_sRegs *hCpswSsRegs, Uint32 qsgmiiId)
void CSL_CPSW_SS_setSGMIIMode(CSL_Xge_cpsw_ss_sRegs *hCpswSsRegs, Uint32 macPortNum, CSL_SGMII_MODE sgmiiModeId)
Holds the CPSW_SS INTD interrupt status info.
Definition: csl_cpsw_ss.h:113
Uint32 link
Definition: csl_cpsw_ss.h:128
CSL_SGMII_MODE
SGMII Mode enumerators.
Definition: csl_cpsw_ss.h:61
Definition: csl_cpsw_ss.h:64
Uint32 minorRevision
Definition: csl_cpsw_ss.h:106
Holds the Ethernet switch subsystem's version info.
Definition: csl_cpsw_ss.h:74
Uint32 CSL_CPSW_SS_getXGMIILinkStatus(CSL_Xge_cpsw_ss_sRegs *hCpswSsRegs, Uint32 xgmiiId)
Uint32 CSL_CPSW_SS_getSGMIILinkStatus(CSL_Xge_cpsw_ss_sRegs *hCpswSsRegs, Uint32 sgmiiId)
Uint32 rtlVer
Definition: csl_cpsw_ss.h:100
void CSL_CPSW_SS_getRGMIIStatus(CSL_Xge_cpsw_ss_sRegs *hCpswSsRegs, Uint32 macPortNum, CSL_CPSW_SS_RGMIISTATUS *pRgmiiStatus)
void CSL_CPSW_SS_INTD_setEnableIntrMdioInterrupt(CSL_cpswRegs_INTD *hCpswIntDRegs, Uint32 enable)
Uint32 id
Definition: csl_cpsw_ss.h:85
Uint32 CSL_CPSW_SS_getSerdesResetIsolation(CSL_Xge_cpsw_ss_sRegs *hCpswSsRegs)
Uint32 rtlVer
Definition: csl_cpsw_ss.h:82
void CSL_CPSW_SS_INTD_setClearIntrCPSWEventInterrupt(CSL_cpswRegs_INTD *hCpswIntDRegs)
Uint32 CSL_CPSW_SS_INTD_getEnableIntrStatInterrupt(CSL_cpswRegs_INTD *hCpswIntDRegs)
void CSL_CPSW_SS_INTD_setEnableIntrStatInterrupt(CSL_cpswRegs_INTD *hCpswIntDRegs, Uint32 enable)
Uint32 CSL_CPSW_SS_INTD_getEOIIntrVector(CSL_cpswRegs_INTD *hCpswIntDRegs)
Uint32 CSL_CPSW_SS_INTD_getIntrVectorOutPulse(CSL_cpswRegs_INTD *hCpswIntDRegs)
void CSL_CPSW_SS_INTD_getVersionInfo(CSL_cpswRegs_INTD *hCpswIntDRegs, CSL_CPSW_SS_INTD_VERSION *versionInfo)
Uint32 cpswEventActive
Definition: csl_cpsw_ss.h:115
Uint32 minorVer
Definition: csl_cpsw_ss.h:76
Uint32 CSL_CPSW_SS_INTD_getEOIVector(CSL_cpswRegs_INTD *hCpswIntDRegs)
void CSL_CPSW_SS_setQSGMIIControlRdCd(CSL_Xge_cpsw_ss_sRegs *hCpswSsRegs, Uint32 qsgmiiId, Uint32 qsgmiiControlRdCd)
Uint32 CSL_CPSW_SS_INTD_getEnableIntrMdioInterrupt(CSL_cpswRegs_INTD *hCpswIntDRegs)
Uint32 statPendInterruptActive
Definition: csl_cpsw_ss.h:119