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PDK API Guide for AM64x
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File containing the AM64x specific interrupt management data for RM.
uint8_t vint_usage_count_DMASS0_INTAGGR_0[184] = {0} |
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struct Sciclient_rmIaInst gRmIaInstances[SCICLIENT_RM_IA_NUM_INST] |
struct Sciclient_rmIrInst gRmIrInstances[SCICLIENT_RM_IR_NUM_INST] |
const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_0_15_to_GICSS0_spi_48_63 |
const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_16_23_to_R5FSS0_CORE0_intr_48_55 |
const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_16_23_to_R5FSS0_CORE1_intr_48_55 |
const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_24_31_to_R5FSS1_CORE0_intr_48_55 |
const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_24_31_to_R5FSS1_CORE1_intr_48_55 |
const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_32_39_to_DMASS0_INTAGGR_0_intaggr_levi_pend_0_7 |
const struct Sciclient_rmIrqIf* const tisci_if_CMP_EVENT_INTROUTER0[] |
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const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_GICSS0_spi_32_47 |
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS0_CORE0_intr_32_47 |
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS0_CORE1_intr_32_47 |
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS1_CORE0_intr_32_47 |
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS1_CORE1_intr_32_47 |
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_30_37_to_DMASS0_INTAGGR_0_intaggr_levi_pend_16_23 |
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_16_17_to_DMASS0_INTAGGR_0_intaggr_levi_pend_24_25 |
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_18_23_to_PRU_ICSSG0_pr1_iep0_cap_intr_req_4_9 |
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_24_29_to_PRU_ICSSG0_pr1_iep1_cap_intr_req_10_15 |
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_38_45_to_PRU_ICSSG0_pr1_slv_intr_46_53 |
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_18_23_to_PRU_ICSSG1_pr1_iep0_cap_intr_req_4_9 |
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_24_29_to_PRU_ICSSG1_pr1_iep1_cap_intr_req_10_15 |
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_46_53_to_PRU_ICSSG1_pr1_slv_intr_46_53 |
const struct Sciclient_rmIrqIf* const tisci_if_MAIN_GPIOMUX_INTROUTER0[] |
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const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_GICSS0_spi_104_107 |
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS0_CORE0_intr_104_107 |
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS0_CORE1_intr_104_107 |
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS1_CORE0_intr_104_107 |
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS1_CORE1_intr_104_107 |
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_4_7_to_MCU_M4FSS0_CORE0_nvic_0_3 |
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event0_88_91 |
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event1_92_95 |
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event2_96_99 |
const struct Sciclient_rmIrqIf* const tisci_if_MCU_MCU_GPIOMUX_INTROUTER0[] |
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const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_0_7_to_DMASS0_INTAGGR_0_intaggr_levi_pend_8_15 |
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_8_8_to_PRU_ICSSG0_pr1_edc0_latch0_in_0_0 |
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_9_9_to_PRU_ICSSG0_pr1_edc0_latch1_in_1_1 |
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_10_10_to_PRU_ICSSG0_pr1_edc1_latch0_in_2_2 |
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_11_11_to_PRU_ICSSG0_pr1_edc1_latch1_in_3_3 |
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_12_12_to_PRU_ICSSG1_pr1_edc0_latch0_in_0_0 |
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_13_13_to_PRU_ICSSG1_pr1_edc0_latch1_in_1_1 |
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_14_14_to_PRU_ICSSG1_pr1_edc1_latch0_in_2_2 |
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_15_15_to_PRU_ICSSG1_pr1_edc1_latch1_in_3_3 |
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_16_16_to_CPTS0_cpts_hw1_push_0_0 |
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_17_17_to_CPTS0_cpts_hw2_push_1_1 |
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_18_18_to_CPTS0_cpts_hw3_push_2_2 |
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_19_19_to_CPTS0_cpts_hw4_push_3_3 |
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_20_20_to_CPTS0_cpts_hw5_push_4_4 |
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_21_21_to_CPTS0_cpts_hw6_push_5_5 |
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_22_22_to_CPTS0_cpts_hw7_push_6_6 |
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_23_23_to_CPTS0_cpts_hw8_push_7_7 |
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_29_29_to_PCIE0_pcie_cpts_hw2_push_0_0 |
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_30_30_to_CPSW0_cpts_hw1_push_0_0 |
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_31_31_to_CPSW0_cpts_hw2_push_1_1 |
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_32_32_to_CPSW0_cpts_hw3_push_2_2 |
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_33_33_to_CPSW0_cpts_hw4_push_3_3 |
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_34_34_to_CPSW0_cpts_hw5_push_4_4 |
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_35_35_to_CPSW0_cpts_hw6_push_5_5 |
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_36_36_to_CPSW0_cpts_hw7_push_6_6 |
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_37_37_to_CPSW0_cpts_hw8_push_7_7 |
const struct Sciclient_rmIrqIf* const tisci_if_TIMESYNC_EVENT_INTROUTER0[] |
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const struct Sciclient_rmIrqIf CPSW0_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_80_80 |
const struct Sciclient_rmIrqIf CPSW0_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_21_21 |
const struct Sciclient_rmIrqIf CPSW0_cpts_genf1_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_22_22 |
const struct Sciclient_rmIrqIf CPSW0_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_34_34 |
const struct Sciclient_rmIrqIf* const tisci_if_CPSW0[] |
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const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_GICSS0_spi_64_103 |
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_72_79_to_R5FSS0_CORE0_intr_8_15 |
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_R5FSS0_CORE0_intr_64_95 |
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_80_87_to_R5FSS0_CORE1_intr_8_15 |
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_R5FSS0_CORE1_intr_64_95 |
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_120_127_to_R5FSS1_CORE0_intr_8_15 |
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_88_119_to_R5FSS1_CORE0_intr_64_95 |
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_128_135_to_R5FSS1_CORE1_intr_8_15 |
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_88_119_to_R5FSS1_CORE1_intr_64_95 |
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_152_159_to_PRU_ICSSG0_pr1_slv_intr_16_23 |
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_160_167_to_PRU_ICSSG1_pr1_slv_intr_16_23 |
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_168_183_to_MCU_M4FSS0_CORE0_nvic_32_47 |
const struct Sciclient_rmIrqIf* const tisci_if_DMASS0_INTAGGR_0[] |
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const struct Sciclient_rmIrqIf TIMER0_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_0_0 |
const struct Sciclient_rmIrqIf* const tisci_if_TIMER0[] |
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const struct Sciclient_rmIrqIf TIMER1_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_1_1 |
const struct Sciclient_rmIrqIf* const tisci_if_TIMER1[] |
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const struct Sciclient_rmIrqIf TIMER2_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_2_2 |
const struct Sciclient_rmIrqIf* const tisci_if_TIMER2[] |
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const struct Sciclient_rmIrqIf TIMER3_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_3_3 |
const struct Sciclient_rmIrqIf* const tisci_if_TIMER3[] |
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const struct Sciclient_rmIrqIf GTC0_gtc_push_event_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_36_36 |
const struct Sciclient_rmIrqIf* const tisci_if_GTC0[] |
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const struct Sciclient_rmIrqIf GPIO0_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_0_89 |
const struct Sciclient_rmIrqIf GPIO0_gpio_bank_90_98_to_MAIN_GPIOMUX_INTROUTER0_in_190_198 |
const struct Sciclient_rmIrqIf* const tisci_if_GPIO0[] |
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const struct Sciclient_rmIrqIf GPIO1_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_90_179 |
const struct Sciclient_rmIrqIf GPIO1_gpio_bank_90_98_to_MAIN_GPIOMUX_INTROUTER0_in_180_188 |
const struct Sciclient_rmIrqIf* const tisci_if_GPIO1[] |
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const struct Sciclient_rmIrqIf MCU_GPIO0_gpio_0_29_to_MCU_MCU_GPIOMUX_INTROUTER0_in_0_29 |
const struct Sciclient_rmIrqIf MCU_GPIO0_gpio_bank_30_31_to_MCU_MCU_GPIOMUX_INTROUTER0_in_30_31 |
const struct Sciclient_rmIrqIf* const tisci_if_MCU_GPIO0[] |
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const struct Sciclient_rmIrqIf GPMC0_gpmc_sdmareq_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_29_29 |
const struct Sciclient_rmIrqIf* const tisci_if_GPMC0[] |
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const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_edc0_sync0_out_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_25_25 |
const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_edc0_sync1_out_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_26_26 |
const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_edc1_sync0_out_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_27_27 |
const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_edc1_sync1_out_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_28_28 |
const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_host_intr_req_4_11_to_CMP_EVENT_INTROUTER0_in_0_7 |
const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_iep0_cmp_intr_req_12_27_to_CMP_EVENT_INTROUTER0_in_16_31 |
const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_iep1_cmp_intr_req_28_43_to_CMP_EVENT_INTROUTER0_in_32_47 |
const struct Sciclient_rmIrqIf* const tisci_if_PRU_ICSSG0[] |
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const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_edc0_sync0_out_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_29_29 |
const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_edc0_sync1_out_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_30_30 |
const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_edc1_sync0_out_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_31_31 |
const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_edc1_sync1_out_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_32_32 |
const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_host_intr_req_4_11_to_CMP_EVENT_INTROUTER0_in_8_15 |
const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_iep0_cmp_intr_req_12_27_to_CMP_EVENT_INTROUTER0_in_48_63 |
const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_iep1_cmp_intr_req_28_43_to_CMP_EVENT_INTROUTER0_in_64_79 |
const struct Sciclient_rmIrqIf* const tisci_if_PRU_ICSSG1[] |
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const struct Sciclient_rmIrqIf CPTS0_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_82_82 |
const struct Sciclient_rmIrqIf CPTS0_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_16_16 |
const struct Sciclient_rmIrqIf CPTS0_cpts_genf1_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_17_17 |
const struct Sciclient_rmIrqIf CPTS0_cpts_genf2_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_18_18 |
const struct Sciclient_rmIrqIf CPTS0_cpts_genf3_4_4_to_TIMESYNC_EVENT_INTROUTER0_in_19_19 |
const struct Sciclient_rmIrqIf CPTS0_cpts_genf4_5_5_to_TIMESYNC_EVENT_INTROUTER0_in_20_20 |
const struct Sciclient_rmIrqIf CPTS0_cpts_genf5_6_6_to_TIMESYNC_EVENT_INTROUTER0_in_24_24 |
const struct Sciclient_rmIrqIf CPTS0_cpts_sync_7_7_to_TIMESYNC_EVENT_INTROUTER0_in_35_35 |
const struct Sciclient_rmIrqIf* const tisci_if_CPTS0[] |
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const struct Sciclient_rmIrqIf EPWM0_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_39_39 |
const struct Sciclient_rmIrqIf* const tisci_if_EPWM0[] |
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const struct Sciclient_rmIrqIf EPWM3_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_40_40 |
const struct Sciclient_rmIrqIf* const tisci_if_EPWM3[] |
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const struct Sciclient_rmIrqIf EPWM6_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_41_41 |
const struct Sciclient_rmIrqIf* const tisci_if_EPWM6[] |
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const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_81_81 |
const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_23_23 |
const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_33_33 |
const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_hw1_push_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_37_37 |
const struct Sciclient_rmIrqIf PCIE0_pcie_ptm_valid_pulse_4_4_to_TIMESYNC_EVENT_INTROUTER0_in_38_38 |
const struct Sciclient_rmIrqIf* const tisci_if_PCIE0[] |
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const struct Sciclient_rmIrqNode* const gRmIrqTree[] |
const uint32_t gRmIrqTreeCount = sizeof(gRmIrqTree)/sizeof(gRmIrqTree[0]) |