65 #define UDMA_INST_ID_BCDMA_0 (UDMA_INST_ID_2) 67 #define UDMA_INST_ID_PKTDMA_0 (UDMA_INST_ID_3) 69 #define UDMA_INST_ID_START (UDMA_INST_ID_2) 71 #define UDMA_INST_ID_MAX (UDMA_INST_ID_3) 73 #define UDMA_NUM_INST_ID (UDMA_INST_ID_MAX - UDMA_INST_ID_START + 1U) 85 #define UDMA_SOC_CFG_UDMAP_PRESENT (0U) 88 #define UDMA_SOC_CFG_LCDMA_PRESENT (1U) 91 #define UDMA_SOC_CFG_PROXY_PRESENT (0U) 94 #define UDMA_SOC_CFG_CLEC_PRESENT (0U) 97 #define UDMA_SOC_CFG_RA_NORMAL_PRESENT (0U) 100 #define UDMA_SOC_CFG_RA_LCDMA_PRESENT (1U) 103 #define UDMA_SOC_CFG_RING_MON_PRESENT (0U) 106 #define UDMA_SOC_CFG_APPLY_RING_WORKAROUND (0U) 118 #define UDMA_TX_UHC_CHANS_FDEPTH (CSL_DMSS_UDMAP_TX_UHC_CHANS_FDEPTH) 120 #define UDMA_TX_HC_CHANS_FDEPTH (CSL_DMSS_UDMAP_TX_HC_CHANS_FDEPTH) 122 #define UDMA_TX_CHANS_FDEPTH (CSL_DMSS_UDMAP_TX_CHANS_FDEPTH) 134 #define UDMA_RINGACC_ASEL_ENDPOINT_PHYSADDR (CSL_LCDMA_RINGACC_ASEL_ENDPOINT_PHYSADDR) 136 #define UDMA_RINGACC_ASEL_ENDPOINT_PCIE0 (CSL_LCDMA_RINGACC_ASEL_ENDPOINT_PCIE0) 138 #define UDMA_RINGACC_ASEL_ENDPOINT_ACP_WR_ALLOC (CSL_LCDMA_RINGACC_ASEL_ENDPOINT_ACP_WR_ALLOC) 140 #define UDMA_RINGACC_ASEL_ENDPOINT_ACP_RD_ALLOC (CSL_LCDMA_RINGACC_ASEL_ENDPOINT_ACP_RD_ALLOC) 144 #define UDMA_RING_MODE_INVALID (CSL_LCDMA_RINGACC_RING_MODE_INVALID) 147 #define UDMA_NUM_MAPPED_TX_GROUP (4U) 156 #define UDMA_MAPPED_TX_GROUP_CPSW (UDMA_MAPPED_GROUP0) 157 #define UDMA_MAPPED_TX_GROUP_SAUL (UDMA_MAPPED_GROUP1) 158 #define UDMA_MAPPED_TX_GROUP_ICSSG_0 (UDMA_MAPPED_GROUP2) 159 #define UDMA_MAPPED_TX_GROUP_ICSSG_1 (UDMA_MAPPED_GROUP3) 163 #define UDMA_NUM_MAPPED_RX_GROUP (4U) 172 #define UDMA_MAPPED_RX_GROUP_CPSW (UDMA_MAPPED_GROUP4) 173 #define UDMA_MAPPED_RX_GROUP_SAUL (UDMA_MAPPED_GROUP5) 174 #define UDMA_MAPPED_RX_GROUP_ICSSG_0 (UDMA_MAPPED_GROUP6) 175 #define UDMA_MAPPED_RX_GROUP_ICSSG_1 (UDMA_MAPPED_GROUP7) 179 #define UDMA_NUM_UTC_INSTANCE (CSL_DMSS_UTC_CNT) 203 #define UDMA_CORE_ID_MPU1_0 (0U) 204 #define UDMA_CORE_ID_MCU2_0 (1U) 205 #define UDMA_CORE_ID_MCU2_1 (2U) 206 #define UDMA_CORE_ID_MCU1_0 (3U) 207 #define UDMA_CORE_ID_MCU1_1 (4U) 208 #define UDMA_CORE_ID_M4F_0 (5U) 210 #define UDMA_NUM_CORE (6U) 222 #define UDMA_RM_RES_ID_BC_UHC (0U) 224 #define UDMA_RM_RES_ID_BC_HC (1U) 226 #define UDMA_RM_RES_ID_BC (2U) 228 #define UDMA_RM_RES_ID_TX_UHC (3U) 230 #define UDMA_RM_RES_ID_TX_HC (4U) 232 #define UDMA_RM_RES_ID_TX (5U) 234 #define UDMA_RM_RES_ID_RX_UHC (6U) 236 #define UDMA_RM_RES_ID_RX_HC (7U) 238 #define UDMA_RM_RES_ID_RX (8U) 240 #define UDMA_RM_RES_ID_GLOBAL_EVENT (9U) 242 #define UDMA_RM_RES_ID_VINTR (10U) 244 #define UDMA_RM_RES_ID_MAPPED_TX_CPSW (11U) 246 #define UDMA_RM_RES_ID_MAPPED_TX_SAUL_0 (12U) 248 #define UDMA_RM_RES_ID_MAPPED_TX_SAUL_1 (13U) 250 #define UDMA_RM_RES_ID_MAPPED_TX_ICSSG_0 (14U) 252 #define UDMA_RM_RES_ID_MAPPED_TX_ICSSG_1 (15U) 254 #define UDMA_RM_RES_ID_MAPPED_RX_CPSW (16U) 256 #define UDMA_RM_RES_ID_MAPPED_RX_SAUL_0 (17U) 258 #define UDMA_RM_RES_ID_MAPPED_RX_SAUL_1 (18U) 260 #define UDMA_RM_RES_ID_MAPPED_RX_SAUL_2 (19U) 262 #define UDMA_RM_RES_ID_MAPPED_RX_SAUL_3 (20U) 264 #define UDMA_RM_RES_ID_MAPPED_RX_ICSSG_0 (21U) 266 #define UDMA_RM_RES_ID_MAPPED_RX_ICSSG_1 (22U) 268 #define UDMA_RM_RES_ID_MAPPED_TX_RING_CPSW (23U) 270 #define UDMA_RM_RES_ID_MAPPED_TX_RING_SAUL_0 (24U) 272 #define UDMA_RM_RES_ID_MAPPED_TX_RING_SAUL_1 (25U) 274 #define UDMA_RM_RES_ID_MAPPED_TX_RING_ICSSG_0 (26U) 276 #define UDMA_RM_RES_ID_MAPPED_TX_RING_ICSSG_1 (27U) 278 #define UDMA_RM_RES_ID_MAPPED_RX_RING_CPSW (28U) 280 #define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_0 (29U) 282 #define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_1 (30U) 284 #define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_2 (31U) 286 #define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_3 (32U) 288 #define UDMA_RM_RES_ID_MAPPED_RX_RING_ICSSG_0 (33U) 290 #define UDMA_RM_RES_ID_MAPPED_RX_RING_ICSSG_1 (34U) 292 #define UDMA_RM_NUM_BCDMA_RES (11U) 294 #define UDMA_RM_NUM_PKTDMA_RES (35U) 296 #define UDMA_RM_NUM_RES (35U) 301 #define UDMA_RM_NUM_SHARED_RES (2U) 304 #define UDMA_RM_SHARED_RES_MAX_INST (UDMA_NUM_CORE) 315 #define UDMA_PSIL_CH_CPSW2_TX (CSL_PSILCFG_DMSS_CPSW2_PSILD_THREAD_OFFSET) 316 #define UDMA_PSIL_CH_SAUL0_TX (CSL_PSILCFG_DMSS_SAUL0_PSILD_THREAD_OFFSET) 317 #define UDMA_PSIL_CH_ICSS_G0_TX (CSL_PSILCFG_DMSS_ICSS_G0_PSILD_THREAD_OFFSET) 318 #define UDMA_PSIL_CH_ICSS_G1_TX (CSL_PSILCFG_DMSS_ICSS_G1_PSILD_THREAD_OFFSET) 320 #define UDMA_PSIL_CH_CPSW2_RX (CSL_PSILCFG_DMSS_CPSW2_PSILS_THREAD_OFFSET) 321 #define UDMA_PSIL_CH_SAUL0_RX (CSL_PSILCFG_DMSS_SAUL0_PSILS_THREAD_OFFSET) 322 #define UDMA_PSIL_CH_ICSS_G0_RX (CSL_PSILCFG_DMSS_ICSS_G0_PSILS_THREAD_OFFSET) 323 #define UDMA_PSIL_CH_ICSS_G1_RX (CSL_PSILCFG_DMSS_ICSS_G1_PSILS_THREAD_OFFSET) 326 #define UDMA_PSIL_CH_CPSW2_TX_CNT (CSL_PSILCFG_DMSS_CPSW2_PSILD_THREAD_CNT) 327 #define UDMA_PSIL_CH_SAUL0_TX_CNT (CSL_PSILCFG_DMSS_SAUL0_PSILD_THREAD_CNT) 328 #define UDMA_PSIL_CH_ICSS_G0_TX_CNT (CSL_PSILCFG_DMSS_ICSS_G0_PSILD_THREAD_CNT) 329 #define UDMA_PSIL_CH_ICSS_G1_TX_CNT (CSL_PSILCFG_DMSS_ICSS_G1_PSILD_THREAD_CNT) 331 #define UDMA_PSIL_CH_CPSW2_RX_CNT (CSL_PSILCFG_DMSS_CPSW2_PSILS_THREAD_CNT) 332 #define UDMA_PSIL_CH_SAUL0_RX_CNT (CSL_PSILCFG_DMSS_SAUL0_PSILS_THREAD_CNT) 333 #define UDMA_PSIL_CH_ICSS_G0_RX_CNT (CSL_PSILCFG_DMSS_ICSS_G0_PSILS_THREAD_CNT) 334 #define UDMA_PSIL_CH_ICSS_G1_RX_CNT (CSL_PSILCFG_DMSS_ICSS_G1_PSILS_THREAD_CNT) 360 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_TX (CSL_PDMA_CH_MAIN0_MCSPI0_CH0_TX) 361 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_TX (CSL_PDMA_CH_MAIN0_MCSPI0_CH1_TX) 362 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_TX (CSL_PDMA_CH_MAIN0_MCSPI0_CH2_TX) 363 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_TX (CSL_PDMA_CH_MAIN0_MCSPI0_CH3_TX) 364 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_TX (CSL_PDMA_CH_MAIN0_MCSPI1_CH0_TX) 365 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_TX (CSL_PDMA_CH_MAIN0_MCSPI1_CH1_TX) 366 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_TX (CSL_PDMA_CH_MAIN0_MCSPI1_CH2_TX) 367 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_TX (CSL_PDMA_CH_MAIN0_MCSPI1_CH3_TX) 368 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_TX (CSL_PDMA_CH_MAIN0_MCSPI2_CH0_TX) 369 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_TX (CSL_PDMA_CH_MAIN0_MCSPI2_CH1_TX) 370 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_TX (CSL_PDMA_CH_MAIN0_MCSPI2_CH2_TX) 371 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_TX (CSL_PDMA_CH_MAIN0_MCSPI2_CH3_TX) 372 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_TX (CSL_PDMA_CH_MAIN0_MCSPI3_CH0_TX) 373 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_TX (CSL_PDMA_CH_MAIN0_MCSPI3_CH1_TX) 374 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_TX (CSL_PDMA_CH_MAIN0_MCSPI3_CH2_TX) 375 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_TX (CSL_PDMA_CH_MAIN0_MCSPI3_CH3_TX) 379 #define UDMA_PDMA_CH_MAIN0_UART0_TX (CSL_PDMA_CH_MAIN0_UART0_CH0_TX) 380 #define UDMA_PDMA_CH_MAIN0_UART1_TX (CSL_PDMA_CH_MAIN0_UART1_CH0_TX) 396 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_RX (CSL_PDMA_CH_MAIN0_MCSPI0_CH0_RX) 397 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_RX (CSL_PDMA_CH_MAIN0_MCSPI0_CH1_RX) 398 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_RX (CSL_PDMA_CH_MAIN0_MCSPI0_CH2_RX) 399 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_RX (CSL_PDMA_CH_MAIN0_MCSPI0_CH3_RX) 400 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_RX (CSL_PDMA_CH_MAIN0_MCSPI1_CH0_RX) 401 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_RX (CSL_PDMA_CH_MAIN0_MCSPI1_CH1_RX) 402 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_RX (CSL_PDMA_CH_MAIN0_MCSPI1_CH2_RX) 403 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_RX (CSL_PDMA_CH_MAIN0_MCSPI1_CH3_RX) 404 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_RX (CSL_PDMA_CH_MAIN0_MCSPI2_CH0_RX) 405 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_RX (CSL_PDMA_CH_MAIN0_MCSPI2_CH1_RX) 406 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_RX (CSL_PDMA_CH_MAIN0_MCSPI2_CH2_RX) 407 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_RX (CSL_PDMA_CH_MAIN0_MCSPI2_CH3_RX) 408 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_RX (CSL_PDMA_CH_MAIN0_MCSPI3_CH0_RX) 409 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_RX (CSL_PDMA_CH_MAIN0_MCSPI3_CH1_RX) 410 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_RX (CSL_PDMA_CH_MAIN0_MCSPI3_CH2_RX) 411 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_RX (CSL_PDMA_CH_MAIN0_MCSPI3_CH3_RX) 415 #define UDMA_PDMA_CH_MAIN0_UART0_RX (CSL_PDMA_CH_MAIN0_UART0_CH0_RX) 416 #define UDMA_PDMA_CH_MAIN0_UART1_RX (CSL_PDMA_CH_MAIN0_UART1_CH0_RX) 432 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_TX (CSL_PDMA_CH_MAIN1_MCSPI4_CH0_TX) 433 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_TX (CSL_PDMA_CH_MAIN1_MCSPI4_CH1_TX) 434 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_TX (CSL_PDMA_CH_MAIN1_MCSPI4_CH2_TX) 435 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_TX (CSL_PDMA_CH_MAIN1_MCSPI4_CH3_TX) 439 #define UDMA_PDMA_CH_MAIN1_UART2_TX (CSL_PDMA_CH_MAIN1_UART2_CH0_TX) 440 #define UDMA_PDMA_CH_MAIN1_UART3_TX (CSL_PDMA_CH_MAIN1_UART3_CH0_TX) 441 #define UDMA_PDMA_CH_MAIN1_UART4_TX (CSL_PDMA_CH_MAIN1_UART4_CH0_TX) 442 #define UDMA_PDMA_CH_MAIN1_UART5_TX (CSL_PDMA_CH_MAIN1_UART5_CH0_TX) 443 #define UDMA_PDMA_CH_MAIN1_UART6_TX (CSL_PDMA_CH_MAIN1_UART6_CH0_TX) 447 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH0_TX (CSL_PDMA_CH_MAIN1_MCAN0_CH0_TX) 448 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH1_TX (CSL_PDMA_CH_MAIN1_MCAN0_CH1_TX) 449 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH2_TX (CSL_PDMA_CH_MAIN1_MCAN0_CH2_TX) 450 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH0_TX (CSL_PDMA_CH_MAIN1_MCAN1_CH0_TX) 451 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH1_TX (CSL_PDMA_CH_MAIN1_MCAN1_CH1_TX) 452 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH2_TX (CSL_PDMA_CH_MAIN1_MCAN1_CH2_TX) 468 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_RX (CSL_PDMA_CH_MAIN1_MCSPI4_CH0_RX) 469 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_RX (CSL_PDMA_CH_MAIN1_MCSPI4_CH1_RX) 470 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_RX (CSL_PDMA_CH_MAIN1_MCSPI4_CH2_RX) 471 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_RX (CSL_PDMA_CH_MAIN1_MCSPI4_CH3_RX) 475 #define UDMA_PDMA_CH_MAIN1_UART2_RX (CSL_PDMA_CH_MAIN1_UART2_CH0_RX) 476 #define UDMA_PDMA_CH_MAIN1_UART3_RX (CSL_PDMA_CH_MAIN1_UART3_CH0_RX) 477 #define UDMA_PDMA_CH_MAIN1_UART4_RX (CSL_PDMA_CH_MAIN1_UART4_CH0_RX) 478 #define UDMA_PDMA_CH_MAIN1_UART5_RX (CSL_PDMA_CH_MAIN1_UART5_CH0_RX) 479 #define UDMA_PDMA_CH_MAIN1_UART6_RX (CSL_PDMA_CH_MAIN1_UART6_CH0_RX) 483 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH0_RX (CSL_PDMA_CH_MAIN1_MCAN0_CH0_RX) 484 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH1_RX (CSL_PDMA_CH_MAIN1_MCAN0_CH1_RX) 485 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH2_RX (CSL_PDMA_CH_MAIN1_MCAN0_CH2_RX) 486 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH0_RX (CSL_PDMA_CH_MAIN1_MCAN1_CH0_RX) 487 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH1_RX (CSL_PDMA_CH_MAIN1_MCAN1_CH1_RX) 488 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH2_RX (CSL_PDMA_CH_MAIN1_MCAN1_CH2_RX) 492 #define UDMA_PDMA_CH_MAIN1_ADC0_CH0_RX (CSL_PDMA_CH_MAIN1_ADC0_CH0_RX) 493 #define UDMA_PDMA_CH_MAIN1_ADC0_CH1_RX (CSL_PDMA_CH_MAIN1_ADC0_CH1_RX) uint32_t Udma_isCacheCoherent(void)
Returns TRUE if the memory is cache coherent.
uint32_t numFreeRing
Definition: udma_soc.h:508
uint32_t Udma_getCoreId(void)
Returns the core ID.
uint32_t startFreeRing
Definition: udma_soc.h:506
UDMA mapped channel ring attributes.
Definition: udma_soc.h:502
uint32_t defaultRing
Definition: udma_soc.h:504
uint16_t Udma_getCoreSciDevId(void)
Returns the core tisci device ID.