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PDK API Guide for AM64x
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UDMA Low Level Driver AM64x SOC specific file.
Go to the source code of this file.
Data Structures | |
struct | Udma_MappedChRingAttributes |
UDMA mapped channel ring attributes. More... | |
Macros | |
#define | UDMA_RING_MODE_INVALID (CSL_LCDMA_RINGACC_RING_MODE_INVALID) |
Invalid Ring Mode. More... | |
#define | UDMA_NUM_MAPPED_TX_GROUP (4U) |
Number of Mapped TX Group. More... | |
#define | UDMA_NUM_MAPPED_RX_GROUP (4U) |
Number of Mapped RX Group. More... | |
#define | UDMA_NUM_UTC_INSTANCE (CSL_DMSS_UTC_CNT) |
Number of UTC instance. More... | |
#define | UDMA_RM_NUM_SHARED_RES (2U) |
Total number of shared resources - Global_Event/IR Intr. More... | |
#define | UDMA_RM_SHARED_RES_MAX_INST (UDMA_NUM_CORE) |
Maximum no.of instances to split a shared resource. This should be max(UDMA_NUM_CORE,UDMA_NUM_INST_ID) More... | |
UDMA Instance ID specific to SOC | |
#define | UDMA_INST_ID_BCDMA_0 (UDMA_INST_ID_2) |
BCDMA instance. More... | |
#define | UDMA_INST_ID_PKTDMA_0 (UDMA_INST_ID_3) |
PKTDMA instance. More... | |
#define | UDMA_INST_ID_START (UDMA_INST_ID_2) |
Start of UDMA instance. More... | |
#define | UDMA_INST_ID_MAX (UDMA_INST_ID_3) |
Maximum number of UDMA instance. More... | |
#define | UDMA_NUM_INST_ID (UDMA_INST_ID_MAX - UDMA_INST_ID_START + 1U) |
Total number of UDMA instances. More... | |
UDMA SOC Configuration | |
#define | UDMA_SOC_CFG_UDMAP_PRESENT (0U) |
Flag to indicate UDMAP module is present or not in the SOC. More... | |
#define | UDMA_SOC_CFG_LCDMA_PRESENT (1U) |
Flag to indicate LCDMA module is present or not in the SOC. More... | |
#define | UDMA_SOC_CFG_PROXY_PRESENT (0U) |
Flag to indicate Proxy is present or not in the SOC. More... | |
#define | UDMA_SOC_CFG_CLEC_PRESENT (0U) |
Flag to indicate Clec is present or not in the SOC. More... | |
#define | UDMA_SOC_CFG_RA_NORMAL_PRESENT (0U) |
Flag to indicate Normal RA is present or not in the SOC. More... | |
#define | UDMA_SOC_CFG_RA_LCDMA_PRESENT (1U) |
Flag to indicate LCDMA RA is present or not in the SOC. More... | |
#define | UDMA_SOC_CFG_RING_MON_PRESENT (0U) |
Flag to indicate Ring Monitor is present or not in the SOC. More... | |
#define | UDMA_SOC_CFG_APPLY_RING_WORKAROUND (0U) |
Flag to indicate the SOC needs ring reset workaround. More... | |
UDMA Tx Channels FDEPTH | |
#define | UDMA_TX_UHC_CHANS_FDEPTH (CSL_DMSS_UDMAP_TX_UHC_CHANS_FDEPTH) |
Tx Ultra High Capacity Channel FDEPTH. More... | |
#define | UDMA_TX_HC_CHANS_FDEPTH (CSL_DMSS_UDMAP_TX_HC_CHANS_FDEPTH) |
Tx High Capacity Channel FDEPTH. More... | |
#define | UDMA_TX_CHANS_FDEPTH (CSL_DMSS_UDMAP_TX_CHANS_FDEPTH) |
Tx Normal Channel FDEPTH. More... | |
UDMA Ringacc address select (asel) endpoint | |
#define | UDMA_RINGACC_ASEL_ENDPOINT_PHYSADDR (CSL_LCDMA_RINGACC_ASEL_ENDPOINT_PHYSADDR) |
Physical address (normal) More... | |
#define | UDMA_RINGACC_ASEL_ENDPOINT_PCIE0 (CSL_LCDMA_RINGACC_ASEL_ENDPOINT_PCIE0) |
PCIE0. More... | |
#define | UDMA_RINGACC_ASEL_ENDPOINT_ACP_WR_ALLOC (CSL_LCDMA_RINGACC_ASEL_ENDPOINT_ACP_WR_ALLOC) |
ARM ACP port: write-allocate cacheable, bufferable. More... | |
#define | UDMA_RINGACC_ASEL_ENDPOINT_ACP_RD_ALLOC (CSL_LCDMA_RINGACC_ASEL_ENDPOINT_ACP_RD_ALLOC) |
ARM ACP port: read-allocate, cacheable, bufferable. More... | |
Mapped TX Group specific to a SOC | |
#define | UDMA_MAPPED_TX_GROUP_CPSW (UDMA_MAPPED_GROUP0) |
#define | UDMA_MAPPED_TX_GROUP_SAUL (UDMA_MAPPED_GROUP1) |
#define | UDMA_MAPPED_TX_GROUP_ICSSG_0 (UDMA_MAPPED_GROUP2) |
#define | UDMA_MAPPED_TX_GROUP_ICSSG_1 (UDMA_MAPPED_GROUP3) |
Mapped RX Group specific to a SOC | |
#define | UDMA_MAPPED_RX_GROUP_CPSW (UDMA_MAPPED_GROUP4) |
#define | UDMA_MAPPED_RX_GROUP_SAUL (UDMA_MAPPED_GROUP5) |
#define | UDMA_MAPPED_RX_GROUP_ICSSG_0 (UDMA_MAPPED_GROUP6) |
#define | UDMA_MAPPED_RX_GROUP_ICSSG_1 (UDMA_MAPPED_GROUP7) |
Core ID specific to a SOC | |
#define | UDMA_CORE_ID_MPU1_0 (0U) |
#define | UDMA_CORE_ID_MCU2_0 (1U) |
#define | UDMA_CORE_ID_MCU2_1 (2U) |
#define | UDMA_CORE_ID_MCU1_0 (3U) |
#define | UDMA_CORE_ID_MCU1_1 (4U) |
#define | UDMA_CORE_ID_M4F_0 (5U) |
#define | UDMA_NUM_CORE (6U) |
UDMA Resources ID | |
#define | UDMA_RM_RES_ID_BC_UHC (0U) |
Ultra High Capacity Block Copy Channels. More... | |
#define | UDMA_RM_RES_ID_BC_HC (1U) |
High Capacity Block Copy Channels. More... | |
#define | UDMA_RM_RES_ID_BC (2U) |
Normal Capacity Block Copy Channels. More... | |
#define | UDMA_RM_RES_ID_TX_UHC (3U) |
Ultra High Capacity TX Channels. More... | |
#define | UDMA_RM_RES_ID_TX_HC (4U) |
High Capacity TX Channels. More... | |
#define | UDMA_RM_RES_ID_TX (5U) |
Normal Capacity TX Channels. More... | |
#define | UDMA_RM_RES_ID_RX_UHC (6U) |
Ultra High Capacity RX Channels. More... | |
#define | UDMA_RM_RES_ID_RX_HC (7U) |
High Capacity RX Channels. More... | |
#define | UDMA_RM_RES_ID_RX (8U) |
Normal Capacity RX Channels. More... | |
#define | UDMA_RM_RES_ID_GLOBAL_EVENT (9U) |
Global Event. More... | |
#define | UDMA_RM_RES_ID_VINTR (10U) |
Virtual Interrupts. More... | |
#define | UDMA_RM_RES_ID_MAPPED_TX_CPSW (11U) |
[Pktdma Only] Mapped TX Channels for CPSW More... | |
#define | UDMA_RM_RES_ID_MAPPED_TX_SAUL_0 (12U) |
[Pktdma Only] Mapped TX Channels for SAUL_0 More... | |
#define | UDMA_RM_RES_ID_MAPPED_TX_SAUL_1 (13U) |
[Pktdma Only] Mapped TX Channels for SAUL_1 More... | |
#define | UDMA_RM_RES_ID_MAPPED_TX_ICSSG_0 (14U) |
[Pktdma Only] Mapped TX Channels for ICSSG_0 More... | |
#define | UDMA_RM_RES_ID_MAPPED_TX_ICSSG_1 (15U) |
[Pktdma Only] Mapped TX Channels for ICSSG_1 More... | |
#define | UDMA_RM_RES_ID_MAPPED_RX_CPSW (16U) |
[Pktdma Only] Mapped RX Channels for CPSW More... | |
#define | UDMA_RM_RES_ID_MAPPED_RX_SAUL_0 (17U) |
[Pktdma Only] Mapped RX Channels for SAUL_0 More... | |
#define | UDMA_RM_RES_ID_MAPPED_RX_SAUL_1 (18U) |
[Pktdma Only] Mapped RX Channels for SAUL_1 More... | |
#define | UDMA_RM_RES_ID_MAPPED_RX_SAUL_2 (19U) |
[Pktdma Only] Mapped RX Channels for SAUL_2 More... | |
#define | UDMA_RM_RES_ID_MAPPED_RX_SAUL_3 (20U) |
[Pktdma Only] Mapped RX Channels for SAUL_3 More... | |
#define | UDMA_RM_RES_ID_MAPPED_RX_ICSSG_0 (21U) |
[Pktdma Only] Mapped RX Channels for ICSSG_0 More... | |
#define | UDMA_RM_RES_ID_MAPPED_RX_ICSSG_1 (22U) |
[Pktdma Only] Mapped RX Channels for ICSSG_1 More... | |
#define | UDMA_RM_RES_ID_MAPPED_TX_RING_CPSW (23U) |
[Pktdma Only] Mapped TX Rings for CPSW More... | |
#define | UDMA_RM_RES_ID_MAPPED_TX_RING_SAUL_0 (24U) |
[Pktdma Only] Mapped TX Rings for SAUL_0 More... | |
#define | UDMA_RM_RES_ID_MAPPED_TX_RING_SAUL_1 (25U) |
[Pktdma Only] Mapped TX Rings for SAUL_1 More... | |
#define | UDMA_RM_RES_ID_MAPPED_TX_RING_ICSSG_0 (26U) |
[Pktdma Only] Mapped TX Rings for ICSSG_0 More... | |
#define | UDMA_RM_RES_ID_MAPPED_TX_RING_ICSSG_1 (27U) |
[Pktdma Only] Mapped TX Rings for ICSSG_1 More... | |
#define | UDMA_RM_RES_ID_MAPPED_RX_RING_CPSW (28U) |
[Pktdma Only] Mapped RX Rings for CPSW More... | |
#define | UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_0 (29U) |
[Pktdma Only] Mapped RX Rings for SAUL_0 More... | |
#define | UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_1 (30U) |
[Pktdma Only] Mapped RX Rings for SAUL_1 More... | |
#define | UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_2 (31U) |
[Pktdma Only] Mapped RX Rings for SAUL_2 More... | |
#define | UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_3 (32U) |
[Pktdma Only] Mapped RX Rings for SAUL_3 More... | |
#define | UDMA_RM_RES_ID_MAPPED_RX_RING_ICSSG_0 (33U) |
[Pktdma Only] Mapped RX Rings for ICSSG_0 More... | |
#define | UDMA_RM_RES_ID_MAPPED_RX_RING_ICSSG_1 (34U) |
[Pktdma Only] Mapped RX Rings for ICSSG_1 More... | |
#define | UDMA_RM_NUM_BCDMA_RES (11U) |
Total number of BCDMA resources. More... | |
#define | UDMA_RM_NUM_PKTDMA_RES (35U) |
Total number of PKTDMA resources. More... | |
#define | UDMA_RM_NUM_RES (35U) |
Total number of resources. More... | |
PSIL Channels | |
#define | UDMA_PSIL_CH_CPSW2_TX (CSL_PSILCFG_DMSS_CPSW2_PSILD_THREAD_OFFSET) |
#define | UDMA_PSIL_CH_SAUL0_TX (CSL_PSILCFG_DMSS_SAUL0_PSILD_THREAD_OFFSET) |
#define | UDMA_PSIL_CH_ICSS_G0_TX (CSL_PSILCFG_DMSS_ICSS_G0_PSILD_THREAD_OFFSET) |
#define | UDMA_PSIL_CH_ICSS_G1_TX (CSL_PSILCFG_DMSS_ICSS_G1_PSILD_THREAD_OFFSET) |
#define | UDMA_PSIL_CH_CPSW2_RX (CSL_PSILCFG_DMSS_CPSW2_PSILS_THREAD_OFFSET) |
#define | UDMA_PSIL_CH_SAUL0_RX (CSL_PSILCFG_DMSS_SAUL0_PSILS_THREAD_OFFSET) |
#define | UDMA_PSIL_CH_ICSS_G0_RX (CSL_PSILCFG_DMSS_ICSS_G0_PSILS_THREAD_OFFSET) |
#define | UDMA_PSIL_CH_ICSS_G1_RX (CSL_PSILCFG_DMSS_ICSS_G1_PSILS_THREAD_OFFSET) |
#define | UDMA_PSIL_CH_CPSW2_TX_CNT (CSL_PSILCFG_DMSS_CPSW2_PSILD_THREAD_CNT) |
#define | UDMA_PSIL_CH_SAUL0_TX_CNT (CSL_PSILCFG_DMSS_SAUL0_PSILD_THREAD_CNT) |
#define | UDMA_PSIL_CH_ICSS_G0_TX_CNT (CSL_PSILCFG_DMSS_ICSS_G0_PSILD_THREAD_CNT) |
#define | UDMA_PSIL_CH_ICSS_G1_TX_CNT (CSL_PSILCFG_DMSS_ICSS_G1_PSILD_THREAD_CNT) |
#define | UDMA_PSIL_CH_CPSW2_RX_CNT (CSL_PSILCFG_DMSS_CPSW2_PSILS_THREAD_CNT) |
#define | UDMA_PSIL_CH_SAUL0_RX_CNT (CSL_PSILCFG_DMSS_SAUL0_PSILS_THREAD_CNT) |
#define | UDMA_PSIL_CH_ICSS_G0_RX_CNT (CSL_PSILCFG_DMSS_ICSS_G0_PSILS_THREAD_CNT) |
#define | UDMA_PSIL_CH_ICSS_G1_RX_CNT (CSL_PSILCFG_DMSS_ICSS_G1_PSILS_THREAD_CNT) |
Main0 TX PDMA Channels | |
#define | UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_TX (CSL_PDMA_CH_MAIN0_MCSPI0_CH0_TX) |
#define | UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_TX (CSL_PDMA_CH_MAIN0_MCSPI0_CH1_TX) |
#define | UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_TX (CSL_PDMA_CH_MAIN0_MCSPI0_CH2_TX) |
#define | UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_TX (CSL_PDMA_CH_MAIN0_MCSPI0_CH3_TX) |
#define | UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_TX (CSL_PDMA_CH_MAIN0_MCSPI1_CH0_TX) |
#define | UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_TX (CSL_PDMA_CH_MAIN0_MCSPI1_CH1_TX) |
#define | UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_TX (CSL_PDMA_CH_MAIN0_MCSPI1_CH2_TX) |
#define | UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_TX (CSL_PDMA_CH_MAIN0_MCSPI1_CH3_TX) |
#define | UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_TX (CSL_PDMA_CH_MAIN0_MCSPI2_CH0_TX) |
#define | UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_TX (CSL_PDMA_CH_MAIN0_MCSPI2_CH1_TX) |
#define | UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_TX (CSL_PDMA_CH_MAIN0_MCSPI2_CH2_TX) |
#define | UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_TX (CSL_PDMA_CH_MAIN0_MCSPI2_CH3_TX) |
#define | UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_TX (CSL_PDMA_CH_MAIN0_MCSPI3_CH0_TX) |
#define | UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_TX (CSL_PDMA_CH_MAIN0_MCSPI3_CH1_TX) |
#define | UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_TX (CSL_PDMA_CH_MAIN0_MCSPI3_CH2_TX) |
#define | UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_TX (CSL_PDMA_CH_MAIN0_MCSPI3_CH3_TX) |
#define | UDMA_PDMA_CH_MAIN0_UART0_TX (CSL_PDMA_CH_MAIN0_UART0_CH0_TX) |
#define | UDMA_PDMA_CH_MAIN0_UART1_TX (CSL_PDMA_CH_MAIN0_UART1_CH0_TX) |
Main0 RX PDMA Channels | |
#define | UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_RX (CSL_PDMA_CH_MAIN0_MCSPI0_CH0_RX) |
#define | UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_RX (CSL_PDMA_CH_MAIN0_MCSPI0_CH1_RX) |
#define | UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_RX (CSL_PDMA_CH_MAIN0_MCSPI0_CH2_RX) |
#define | UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_RX (CSL_PDMA_CH_MAIN0_MCSPI0_CH3_RX) |
#define | UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_RX (CSL_PDMA_CH_MAIN0_MCSPI1_CH0_RX) |
#define | UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_RX (CSL_PDMA_CH_MAIN0_MCSPI1_CH1_RX) |
#define | UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_RX (CSL_PDMA_CH_MAIN0_MCSPI1_CH2_RX) |
#define | UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_RX (CSL_PDMA_CH_MAIN0_MCSPI1_CH3_RX) |
#define | UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_RX (CSL_PDMA_CH_MAIN0_MCSPI2_CH0_RX) |
#define | UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_RX (CSL_PDMA_CH_MAIN0_MCSPI2_CH1_RX) |
#define | UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_RX (CSL_PDMA_CH_MAIN0_MCSPI2_CH2_RX) |
#define | UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_RX (CSL_PDMA_CH_MAIN0_MCSPI2_CH3_RX) |
#define | UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_RX (CSL_PDMA_CH_MAIN0_MCSPI3_CH0_RX) |
#define | UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_RX (CSL_PDMA_CH_MAIN0_MCSPI3_CH1_RX) |
#define | UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_RX (CSL_PDMA_CH_MAIN0_MCSPI3_CH2_RX) |
#define | UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_RX (CSL_PDMA_CH_MAIN0_MCSPI3_CH3_RX) |
#define | UDMA_PDMA_CH_MAIN0_UART0_RX (CSL_PDMA_CH_MAIN0_UART0_CH0_RX) |
#define | UDMA_PDMA_CH_MAIN0_UART1_RX (CSL_PDMA_CH_MAIN0_UART1_CH0_RX) |
Main1 TX PDMA Channels | |
#define | UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_TX (CSL_PDMA_CH_MAIN1_MCSPI4_CH0_TX) |
#define | UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_TX (CSL_PDMA_CH_MAIN1_MCSPI4_CH1_TX) |
#define | UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_TX (CSL_PDMA_CH_MAIN1_MCSPI4_CH2_TX) |
#define | UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_TX (CSL_PDMA_CH_MAIN1_MCSPI4_CH3_TX) |
#define | UDMA_PDMA_CH_MAIN1_UART2_TX (CSL_PDMA_CH_MAIN1_UART2_CH0_TX) |
#define | UDMA_PDMA_CH_MAIN1_UART3_TX (CSL_PDMA_CH_MAIN1_UART3_CH0_TX) |
#define | UDMA_PDMA_CH_MAIN1_UART4_TX (CSL_PDMA_CH_MAIN1_UART4_CH0_TX) |
#define | UDMA_PDMA_CH_MAIN1_UART5_TX (CSL_PDMA_CH_MAIN1_UART5_CH0_TX) |
#define | UDMA_PDMA_CH_MAIN1_UART6_TX (CSL_PDMA_CH_MAIN1_UART6_CH0_TX) |
#define | UDMA_PDMA_CH_MAIN1_MCAN0_CH0_TX (CSL_PDMA_CH_MAIN1_MCAN0_CH0_TX) |
#define | UDMA_PDMA_CH_MAIN1_MCAN0_CH1_TX (CSL_PDMA_CH_MAIN1_MCAN0_CH1_TX) |
#define | UDMA_PDMA_CH_MAIN1_MCAN0_CH2_TX (CSL_PDMA_CH_MAIN1_MCAN0_CH2_TX) |
#define | UDMA_PDMA_CH_MAIN1_MCAN1_CH0_TX (CSL_PDMA_CH_MAIN1_MCAN1_CH0_TX) |
#define | UDMA_PDMA_CH_MAIN1_MCAN1_CH1_TX (CSL_PDMA_CH_MAIN1_MCAN1_CH1_TX) |
#define | UDMA_PDMA_CH_MAIN1_MCAN1_CH2_TX (CSL_PDMA_CH_MAIN1_MCAN1_CH2_TX) |
Main1 RX PDMA Channels | |
#define | UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_RX (CSL_PDMA_CH_MAIN1_MCSPI4_CH0_RX) |
#define | UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_RX (CSL_PDMA_CH_MAIN1_MCSPI4_CH1_RX) |
#define | UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_RX (CSL_PDMA_CH_MAIN1_MCSPI4_CH2_RX) |
#define | UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_RX (CSL_PDMA_CH_MAIN1_MCSPI4_CH3_RX) |
#define | UDMA_PDMA_CH_MAIN1_UART2_RX (CSL_PDMA_CH_MAIN1_UART2_CH0_RX) |
#define | UDMA_PDMA_CH_MAIN1_UART3_RX (CSL_PDMA_CH_MAIN1_UART3_CH0_RX) |
#define | UDMA_PDMA_CH_MAIN1_UART4_RX (CSL_PDMA_CH_MAIN1_UART4_CH0_RX) |
#define | UDMA_PDMA_CH_MAIN1_UART5_RX (CSL_PDMA_CH_MAIN1_UART5_CH0_RX) |
#define | UDMA_PDMA_CH_MAIN1_UART6_RX (CSL_PDMA_CH_MAIN1_UART6_CH0_RX) |
#define | UDMA_PDMA_CH_MAIN1_MCAN0_CH0_RX (CSL_PDMA_CH_MAIN1_MCAN0_CH0_RX) |
#define | UDMA_PDMA_CH_MAIN1_MCAN0_CH1_RX (CSL_PDMA_CH_MAIN1_MCAN0_CH1_RX) |
#define | UDMA_PDMA_CH_MAIN1_MCAN0_CH2_RX (CSL_PDMA_CH_MAIN1_MCAN0_CH2_RX) |
#define | UDMA_PDMA_CH_MAIN1_MCAN1_CH0_RX (CSL_PDMA_CH_MAIN1_MCAN1_CH0_RX) |
#define | UDMA_PDMA_CH_MAIN1_MCAN1_CH1_RX (CSL_PDMA_CH_MAIN1_MCAN1_CH1_RX) |
#define | UDMA_PDMA_CH_MAIN1_MCAN1_CH2_RX (CSL_PDMA_CH_MAIN1_MCAN1_CH2_RX) |
#define | UDMA_PDMA_CH_MAIN1_ADC0_CH0_RX (CSL_PDMA_CH_MAIN1_ADC0_CH0_RX) |
#define | UDMA_PDMA_CH_MAIN1_ADC0_CH1_RX (CSL_PDMA_CH_MAIN1_ADC0_CH1_RX) |
Functions | |
uint32_t | Udma_getCoreId (void) |
Returns the core ID. More... | |
uint16_t | Udma_getCoreSciDevId (void) |
Returns the core tisci device ID. More... | |
uint32_t | Udma_isCacheCoherent (void) |
Returns TRUE if the memory is cache coherent. More... | |
#define UDMA_INST_ID_BCDMA_0 (UDMA_INST_ID_2) |
BCDMA instance.
#define UDMA_INST_ID_PKTDMA_0 (UDMA_INST_ID_3) |
PKTDMA instance.
#define UDMA_INST_ID_START (UDMA_INST_ID_2) |
Start of UDMA instance.
#define UDMA_INST_ID_MAX (UDMA_INST_ID_3) |
Maximum number of UDMA instance.
#define UDMA_NUM_INST_ID (UDMA_INST_ID_MAX - UDMA_INST_ID_START + 1U) |
Total number of UDMA instances.
#define UDMA_SOC_CFG_UDMAP_PRESENT (0U) |
Flag to indicate UDMAP module is present or not in the SOC.
#define UDMA_SOC_CFG_LCDMA_PRESENT (1U) |
Flag to indicate LCDMA module is present or not in the SOC.
#define UDMA_SOC_CFG_PROXY_PRESENT (0U) |
Flag to indicate Proxy is present or not in the SOC.
#define UDMA_SOC_CFG_CLEC_PRESENT (0U) |
Flag to indicate Clec is present or not in the SOC.
#define UDMA_SOC_CFG_RA_NORMAL_PRESENT (0U) |
Flag to indicate Normal RA is present or not in the SOC.
#define UDMA_SOC_CFG_RA_LCDMA_PRESENT (1U) |
Flag to indicate LCDMA RA is present or not in the SOC.
#define UDMA_SOC_CFG_RING_MON_PRESENT (0U) |
Flag to indicate Ring Monitor is present or not in the SOC.
#define UDMA_SOC_CFG_APPLY_RING_WORKAROUND (0U) |
Flag to indicate the SOC needs ring reset workaround.
#define UDMA_TX_UHC_CHANS_FDEPTH (CSL_DMSS_UDMAP_TX_UHC_CHANS_FDEPTH) |
Tx Ultra High Capacity Channel FDEPTH.
#define UDMA_TX_HC_CHANS_FDEPTH (CSL_DMSS_UDMAP_TX_HC_CHANS_FDEPTH) |
Tx High Capacity Channel FDEPTH.
#define UDMA_TX_CHANS_FDEPTH (CSL_DMSS_UDMAP_TX_CHANS_FDEPTH) |
Tx Normal Channel FDEPTH.
#define UDMA_RINGACC_ASEL_ENDPOINT_PHYSADDR (CSL_LCDMA_RINGACC_ASEL_ENDPOINT_PHYSADDR) |
Physical address (normal)
#define UDMA_RINGACC_ASEL_ENDPOINT_PCIE0 (CSL_LCDMA_RINGACC_ASEL_ENDPOINT_PCIE0) |
PCIE0.
#define UDMA_RINGACC_ASEL_ENDPOINT_ACP_WR_ALLOC (CSL_LCDMA_RINGACC_ASEL_ENDPOINT_ACP_WR_ALLOC) |
ARM ACP port: write-allocate cacheable, bufferable.
#define UDMA_RINGACC_ASEL_ENDPOINT_ACP_RD_ALLOC (CSL_LCDMA_RINGACC_ASEL_ENDPOINT_ACP_RD_ALLOC) |
ARM ACP port: read-allocate, cacheable, bufferable.
#define UDMA_RING_MODE_INVALID (CSL_LCDMA_RINGACC_RING_MODE_INVALID) |
Invalid Ring Mode.
#define UDMA_NUM_MAPPED_TX_GROUP (4U) |
Number of Mapped TX Group.
#define UDMA_MAPPED_TX_GROUP_CPSW (UDMA_MAPPED_GROUP0) |
#define UDMA_MAPPED_TX_GROUP_SAUL (UDMA_MAPPED_GROUP1) |
#define UDMA_MAPPED_TX_GROUP_ICSSG_0 (UDMA_MAPPED_GROUP2) |
#define UDMA_MAPPED_TX_GROUP_ICSSG_1 (UDMA_MAPPED_GROUP3) |
#define UDMA_NUM_MAPPED_RX_GROUP (4U) |
Number of Mapped RX Group.
#define UDMA_MAPPED_RX_GROUP_CPSW (UDMA_MAPPED_GROUP4) |
#define UDMA_MAPPED_RX_GROUP_SAUL (UDMA_MAPPED_GROUP5) |
#define UDMA_MAPPED_RX_GROUP_ICSSG_0 (UDMA_MAPPED_GROUP6) |
#define UDMA_MAPPED_RX_GROUP_ICSSG_1 (UDMA_MAPPED_GROUP7) |
#define UDMA_NUM_UTC_INSTANCE (CSL_DMSS_UTC_CNT) |
Number of UTC instance.
#define UDMA_CORE_ID_MPU1_0 (0U) |
#define UDMA_CORE_ID_MCU2_0 (1U) |
#define UDMA_CORE_ID_MCU2_1 (2U) |
#define UDMA_CORE_ID_MCU1_0 (3U) |
#define UDMA_CORE_ID_MCU1_1 (4U) |
#define UDMA_CORE_ID_M4F_0 (5U) |
#define UDMA_NUM_CORE (6U) |
#define UDMA_RM_RES_ID_BC_UHC (0U) |
Ultra High Capacity Block Copy Channels.
#define UDMA_RM_RES_ID_BC_HC (1U) |
High Capacity Block Copy Channels.
#define UDMA_RM_RES_ID_BC (2U) |
Normal Capacity Block Copy Channels.
#define UDMA_RM_RES_ID_TX_UHC (3U) |
Ultra High Capacity TX Channels.
#define UDMA_RM_RES_ID_TX_HC (4U) |
High Capacity TX Channels.
#define UDMA_RM_RES_ID_TX (5U) |
Normal Capacity TX Channels.
#define UDMA_RM_RES_ID_RX_UHC (6U) |
Ultra High Capacity RX Channels.
#define UDMA_RM_RES_ID_RX_HC (7U) |
High Capacity RX Channels.
#define UDMA_RM_RES_ID_RX (8U) |
Normal Capacity RX Channels.
#define UDMA_RM_RES_ID_GLOBAL_EVENT (9U) |
Global Event.
#define UDMA_RM_RES_ID_VINTR (10U) |
Virtual Interrupts.
#define UDMA_RM_RES_ID_MAPPED_TX_CPSW (11U) |
[Pktdma Only] Mapped TX Channels for CPSW
#define UDMA_RM_RES_ID_MAPPED_TX_SAUL_0 (12U) |
[Pktdma Only] Mapped TX Channels for SAUL_0
#define UDMA_RM_RES_ID_MAPPED_TX_SAUL_1 (13U) |
[Pktdma Only] Mapped TX Channels for SAUL_1
#define UDMA_RM_RES_ID_MAPPED_TX_ICSSG_0 (14U) |
[Pktdma Only] Mapped TX Channels for ICSSG_0
#define UDMA_RM_RES_ID_MAPPED_TX_ICSSG_1 (15U) |
[Pktdma Only] Mapped TX Channels for ICSSG_1
#define UDMA_RM_RES_ID_MAPPED_RX_CPSW (16U) |
[Pktdma Only] Mapped RX Channels for CPSW
#define UDMA_RM_RES_ID_MAPPED_RX_SAUL_0 (17U) |
[Pktdma Only] Mapped RX Channels for SAUL_0
#define UDMA_RM_RES_ID_MAPPED_RX_SAUL_1 (18U) |
[Pktdma Only] Mapped RX Channels for SAUL_1
#define UDMA_RM_RES_ID_MAPPED_RX_SAUL_2 (19U) |
[Pktdma Only] Mapped RX Channels for SAUL_2
#define UDMA_RM_RES_ID_MAPPED_RX_SAUL_3 (20U) |
[Pktdma Only] Mapped RX Channels for SAUL_3
#define UDMA_RM_RES_ID_MAPPED_RX_ICSSG_0 (21U) |
[Pktdma Only] Mapped RX Channels for ICSSG_0
#define UDMA_RM_RES_ID_MAPPED_RX_ICSSG_1 (22U) |
[Pktdma Only] Mapped RX Channels for ICSSG_1
#define UDMA_RM_RES_ID_MAPPED_TX_RING_CPSW (23U) |
[Pktdma Only] Mapped TX Rings for CPSW
#define UDMA_RM_RES_ID_MAPPED_TX_RING_SAUL_0 (24U) |
[Pktdma Only] Mapped TX Rings for SAUL_0
#define UDMA_RM_RES_ID_MAPPED_TX_RING_SAUL_1 (25U) |
[Pktdma Only] Mapped TX Rings for SAUL_1
#define UDMA_RM_RES_ID_MAPPED_TX_RING_ICSSG_0 (26U) |
[Pktdma Only] Mapped TX Rings for ICSSG_0
#define UDMA_RM_RES_ID_MAPPED_TX_RING_ICSSG_1 (27U) |
[Pktdma Only] Mapped TX Rings for ICSSG_1
#define UDMA_RM_RES_ID_MAPPED_RX_RING_CPSW (28U) |
[Pktdma Only] Mapped RX Rings for CPSW
#define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_0 (29U) |
[Pktdma Only] Mapped RX Rings for SAUL_0
#define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_1 (30U) |
[Pktdma Only] Mapped RX Rings for SAUL_1
#define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_2 (31U) |
[Pktdma Only] Mapped RX Rings for SAUL_2
#define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_3 (32U) |
[Pktdma Only] Mapped RX Rings for SAUL_3
#define UDMA_RM_RES_ID_MAPPED_RX_RING_ICSSG_0 (33U) |
[Pktdma Only] Mapped RX Rings for ICSSG_0
#define UDMA_RM_RES_ID_MAPPED_RX_RING_ICSSG_1 (34U) |
[Pktdma Only] Mapped RX Rings for ICSSG_1
#define UDMA_RM_NUM_BCDMA_RES (11U) |
Total number of BCDMA resources.
#define UDMA_RM_NUM_PKTDMA_RES (35U) |
Total number of PKTDMA resources.
#define UDMA_RM_NUM_RES (35U) |
Total number of resources.
#define UDMA_RM_NUM_SHARED_RES (2U) |
Total number of shared resources - Global_Event/IR Intr.
#define UDMA_RM_SHARED_RES_MAX_INST (UDMA_NUM_CORE) |
Maximum no.of instances to split a shared resource. This should be max(UDMA_NUM_CORE,UDMA_NUM_INST_ID)
#define UDMA_PSIL_CH_CPSW2_TX (CSL_PSILCFG_DMSS_CPSW2_PSILD_THREAD_OFFSET) |
#define UDMA_PSIL_CH_SAUL0_TX (CSL_PSILCFG_DMSS_SAUL0_PSILD_THREAD_OFFSET) |
#define UDMA_PSIL_CH_ICSS_G0_TX (CSL_PSILCFG_DMSS_ICSS_G0_PSILD_THREAD_OFFSET) |
#define UDMA_PSIL_CH_ICSS_G1_TX (CSL_PSILCFG_DMSS_ICSS_G1_PSILD_THREAD_OFFSET) |
#define UDMA_PSIL_CH_CPSW2_RX (CSL_PSILCFG_DMSS_CPSW2_PSILS_THREAD_OFFSET) |
#define UDMA_PSIL_CH_SAUL0_RX (CSL_PSILCFG_DMSS_SAUL0_PSILS_THREAD_OFFSET) |
#define UDMA_PSIL_CH_ICSS_G0_RX (CSL_PSILCFG_DMSS_ICSS_G0_PSILS_THREAD_OFFSET) |
#define UDMA_PSIL_CH_ICSS_G1_RX (CSL_PSILCFG_DMSS_ICSS_G1_PSILS_THREAD_OFFSET) |
#define UDMA_PSIL_CH_CPSW2_TX_CNT (CSL_PSILCFG_DMSS_CPSW2_PSILD_THREAD_CNT) |
#define UDMA_PSIL_CH_SAUL0_TX_CNT (CSL_PSILCFG_DMSS_SAUL0_PSILD_THREAD_CNT) |
#define UDMA_PSIL_CH_ICSS_G0_TX_CNT (CSL_PSILCFG_DMSS_ICSS_G0_PSILD_THREAD_CNT) |
#define UDMA_PSIL_CH_ICSS_G1_TX_CNT (CSL_PSILCFG_DMSS_ICSS_G1_PSILD_THREAD_CNT) |
#define UDMA_PSIL_CH_CPSW2_RX_CNT (CSL_PSILCFG_DMSS_CPSW2_PSILS_THREAD_CNT) |
#define UDMA_PSIL_CH_SAUL0_RX_CNT (CSL_PSILCFG_DMSS_SAUL0_PSILS_THREAD_CNT) |
#define UDMA_PSIL_CH_ICSS_G0_RX_CNT (CSL_PSILCFG_DMSS_ICSS_G0_PSILS_THREAD_CNT) |
#define UDMA_PSIL_CH_ICSS_G1_RX_CNT (CSL_PSILCFG_DMSS_ICSS_G1_PSILS_THREAD_CNT) |
#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_TX (CSL_PDMA_CH_MAIN0_MCSPI0_CH0_TX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_TX (CSL_PDMA_CH_MAIN0_MCSPI0_CH1_TX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_TX (CSL_PDMA_CH_MAIN0_MCSPI0_CH2_TX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_TX (CSL_PDMA_CH_MAIN0_MCSPI0_CH3_TX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_TX (CSL_PDMA_CH_MAIN0_MCSPI1_CH0_TX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_TX (CSL_PDMA_CH_MAIN0_MCSPI1_CH1_TX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_TX (CSL_PDMA_CH_MAIN0_MCSPI1_CH2_TX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_TX (CSL_PDMA_CH_MAIN0_MCSPI1_CH3_TX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_TX (CSL_PDMA_CH_MAIN0_MCSPI2_CH0_TX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_TX (CSL_PDMA_CH_MAIN0_MCSPI2_CH1_TX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_TX (CSL_PDMA_CH_MAIN0_MCSPI2_CH2_TX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_TX (CSL_PDMA_CH_MAIN0_MCSPI2_CH3_TX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_TX (CSL_PDMA_CH_MAIN0_MCSPI3_CH0_TX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_TX (CSL_PDMA_CH_MAIN0_MCSPI3_CH1_TX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_TX (CSL_PDMA_CH_MAIN0_MCSPI3_CH2_TX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_TX (CSL_PDMA_CH_MAIN0_MCSPI3_CH3_TX) |
#define UDMA_PDMA_CH_MAIN0_UART0_TX (CSL_PDMA_CH_MAIN0_UART0_CH0_TX) |
#define UDMA_PDMA_CH_MAIN0_UART1_TX (CSL_PDMA_CH_MAIN0_UART1_CH0_TX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_RX (CSL_PDMA_CH_MAIN0_MCSPI0_CH0_RX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_RX (CSL_PDMA_CH_MAIN0_MCSPI0_CH1_RX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_RX (CSL_PDMA_CH_MAIN0_MCSPI0_CH2_RX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_RX (CSL_PDMA_CH_MAIN0_MCSPI0_CH3_RX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_RX (CSL_PDMA_CH_MAIN0_MCSPI1_CH0_RX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_RX (CSL_PDMA_CH_MAIN0_MCSPI1_CH1_RX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_RX (CSL_PDMA_CH_MAIN0_MCSPI1_CH2_RX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_RX (CSL_PDMA_CH_MAIN0_MCSPI1_CH3_RX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_RX (CSL_PDMA_CH_MAIN0_MCSPI2_CH0_RX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_RX (CSL_PDMA_CH_MAIN0_MCSPI2_CH1_RX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_RX (CSL_PDMA_CH_MAIN0_MCSPI2_CH2_RX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_RX (CSL_PDMA_CH_MAIN0_MCSPI2_CH3_RX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_RX (CSL_PDMA_CH_MAIN0_MCSPI3_CH0_RX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_RX (CSL_PDMA_CH_MAIN0_MCSPI3_CH1_RX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_RX (CSL_PDMA_CH_MAIN0_MCSPI3_CH2_RX) |
#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_RX (CSL_PDMA_CH_MAIN0_MCSPI3_CH3_RX) |
#define UDMA_PDMA_CH_MAIN0_UART0_RX (CSL_PDMA_CH_MAIN0_UART0_CH0_RX) |
#define UDMA_PDMA_CH_MAIN0_UART1_RX (CSL_PDMA_CH_MAIN0_UART1_CH0_RX) |
#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_TX (CSL_PDMA_CH_MAIN1_MCSPI4_CH0_TX) |
#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_TX (CSL_PDMA_CH_MAIN1_MCSPI4_CH1_TX) |
#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_TX (CSL_PDMA_CH_MAIN1_MCSPI4_CH2_TX) |
#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_TX (CSL_PDMA_CH_MAIN1_MCSPI4_CH3_TX) |
#define UDMA_PDMA_CH_MAIN1_UART2_TX (CSL_PDMA_CH_MAIN1_UART2_CH0_TX) |
#define UDMA_PDMA_CH_MAIN1_UART3_TX (CSL_PDMA_CH_MAIN1_UART3_CH0_TX) |
#define UDMA_PDMA_CH_MAIN1_UART4_TX (CSL_PDMA_CH_MAIN1_UART4_CH0_TX) |
#define UDMA_PDMA_CH_MAIN1_UART5_TX (CSL_PDMA_CH_MAIN1_UART5_CH0_TX) |
#define UDMA_PDMA_CH_MAIN1_UART6_TX (CSL_PDMA_CH_MAIN1_UART6_CH0_TX) |
#define UDMA_PDMA_CH_MAIN1_MCAN0_CH0_TX (CSL_PDMA_CH_MAIN1_MCAN0_CH0_TX) |
#define UDMA_PDMA_CH_MAIN1_MCAN0_CH1_TX (CSL_PDMA_CH_MAIN1_MCAN0_CH1_TX) |
#define UDMA_PDMA_CH_MAIN1_MCAN0_CH2_TX (CSL_PDMA_CH_MAIN1_MCAN0_CH2_TX) |
#define UDMA_PDMA_CH_MAIN1_MCAN1_CH0_TX (CSL_PDMA_CH_MAIN1_MCAN1_CH0_TX) |
#define UDMA_PDMA_CH_MAIN1_MCAN1_CH1_TX (CSL_PDMA_CH_MAIN1_MCAN1_CH1_TX) |
#define UDMA_PDMA_CH_MAIN1_MCAN1_CH2_TX (CSL_PDMA_CH_MAIN1_MCAN1_CH2_TX) |
#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_RX (CSL_PDMA_CH_MAIN1_MCSPI4_CH0_RX) |
#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_RX (CSL_PDMA_CH_MAIN1_MCSPI4_CH1_RX) |
#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_RX (CSL_PDMA_CH_MAIN1_MCSPI4_CH2_RX) |
#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_RX (CSL_PDMA_CH_MAIN1_MCSPI4_CH3_RX) |
#define UDMA_PDMA_CH_MAIN1_UART2_RX (CSL_PDMA_CH_MAIN1_UART2_CH0_RX) |
#define UDMA_PDMA_CH_MAIN1_UART3_RX (CSL_PDMA_CH_MAIN1_UART3_CH0_RX) |
#define UDMA_PDMA_CH_MAIN1_UART4_RX (CSL_PDMA_CH_MAIN1_UART4_CH0_RX) |
#define UDMA_PDMA_CH_MAIN1_UART5_RX (CSL_PDMA_CH_MAIN1_UART5_CH0_RX) |
#define UDMA_PDMA_CH_MAIN1_UART6_RX (CSL_PDMA_CH_MAIN1_UART6_CH0_RX) |
#define UDMA_PDMA_CH_MAIN1_MCAN0_CH0_RX (CSL_PDMA_CH_MAIN1_MCAN0_CH0_RX) |
#define UDMA_PDMA_CH_MAIN1_MCAN0_CH1_RX (CSL_PDMA_CH_MAIN1_MCAN0_CH1_RX) |
#define UDMA_PDMA_CH_MAIN1_MCAN0_CH2_RX (CSL_PDMA_CH_MAIN1_MCAN0_CH2_RX) |
#define UDMA_PDMA_CH_MAIN1_MCAN1_CH0_RX (CSL_PDMA_CH_MAIN1_MCAN1_CH0_RX) |
#define UDMA_PDMA_CH_MAIN1_MCAN1_CH1_RX (CSL_PDMA_CH_MAIN1_MCAN1_CH1_RX) |
#define UDMA_PDMA_CH_MAIN1_MCAN1_CH2_RX (CSL_PDMA_CH_MAIN1_MCAN1_CH2_RX) |
#define UDMA_PDMA_CH_MAIN1_ADC0_CH0_RX (CSL_PDMA_CH_MAIN1_ADC0_CH0_RX) |
#define UDMA_PDMA_CH_MAIN1_ADC0_CH1_RX (CSL_PDMA_CH_MAIN1_ADC0_CH1_RX) |
uint32_t Udma_getCoreId | ( | void | ) |
Returns the core ID.
uint16_t Udma_getCoreSciDevId | ( | void | ) |
Returns the core tisci device ID.
uint32_t Udma_isCacheCoherent | ( | void | ) |
Returns TRUE if the memory is cache coherent.