 |
PDK API Guide for AM64x
|
Go to the documentation of this file. 54 #ifndef TISCI_PROTOCOL_H 55 #define TISCI_PROTOCOL_H 61 #define TISCI_MSG_FLAG_RESERVED0 TISCI_BIT(0) 69 #define TISCI_MSG_FLAG_AOP TISCI_BIT(1) 72 #define TISCI_MSG_FLAG_SEC TISCI_BIT(2) 78 #define TISCI_MSG_FLAG_ACK TISCI_BIT(1) 130 #define TISCI_MSG_VERSION (0x0002U) 131 #define TISCI_MSG_BOOT_NOTIFICATION (0x000AU) 132 #define TISCI_MSG_BOARD_CONFIG (0x000BU) 133 #define TISCI_MSG_BOARD_CONFIG_RM (0x000CU) 134 #define TISCI_MSG_BOARD_CONFIG_SECURITY (0x000DU) 135 #define TISCI_MSG_BOARD_CONFIG_PM (0x000EU) 137 #define TISCI_MSG_ENABLE_WDT (0x0000U) 138 #define TISCI_MSG_WAKE_RESET (0x0001U) 139 #define TISCI_MSG_WAKE_REASON (0x0003U) 140 #define TISCI_MSG_GOODBYE (0x0004U) 141 #define TISCI_MSG_SYS_RESET (0x0005U) 143 #define TISCI_MSG_QUERY_MSMC (0x0020U) 145 #define TISCI_MSG_SET_CLOCK (0x0100U) 146 #define TISCI_MSG_GET_CLOCK (0x0101U) 147 #define TISCI_MSG_SET_CLOCK_PARENT (0x0102U) 148 #define TISCI_MSG_GET_CLOCK_PARENT (0x0103U) 149 #define TISCI_MSG_GET_NUM_CLOCK_PARENTS (0x0104U) 150 #define TISCI_MSG_SET_FREQ (0x010cU) 151 #define TISCI_MSG_QUERY_FREQ (0x010dU) 152 #define TISCI_MSG_GET_FREQ (0x010eU) 154 #define TISCI_MSG_SET_DEVICE (0x0200U) 155 #define TISCI_MSG_GET_DEVICE (0x0201U) 156 #define TISCI_MSG_SET_DEVICE_RESETS (0x0202U) 157 #define TISCI_MSG_DEVICE_DROP_POWERUP_REF (0x0203U) 160 #define TISCI_MSG_SET_FWL_REGION (0x9000U) 162 #define TISCI_MSG_GET_FWL_REGION (0x9001U) 164 #define TISCI_MSG_CHANGE_FWL_OWNER (0x9002U) 166 #define TISCI_MSG_SA2UL_SET_DKEK (0x9003U) 168 #define TISCI_MSG_SA2UL_RELEASE_DKEK (0x9004U) 170 #define TISCI_MSG_KEYSTORE_IMPORT_SKEY (0x9005U) 172 #define TISCI_MSG_KEYSTORE_ERASE_SKEY (0x9006U) 174 #define TISCI_MSG_SEC_RESERVED_9007 (0x9007U) 176 #define TISCI_MSG_SEC_RESERVED_9008 (0x9008U) 178 #define TISCI_MSG_SET_ISC_REGION (0x9009U) 180 #define TISCI_MSG_GET_ISC_REGION (0x900AU) 182 #define TISCI_MSG_FWL_EXCP_NOTIFICATION (0x900BU) 184 #define TISCI_MSG_OPEN_DEBUG_FWLS (0x900CU) 189 #define TISCI_MSG_KEYSTORE_WRITE (0x900DU) 194 #define TISCI_MSG_KEYSTORE_EXPORT_ALL (0x900EU) 196 #define TISCI_MSG_KEYSTORE_IMPORT_ALL (0x900FU) 198 #define TISCI_MSG_SEC_RESERVED_9010 (0x9010U) 200 #define TISCI_MSG_SEC_RESERVED_9011 (0x9011U) 202 #define TISCI_MSG_SEC_RESERVED_9012 (0x9012U) 204 #define TISCI_MSG_SEC_RESERVED_9013 (0x9013U) 206 #define TISCI_MSG_SEC_RESERVED_9014 (0x9014U) 208 #define TISCI_MSG_SEC_RESERVED_9015 (0x9015U) 211 #define TISCI_MSG_SEC_RESERVED_9016 (0x9016U) 214 #define TISCI_MSG_SA2UL_AUTH_RES_ACQUIRE (0x9017U) 217 #define TISCI_MSG_SA2UL_AUTH_RES_RELEASE (0x9018U) 220 #define TISCI_MSG_SEC_RESERVED_9020 (0x9020U) 223 #define TISCI_MSG_GET_SOC_UID (0x9021U) 229 #define TISCI_MSG_READ_OTP_MMR (0x9022U) 232 #define TISCI_MSG_WRITE_OTP_ROW (0x9023U) 235 #define TISCI_MSG_LOCK_OTP_ROW (0x9024U) 238 #define TISCI_MSG_SOFT_LOCK_OTP_WRITE_GLOBAL (0x9025U) 241 #define TISCI_MSG_GET_OTP_ROW_LOCK_STATUS (0x9026U) 244 #define TISCI_MSG_RSVD_OTP_1 (0x9027U) 247 #define TISCI_MSG_RSVD_OTP_2 (0x9028U) 250 #define TISCI_MSG_SA2UL_GET_DKEK (0x9029U) 255 #define TISCI_MSG_SEC_HANDOVER (0x9030U) 260 #define TISCI_MSG_KEY_WRITER (0x9031U) 265 #define TISCI_MSG_PROC_REQUEST (0xC000U) 267 #define TISCI_MSG_PROC_RELEASE (0xC001U) 269 #define TISCI_MSG_PROC_HANDOVER (0xC005U) 272 #define TISCI_MSG_PROC_SET_CONFIG (0xC100U) 274 #define TISCI_MSG_PROC_SET_CONTROL (0xC101U) 277 #define TISCI_MSG_PROC_GET_STATUS (0xC400U) 280 #define TISCI_MSG_PROC_WAIT_STATUS (0xC401U) 283 #define TISCI_MSG_PROC_AUTH_BOOT (0xC120U) 290 #define TISCI_MSG_RM_GET_RESOURCE_RANGE (0x1500U) 294 #define TISCI_MSG_RM_IRQ_SET (0x1000U) 298 #define TISCI_MSG_RM_IRQ_RELEASE (0x1001U) 300 #define TISCI_MSG_RM_RESERVED_1100 (0x1100U) 302 #define TISCI_MSG_RM_RESERVED_1101 (0x1101U) 304 #define TISCI_MSG_RM_RESERVED_1102 (0x1102U) 306 #define TISCI_MSG_RM_RESERVED_1103 (0x1103U) 310 #define TISCI_MSG_RM_RING_CFG (0x1110U) 312 #define TISCI_MSG_RM_RESERVED_1111 (0x1111U) 316 #define TISCI_MSG_RM_RING_MON_CFG (0x1120U) 318 #define TISCI_MSG_RM_RESERVED_1200 (0x1200U) 320 #define TISCI_MSG_RM_RESERVED_1201 (0x1201U) 324 #define TISCI_MSG_RM_UDMAP_TX_CH_CFG (0x1205U) 326 #define TISCI_MSG_RM_RESERVED_1206 (0x1206U) 328 #define TISCI_MSG_RM_RESERVED_1210 (0x1210U) 330 #define TISCI_MSG_RM_RESERVED_1211 (0x1211U) 334 #define TISCI_MSG_RM_UDMAP_RX_CH_CFG (0x1215U) 335 #define TISCI_MSG_RM_RESERVED_1216 (0x1216U) 337 #define TISCI_MSG_RM_RESERVED_1220 (0x1220U) 339 #define TISCI_MSG_RM_RESERVED_1221 (0x1221U) 343 #define TISCI_MSG_RM_UDMAP_FLOW_CFG (0x1230U) 348 #define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG (0x1231U) 350 #define TISCI_MSG_RM_RESERVED_1232 (0x1232U) 352 #define TISCI_MSG_RM_RESERVED_1233 (0x1233U) 356 #define TISCI_MSG_RM_UDMAP_FLOW_DELEGATE (0x1234U) 361 #define TISCI_MSG_RM_UDMAP_GCFG_CFG (0x1240U) 363 #define TISCI_MSG_RM_RESERVED_1241 (0x1241U) 367 #define TISCI_MSG_RM_PSIL_PAIR (0x1280U) 371 #define TISCI_MSG_RM_PSIL_UNPAIR (0x1281U) 375 #define TISCI_MSG_RM_PSIL_READ (0x1282U) 379 #define TISCI_MSG_RM_PSIL_WRITE (0x1283U) 384 #define TISCI_MSG_RM_PROXY_CFG (0x1300U)