5.9.1.1. DMSS (Data Movement Subsystem)¶
5.9.1.1.1. Introduction¶
The primary goal of the Data Movement Subsystem (DMSS) is to ensure that data can be efficiently transferred from a producer to a consumer so that the real time requirements of the system can be met.

Fig. 5.8 DMSS Top Level Block Diagram
The block diagram provides a high level picture of not only the 2 different interconnect fabrics but also some key standard data movement components that have been defined and placed in the various parts of the low cost compliant SoC. The following sections will provide a high level overview of Packet DMA (PKTDMA) and Block Copy DMA (BCDMA) which are the two instances of the DMSS specification serving different use cases as described below:
5.9.1.1.2. Block Copy DMA (BCDMA)¶
The BCDMA module moves data from a memory mapped source address set to a corresponding memory mapped address set. The BCDMA maintains state information for each of the channels which allows data copy operations to be time division multiplexed between channels in order to share the underlying DMA hardware. An internal DMA scheduler is used to control the ordering and rate at which this multiplexing occurs.
A block diagram of the Block Copy DMA Controller is shown below:

Fig. 5.9 Block Copy DMA Block Diagram
5.9.1.1.3. Packet DMA (PKTDMA)¶
The PKTDMA module supports the transmission and reception of various packet types. The PKTDMA is architected to facilitate the segmentation and reassembly of DMA data structure compliant packets to/from smaller data blocks that are natively compatible with the specific requirements of each connected peripheral. Multiple TX and RX channels are provided within the DMA which allow multiple segmentation or reassembly operations to be ongoing. The DMA controller maintains state information for each of the channels which allows packet segmentation and reassembly operations to be time division multiplexed between channels in order to share the underlying DMA hardware. An internal DMA scheduler is used to control the ordering and rate at which this multiplexing occurs for Transmit operations. The ordering and rate of Receive operations is indirectly controlled by the order in which blocks are pushed into the DMA on the RX PSI-L interface.
A block diagram of the PKTDMA Controller is shown below:

Fig. 5.10 PKTDMA DMA Block Diagram
5.9.1.1.3.1. Channels in PKTDMA¶
In case of AM64x , PKTDMA instance has 42 TX channels and 29 RX channels. Among this some channels are hardwired to specific peripherals. i.e., There is no dynamic thread mapping.
The 42 TX Channels are grouped as given below:
- 16 Peripheral TX Channels
- 8 CPSW TX Channels
- 2 SAUL TX Channels
- 8 ICSSG 0 TX Channels
- 8 ICSSG 1 TX Channels
NOTE: The TX channels reserved for CPSW / SAUL / ICSSG_0 / ICSSG_1 will be referred as ‘MAPPED TX’ channels in UDMA LLD.
The 29 RX Channels are grouped as given below:
- 16 Peripheral RX Channels
- 1 CPSW RX Channels
- 4 SAUL RX Channels
- 4 ICSSG 0 RX Channels
- 4 ICSSG 1 RX Channels
NOTE: The RX channels reserved for CPSW / SAUL / ICSSG_0 / ICSSG_1 will be referred as ‘MAPPED RX’ channels in UDMA LLD.
5.9.1.1.3.2. Flows / Rings in PKTDMA¶
DMSS eliminates all ring steering. The rings are now dedicated for a single TX or RX flow. Henceforth the Flows specified in the DMSS specs are equivalent to Rings in UDMA LLD.
DMSS introduced the new feature ‘TX-FLOW’ for TX channels (similar to RX-FLOW for RX channels). It allows separate TX exposed rings to be multiplexed onto one TX channel. The multiplexing is done on packet / entire block copy work units. It does not allow interleaving of individual transfers within the DMA operation.
PKTDMA has a reduced RX flow feature set. There is no multiple ‘free pool’ selection based on incoming packet size and no destination ring override. Destination ring is hard wired to the flow effectively. RX flows are hard-wired to the DMA channel. There is no generic pool of flows that can be assigned ad hoc to any channel. The following diagrams show how the flow(s) are tied to different channels in PKTMDA.

Fig. 5.11 TX Channels and Flows in PKTMDA

Fig. 5.12 RX Channels and Flows in PKTMDA
5.9.1.1.4. Comparison of BCDMA and PKTDMA¶
This following table gives an overview of the comparison between BCDMA and PKTDMA, the two instances of the DMSS specification.
BCDMA | PKTDMA | |
---|---|---|
Descriptors | The Block Copy DMA architecture provides for a single descriptor type:
All applications using TRPD must use BCDMA instance. |
PKTDMA architecture provides for 2 basic types of descriptors:
All applications using HPD/HBD must use PKTDMA instance. |
Channels |
(Refer TRM for SoC specific details) |
|
Flows / Rings | Each flow is tied to a channel.
There are no free / no extra flows. Only default flow is available.
|
No free flows.
Extra flow(s) tied to channels.
|