PDK API Guide for AM64x
csl_cpgmac_sl.h
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1 
42 #ifndef CSL_CPGMAC_SL_V5_H_
43 #define CSL_CPGMAC_SL_V5_H_
44 
45 #ifdef __cplusplus
46 extern "C" {
47 #endif
48 
49 #include <stdbool.h>
50 #include <ti/csl/soc.h>
51 #include <ti/csl/csl.h>
52 #include <ti/csl/cslr_xge_cpsw.h>
53 
54 
90 #define CSL_CPGMAC_SL_MACCONTROL_FULLDUPLEX_EN (1 << 0u)
91 
93 #define CSL_CPGMAC_SL_MACCONTROL_LOOPBACK_EN (1 << 1u)
94 
96 #define CSL_CPGMAC_SL_MACCONTROL_RX_FLOW_EN (1 << 3u)
97 
99 #define CSL_CPGMAC_SL_MACCONTROL_TX_FLOW_EN (1 << 4u)
100 
102 #define CSL_CPGMAC_SL_MACCONTROL_GMII_EN (1 << 5u)
103 
105 #define CSL_CPGMAC_SL_MACCONTROL_TX_PACE_EN (1 << 6u)
106 
108 #define CSL_CPGMAC_SL_MACCONTROL_GIG_EN (1 << 7u)
109 
111 #define CSL_CPGMAC_SL_MACCONTROL_TX_SHORT_GAP_EN (1 << 10u)
112 
114 #define CSL_CPGMAC_SL_MACCONTROL_CMD_IDLE_EN (1 << 11u)
115 
117 #define CSL_CPGMAC_SL_MACCONTROL_CASTAGNOLI_CRC (1 << 12u)
118 
120 #define CSL_CPGMAC_SL_MACCONTROL_IFCTL_A_EN (1 << 15u)
121 
123 #define CSL_CPGMAC_SL_MACCONTROL_IFCTL_B_EN (1 << 16u)
124 
126 #define CSL_CPGMAC_SL_MACCONTROL_GIG_FORCE_EN (1 << 17u)
127 
129 #define CSL_CPGMAC_SL_MACCONTROL_EXT_EN (1 << 18u)
130 
132 #define CSL_CPGMAC_SL_MACCONTROL_EXT_EN_RX_FLOW (1 << 19u)
133 
135 #define CSL_CPGMAC_SL_MACCONTROL_EXT_EN_TX_FLOW (1 << 20u)
136 
138 #define CSL_CPGMAC_SL_MACCONTROL_RX_CEF_EN (1 << 22u)
139 
141 #define CSL_CPGMAC_SL_MACCONTROL_RX_CSF_EN (1 << 23u)
142 
144 #define CSL_CPGMAC_SL_MACCONTROL_RX_CMF_EN (1 << 24u)
145 
150 typedef struct {
152  Uint32 minorVer;
153 
155  Uint32 majorVer;
156 
158  Uint32 rtlVer;
159 
161  Uint32 id;
163 
168 typedef struct {
175  Uint32 txFlowActive;
179  Uint32 rxFlowActive;
193  Uint32 rxPfcFlowAct;
195  Uint32 txPfcFlowAct;
199  Uint32 torfPri;
201  Uint32 torf;
203  Uint32 macTxIdle;
209  Uint32 idle;
211 
220 /********************************************************************************
221 *************** Ethernet Media Access Controller (EMAC) Submodule ***************
222 ********************************************************************************/
223 
267 (CSL_Xge_cpswRegs *hCpswRegs,
268  Uint32 portNum
269 );
270 
305 (CSL_Xge_cpswRegs *hCpswRegs,
306  Uint32 portNum
307 );
308 
343 (CSL_Xge_cpswRegs *hCpswRegs,
344  Uint32 portNum
345 );
346 
389 (CSL_Xge_cpswRegs *hCpswRegs,
390  Uint32 portNum
391 );
392 
427 (CSL_Xge_cpswRegs *hCpswRegs,
428  Uint32 portNum
429 );
430 
464 (CSL_Xge_cpswRegs *hCpswRegs,
465  Uint32 portNum
466 );
467 
510 (CSL_Xge_cpswRegs *hCpswRegs,
511  Uint32 portNum
512 );
513 
548 (CSL_Xge_cpswRegs *hCpswRegs,
549  Uint32 portNum
550 );
551 
586 (CSL_Xge_cpswRegs *hCpswRegs,
587  Uint32 portNum
588 );
589 
632 (CSL_Xge_cpswRegs *hCpswRegs,
633  Uint32 portNum
634 );
635 
670 (CSL_Xge_cpswRegs *hCpswRegs,
671  Uint32 portNum
672 );
673 
708 (CSL_Xge_cpswRegs *hCpswRegs,
709  Uint32 portNum
710 );
711 
712 
755 (CSL_Xge_cpswRegs *hCpswRegs,
756  Uint32 portNum
757 );
758 
793 (CSL_Xge_cpswRegs *hCpswRegs,
794  Uint32 portNum
795 );
796 
831 (CSL_Xge_cpswRegs *hCpswRegs,
832  Uint32 portNum
833 );
834 
877 (CSL_Xge_cpswRegs *hCpswRegs,
878  Uint32 portNum
879 );
880 
915 (CSL_Xge_cpswRegs *hCpswRegs,
916  Uint32 portNum
917 );
918 
953 (CSL_Xge_cpswRegs *hCpswRegs,
954  Uint32 portNum
955 );
956 
999 (CSL_Xge_cpswRegs *hCpswRegs,
1000  Uint32 portNum
1001 );
1002 
1037 (CSL_Xge_cpswRegs *hCpswRegs,
1038  Uint32 portNum
1039 );
1040 
1075 (CSL_Xge_cpswRegs *hCpswRegs,
1076  Uint32 portNum
1077 );
1078 
1079 
1080 
1123 (CSL_Xge_cpswRegs *hCpswRegs,
1124  Uint32 portNum
1125 );
1126 
1161 (CSL_Xge_cpswRegs *hCpswRegs,
1162  Uint32 portNum
1163 );
1164 
1199 (CSL_Xge_cpswRegs *hCpswRegs,
1200  Uint32 portNum
1201 );
1202 
1203 
1204 
1247 (CSL_Xge_cpswRegs *hCpswRegs,
1248  Uint32 portNum
1249 );
1250 
1285 (CSL_Xge_cpswRegs *hCpswRegs,
1286  Uint32 portNum
1287 );
1288 
1323 (CSL_Xge_cpswRegs *hCpswRegs,
1324  Uint32 portNum
1325 );
1368 (CSL_Xge_cpswRegs *hCpswRegs,
1369  Uint32 portNum
1370 );
1371 
1406 (CSL_Xge_cpswRegs *hCpswRegs,
1407  Uint32 portNum
1408 );
1409 
1444 (CSL_Xge_cpswRegs *hCpswRegs,
1445  Uint32 portNum
1446 );
1447 
1448 
1491 (CSL_Xge_cpswRegs *hCpswRegs,
1492  Uint32 portNum
1493 );
1494 
1529 (CSL_Xge_cpswRegs *hCpswRegs,
1530  Uint32 portNum
1531 );
1532 
1567 (CSL_Xge_cpswRegs *hCpswRegs,
1568  Uint32 portNum
1569 );
1570 
1613 (CSL_Xge_cpswRegs *hCpswRegs,
1614  Uint32 portNum
1615 );
1616 
1651 (CSL_Xge_cpswRegs *hCpswRegs,
1652  Uint32 portNum
1653 );
1654 
1689 (CSL_Xge_cpswRegs *hCpswRegs,
1690  Uint32 portNum
1691 );
1692 
1735 (CSL_Xge_cpswRegs *hCpswRegs,
1736  Uint32 portNum
1737 );
1738 
1773 (CSL_Xge_cpswRegs *hCpswRegs,
1774  Uint32 portNum
1775 );
1776 
1811 (CSL_Xge_cpswRegs *hCpswRegs,
1812  Uint32 portNum
1813 );
1814 
1859 (CSL_Xge_cpswRegs *hCpswRegs,
1860  Uint32 portNum
1861 );
1862 
1897 (CSL_Xge_cpswRegs *hCpswRegs,
1898  Uint32 portNum
1899 );
1900 
1935 (CSL_Xge_cpswRegs *hCpswRegs,
1936  Uint32 portNum
1937 );
1938 
1983 (CSL_Xge_cpswRegs *hCpswRegs,
1984  Uint32 portNum
1985 );
1986 
2021 (CSL_Xge_cpswRegs *hCpswRegs,
2022  Uint32 portNum
2023 );
2024 
2059 (CSL_Xge_cpswRegs *hCpswRegs,
2060  Uint32 portNum
2061 );
2062 
2107 (CSL_Xge_cpswRegs *hCpswRegs,
2108  Uint32 portNum
2109 );
2110 
2145 (CSL_Xge_cpswRegs *hCpswRegs,
2146  Uint32 portNum
2147 );
2148 
2183 (CSL_Xge_cpswRegs *hCpswRegs,
2184  Uint32 portNum
2185 );
2186 
2187 
2232 (CSL_Xge_cpswRegs *hCpswRegs,
2233  Uint32 portNum
2234 );
2235 
2270 (CSL_Xge_cpswRegs *hCpswRegs,
2271  Uint32 portNum
2272 );
2273 
2308 (CSL_Xge_cpswRegs *hCpswRegs,
2309  Uint32 portNum
2310 );
2311 
2356 (CSL_Xge_cpswRegs *hCpswRegs,
2357  Uint32 portNum
2358 );
2359 
2394 (CSL_Xge_cpswRegs *hCpswRegs,
2395  Uint32 portNum
2396 );
2397 
2432 (CSL_Xge_cpswRegs *hCpswRegs,
2433  Uint32 portNum
2434 );
2435 
2480 (CSL_Xge_cpswRegs *hCpswRegs,
2481  Uint32 portNum
2482 );
2483 
2518 (CSL_Xge_cpswRegs *hCpswRegs,
2519  Uint32 portNum
2520 );
2521 
2556 (CSL_Xge_cpswRegs *hCpswRegs,
2557  Uint32 portNum
2558 );
2559 
2594 (CSL_Xge_cpswRegs *hCpswRegs,
2595  Uint32 portNum
2596 );
2597 
2638 (CSL_Xge_cpswRegs *hCpswRegs,
2639  Uint32 portNum,
2640  Uint32 macControlRegVal
2641 );
2642 
2686 (CSL_Xge_cpswRegs *hCpswRegs,
2687  Uint32 portNum,
2688  CSL_CPGMAC_SL_MACSTATUS* pMacStatus
2689 );
2690 
2725 (CSL_Xge_cpswRegs *hCpswRegs,
2726  Uint32 portNum
2727 );
2728 
2768 (CSL_Xge_cpswRegs *hCpswRegs,
2769  Uint32 portNum
2770 );
2771 
2807 (CSL_Xge_cpswRegs *hCpswRegs,
2808  Uint32 portNum
2809 );
2810 
2849 (CSL_Xge_cpswRegs *hCpswRegs,
2850  Uint32 portNum,
2851  Uint32 rxMaxLen
2852 );
2853 
2854 
2890 (CSL_Xge_cpswRegs *hCpswRegs,
2891  Uint32 portNum
2892 );
2893 
2932 (CSL_Xge_cpswRegs *hCpswRegs,
2933  Uint32 portNum,
2934  Uint32 txGap
2935 );
2936 
2972 (CSL_Xge_cpswRegs *hCpswRegs,
2973  Uint32 portNum
2974 );
2975 
3010 (CSL_Xge_cpswRegs *hCpswRegs,
3011  Uint32 portNum,
3012  Uint32 rxPauseTimer
3013 );
3014 
3050 (CSL_Xge_cpswRegs *hCpswRegs,
3051  Uint32 portNum
3052 );
3053 
3088 (CSL_Xge_cpswRegs *hCpswRegs,
3089  Uint32 portNum,
3090  Uint32 txPauseTimer
3091 );
3092 
3130 (CSL_Xge_cpswRegs *hCpswRegs,
3131  Uint32 portNum,
3132  Uint32* pEmulFreeBit,
3133  Uint32* pEmulSoftBit
3134 );
3135 
3175 (CSL_Xge_cpswRegs *hCpswRegs,
3176  Uint32 portNum,
3177  Uint32 emulFreeBit,
3178  Uint32 emulSoftBit
3179 );
3180 
3226 (CSL_Xge_cpswRegs *hCpswRegs,
3227  Uint32 portNum,
3228  Uint32* pMacRxPriMap
3229 );
3230 
3276 (CSL_Xge_cpswRegs *hCpswRegs,
3277  Uint32 portNum,
3278  Uint32* pMacRxPriMap
3279 );
3280 
3304 void CSL_CPGMAC_SL_clearMacStatusTorf (CSL_Xge_cpswRegs *hCpswRegs,
3305  Uint32 portNum);
3329 void CSL_CPGMAC_SL_clearMacStatusTorfPri (CSL_Xge_cpswRegs *hCpswRegs,
3330  Uint32 portNum);
3331 
3353 void CSL_CPGMAC_SL_getInterVLANCfg(CSL_Xge_cpswRegs *hCpswRegs,
3354  Uint32 portNum,
3355  Uint32 routeIndex,
3356  CSL_CPSW_INTERVLANCFG *pInterVLANCfg);
3357 
3379 void CSL_CPGMAC_SL_setInterVLANCfg(CSL_Xge_cpswRegs *hCpswRegs,
3380  Uint32 portNum,
3381  Uint32 routeIndex,
3382  CSL_CPSW_INTERVLANCFG *pInterVLANCfg);
3383 
3384 
3402 void CSL_CPGMAC_SL_getFifoStatus(CSL_Xge_cpswRegs *hCpswRegs,
3403  Uint32 portNum,
3404  CSL_CPGMAC_SL_FIFOSTATUS *pFifoStatus);
3405 
3433 Uint32 CSL_CPGMAC_SL_isTxShortGapLimitEnabled(CSL_Xge_cpswRegs *hCpswRegs,
3434  Uint32 portNum);
3435 
3461 void CSL_CPGMAC_SL_enableTxShortGapLimit(CSL_Xge_cpswRegs *hCpswRegs,
3462  Uint32 portNum);
3480 void CSL_CPGMAC_SL_disableTxShortGapLimit(CSL_Xge_cpswRegs *hCpswRegs,
3481  Uint32 portNum);
3482 
3483 #ifdef __cplusplus
3484 }
3485 #endif
3486 
3487 #endif
3488 
Uint32 CSL_CPGMAC_SL_isGigForceModeEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_resetMac(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_enableRxCSF(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_isRxCSFEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 idle
Definition: csl_cpgmac_sl.h:209
void CSL_CPGMAC_SL_enableRxCMF(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableRxCEF(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 macTxIdle
Definition: csl_cpgmac_sl.h:203
void CSL_CPGMAC_SL_enableRxCEF(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_getRxPauseTimerReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_enableTxShortGapLimit(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_enableTxFlowControl(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_enableTxShortGap(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 extFullDuplexEnabled
Definition: csl_cpgmac_sl.h:181
void CSL_CPGMAC_SL_enableGMII(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_setTxPauseTimerReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 txPauseTimer)
Uint32 CSL_CPGMAC_SL_isExtControlEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableGigabit(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_isTxShortGapEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableTxShortGapLimit(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableLoopback(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableIFCTLA(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableFullDuplex(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_isExtTxFlowEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_setRxMaxLen(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 rxMaxLen)
Uint32 CSL_CPGMAC_SL_isIFCTLBEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableExtControl(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 txPfcFlowAct
Definition: csl_cpgmac_sl.h:195
void CSL_CPGMAC_SL_enableFullDuplex(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_setMacRxPriMapReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pMacRxPriMap)
Uint32 CSL_CPGMAC_SL_setTxGap(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 txGap)
Uint32 rxPfcFlowAct
Definition: csl_cpgmac_sl.h:193
Holds the Sliver submodule's version info.
Definition: csl_cpgmac_sl.h:150
void CSL_CPGMAC_SL_getInterVLANCfg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 routeIndex, CSL_CPSW_INTERVLANCFG *pInterVLANCfg)
Uint32 rtlVer
Definition: csl_cpgmac_sl.h:158
void CSL_CPGMAC_SL_getMacRxPriMapReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pMacRxPriMap)
Holds the Enet_Pn_FIFO_Status register contents.
Definition: csl_cpsw.h:1651
void CSL_CPGMAC_SL_disableTxFlowControl(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableIFCTLB(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableGMII(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_isExtRxFlowEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_enableGigabit(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_isTxShortGapLimitEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_enableIFCTLB(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_isTxPaceEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_isRxCEFEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Holds MAC status register contents.
Definition: csl_cpgmac_sl.h:168
void CSL_CPGMAC_SL_enableIdleMode(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_enableCastagnoliCRC(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_clearMacStatusTorf(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_enableTxPace(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 extRxFlowEnabled
Definition: csl_cpgmac_sl.h:187
void CSL_CPGMAC_SL_enableExtTxFlow(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_getTxPauseTimerReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 torfPri
Definition: csl_cpgmac_sl.h:199
void CSL_CPGMAC_SL_getMacStatusReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPGMAC_SL_MACSTATUS *pMacStatus)
Uint32 CSL_CPGMAC_SL_getRxMaxLen(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_enableExtRxFlow(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Holds the Port intervlan configuration info.
Definition: csl_cpsw.h:1615
Uint32 extTxFlowEnabled
Definition: csl_cpgmac_sl.h:191
void CSL_CPGMAC_SL_enableGigForceMode(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_isMACResetDone(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_isRxCMFEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 majorVer
Definition: csl_cpgmac_sl.h:155
void CSL_CPGMAC_SL_disableRxCSF(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 preemptMacIdle
Definition: csl_cpgmac_sl.h:207
Uint32 CSL_CPGMAC_SL_isIFCTLAEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 extGigabitEnabled
Definition: csl_cpgmac_sl.h:183
Uint32 CSL_CPGMAC_SL_isGMIIEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_enableExtControl(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_isTxFlowControlEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableRxFlowControl(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_enableIFCTLA(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableCastagnoliCRC(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableTxShortGap(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_setMacControlReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 macControlRegVal)
Uint32 CSL_CPGMAC_SL_isIdleModeEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 txFlowActive
Definition: csl_cpgmac_sl.h:175
void CSL_CPGMAC_SL_enableRxFlowControl(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_getEmulControlReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pEmulFreeBit, Uint32 *pEmulSoftBit)
void CSL_CPGMAC_SL_setEmulControlReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 emulFreeBit, Uint32 emulSoftBit)
void CSL_CPGMAC_SL_disableRxCMF(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_enableLoopback(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableGigForceMode(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_clearMacStatusTorfPri(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_isGigabitEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 torf
Definition: csl_cpgmac_sl.h:201
Uint32 CSL_CPGMAC_SL_isFullDuplexEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableExtTxFlow(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableIdleMode(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_getMacControlReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_isCastagnoliCRCEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_isLoopbackModeEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 id
Definition: csl_cpgmac_sl.h:161
void CSL_CPGMAC_SL_setInterVLANCfg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 routeIndex, CSL_CPSW_INTERVLANCFG *pInterVLANCfg)
Uint32 rxFlowActive
Definition: csl_cpgmac_sl.h:179
Uint32 CSL_CPGMAC_SL_getTxGap(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 expressMacIdle
Definition: csl_cpgmac_sl.h:205
void CSL_CPGMAC_SL_getFifoStatus(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPGMAC_SL_FIFOSTATUS *pFifoStatus)
Uint32 CSL_CPGMAC_SL_isRxFlowControlEnabled(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
void CSL_CPGMAC_SL_disableExtRxFlow(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 minorVer
Definition: csl_cpgmac_sl.h:152
void CSL_CPGMAC_SL_disableTxPace(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 CSL_CPGMAC_SL_setRxPauseTimerReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 rxPauseTimer)