PDK API Guide for AM64x
CSL_CPSW_CPPI_P0_RXGAP Struct Reference

Detailed Description

Holds CPPI_P0_Rx_Gap register contents. This is applicable only for 2 port switch.

Data Fields

Uint32 rxGapCnt
 
Uint32 rxGapEnPri7
 
Uint32 rxGapEnPri6
 
Uint32 rxGapEnPri5
 
Uint32 rxGapEnPri4
 
Uint32 rxGapEnPri3
 
Uint32 rxGapEnPri2
 
Uint32 rxGapEnPri1
 
Uint32 rxGapEnPri0
 

Field Documentation

◆ rxGapCnt

Uint32 CSL_CPSW_CPPI_P0_RXGAP::rxGapCnt

Receive Gap Count - This is the number of clocks that will in the gap between received packet on port 0 when a priority has rxGapEnPri[7-0] set

◆ rxGapEnPri7

Uint32 CSL_CPSW_CPPI_P0_RXGAP::rxGapEnPri7

Receive Gap Enable for Priority 7

◆ rxGapEnPri6

Uint32 CSL_CPSW_CPPI_P0_RXGAP::rxGapEnPri6

Receive Gap Enable for Priority 6

◆ rxGapEnPri5

Uint32 CSL_CPSW_CPPI_P0_RXGAP::rxGapEnPri5

Receive Gap Enable for Priority 5

◆ rxGapEnPri4

Uint32 CSL_CPSW_CPPI_P0_RXGAP::rxGapEnPri4

Receive Gap Enable for Priority 4

◆ rxGapEnPri3

Uint32 CSL_CPSW_CPPI_P0_RXGAP::rxGapEnPri3

Receive Gap Enable for Priority 3

◆ rxGapEnPri2

Uint32 CSL_CPSW_CPPI_P0_RXGAP::rxGapEnPri2

Receive Gap Enable for Priority 2

◆ rxGapEnPri1

Uint32 CSL_CPSW_CPPI_P0_RXGAP::rxGapEnPri1

Receive Gap Enable for Priority 1

◆ rxGapEnPri0

Uint32 CSL_CPSW_CPPI_P0_RXGAP::rxGapEnPri0

Receive Gap Enable for Priority 0