![]() |
PDK API Guide for AM64x
|
API Auxilary header file for Ethernet MAC submodule CSL.
Contains the different control command and status query functions definations
(C) Copyright 2009-2013, Texas Instruments, Inc.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
Neither the name of Texas Instruments Incorporated nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Go to the source code of this file.
Data Structures | |
struct | CSL_CPGMAC_SL_VERSION |
Holds the Sliver submodule's version info. More... | |
struct | CSL_CPGMAC_SL_MACSTATUS |
Holds MAC status register contents. More... | |
Functions | |
Uint32 | CSL_CPGMAC_SL_isFullDuplexEnabled (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_enableFullDuplex (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_disableFullDuplex (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
Uint32 | CSL_CPGMAC_SL_isLoopbackModeEnabled (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_enableLoopback (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_disableLoopback (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
Uint32 | CSL_CPGMAC_SL_isRxFlowControlEnabled (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_enableRxFlowControl (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_disableRxFlowControl (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
Uint32 | CSL_CPGMAC_SL_isTxFlowControlEnabled (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_enableTxFlowControl (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_disableTxFlowControl (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
Uint32 | CSL_CPGMAC_SL_isGMIIEnabled (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_enableGMII (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_disableGMII (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
Uint32 | CSL_CPGMAC_SL_isTxPaceEnabled (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_enableTxPace (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_disableTxPace (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
Uint32 | CSL_CPGMAC_SL_isGigabitEnabled (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_enableGigabit (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_disableGigabit (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
Uint32 | CSL_CPGMAC_SL_isTxShortGapEnabled (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_enableTxShortGap (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_disableTxShortGap (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
Uint32 | CSL_CPGMAC_SL_isIdleModeEnabled (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_enableIdleMode (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_disableIdleMode (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
Uint32 | CSL_CPGMAC_SL_isCastagnoliCRCEnabled (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_enableCastagnoliCRC (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_disableCastagnoliCRC (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
Uint32 | CSL_CPGMAC_SL_isIFCTLAEnabled (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_enableIFCTLA (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_disableIFCTLA (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
Uint32 | CSL_CPGMAC_SL_isIFCTLBEnabled (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_enableIFCTLB (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_disableIFCTLB (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
Uint32 | CSL_CPGMAC_SL_isGigForceModeEnabled (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_enableGigForceMode (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_disableGigForceMode (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
Uint32 | CSL_CPGMAC_SL_isExtControlEnabled (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_enableExtControl (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_disableExtControl (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
Uint32 | CSL_CPGMAC_SL_isExtRxFlowEnabled (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_enableExtRxFlow (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_disableExtRxFlow (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
Uint32 | CSL_CPGMAC_SL_isExtTxFlowEnabled (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_enableExtTxFlow (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_disableExtTxFlow (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
Uint32 | CSL_CPGMAC_SL_isRxCEFEnabled (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_enableRxCEF (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_disableRxCEF (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
Uint32 | CSL_CPGMAC_SL_isRxCSFEnabled (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_enableRxCSF (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_disableRxCSF (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
Uint32 | CSL_CPGMAC_SL_isRxCMFEnabled (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_enableRxCMF (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_disableRxCMF (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
Uint32 | CSL_CPGMAC_SL_getMacControlReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_setMacControlReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 macControlRegVal) |
void | CSL_CPGMAC_SL_getMacStatusReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPGMAC_SL_MACSTATUS *pMacStatus) |
void | CSL_CPGMAC_SL_resetMac (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
Uint32 | CSL_CPGMAC_SL_isMACResetDone (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
Uint32 | CSL_CPGMAC_SL_getRxMaxLen (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
Uint32 | CSL_CPGMAC_SL_setRxMaxLen (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 rxMaxLen) |
Uint32 | CSL_CPGMAC_SL_getTxGap (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
Uint32 | CSL_CPGMAC_SL_setTxGap (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 txGap) |
Uint32 | CSL_CPGMAC_SL_getRxPauseTimerReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
Uint32 | CSL_CPGMAC_SL_setRxPauseTimerReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 rxPauseTimer) |
Uint32 | CSL_CPGMAC_SL_getTxPauseTimerReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
Uint32 | CSL_CPGMAC_SL_setTxPauseTimerReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 txPauseTimer) |
void | CSL_CPGMAC_SL_getEmulControlReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pEmulFreeBit, Uint32 *pEmulSoftBit) |
void | CSL_CPGMAC_SL_setEmulControlReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 emulFreeBit, Uint32 emulSoftBit) |
void | CSL_CPGMAC_SL_getMacRxPriMapReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pMacRxPriMap) |
void | CSL_CPGMAC_SL_setMacRxPriMapReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pMacRxPriMap) |
void | CSL_CPGMAC_SL_clearMacStatusTorf (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_clearMacStatusTorfPri (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_getInterVLANCfg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 routeIndex, CSL_CPSW_INTERVLANCFG *pInterVLANCfg) |
void | CSL_CPGMAC_SL_setInterVLANCfg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 routeIndex, CSL_CPSW_INTERVLANCFG *pInterVLANCfg) |
void | CSL_CPGMAC_SL_getFifoStatus (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPGMAC_SL_FIFOSTATUS *pFifoStatus) |
Uint32 | CSL_CPGMAC_SL_isTxShortGapLimitEnabled (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_enableTxShortGapLimit (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
void | CSL_CPGMAC_SL_disableTxShortGapLimit (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |