PDK API Guide for AM64x
CacheP.h
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2015-2017, Texas Instruments Incorporated
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  *
9  * * Redistributions of source code must retain the above copyright
10  * notice, this list of conditions and the following disclaimer.
11  *
12  * * Redistributions in binary form must reproduce the above copyright
13  * notice, this list of conditions and the following disclaimer in the
14  * documentation and/or other materials provided with the distribution.
15  *
16  * * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
50 #ifndef ti_osal_CacheP__include
51 #define ti_osal_CacheP__include
52 
53 #ifdef __cplusplus
54 extern "C" {
55 #endif
56 
57 #include <stdint.h>
58 #include <stdbool.h>
59 #include <stddef.h>
60 
69 typedef uint32_t Osal_CacheP_isCoherent;
71 #define OSAL_CACHEP_COHERENT ((uint32_t) 0U)
72 
73 #define OSAL_CACHEP_NOT_COHERENT ((uint32_t) 1U)
74 /* @} */
75 
84 extern void CacheP_wb(const void * addr, int32_t size);
85 
86 
95 extern void CacheP_Inv(const void * addr, int32_t size);
96 
97 
106 extern void CacheP_wbInv(const void * addr, int32_t size);
107 
118 void CacheP_fenceCpu2Dma(uintptr_t addr, uint32_t size, Osal_CacheP_isCoherent isCoherent);
119 
130 void CacheP_fenceDma2Cpu(uintptr_t addr, uint32_t size, Osal_CacheP_isCoherent isCoherent);
131 
132 #ifdef __cplusplus
133 }
134 #endif
135 
136 #endif /* ti_osal_CacheP__include */
137 /* @} */
void CacheP_fenceDma2Cpu(uintptr_t addr, uint32_t size, Osal_CacheP_isCoherent isCoherent)
Function to call before reading the memory to CPU after DMA operations.
uint32_t Osal_CacheP_isCoherent
This enumerator defines the cache coherent types.
Definition: CacheP.h:69
void CacheP_fenceCpu2Dma(uintptr_t addr, uint32_t size, Osal_CacheP_isCoherent isCoherent)
Function to call before handing over the memory buffer to DMA from CPU.
void CacheP_wbInv(const void *addr, int32_t size)
Function to write back and invalidate cache lines.
void CacheP_wb(const void *addr, int32_t size)
Function to write back cache lines.
void CacheP_Inv(const void *addr, int32_t size)
Function to invalidate cache lines.
uint64_t addr
Definition: csl_bcdma.h:1291
uint16_t size
Definition: tisci_boardcfg.h:112