PDK API Guide for AM64x
csl_cpsw.h
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1 
42 #ifndef CSL_CPSW_V5_H_
43 #define CSL_CPSW_V5_H_
44 
45 #ifdef __cplusplus
46 extern "C" {
47 #endif
48 
49 #include <stdbool.h>
50 #include <ti/csl/soc.h>
51 #include <ti/csl/csl.h>
52 #include <ti/csl/cslr_ale.h>
53 #include <ti/csl/cslr_xge_cpsw.h>
54 
61 #define CSL_CPSW_ALECONTROL_RATELIMIT_EN (1 << 0u)
62 
64 #define CSL_CPSW_ALECONTROL_AUTHMODE_EN (1 << 1u)
65 
67 #define CSL_CPSW_ALECONTROL_VLANAWARE_EN (1 << 2u)
68 
70 #define CSL_CPSW_ALECONTROL_RATELIMIT_TX_EN (1 << 3u)
71 
73 #define CSL_CPSW_ALECONTROL_OUIDENY_EN (1 << 5u)
74 
76 #define CSL_CPSW_ALECONTROL_VID0MODE_EN (1 << 6u)
77 
79 #define CSL_CPSW_ALECONTROL_LEARN_NO_VID_EN (1 << 7u)
80 
82 #define CSL_CPSW_ALECONTROL_AGEOUT_NOW_EN (1 << 29u)
83 
85 #define CSL_CPSW_ALECONTROL_CLRTABLE_EN (1 << 30u)
86 
88 #define CSL_CPSW_ALECONTROL_ALE_EN (1 << 31u)
89 
93 #define CSL_CPSW_PORTMASK_PORT0_EN (1 << 0u)
94 
96 #define CSL_CPSW_PORTMASK_PORT1_EN (1 << 1u)
97 
99 #define CSL_CPSW_PORTMASK_PORT2_EN (1 << 2u)
100 
102 #define CSL_CPSW_PORTMASK_PORT3_EN (1 << 3u)
103 
105 #define CSL_CPSW_PORTMASK_PORT4_EN (1 << 4u)
106 
108 #define CSL_CPSW_PORTMASK_PORT5_EN (1 << 5u)
109 
111 #define CSL_CPSW_PORTMASK_PORT6_EN (1 << 6u)
112 
114 #define CSL_CPSW_PORTMASK_PORT7_EN (1 << 7u)
115 
117 #define CSL_CPSW_PORTMASK_PORT8_EN (1 << 8u)
118 
123 typedef struct {
125  Uint32 minorVer;
126 
128  Uint32 majorVer;
129 
131  Uint32 rtlVer;
132 
134  Uint32 id;
136 
141 typedef struct {
143  Uint32 fifoLb;
144 
146  Uint32 vlanAware;
147 
149  Uint32 p0Enable;
150 
152  Uint32 p0PassPriTag;
153 
155  Uint32 p1PassPriTag;
156 
158  Uint32 p2PassPriTag;
159 
161  Uint32 p3PassPriTag;
162 
164  Uint32 p4PassPriTag;
165 
167  Uint32 p5PassPriTag;
168 
170  Uint32 p6PassPriTag;
171 
173  Uint32 p7PassPriTag;
174 
176  Uint32 p8PassPriTag;
177 
180 
187  Uint32 p0RxPad;
188 
191 
193  Uint32 eeeEnable;
194 
196 
201 typedef struct {
218 
223 typedef struct {
226 
229 
232 
236  Uint32 p0RxEccErrEn;
237 
241  Uint32 p0TxEccErrEn;
242 
247  Uint32 p0DscpIpv6En;
248 
253  Uint32 p0DscpIpv4En;
254 
259  Uint32 p0RxChksumEn;
260 
262 
268 typedef struct
269 {
274  Uint32 rxGapCnt;
275 
277  Uint32 rxGapEnPri7;
278 
280  Uint32 rxGapEnPri6;
281 
283  Uint32 rxGapEnPri5;
284 
286  Uint32 rxGapEnPri4;
287 
289  Uint32 rxGapEnPri3;
290 
292  Uint32 rxGapEnPri2;
293 
295  Uint32 rxGapEnPri1;
296 
298  Uint32 rxGapEnPri0;
299 
301 
307 typedef struct
308 {
315 
322 
329 
336 
343 
350 
357 
364 
366 
372 typedef struct
373 {
377 
381 
385 
389 
393 
397 
401 
405 
407 
412 typedef struct {
414  Uint32 p0FlowEnable;
415 
417  Uint32 p1FlowEnable;
418 
420  Uint32 p2FlowEnable;
421 
423  Uint32 p3FlowEnable;
424 
426  Uint32 p4FlowEnable;
427 
429  Uint32 p5FlowEnable;
430 
432  Uint32 p6FlowEnable;
433 
435  Uint32 p7FlowEnable;
436 
438  Uint32 p8FlowEnable;
439 
441 
446 typedef struct {
448  Uint32 minorVer;
449 
451  Uint32 majorVer;
452 
454  Uint32 rtlVer;
455 
457  Uint32 id;
459 
464 typedef enum {
468 
473 typedef enum {
479 
484 typedef struct {
487 
490 
493 
496 
499 
514 
520 
529 
531  Uint32 mcastLimit;
532 
534  Uint32 bcastLimit;
538  Uint32 dropDualVlan;
544 
546 
551 typedef enum {
557 
562 #define CSL_ALE_ENTRYTYPE_MAC_ADDR CSL_ALE_ENTRYTYPE_ADDRESS
563 
568 #define CSL_ALE_ENTRYTYPE_POLICER CSL_ALE_ENTRYTYPE_VLAN
569 
574 typedef enum {
580 
585 typedef enum {
590 
591 
596 typedef enum {
603 
609 typedef struct {
611  Uint8 macAddress [6];
612 
615 
617  Uint32 superEnable;
618 
620  Uint32 portMask;
621 
623  Uint32 ignMBits;
625 
631 typedef struct {
633  Uint8 macAddress [6];
634 
636  Uint32 vlanId;
637 
640 
642  Uint32 superEnable;
643 
645  Uint32 portMask;
646 
648  Uint32 ignMBits;
650 
656 typedef struct {
658  Uint8 macAddress [6];
659 
661  Uint32 ageable;
662 
664  Uint32 touched;
665 
666 
668  Uint32 secureEnable;
669 
671  Uint32 blockEnable;
672 
674  Uint32 portNumber;
675 
679  Uint32 trunkFlag;
680 
682 
688 typedef struct {
690  Uint8 ouiAddress [3];
691 
693  Uint32 ageable;
694 
696  Uint32 touched;
698 
704 typedef struct {
706  Uint8 macAddress [6];
707 
709  Uint32 vlanId;
710 
712  Uint32 ageable;
713 
715  Uint32 touched;
716 
718  Uint32 secureEnable;
719 
721  Uint32 blockEnable;
722 
724  Uint32 portNumber;
726  Uint32 trunkFlag;
728 
733 typedef struct {
735  Uint32 vlanId;
736 
738  Uint32 vlanMemList;
739 
742 
747 
752 
755 
757  Uint32 noLearnMask;
758 
761 
764 
766 
772 
777 typedef struct {
779  Uint32 ethertype;
780 
782 
783 
789 typedef struct {
791  Uint8 address [4];
793  UInt32 numLSBIgnore;
794 
796 
802 typedef struct {
804  Uint8 address [16];
806  UInt32 numLSBIgnore;
807 
809 
810 
811 #define CSL_CPSW_NUMALE_ENTRIES_MIN (64)
812 
813 #define CSL_CPSW_NUMSTATBLOCKS (9)
814 
815 
816 
830 typedef enum {
835 
840 typedef enum {
845 
850 typedef struct {
852  Uint32 p0StatEnable;
853 
855  Uint32 p1StatEnable;
856 
858  Uint32 p2StatEnable;
859 
861  Uint32 p3StatEnable;
862 
864  Uint32 p4StatEnable;
865 
867  Uint32 p5StatEnable;
868 
870  Uint32 p6StatEnable;
871 
873  Uint32 p7StatEnable;
874 
876  Uint32 p8StatEnable;
877 
879 
884 typedef struct {
887 
890 
893 
896 
899 
902 
905 
908 
911 
914 
917 
920 
923 
925 
926 
931 typedef struct {
934 
937 
940 
943 
946 
949 
952 
955 
958 
961 
964 
967 
970 
975  Uint32 tsUniEnable;
976 
981  Uint32 ts107Enable;
982 
987  Uint32 ts129Enable;
988 
993  Uint32 ts130Enable;
994 
999  Uint32 ts131Enable;
1000 
1005  Uint32 ts132Enable;
1006 
1008  Uint32 ts319Enable;
1009 
1011  Uint32 ts320Enable;
1012 
1015 
1018 
1020  Uint32 tsLType1;
1021 
1023  Uint32 tsLType2;
1024 
1027 
1030 
1033 
1036 
1038 
1039 
1044 typedef struct {
1053 
1056 
1059 
1061 
1062 
1067 typedef struct {
1074 
1076  Uint32 idleStep[8];
1077 
1079  Uint32 sendStep[8];
1080 
1082 
1087 typedef struct {
1089  Uint32 enable;
1090 
1092  Uint32 prescale;
1093 
1095 
1100 typedef struct {
1109 
1115  Uint32 idle2lpi;
1116 
1124  Uint32 lpi2wake;
1125 
1127 
1128 
1133 typedef struct {
1136 
1138  Uint32 rxLpi;
1139 
1141  Uint32 txLpi;
1142 
1145  Uint32 txWake;
1146 
1149  Uint32 txFifoHold;
1150 
1152  Uint32 rxFifoEmpty;
1153 
1155  Uint32 txFifoEmpty;
1156 
1158 
1171 typedef enum {
1181 
1186 typedef struct {
1195 
1197  Uint32 defThread;
1198 
1200 
1201 typedef struct {
1202  Uint32 trunkBase;
1210 
1211 
1212 typedef struct {
1216 
1217 typedef struct {
1221 
1222 #define CSL_ALE_TABLE_POLICER_ENUM2REG(policerType) ((policerType) << 0x1)
1223 
1224 
1227 #define CSL_CPSW_ALE_POLICER_PORT_VALID (1 << 0u)
1228 
1230 #define CSL_CPSW_ALE_POLICER_PRI_VALID (1 << 1u)
1231 
1233 #define CSL_CPSW_ALE_POLICER_OUI_VALID (1 << 2u)
1234 
1236 #define CSL_CPSW_ALE_POLICER_DST_MAC_VALID (1 << 3u)
1237 
1239 #define CSL_CPSW_ALE_POLICER_SRC_MAC_VALID (1 << 4u)
1240 
1242 #define CSL_CPSW_ALE_POLICER_OVLAN_VALID (1 << 5u)
1243 
1245 #define CSL_CPSW_ALE_POLICER_VLAN_VALID (1 << 6u)
1246 
1248 #define CSL_CPSW_ALE_POLICER_ETHERTYPE_VALID (1 << 7u)
1249 
1251 #define CSL_CPSW_ALE_POLICER_SRC_IP_VALID ( 1 << 8u)
1252 
1254 #define CSL_CPSW_ALE_POLICER_DST_IP_VALID (1 << 9u)
1255 
1258 #define CSL_CPSW_ALE_POLICER_THREAD_VALID ( 1 << 10u)
1259 
1261 #define CSL_CPSW_ALE_POLICER_PIR_VALID ( 1 << 11u)
1262 
1264 #define CSL_CPSW_ALE_POLICER_CIR_VALID ( 1 << 12u)
1265 
1267 #define CSL_CPSW_ALE_POLICER_PORT_TRUNK_VALID (1 << 13u)
1268 
1270 #define CSL_CPSW_ALE_POLICER_EGRESSOP_VALID (1 << 14u)
1271 
1276 typedef struct {
1278  Uint32 validBitmap;
1279 
1281  Uint32 port;
1282 
1284  Uint32 pri;
1285 
1287  Uint32 ouiIdx;
1288 
1290  Uint32 dstMacIdx;
1291 
1293  Uint32 srcMacIdx;
1294 
1296  Uint32 ovlanIdx;
1297 
1299  Uint32 vlanIdx;
1300 
1303 
1305  Uint32 srcIpIdx;
1306 
1308  Uint32 dstIpIdx;
1309 
1311  Uint32 thread;
1312 
1318 
1329  Uint32 egressOp;
1350 
1352 
1361 typedef struct {
1364 
1367 
1370 
1373 
1375  Uint32 RxCRCErrors;
1376 
1379 
1381  Uint32 RxOversized;
1382 
1384  Uint32 RxJabber;
1385 
1388 
1390  Uint32 RxFragments;
1391 
1393  Uint32 RxAleDrop;
1394 
1397 
1399  Uint32 RxOctets;
1400 
1403 
1406 
1409 
1412 
1414  Uint32 TxDeferred;
1415 
1417  Uint32 TxCollision;
1418 
1421 
1423  Uint32 TxMultiColl;
1424 
1427 
1429  Uint32 TxLateColl;
1430 
1432  Uint32 RxIpgError;
1433 
1436 
1438  Uint32 TxOctets;
1439 
1441  Uint32 Frame64;
1442 
1444  Uint32 Frame65t127;
1445 
1448 
1451 
1454 
1457 
1459  Uint32 NetOctets;
1460 
1463 
1466 
1468  Uint32 RxDropTop;
1469 
1472 
1474  Uint32 AleVidDrop;
1475 
1478 
1480  Uint32 Resv1[3];
1481 
1483  Uint32 AleUnKnUni;
1484 
1487 
1490 
1493 
1496 
1499 
1501  Uint32 AlePolMatch;
1502 
1504  Uint32 Resv2[46];
1505 
1508 
1510  Uint32 TxPriPktCnt[8];
1511 
1513  Uint32 TxPriByteCnt[8];
1514 
1516  Uint32 TxPriDropPktCnt[8];
1517 
1519  Uint32 TxPriDropByteCnt[8];
1520 
1521 } CSL_CPSW_STATS;
1522 
1523 typedef enum {
1529 
1530 typedef enum {
1540 
1541 typedef struct
1542 {
1551 
1552 typedef struct
1553 {
1558  Uint32 polTestIdx;
1560 
1561 typedef struct
1562 {
1563  Uint32 polHit ;
1564  Uint32 polRedhit ;
1565  Uint32 polYellowhit ;
1567 
1572 typedef struct {
1575 
1578 
1581 
1584 
1587 
1590 
1593 
1596 
1599 
1609 } CSL_CPSW_PTYPE;
1610 
1615 typedef struct {
1617  Uint8 dstMacAddress [6];
1619  Uint8 srcMacAddress [6];
1638  Uint32 replaceDaSa;
1642  Uint32 replaceVid;
1644  Uint32 vid;
1646 
1651 typedef struct {
1657  Uint32 estBufAct;
1663  Uint32 estAddErr;
1669  Uint32 estCntErr;
1683  Uint32 txPriActive;
1685 
1686 
1687 
1696 /********************************************************************************
1697 ************************* Ethernet Switch (CPSW) Submodule **********************
1698 ********************************************************************************/
1699 
1700 
1737 void CSL_CPSW_getCpswVersionInfo (CSL_Xge_cpswRegs *hCpswRegs,
1738  CSL_CPSW_VERSION* pVersionInfo
1739 );
1740 
1741 
1778 Uint32 CSL_CPSW_isVlanAwareEnabled (CSL_Xge_cpswRegs *hCpswRegs);
1779 
1780 
1811 void CSL_CPSW_enableVlanAware (CSL_Xge_cpswRegs *hCpswRegs);
1812 
1813 
1814 void CSL_CPSW_setVlanType (CSL_Xge_cpswRegs *hCpswRegs,Uint32 vlanType);
1815 
1816 
1847 void CSL_CPSW_disableVlanAware (CSL_Xge_cpswRegs *hCpswRegs);
1848 
1849 
1886 Uint32 CSL_CPSW_isPort0Enabled (CSL_Xge_cpswRegs *hCpswRegs);
1887 
1888 
1918 void CSL_CPSW_enablePort0 (CSL_Xge_cpswRegs *hCpswRegs);
1919 
1920 
1950 void CSL_CPSW_disablePort0 (CSL_Xge_cpswRegs *hCpswRegs);
1951 
1952 
1988 Uint32 CSL_CPSW_isPort0PassPriTagEnabled (CSL_Xge_cpswRegs *hCpswRegs);
1989 
1990 
2021 void CSL_CPSW_enablePort0PassPriTag (CSL_Xge_cpswRegs *hCpswRegs);
2022 
2023 
2054 void CSL_CPSW_disablePort0PassPriTag (CSL_Xge_cpswRegs *hCpswRegs);
2055 
2056 
2092 Uint32 CSL_CPSW_isPort1PassPriTagEnabled (CSL_Xge_cpswRegs *hCpswRegs);
2093 
2094 
2125 void CSL_CPSW_enablePortPassPriTag (CSL_Xge_cpswRegs *hCpswRegs,Uint32 portNum);
2126 
2127 
2158 void CSL_CPSW_disablePortPassPriTag (CSL_Xge_cpswRegs *hCpswRegs,Uint32 portNum);
2159 
2160 
2201 void CSL_CPSW_getCpswControlReg (CSL_Xge_cpswRegs *hCpswRegs,
2202  CSL_CPSW_CONTROL* pControlRegInfo
2203 );
2204 
2205 
2250 void CSL_CPSW_setCpswControlReg (CSL_Xge_cpswRegs *hCpswRegs,
2251  CSL_CPSW_CONTROL* pControlRegInfo
2252 );
2253 
2254 
2289 void CSL_CPSW_getEmulationControlReg (CSL_Xge_cpswRegs *hCpswRegs,
2290  Uint32* pFree,
2291  Uint32* pSoft
2292 );
2293 
2294 
2332 void CSL_CPSW_setEmulationControlReg (CSL_Xge_cpswRegs *hCpswRegs,
2333  Uint32 free,
2334  Uint32 soft
2335 );
2336 
2337 
2373 void CSL_CPSW_getPortStatsEnableReg (CSL_Xge_cpswRegs *hCpswRegs,
2374  CSL_CPSW_PORTSTAT* pPortStatsCfg
2375 );
2376 
2377 
2417 void CSL_CPSW_setPortStatsEnableReg (CSL_Xge_cpswRegs *hCpswRegs,
2418  CSL_CPSW_PORTSTAT* pPortStatsCfg
2419 );
2420 
2421 
2458 Uint32 CSL_CPSW_isSoftIdle (CSL_Xge_cpswRegs *hCpswRegs);
2459 
2460 
2491 void CSL_CPSW_enableSoftIdle (CSL_Xge_cpswRegs *hCpswRegs);
2492 
2493 
2524 void CSL_CPSW_disableSoftIdle (CSL_Xge_cpswRegs *hCpswRegs);
2525 
2526 
2572 void CSL_CPSW_getPortControlReg (CSL_Xge_cpswRegs *hCpswRegs,
2573  Uint32 portNum,
2574  CSL_CPSW_PORT_CONTROL* pControlInfo
2575 );
2576 
2577 
2629 void CSL_CPSW_setPortControlReg (CSL_Xge_cpswRegs *hCpswRegs,
2630  Uint32 portNum,
2631  CSL_CPSW_PORT_CONTROL* pControlInfo
2632 );
2633 
2634 
2668 void CSL_CPSW_getCppiSourceIdReg (CSL_Xge_cpswRegs *hCpswRegs,
2669  Uint32* pTxSrcId
2670 );
2671 
2672 
2709 void CSL_CPSW_setCppiSourceIdReg (CSL_Xge_cpswRegs *hCpswRegs,
2710  Uint32* pTxSrcId
2711 );
2712 
2713 
2750 void CSL_CPSW_getPort0VlanReg (CSL_Xge_cpswRegs *hCpswRegs,
2751  Uint32* pPortVID,
2752  Uint32* pPortCFI,
2753  Uint32* pPortPRI
2754 );
2755 
2756 
2798 void CSL_CPSW_setPort0VlanReg (CSL_Xge_cpswRegs *hCpswRegs,
2799  Uint32 portVID,
2800  Uint32 portCFI,
2801  Uint32 portPRI
2802 );
2803 
2804 
2847 void CSL_CPSW_getPort0RxPriMapReg (CSL_Xge_cpswRegs *hCpswRegs,
2848  Uint32* pPortRxPriMap
2849 );
2850 
2851 
2896 void CSL_CPSW_setPort0RxPriMapReg (CSL_Xge_cpswRegs *hCpswRegs,
2897  Uint32* pPortRxPriMap
2898 );
2899 
2900 
2933 Uint32 CSL_CPSW_getPort0FlowIdOffset (CSL_Xge_cpswRegs *hCpswRegs);
2934 
2935 
2972 void CSL_CPSW_setPort0FlowIdOffset (CSL_Xge_cpswRegs *hCpswRegs,
2973  Uint32 flowIdOffset
2974 );
2975 
2976 
3008 Uint32 CSL_CPSW_getPort0RxMaxLen (CSL_Xge_cpswRegs *hCpswRegs);
3009 
3010 
3045 void CSL_CPSW_setPort0RxMaxLen (CSL_Xge_cpswRegs *hCpswRegs,
3046  Uint32 rxMaxLen
3047 );
3048 
3049 
3050 
3095 void CSL_CPSW_getPortBlockCountReg (CSL_Xge_cpswRegs *hCpswRegs,
3096  Uint32 portNum,
3097  Uint32* pRxBlkCnt_e,
3098  Uint32* pRxBlkCnt_p,
3099  Uint32* pTxBlkCnt);
3100 
3101 
3136 Uint32 CSL_CPSW_getPortRxMaxLen (CSL_Xge_cpswRegs *hCpswRegs,
3137  Uint32 portNum
3138 );
3139 
3140 
3179 void CSL_CPSW_setPortRxMaxLen (CSL_Xge_cpswRegs *hCpswRegs,
3180  Uint32 portNum,
3181  Uint32 rxMaxLen
3182 );
3183 
3184 
3240  CSL_Xge_cpswRegs *hCpswRegs,
3241  Uint32 portNum,
3242  Uint32* pPortTxPriMap
3243 );
3244 
3245 
3303  CSL_Xge_cpswRegs *hCpswRegs,
3304  Uint32 portNum,
3305  Uint32* pPortTxPriMap
3306 );
3307 
3308 
3309 
3364 void CSL_CPSW_getPortRxPriMapReg (CSL_Xge_cpswRegs *hCpswRegs,
3365  Uint32 portNum,
3366  Uint32* pPortRxPriMap
3367 );
3368 
3369 
3426 void CSL_CPSW_setPortRxPriMapReg (CSL_Xge_cpswRegs *hCpswRegs,
3427  Uint32 portNum,
3428  Uint32* pPortRxPriMap
3429 );
3430 
3431 
3487 void CSL_CPSW_getPortRxDscpMap (CSL_Xge_cpswRegs *hCpswRegs,
3488  Uint32 portNum,
3489  Uint32* pRxDscpPriMap
3490 );
3491 
3492 
3552 void CSL_CPSW_setPortRxDscpMap (CSL_Xge_cpswRegs *hCpswRegs,
3553  Uint32 portNum,
3554  Uint32* pRxDscpPriMap
3555 );
3556 
3557 
3594 void CSL_CPSW_getEEEGlobConfig (CSL_Xge_cpswRegs *hCpswRegs,
3595  CSL_CPSW_EEE_GLOB_CONFIG* pGlobConfig
3596 );
3597 
3598 
3639 void CSL_CPSW_setEEEGlobConfig (CSL_Xge_cpswRegs *hCpswRegs,
3640  CSL_CPSW_EEE_GLOB_CONFIG* pGlobConfig
3641 );
3642 
3643 
3687 void CSL_CPSW_getEEEPortConfig (CSL_Xge_cpswRegs *hCpswRegs,
3688  Uint32 portNum,
3689  CSL_CPSW_EEE_PORT_CONFIG* pPortConfig
3690 );
3691 
3692 
3740 void CSL_CPSW_setEEEPortConfig (CSL_Xge_cpswRegs *hCpswRegs,
3741  Uint32 portNum,
3742  CSL_CPSW_EEE_PORT_CONFIG* pPortConfig
3743 );
3744 
3745 
3800 void CSL_CPSW_EEEPortStatus (CSL_Xge_cpswRegs *hCpswRegs,
3801  Uint32 portNum,
3802  CSL_CPSW_EEE_PORT_STATUS* pPortStatus
3803 );
3804 
3805 
3806 
3852 void CSL_CPSW_getPortVlanReg (CSL_Xge_cpswRegs *hCpswRegs,
3853  Uint32 portNum,
3854  Uint32* pPortVID,
3855  Uint32* pPortCFI,
3856  Uint32* pPortPRI
3857 );
3858 
3859 
3860 
3910 void CSL_CPSW_setPortVlanReg (CSL_Xge_cpswRegs *hCpswRegs,
3911  Uint32 portNum,
3912  Uint32 portVID,
3913  Uint32 portCFI,
3914  Uint32 portPRI
3915 );
3916 
3917 
3966 void CSL_CPSW_getPortMaxBlksReg (CSL_Xge_cpswRegs *hCpswRegs,
3967  Uint32 portNum,
3968  Uint32* pRxMaxBlks,
3969  Uint32* pTxMaxBlks
3970 );
3971 
3972 
4021 void CSL_CPSW_setPortMaxBlksReg (CSL_Xge_cpswRegs *hCpswRegs,
4022  Uint32 portNum,
4023  Uint32 rxMaxBlks,
4024  Uint32 txMaxBlks
4025 );
4026 
4027 
4071 void CSL_CPSW_getPortMACAddress (CSL_Xge_cpswRegs *hCpswRegs,
4072  Uint32 portNum,
4073  Uint8* pMacAddress
4074 );
4075 
4076 
4125 void CSL_CPSW_setPortMACAddress (CSL_Xge_cpswRegs *hCpswRegs,
4126  Uint32 portNum,
4127  Uint8* pMacAddress
4128 );
4129 
4130 
4131 
4182 void CSL_CPSW_getPortTimeSyncCntlReg (CSL_Xge_cpswRegs *hCpswRegs,
4183  Uint32 portNum,
4184  CSL_CPSW_TSCNTL* pTimeSyncCntlCfg
4185 );
4186 
4187 
4243 void CSL_CPSW_setPortTimeSyncCntlReg (CSL_Xge_cpswRegs *hCpswRegs,
4244  Uint32 portNum,
4245  CSL_CPSW_TSCNTL* pTimeSyncCntlCfg
4246 );
4247 
4248 
4287 void CSL_CPSW_getPortTimeSyncSeqIdReg (CSL_Xge_cpswRegs *hCpswRegs,
4288  Uint32 portNum,
4289  Uint32* pTsLtype,
4290  Uint32* pTsSeqIdOffset
4291 );
4292 
4293 
4294 void CSL_CPSW_getVlanLTypeReg (CSL_Xge_cpswRegs *hCpswRegs,
4295  Uint32* pVlanLtypeInner,
4296  Uint32* pVlanLtypeOuter
4297 );
4298 
4299 
4336 void CSL_CPSW_setVlanLTypeReg (CSL_Xge_cpswRegs *hCpswRegs,
4337  Uint32 pVlanLtypeInner,
4338  Uint32 pVlanLtypeOuter
4339 );
4340 
4341 
4382 void CSL_CPSW_setPortTimeSyncSeqIdReg (CSL_Xge_cpswRegs *hCpswRegs,
4383  Uint32 portNum,
4384  Uint32 tsLtype,
4385  Uint32 tsSeqIdOffset
4386 );
4387 
4388 
4426 void CSL_CPSW_getPortTimeSyncVlanLTypeReg (CSL_Xge_cpswRegs *hCpswRegs,
4427  Uint32 portNum,
4428  Uint32* pTsVlanLtype1,
4429  Uint32* pTsVlanLtype2
4430 );
4431 
4432 
4472 void CSL_CPSW_setPortTimeSyncVlanLTypeReg (CSL_Xge_cpswRegs *hCpswRegs,
4473  Uint32 portNum,
4474  Uint32 tsVlanLtype1,
4475  Uint32 tsVlanLtype2
4476 );
4477 
4478 
4550 void CSL_CPSW_getPortTimeSyncConfig (CSL_Xge_cpswRegs *hCpswRegs,
4551  Uint32 portNum,
4552  CSL_CPSW_TSCONFIG* pTimeSyncConfig
4553 );
4554 
4555 
4631 void CSL_CPSW_setPortTimeSyncConfig (CSL_Xge_cpswRegs *hCpswRegs,
4632  Uint32 portNum,
4633  CSL_CPSW_TSCONFIG* pTimeSyncConfig
4634 );
4635 
4636 
4637 
4638 
4639 /********************************************************************************
4640 ************************* Statistics (STATS) Submodule *************************
4641 ********************************************************************************/
4642 
4787 void CSL_CPSW_getStats (CSL_Xge_cpswRegs *hCpswRegs,
4788  CSL_CPSW_STATS* pCpswStats
4789 );
4790 
4791 
4792 void CSL_CPSW_getPortStats (CSL_Xge_cpswRegs *hCpswRegs,
4793  Uint32 portNum,
4794  CSL_CPSW_STATS* pCpswStats
4795 );
4796 
4797 
4906 void CSL_CPSW_getRawStats (CSL_Xge_cpswRegs *hCpswRegs,
4907  CSL_CPSW_STATS* pCpswStats
4908 );
4909 
4910 
4911 void CSL_CPSW_getPortRawStats (CSL_Xge_cpswRegs *hCpswRegs,
4912  Uint32 portNum,
4913  CSL_CPSW_STATS* pCpswStats
4914 );
4915 
4916 
4917 
4918 /********************************************************************************
4919 ******************** Address Lookup Engine (ALE) Submodule *********************
4920 ********************************************************************************/
4921 
4959 void CSL_CPSW_getAleVersionInfo (CSL_AleRegs *hCpswAleRegs,
4960  CSL_CPSW_ALE_VERSION* pVersionInfo
4961 );
4962 
4963 
5003 Uint32 CSL_CPSW_isAleRateLimitEnabled (CSL_AleRegs *hCpswAleRegs);
5004 
5005 
5036 void CSL_CPSW_enableAleRateLimit (CSL_AleRegs *hCpswAleRegs);
5037 
5038 
5069 void CSL_CPSW_disableAleRateLimit (CSL_AleRegs *hCpswAleRegs);
5070 
5071 
5107 Uint32 CSL_CPSW_isAleMacAuthModeEnabled (CSL_AleRegs *hCpswAleRegs);
5108 
5109 
5140 void CSL_CPSW_enableAleMacAuthMode (CSL_AleRegs *hCpswAleRegs);
5141 
5142 
5173 void CSL_CPSW_disableAleMacAuthMode (CSL_AleRegs *hCpswAleRegs);
5174 
5175 
5211 Uint32 CSL_CPSW_isAleVlanAwareEnabled (CSL_AleRegs *hCpswAleRegs);
5212 
5213 
5244 void CSL_CPSW_enableAleVlanAware (CSL_AleRegs *hCpswAleRegs);
5245 
5246 
5277 void CSL_CPSW_disableAleVlanAware (CSL_AleRegs *hCpswAleRegs);
5278 
5279 
5318 Uint32 CSL_CPSW_isAleTxRateLimitEnabled (CSL_AleRegs *hCpswAleRegs);
5319 
5320 
5351 void CSL_CPSW_enableAleTxRateLimit (CSL_AleRegs *hCpswAleRegs);
5352 
5353 
5384 void CSL_CPSW_disableAleTxRateLimit (CSL_AleRegs *hCpswAleRegs);
5385 
5386 
5422 Uint32 CSL_CPSW_isAleBypassEnabled (CSL_AleRegs *hCpswAleRegs);
5423 
5424 
5454 void CSL_CPSW_enableAleBypass (CSL_AleRegs *hCpswAleRegs);
5455 
5456 
5486 void CSL_CPSW_disableAleBypass (CSL_AleRegs *hCpswAleRegs);
5487 
5488 
5524 Uint32 CSL_CPSW_isAleOUIDenyModeEnabled (CSL_AleRegs *hCpswAleRegs);
5525 
5526 
5556 void CSL_CPSW_enableAleOUIDenyMode (CSL_AleRegs *hCpswAleRegs);
5557 
5558 
5588 void CSL_CPSW_disableAleOUIDenyMode (CSL_AleRegs *hCpswAleRegs);
5589 
5590 
5628 Uint32 CSL_CPSW_isAleVID0ModeEnabled (CSL_AleRegs *hCpswAleRegs);
5629 
5630 
5660 void CSL_CPSW_enableAleVID0Mode (CSL_AleRegs *hCpswAleRegs);
5661 
5662 
5692 void CSL_CPSW_disableAleVID0Mode (CSL_AleRegs *hCpswAleRegs);
5693 
5694 
5732 Uint32 CSL_CPSW_isAleLearnNoVIDEnabled (CSL_AleRegs *hCpswAleRegs);
5733 
5734 
5765 void CSL_CPSW_enableAleLearnNoVID (CSL_AleRegs *hCpswAleRegs);
5766 
5767 
5797 void CSL_CPSW_disableAleLearnNoVID (CSL_AleRegs *hCpswAleRegs);
5798 
5799 
5836 Uint32 CSL_CPSW_isAleUUNIToHostEnabled (CSL_AleRegs *hCpswAleRegs);
5837 
5838 
5869 void CSL_CPSW_enableAleUUNIToHost (CSL_AleRegs *hCpswAleRegs);
5870 
5871 
5902 void CSL_CPSW_disableAleUUNIToHost (CSL_AleRegs *hCpswAleRegs);
5903 
5904 
5945 Uint32 CSL_CPSW_isAleUVLANNoLearnEnabled (CSL_AleRegs *hCpswAleRegs);
5946 
5947 
5978 void CSL_CPSW_enableAleUVLANNoLearn (CSL_AleRegs *hCpswAleRegs);
5979 
5980 
6011 void CSL_CPSW_disableAleUVLANNoLearn (CSL_AleRegs *hCpswAleRegs);
6012 
6013 
6045 Uint32 CSL_CPSW_getAleUpdateBW (CSL_AleRegs *hCpswAleRegs);
6046 
6047 
6079 (CSL_AleRegs *hCpswAleRegs,
6080  Uint32 aleUpdBW
6081 );
6082 
6083 
6084 
6116 void CSL_CPSW_startAleAgeOutNow (CSL_AleRegs *hCpswAleRegs);
6117 
6118 
6150 Uint32 CSL_CPSW_isAleAgeOutDone (CSL_AleRegs *hCpswAleRegs);
6151 
6152 
6183 void CSL_CPSW_clearAleTable (CSL_AleRegs *hCpswAleRegs);
6184 
6185 
6221 Uint32 CSL_CPSW_isAleEnabled (CSL_AleRegs *hCpswAleRegs);
6222 
6223 
6253 void CSL_CPSW_enableAle (CSL_AleRegs *hCpswAleRegs);
6254 
6255 
6285 void CSL_CPSW_disableAle (CSL_AleRegs *hCpswAleRegs);
6286 
6287 
6318 Uint32 CSL_CPSW_getAleControlReg (CSL_AleRegs *hCpswAleRegs);
6319 
6320 
6357 (CSL_AleRegs *hCpswAleRegs,
6358  Uint32 aleCtrlVal
6359 );
6360 
6361 
6398 (CSL_AleRegs *hCpswAleRegs,
6399  Uint32* pNumPolicers,
6400  Uint32* pNumEntries
6401 );
6402 
6403 
6404 void CSL_CPSW_getAleStatusNumAleEntries(CSL_AleRegs *hCpswAleRegs,Uint32* pNumEntries);
6405 
6406 
6407 CSL_CPSW_ALE_RAMDEPTH_E CSL_CPSW_getAleStatusRamDepth(CSL_AleRegs *hCpswAleRegs);
6408 
6409 
6410 
6411 void CSL_CPSW_getAleStatusVlanMask(CSL_AleRegs *hCpswAleRegs,
6412  bool *vlanMsk08,
6413  bool *vlanMsk12);
6414 
6415 
6446 Uint32 CSL_CPSW_getAlePrescaleReg (CSL_AleRegs *hCpswAleRegs);
6447 
6448 
6484 (CSL_AleRegs *hCpswAleRegs,
6485  Uint32 alePrescaleVal
6486 );
6487 
6488 
6531 (CSL_AleRegs *hCpswAleRegs,
6532  Uint32* pAgingPrescale,
6533  Uint32* pAgingPeriod
6534 );
6535 
6536 
6582 (CSL_AleRegs *hCpswAleRegs,
6583  Uint32 agingPrescale,
6584  Uint32 agingPeriod
6585 );
6586 
6587 
6630 (CSL_AleRegs *hCpswAleRegs,
6631  Uint32* pUnVlanMemList,
6632  Uint32* pUnMcastFloodMask,
6633  Uint32* pUnRegMcastFloodMask,
6634  Uint32* pUnForceUntagEgress
6635 );
6636 
6637 
6685 (CSL_AleRegs *hCpswAleRegs,
6686  Uint32 unVlanMemList,
6687  Uint32 unMcastFloodMask,
6688  Uint32 unRegMcastFloodMask,
6689  Uint32 unForceUntagEgress
6690 );
6691 
6692 
6733 (CSL_AleRegs *hCpswAleRegs,
6734  Uint32* vlanMaskMux
6735 );
6736 
6737 
6781 (CSL_AleRegs *hCpswAleRegs,
6782  Uint32* vlanMaskMux
6783 );
6784 
6785 
6826 (
6827  CSL_AleRegs *hCpswAleRegs,
6828  Uint32 maskMuxIndex,
6829  Uint32* vlanMaskMuxPtr
6830 );
6831 
6832 
6877 (
6878  CSL_AleRegs *hCpswAleRegs,
6879  Uint32 maskMuxIndex,
6880  Uint32 vlanMaskMuxVal
6881 );
6882 
6883 
6935 (CSL_AleRegs *hCpswAleRegs,
6936  Uint32 index,
6937  Uint32* pAleInfoWd0,
6938  Uint32* pAleInfoWd1,
6939  Uint32* pAleInfoWd2
6940 );
6941 
6942 
6996 (CSL_AleRegs *hCpswAleRegs,
6997  Uint32 index,
6998  Uint32 aleInfoWd0,
6999  Uint32 aleInfoWd1,
7000  Uint32 aleInfoWd2
7001 );
7002 
7003 
7047 CSL_CPSW_ALE_ENTRYTYPE CSL_CPSW_getALEEntryType(CSL_AleRegs *hCpswAleRegs,
7048  Uint32 index,
7049  CSL_CPSW_ALETABLE_TYPE aleType);
7050 
7107 CSL_CPSW_ALE_ADDRTYPE CSL_CPSW_getALEAddressType(CSL_AleRegs *hCpswAleRegs,
7108  Uint32 index,
7109  CSL_CPSW_ALETABLE_TYPE aleType);
7110 
7171  Uint32 index,
7172  CSL_CPSW_ALETABLE_TYPE aleType);
7173 
7229 void CSL_CPSW_getAleMcastAddrEntry(CSL_AleRegs *hCpswAleRegs,
7230  Uint32 index,
7231  CSL_CPSW_ALE_MCASTADDR_ENTRY* pMcastAddrCfg,
7232  CSL_CPSW_ALETABLE_TYPE aleType);
7233 
7234 
7287 void CSL_CPSW_setAleMcastAddrEntry(CSL_AleRegs *hCpswAleRegs,
7288  Uint32 index,
7289  CSL_CPSW_ALE_MCASTADDR_ENTRY* pMcastAddrCfg,
7290  CSL_CPSW_ALETABLE_TYPE aleType);
7291 
7347 void CSL_CPSW_getAleVlanMcastAddrEntry(CSL_AleRegs *hCpswAleRegs,
7348  Uint32 index,
7349  CSL_CPSW_ALE_VLANMCASTADDR_ENTRY* pVlanMcastAddrCfg,
7350  CSL_CPSW_ALETABLE_TYPE aleType);
7351 
7404 void CSL_CPSW_setAleVlanMcastAddrEntry(CSL_AleRegs *hCpswAleRegs,
7405  Uint32 index,
7406  CSL_CPSW_ALE_VLANMCASTADDR_ENTRY* pVlanMcastAddrCfg,
7407  CSL_CPSW_ALETABLE_TYPE aleType);
7408 
7464 void CSL_CPSW_getAleUnicastAddrEntry(CSL_AleRegs *hCpswAleRegs,
7465  Uint32 index,
7466  CSL_CPSW_ALE_UNICASTADDR_ENTRY* pUcastAddrCfg,
7467  CSL_CPSW_ALETABLE_TYPE aleType);
7468 
7521 void CSL_CPSW_setAleUnicastAddrEntry(CSL_AleRegs *hCpswAleRegs,
7522  Uint32 index,
7523  CSL_CPSW_ALE_UNICASTADDR_ENTRY* pUcastAddrCfg,
7524  CSL_CPSW_ALETABLE_TYPE aleType);
7525 
7581 void CSL_CPSW_getAleOUIAddrEntry(CSL_AleRegs *hCpswAleRegs,
7582  Uint32 index,
7583  CSL_CPSW_ALE_OUIADDR_ENTRY* pOUIAddrCfg,
7584  CSL_CPSW_ALETABLE_TYPE aleType);
7585 
7638 void CSL_CPSW_setAleOUIAddrEntry(CSL_AleRegs *hCpswAleRegs,
7639  Uint32 index,
7640  CSL_CPSW_ALE_OUIADDR_ENTRY* pOUIAddrCfg,
7641  CSL_CPSW_ALETABLE_TYPE aleType);
7642 
7698 void CSL_CPSW_getAleVlanUnicastAddrEntry(CSL_AleRegs *hCpswAleRegs,
7699  Uint32 index,
7700  CSL_CPSW_ALE_VLANUNICASTADDR_ENTRY* pVlanUcastAddrCfg,
7701  CSL_CPSW_ALETABLE_TYPE aleType);
7702 
7755 void CSL_CPSW_setAleVlanUnicastAddrEntry(CSL_AleRegs *hCpswAleRegs,
7756  Uint32 index,
7757  CSL_CPSW_ALE_VLANUNICASTADDR_ENTRY* pVlanUcastAddrCfg,
7758  CSL_CPSW_ALETABLE_TYPE aleType);
7759 
7779 void CSL_CPSW_getAleVlanEntry(CSL_AleRegs *hCpswAleRegs,
7780  Uint32 index,
7781  CSL_CPSW_ALE_VLAN_ENTRY* pVlanCfg,
7782  CSL_CPSW_ALETABLE_TYPE aleType);
7783 
7784 
7836 void CSL_CPSW_setAleVlanEntry(CSL_AleRegs *hCpswAleRegs,
7837  Uint32 index,
7838  CSL_CPSW_ALE_VLAN_ENTRY* pVlanCfg,
7839  CSL_CPSW_ALETABLE_TYPE aleType);
7840 
7893 void CSL_CPSW_getAleOutVlanEntry(CSL_AleRegs *hCpswAleRegs,
7894  Uint32 index,
7895  CSL_CPSW_ALE_OUTER_VLAN_ENTRY * pOutVlanCfg,
7896  CSL_CPSW_ALETABLE_TYPE aleType);
7897 
7950 void CSL_CPSW_setAleOutVlanEntry(CSL_AleRegs *hCpswAleRegs,
7951  Uint32 index,
7952  CSL_CPSW_ALE_OUTER_VLAN_ENTRY* pOutVlanCfg,
7953  CSL_CPSW_ALETABLE_TYPE aleType);
7954 
8007 void CSL_CPSW_getAleEthertypeEntry(CSL_AleRegs *hCpswAleRegs,
8008  Uint32 index,
8009  CSL_CPSW_ALE_ETHERTYPE_ENTRY* pEthertypeCfg,
8010  CSL_CPSW_ALETABLE_TYPE aleType);
8011 
8063 void CSL_CPSW_setAleEthertypeEntry(CSL_AleRegs *hCpswAleRegs,
8064  Uint32 index,
8065  CSL_CPSW_ALE_ETHERTYPE_ENTRY* pEthertypeCfg,
8066  CSL_CPSW_ALETABLE_TYPE aleType);
8067 
8120 void CSL_CPSW_getAleIPv4Entry(CSL_AleRegs *hCpswAleRegs,
8121  Uint32 index,
8122  CSL_CPSW_ALE_IPv4_ENTRY* pIPv4Cfg,
8123  CSL_CPSW_ALETABLE_TYPE aleType);
8124 
8125 
8177 void CSL_CPSW_setAleIPv4Entry(CSL_AleRegs *hCpswAleRegs,
8178  Uint32 index,
8179  CSL_CPSW_ALE_IPv4_ENTRY* pIPv4Cfg,
8180  CSL_CPSW_ALETABLE_TYPE aleType);
8181 
8199 Uint32 CSL_CPSW_getAleIPv6HighEntryOffset(CSL_AleRegs *hCpswAleRegs);
8200 
8218 Uint32 CSL_CPSW_getAleIPv6HighEntryIndex(CSL_AleRegs *hCpswAleRegs,Uint32 entryIndex);
8219 
8237 Uint32 CSL_CPSW_getAleIPv6LowEntryIndex(CSL_AleRegs *hCpswAleRegs,Uint32 entryIndex);
8238 
8291 void CSL_CPSW_getAleIPv6Entry(CSL_AleRegs *hCpswAleRegs,
8292  Uint32 index,
8293  CSL_CPSW_ALE_IPv6_ENTRY* pIPv6Cfg,
8294  CSL_CPSW_ALETABLE_TYPE aleType);
8295 
8348 void CSL_CPSW_setAleIPv6Entry(CSL_AleRegs *hCpswAleRegs,
8349  Uint32 index,
8350  CSL_CPSW_ALE_IPv6_ENTRY* pIPv6Cfg,
8351  CSL_CPSW_ALETABLE_TYPE aleType);
8352 
8369 void CSL_CPSW_mapTableWord2MacAddr(uint32_t word0,
8370  uint32_t word1,
8371  uint8_t * macAddr,
8372  CSL_CPSW_ALETABLE_TYPE aleType);
8373 
8390 void CSL_CPSW_mapMacAddr2TableWord(uint32_t *word0,
8391  uint32_t *word1,
8392  uint8_t * macAddr,
8393  CSL_CPSW_ALETABLE_TYPE aleType);
8394 
8411 Uint32 CSL_CPSW_extractVid(Uint32 word1,
8412  CSL_CPSW_ALETABLE_TYPE aleType);
8413 
8430 
8431 
8448 
8449 
8466 
8506 (CSL_AleRegs *hCpswAleRegs,
8507  Uint32 index
8508 );
8509 
8510 
8561 (CSL_AleRegs *hCpswAleRegs,
8562  Uint32 portNo,
8563  CSL_CPSW_ALE_PORTCONTROL* pPortControlInfo
8564 );
8565 
8566 
8618 (CSL_AleRegs *hCpswAleRegs,
8619  Uint32 portNo,
8620  CSL_CPSW_ALE_PORTCONTROL* pPortControlInfo
8621 );
8622 
8623 
8625 (
8626  CSL_AleRegs *hCpswAleRegs,
8627  Uint32 portNo,
8628  bool trunkEnable,
8629  Uint32 trunkNum
8630 );
8631 
8638 (
8639  CSL_AleRegs *hCpswAleRegs,
8640  Uint32 portNo,
8641  CSL_CPSW_ALE_PORTSTATE *pPortState
8642 );
8643 
8644 
8651 (
8652  CSL_AleRegs *hCpswAleRegs,
8653  Uint32 portNo,
8654  CSL_CPSW_ALE_PORTSTATE portState
8655 );
8656 
8657 
8663 void CSL_CPSW_setAlePortMirrorSouce(CSL_AleRegs *hCpswAleRegs,
8664  Uint32 portNo,
8665  bool enableMirror);
8666 
8667 
8673 void CSL_CPSW_setAleCtrl2MirrorMatchIndex(CSL_AleRegs *hCpswAleRegs,
8674  Uint32 mirrorMatchIndex);
8675 
8676 
8682 void CSL_CPSW_setAleCtrl2TrunkParams(CSL_AleRegs *hCpswAleRegs,
8684 
8685 
8691 void CSL_CPSW_setAleCtrl2IPPktFilterConfig(CSL_AleRegs *hCpswAleRegs,
8692  CSL_CPSW_ALE_CTRL2_IPPKTFLT_CONFIG *ipPktFltCfg);
8693 
8694 
8700 void CSL_CPSW_setAleCtrl2MalformedFrameConfig(CSL_AleRegs *hCpswAleRegs,
8702 
8703 
8709 void CSL_CPSW_setAleIPNxtHdrWhitelist(CSL_AleRegs *hCpswAleRegs,
8710  Uint8 ipNxtHdr0,
8711  Uint8 ipNxtHdr1,
8712  Uint8 ipNxtHdr2,
8713  Uint8 ipNxtHdr3);
8714 
8715 
8753 void CSL_CPSW_getAlePolicerGlobConfig (CSL_AleRegs *hCpswAleRegs,
8755 );
8756 
8757 
8798 void CSL_CPSW_setAlePolicerGlobConfig (CSL_AleRegs *hCpswAleRegs,
8800 );
8801 
8802 
8869 (CSL_AleRegs *hCpswAleRegs,
8870  Uint32 index,
8872 );
8873 
8874 
8940 (CSL_AleRegs *hCpswAleRegs,
8941  Uint32 index,
8943 );
8944 
8945 
8946 void CSL_CPSW_disableAlePolicerThread(CSL_AleRegs *hCpswAleRegs,
8947  Uint32 index);
8948 
8949 
8950 
8951 
8988 (
8989  CSL_AleRegs *hCpswAleRegs,
8990  Uint32 aleUnknwnVlanMemberVal
8991 );
8992 
8993 
8994 
9031 (
9032  CSL_AleRegs *hCpswAleRegs,
9033  Uint32 aleUnknwnVlanUntagVal
9034 );
9035 
9052 void CSL_CPSW_setCppiP0Control(CSL_Xge_cpswRegs *hCpswRegs,
9053  CSL_CPSW_CPPI_P0_CONTROL *pCppiP0ControlCfg);
9055 (
9056  CSL_AleRegs *hCpswAleRegs,
9057  Uint32 aleUnknwnVlanUnregMcastVal
9058 );
9059 
9060 
9062 (
9063  CSL_AleRegs *hCpswAleRegs,
9064  Uint32 aleUnknwnVlanRegMcastVal
9065 );
9066 
9067 
9068 void CSL_CPSW_setAlePolicerControlReg(CSL_AleRegs *hCpswAleRegs,CSL_CPSW_ALE_POLICER_CONTROL *policerCntrlCfg);
9069 
9070 
9071 void CSL_CPSW_getAlePolicerControlReg(CSL_AleRegs *hCpswAleRegs,CSL_CPSW_ALE_POLICER_CONTROL *policerCntrlCfg);
9072 
9073 
9074 void CSL_CPSW_setAlePolicerTestControlReg(CSL_AleRegs *hCpswAleRegs,CSL_CPSW_ALE_POLICER_TEST_CONTROL *policerTestCntrlCfg);
9075 
9076 
9077 void CSL_CPSW_getAlePolicerHstatReg(CSL_AleRegs *hCpswAleRegs,CSL_CPSW_ALE_POLICER_HSTAT *policerHStatCfg);
9078 
9079 
9080 
9086 void CSL_CPSW_setAleOAMLpbkControl(CSL_AleRegs *hCpswAleRegs,
9087  Uint32 lpbkEnablePortMask);
9088 
9089 
9090 void CSL_CPSW_getAleStatusNumPolicers(CSL_AleRegs *hCpswAleRegs,Uint32* pNumPolicers);
9091 
9092 
9093 void CSL_CPSW_setCppiPriCirEir(CSL_Xge_cpswRegs *hCpswRegs,Uint32 pri, Uint32 cir, Uint32 eir);
9094 
9095 
9096 void CSL_CPSW_getCppiPriCirEir(CSL_Xge_cpswRegs *hCpswRegs,Uint32 pri, Uint32 *cir, Uint32 *eir);
9097 
9098 
9099 void CSL_CPSW_setPriCirEir(CSL_Xge_cpswRegs *hCpswRegs,Uint32 portNo, Uint32 pri, Uint32 cir, Uint32 eir);
9100 
9101 
9102 void CSL_CPSW_getPriCirEir(CSL_Xge_cpswRegs *hCpswRegs,Uint32 portNo, Uint32 pri, Uint32 *cir, Uint32 *eir);
9103 
9104 
9105 void CSL_CPSW_setCppiRxPriFlowControl(CSL_Xge_cpswRegs *hCpswRegs,Uint8 pri);
9106 
9107 
9108 Uint8 CSL_CPSW_getCppiRxPriFlowControl(CSL_Xge_cpswRegs *hCpswRegs);
9109 
9110 
9111 void CSL_CPSW_setCppiTxDstThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs,Uint32 pri, Uint32 setVal);
9112 
9113 
9114 Uint32 CSL_CPSW_getCppiTxDstThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs,Uint32 pri);
9115 
9116 
9117 void CSL_CPSW_setCppiTxDstThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs,Uint32 pri, Uint32 setVal);
9118 
9119 
9120 Uint32 CSL_CPSW_getCppiDstTxThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs,Uint32 pri);
9121 
9122 
9123 void CSL_CPSW_setCppiTxGlobalBufThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs,Uint32 pri, Uint32 setVal);
9124 
9125 
9126 Uint32 CSL_CPSW_getCppiTxGlobalBufThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs,Uint32 pri);
9127 
9128 
9129 void CSL_CPSW_setCppiTxGlobalBufThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs,Uint32 pri, Uint32 setVal);
9130 
9131 
9132 Uint32 CSL_CPSW_getCppiTxGlobalBufThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs,Uint32 pri);
9133 
9134 
9135 void CSL_CPSW_setcppiTxBlksPri(CSL_Xge_cpswRegs *hCpswRegs,Uint8 pri, Uint32 blks);
9136 
9137 
9138 Uint32 CSL_CPSW_getCppiTxBlksPri(CSL_Xge_cpswRegs *hCpswRegs,Uint8 pri);
9139 
9140 
9141 void CSL_CPSW_setTxBlksPri(CSL_Xge_cpswRegs *hCpswRegs,Uint32 portNo, Uint8 pri, Uint32 blks);
9142 
9143 
9144 Uint32 CSL_CPSW_getTxBlksPri(CSL_Xge_cpswRegs *hCpswRegs,Uint32 portNo, Uint8 pri);
9145 
9146 
9147 void CSL_CPSW_setTxPriFlowControl(CSL_Xge_cpswRegs *hCpswRegs,Uint32 portNo, Uint8 pri);
9148 
9149 
9150 Uint8 CSL_CPSW_getTxPriFlowControl(CSL_Xge_cpswRegs *hCpswRegs,Uint32 portNo);
9151 
9152 
9153 void CSL_CPSW_setRxPriFlowControl(CSL_Xge_cpswRegs *hCpswRegs,Uint32 portNo, Uint8 pri);
9154 
9155 
9156 Uint8 CSL_CPSW_getRxPriFlowControl(CSL_Xge_cpswRegs *hCpswRegs,Uint32 portNo);
9157 
9158 
9159 Uint32 CSL_CPSW_getTxHostBlksRem(CSL_Xge_cpswRegs *hCpswRegs,Uint32 portNo);
9160 
9161 
9162 void CSL_CPSW_setTxHostBlksRem(CSL_Xge_cpswRegs *hCpswRegs,Uint32 portNo, Uint32 txBlksRem);
9163 
9164 
9165 void CSL_CPSW_setTxDstThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs,Uint32 portNo, Uint32 pri, Uint32 setVal);
9166 
9167 
9168 Uint32 CSL_CPSW_getTxDstThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs,Uint32 portNo, Uint32 pri);
9169 
9170 
9171 void CSL_CPSW_setTxDstThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs,Uint32 portNo, Uint32 pri, Uint32 setVal);
9172 
9173 
9174 Uint32 CSL_CPSW_getTxDstThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs,Uint32 portNo, Uint32 pri);
9175 
9176 
9177 void CSL_CPSW_setTxGlobalBufThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs,Uint32 portNo, Uint32 pri, Uint32 setVal);
9178 
9179 
9180 Uint32 CSL_CPSW_getTxGlobalBufThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs,Uint32 portNo, Uint32 pri);
9181 
9182 
9183 void CSL_CPSW_setTxGlobalBufThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs,Uint32 portNo, Uint32 pri, Uint32 setVal);
9184 
9185 
9186 Uint32 CSL_CPSW_getTxGlobalBufThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs,Uint32 portNo, Uint32 pri);
9187 
9188 
9189 void CSL_CPSW_setTxDstBasedOutFlowAddValX(CSL_Xge_cpswRegs *hCpswRegs,Uint32 portNo, Uint32 pri, Uint32 addVal);
9190 
9191 
9192 Uint32 CSL_CPSW_getTxDstBasedOutFlowAddValX(CSL_Xge_cpswRegs *hCpswRegs,Uint32 portNo, Uint32 pri);
9193 
9194 
9195 void CSL_CPSW_setTxGlobalOutFlowThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs,Uint32 pri, Uint32 setVal);
9196 
9197 
9198 Uint32 CSL_CPSW_getTxGlobalOutFlowThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs,Uint32 pri);
9199 
9200 
9201 void CSL_CPSW_setTxGlobalOutFlowThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs,Uint32 pri, Uint32 setVal);
9202 
9203 
9204 Uint32 CSL_CPSW_getTxGlobalOutFlowThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs,Uint32 pri);
9205 
9206 
9207 
9208 void CSL_CPSW_setCpswTxGlobalBufThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs,Uint32 pri, Uint32 setVal);
9209 
9210 
9211 Uint32 CSL_CPSW_getCpswTxGlobalBufThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs,Uint32 pri);
9212 
9213 
9214 void CSL_CPSW_setCpswTxGlobalBufThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs,Uint32 pri, Uint32 setVal);
9215 
9216 
9217 Uint32 CSL_CPSW_getCpswTxGlobalBufThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs,Uint32 pri);
9218 
9233 Uint32 CSL_CPSW_isP0TxCastagnoliCRCEnabled (CSL_Xge_cpswRegs *hCpswRegs);
9234 
9247 void CSL_CPSW_enableP0TxCastagnoliCRC(CSL_Xge_cpswRegs *hCpswRegs);
9248 
9261 void CSL_CPSW_disableP0TxCastagnoliCRC(CSL_Xge_cpswRegs *hCpswRegs);
9262 
9280 void CSL_CPSW_getPTypeReg (CSL_Xge_cpswRegs *hCpswRegs,
9281  CSL_CPSW_PTYPE* pPtypeCfg);
9282 
9300 void CSL_CPSW_setPTypeReg (CSL_Xge_cpswRegs *hCpswRegs,
9301  CSL_CPSW_PTYPE* pPtypeCfg);
9302 
9320 void CSL_CPSW_getThruRateReg (CSL_Xge_cpswRegs *hCpswRegs,
9321  CSL_CPSW_THRURATE * pThruRateCfg);
9322 
9350 Uint32 CSL_CPSW_getGapThreshold(CSL_Xge_cpswRegs *hCpswRegs);
9351 
9382 void CSL_CPSW_setGapThreshold(CSL_Xge_cpswRegs *hCpswRegs,Uint32 gapThreshold);
9383 
9408 Uint32 CSL_CPSW_getTxStartWords(CSL_Xge_cpswRegs *hCpswRegs);
9409 
9426 Uint32 CSL_CPSW_getTxMaxLenPerPriority(CSL_Xge_cpswRegs *hCpswRegs,
9427  Uint32 priority);
9428 
9446 void CSL_CPSW_setTxMaxLenPerPriority(CSL_Xge_cpswRegs *hCpswRegs,
9447  Uint32 priority,
9448  Uint32 maxLen);
9449 
9466 void CSL_CPSW_getCppiP0Control(CSL_Xge_cpswRegs *hCpswRegs,
9467  CSL_CPSW_CPPI_P0_CONTROL *pCppiP0ControlCfg);
9484 void CSL_CPSW_setCppiP0Control(CSL_Xge_cpswRegs *hCpswRegs,
9485  CSL_CPSW_CPPI_P0_CONTROL *pCppiP0ControlCfg);
9486 
9505 void CSL_CPSW_setCppiRxPType(CSL_Xge_cpswRegs *hCpswRegs,Uint32 p0RxPtype);
9506 
9525 Uint32 CSL_CPSW_getCppiRxPType(CSL_Xge_cpswRegs *hCpswRegs);
9526 
9545 Uint32 CSL_CPSW_getCppiRxPacketsPriority(CSL_Xge_cpswRegs *hCpswRegs,
9546  Uint32 priority);
9547 
9567 void CSL_CPSW_setCppiRxPacketsPriority(CSL_Xge_cpswRegs *hCpswRegs,
9568  Uint32 priority,
9569  Uint32 rxPackets);
9570 
9588 void CSL_CPSW_getCppiRxGapReg(CSL_Xge_cpswRegs *hCpswRegs,
9589  CSL_CPSW_CPPI_P0_RXGAP *pCppiRxGap);
9590 
9608 void CSL_CPSW_setCppiRxGapReg(CSL_Xge_cpswRegs *hCpswRegs,
9609  CSL_CPSW_CPPI_P0_RXGAP *pCppiRxGap);
9610 
9628 void CSL_CPSW_getP0FifoStatus(CSL_Xge_cpswRegs *hCpswRegs,
9629  CSL_CPSW_CPPI_P0_FIFOSTATUS *pCppiFifoStats);
9630 
9648 void CSL_CPSW_getP0HostBlksPri(CSL_Xge_cpswRegs *hCpswRegs,
9649  CSL_CPSW_CPPI_P0_HOSTBLKSPRI *pCppiHostBlksPri);
9650 
9668 void CSL_CPSW_setP0HostBlksPri(CSL_Xge_cpswRegs *hCpswRegs,
9669  CSL_CPSW_CPPI_P0_HOSTBLKSPRI *pCppiHostBlksPri);
9670 
9671 #ifdef __cplusplus
9672 }
9673 #endif
9674 
9675 #endif
9676 
CSL_CPSW_ALE_RAMDEPTH_E CSL_CPSW_getAleStatusRamDepth(CSL_AleRegs *hCpswAleRegs)
Uint32 tsVlanLType2
Definition: csl_cpsw.h:1029
Holds CPSW EEE (Energy Efficient Ethernet) Per-Port Configuration.
Definition: csl_cpsw.h:1100
Uint32 rtlVer
Definition: csl_cpsw.h:131
void CSL_CPSW_getAleStatusReg(CSL_AleRegs *hCpswAleRegs, Uint32 *pNumPolicers, Uint32 *pNumEntries)
void CSL_CPSW_getPortTxPriMapReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pPortTxPriMap)
Uint32 p3PassPriTag
Definition: csl_cpsw.h:161
Uint32 touched
Definition: csl_cpsw.h:696
Holds CPSW EEE (Energy Efficient Ethernet) Global Configuration.
Definition: csl_cpsw.h:1087
uint16_t index
Definition: tisci_rm_proxy.h:153
Uint32 p0TxPriActivePri6
Definition: csl_cpsw.h:356
void CSL_CPSW_mapMacAddr2TableWord(uint32_t *word0, uint32_t *word1, uint8_t *macAddr, CSL_CPSW_ALETABLE_TYPE aleType)
CSL_CPSW_ALE_AGT_PRESCALE_E
Defines ALE Aging Timer Prescale.
Definition: csl_cpsw.h:840
Definition: csl_cpsw.h:588
Uint32 p0TxPriActivePri1
Definition: csl_cpsw.h:321
Uint32 rxGapEnPri2
Definition: csl_cpsw.h:292
void CSL_CPSW_setCpswTxGlobalBufThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal)
void CSL_CPSW_setTxDstThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri, Uint32 setVal)
void CSL_CPSW_disableSoftIdle(CSL_Xge_cpswRegs *hCpswRegs)
Uint32 AleUnKnUni
Definition: csl_cpsw.h:1483
Uint32 p0HostBlksPri2
Definition: csl_cpsw.h:396
Uint32 tsTxAnnexDEnable
Definition: csl_cpsw.h:901
void CSL_CPSW_setAleCtrl2MalformedFrameConfig(CSL_AleRegs *hCpswAleRegs, CSL_CPSW_ALE_CTRL2_MALFORMEDFRAME_CONFIG *badFrmCfg)
Uint32 RxCRCErrors
Definition: csl_cpsw.h:1375
Uint32 pri
Definition: csl_cpsw.h:1284
void CSL_CPSW_getCpswVersionInfo(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_VERSION *pVersionInfo)
Holds CPSW priority type register contents.
Definition: csl_cpsw.h:1572
Definition: csl_cpsw.h:843
Definition: csl_cpsw.h:552
Definition: csl_cpsw.h:577
Uint32 p0FlowEnable
Definition: csl_cpsw.h:414
Uint32 RxIpgError
Definition: csl_cpsw.h:1432
Uint32 p6FlowEnable
Definition: csl_cpsw.h:432
bool ipPktFltEnableDefNoFrag
Definition: csl_cpsw.h:1214
void CSL_CPSW_setCppiTxGlobalBufThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal)
CSL_CPSW_ALE_POLICER_CONTROL_YELLOWTHRESH yellowDropThresh
Definition: csl_cpsw.h:1544
Uint32 dstMacIdx
Definition: csl_cpsw.h:1290
Uint32 tsRxAnnexFEnable
Definition: csl_cpsw.h:892
Definition: csl_cpsw.h:1176
void CSL_CPSW_setAleControlReg(CSL_AleRegs *hCpswAleRegs, Uint32 aleCtrlVal)
Uint32 tsTxVlanLType2Enable
Definition: csl_cpsw.h:960
Uint32 Frame1024tUp
Definition: csl_cpsw.h:1456
void CSL_CPSW_enableAleOUIDenyMode(CSL_AleRegs *hCpswAleRegs)
void CSL_CPSW_enableAleMacAuthMode(CSL_AleRegs *hCpswAleRegs)
Definition: csl_cpsw.h:477
Uint32 blockEnable
Definition: csl_cpsw.h:721
Uint32 port6PriorityTypeEscalateEnable
Definition: csl_cpsw.h:1592
Holds CPSW control register contents.
Definition: csl_cpsw.h:141
void CSL_CPSW_getPortTimeSyncCntlReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_TSCNTL *pTimeSyncCntlCfg)
void CSL_CPSW_getVlanLTypeReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 *pVlanLtypeInner, Uint32 *pVlanLtypeOuter)
void CSL_CPSW_setTxPriFlowControl(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint8 pri)
Uint32 yellowDropEnable
Definition: csl_cpsw.h:1545
void CSL_CPSW_getAlePolicerEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_POLICER_ENTRY *pPolCfg)
void CSL_CPSW_getAlePortControlReg(CSL_AleRegs *hCpswAleRegs, Uint32 portNo, CSL_CPSW_ALE_PORTCONTROL *pPortControlInfo)
Uint8 CSL_CPSW_getTxPriFlowControl(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo)
void CSL_CPSW_setPriCirEir(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri, Uint32 cir, Uint32 eir)
Uint32 unRegMcastFloodMask
Definition: csl_cpsw.h:746
Uint32 bcastLimit
Definition: csl_cpsw.h:534
void CSL_CPSW_disablePortPassPriTag(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 tsRxAnnexEEnable
Definition: csl_cpsw.h:889
void CSL_CPSW_setAlePortState(CSL_AleRegs *hCpswAleRegs, Uint32 portNo, CSL_CPSW_ALE_PORTSTATE portState)
Uint32 AleUnKnMultiBytes
Definition: csl_cpsw.h:1492
Uint32 RxJabber
Definition: csl_cpsw.h:1384
Definition: csl_cpsw.h:587
Uint32 CSL_CPSW_getCppiRxPacketsPriority(CSL_Xge_cpswRegs *hCpswRegs, Uint32 priority)
Uint32 AleUnKnBCast
Definition: csl_cpsw.h:1495
Uint32 AleAddrEqDrop
Definition: csl_cpsw.h:1477
Uint32 pirIdleIncVal
Definition: csl_cpsw.h:1317
void CSL_CPSW_getCpswControlReg(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_CONTROL *pControlRegInfo)
Uint32 tsRxAnnexEEnable
Definition: csl_cpsw.h:936
Uint32 p8FlowEnable
Definition: csl_cpsw.h:438
Definition: csl_cpsw.h:474
Uint32 RxAlignCodeErrors
Definition: csl_cpsw.h:1378
Uint32 CSL_CPSW_getAleIPv6HighEntryIndex(CSL_AleRegs *hCpswAleRegs, Uint32 entryIndex)
void CSL_CPSW_setPortRxPriMapReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pPortRxPriMap)
Uint32 CSL_CPSW_getCpswTxGlobalBufThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri)
Definition: csl_cpsw.h:578
void CSL_CPSW_setcppiTxBlksPri(CSL_Xge_cpswRegs *hCpswRegs, Uint8 pri, Uint32 blks)
void CSL_CPSW_getP0FifoStatus(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_CPPI_P0_FIFOSTATUS *pCppiFifoStats)
void CSL_CPSW_setVlanLTypeReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pVlanLtypeInner, Uint32 pVlanLtypeOuter)
CSL_CPSW_ALE_RAMDEPTH_E
Number of statistic blocks.
Definition: csl_cpsw.h:830
void CSL_CPSW_setAlePortControlTrunk(CSL_AleRegs *hCpswAleRegs, Uint32 portNo, bool trunkEnable, Uint32 trunkNum)
Int32 CSL_CPSW_setAleVlanMaskMuxEntryReg(CSL_AleRegs *hCpswAleRegs, Uint32 maskMuxIndex, Uint32 vlanMaskMuxVal)
CSL_CPSW_ALE_ENTRYTYPE CSL_CPSW_getALEEntryType(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALETABLE_TYPE aleType)
void CSL_CPSW_getCppiRxGapReg(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_CPPI_P0_RXGAP *pCppiRxGap)
Definition: csl_cpsw.h:1175
Uint32 ingressCheckFlag
Definition: csl_cpsw.h:754
bool trunkEnableDestIP
Definition: csl_cpsw.h:1203
void CSL_CPSW_setPortTimeSyncConfig(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_TSCONFIG *pTimeSyncConfig)
Uint32 CSL_CPSW_getTxHostBlksRem(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo)
Uint32 CSL_CPSW_getTxMaxLenPerPriority(CSL_Xge_cpswRegs *hCpswRegs, Uint32 priority)
Definition: csl_cpsw.h:1212
void CSL_CPSW_getPortRxPriMapReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pPortRxPriMap)
Uint32 blockEnable
Definition: csl_cpsw.h:671
Definition: csl_cpsw.h:465
CSL_CPSW_ALE_POLICER_ENTRYTYPE CSL_CPSW_getALEPolicerEntryType(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALETABLE_TYPE aleType)
CSL_CPSW_ALETABLE_TYPE
Defines ALE table types support.
Definition: csl_cpsw.h:464
Uint32 txLpiClkstopEnable
Definition: csl_cpsw.h:1108
void CSL_CPSW_setAleMcastAddrEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_MCASTADDR_ENTRY *pMcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 TxSingleColl
Definition: csl_cpsw.h:1420
Uint32 RxOversized
Definition: csl_cpsw.h:1381
Uint32 CSL_CPSW_getTxBlksPri(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint8 pri)
Holds CPPI_P0_Rx_Gap register contents. This is applicable only for 2 port switch.
Definition: csl_cpsw.h:268
Uint32 destForceUntaggedEgress
Definition: csl_cpsw.h:1633
Uint32 p1StatEnable
Definition: csl_cpsw.h:855
Uint8 CSL_CPSW_getCppiRxPriFlowControl(CSL_Xge_cpswRegs *hCpswRegs)
Uint32 p1PassPriTag
Definition: csl_cpsw.h:155
void CSL_CPSW_setPortTimeSyncSeqIdReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 tsLtype, Uint32 tsSeqIdOffset)
Holds the ALE Ethertype Table entry configuration.
Definition: csl_cpsw.h:777
Uint32 CSL_CPSW_getPortRxMaxLen(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 txFifoEmpty
Definition: csl_cpsw.h:1155
void CSL_CPSW_disableAleVID0Mode(CSL_AleRegs *hCpswAleRegs)
void CSL_CPSW_setVlanType(CSL_Xge_cpswRegs *hCpswRegs, Uint32 vlanType)
Holds Port Statistics Enable register contents.
Definition: csl_cpsw.h:850
Uint32 tsRxVlanLType1Enable
Definition: csl_cpsw.h:942
Uint32 enable
Definition: csl_cpsw.h:1089
Uint32 tsSeqIdOffset
Definition: csl_cpsw.h:1032
void CSL_CPSW_getAleUnkownVlanReg(CSL_AleRegs *hCpswAleRegs, Uint32 *pUnVlanMemList, Uint32 *pUnMcastFloodMask, Uint32 *pUnRegMcastFloodMask, Uint32 *pUnForceUntagEgress)
Uint32 ignMBits
Definition: csl_cpsw.h:648
void CSL_CPSW_setAleCtrl2IPPktFilterConfig(CSL_AleRegs *hCpswAleRegs, CSL_CPSW_ALE_CTRL2_IPPKTFLT_CONFIG *ipPktFltCfg)
Uint32 p2StatEnable
Definition: csl_cpsw.h:858
Holds CPSW Port Rx Rate Limit Configuration for CPPI Port Ingress Rate Limitaion Operation.
Definition: csl_cpsw.h:1067
Definition: csl_cpsw.h:1178
Holds the EMAC statistics.
Definition: csl_cpsw.h:1361
Uint32 rxGapEnPri0
Definition: csl_cpsw.h:298
Uint32 superEnable
Definition: csl_cpsw.h:642
Holds the ALE VLAN Unicast Address Table entry configuration.
Definition: csl_cpsw.h:704
Uint32 ts132Enable
Definition: csl_cpsw.h:1005
Uint32 policingEnable
Definition: csl_cpsw.h:1547
void CSL_CPSW_getAlePolicerHstatReg(CSL_AleRegs *hCpswAleRegs, CSL_CPSW_ALE_POLICER_HSTAT *policerHStatCfg)
void CSL_CPSW_setPortControlReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_PORT_CONTROL *pControlInfo)
Uint32 p3FlowEnable
Definition: csl_cpsw.h:423
Uint32 port0PriorityTypeEscalateEnable
Definition: csl_cpsw.h:1574
Uint32 portNumber
Definition: csl_cpsw.h:724
void CSL_CPSW_getAleTableEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, Uint32 *pAleInfoWd0, Uint32 *pAleInfoWd1, Uint32 *pAleInfoWd2)
Uint32 tsRxVlanLType2Enable
Definition: csl_cpsw.h:898
UInt32 numLSBIgnore
Definition: csl_cpsw.h:806
Uint32 polClrallYellowhit
Definition: csl_cpsw.h:1556
Uint32 ts130Enable
Definition: csl_cpsw.h:993
Uint32 enetRxThruRate
Definition: csl_cpsw.h:209
void CSL_CPSW_setPortTimeSyncVlanLTypeReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 tsVlanLtype1, Uint32 tsVlanLtype2)
void CSL_CPSW_getPortMaxBlksReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pRxMaxBlks, Uint32 *pTxMaxBlks)
Uint32 tsTxVlanLType2Enable
Definition: csl_cpsw.h:913
void CSL_CPSW_getAleEthertypeEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_ETHERTYPE_ENTRY *pEthertypeCfg, CSL_CPSW_ALETABLE_TYPE aleType)
void CSL_CPSW_getPort0VlanReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 *pPortVID, Uint32 *pPortCFI, Uint32 *pPortPRI)
void CSL_CPSW_getAlePortState(CSL_AleRegs *hCpswAleRegs, Uint32 portNo, CSL_CPSW_ALE_PORTSTATE *pPortState)
void CSL_CPSW_setAleVlanEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_VLAN_ENTRY *pVlanCfg, CSL_CPSW_ALETABLE_TYPE aleType)
void CSL_CPSW_getAleVlanMcastAddrEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_VLANMCASTADDR_ENTRY *pVlanMcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 tsTxAnnexEEnable
Definition: csl_cpsw.h:904
Uint32 vlanId
Definition: csl_cpsw.h:636
void CSL_CPSW_setPortVlanReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 portVID, Uint32 portCFI, Uint32 portPRI)
Uint32 ignMBits
Definition: csl_cpsw.h:623
Uint32 CSL_CPSW_isSoftIdle(CSL_Xge_cpswRegs *hCpswRegs)
void CSL_CPSW_enableSoftIdle(CSL_Xge_cpswRegs *hCpswRegs)
void CSL_CPSW_setPort0VlanReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portVID, Uint32 portCFI, Uint32 portPRI)
Uint32 p4PassPriTag
Definition: csl_cpsw.h:164
Uint32 defThread
Definition: csl_cpsw.h:1197
void CSL_CPSW_disableAleVlanAware(CSL_AleRegs *hCpswAleRegs)
Uint32 disallowIPFragmentation
Definition: csl_cpsw.h:763
Uint32 touched
Definition: csl_cpsw.h:664
void CSL_CPSW_setTxGlobalOutFlowThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal)
void CSL_CPSW_enableP0TxCastagnoliCRC(CSL_Xge_cpswRegs *hCpswRegs)
Uint32 NetOctets
Definition: csl_cpsw.h:1459
Uint32 CSL_CPSW_getIpv6IgnBitsMax(CSL_CPSW_ALETABLE_TYPE aleType)
void CSL_CPSW_setAleUnkownVlanReg(CSL_AleRegs *hCpswAleRegs, Uint32 unVlanMemList, Uint32 unMcastFloodMask, Uint32 unRegMcastFloodMask, Uint32 unForceUntagEgress)
void CSL_CPSW_setCppiP0Control(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_CPPI_P0_CONTROL *pCppiP0ControlCfg)
void CSL_CPSW_setAlePrescaleReg(CSL_AleRegs *hCpswAleRegs, Uint32 alePrescaleVal)
Uint32 TxCollision
Definition: csl_cpsw.h:1417
Uint32 dscpIpv6Enable
Definition: csl_cpsw.h:1055
void CSL_CPSW_setCppiTxDstThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal)
Uint32 CSL_CPSW_getTxGlobalOutFlowThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri)
Uint32 srcIpIdx
Definition: csl_cpsw.h:1305
Uint32 p4StatEnable
Definition: csl_cpsw.h:864
void CSL_CPSW_setCppiSourceIdReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 *pTxSrcId)
void CSL_CPSW_disablePort0(CSL_Xge_cpswRegs *hCpswRegs)
Holds the ALE Multicast Address Table entry configuration.
Definition: csl_cpsw.h:609
void CSL_CPSW_getPortStats(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_STATS *pCpswStats)
void CSL_CPSW_getPTypeReg(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_PTYPE *pPtypeCfg)
Uint32 macOnlyEnable
Definition: csl_cpsw.h:513
Uint32 replaceVid
Definition: csl_cpsw.h:1642
bool dropBadLen
Definition: csl_cpsw.h:1218
Definition: csl_cpsw.h:1174
void CSL_CPSW_getPriCirEir(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri, Uint32 *cir, Uint32 *eir)
Definition: csl_cpsw.h:576
Uint32 p4FlowEnable
Definition: csl_cpsw.h:426
Uint32 RxBCastFrames
Definition: csl_cpsw.h:1366
Uint32 CSL_CPSW_isVlanAwareEnabled(CSL_Xge_cpswRegs *hCpswRegs)
Uint32 tsDomainOffset
Definition: csl_cpsw.h:1035
Uint32 p5StatEnable
Definition: csl_cpsw.h:867
Uint32 port8PriorityTypeEscalateEnable
Definition: csl_cpsw.h:1598
void CSL_CPSW_setCppiRxPacketsPriority(CSL_Xge_cpswRegs *hCpswRegs, Uint32 priority, Uint32 rxPackets)
Uint32 CSL_CPSW_isAleRateLimitEnabled(CSL_AleRegs *hCpswAleRegs)
void CSL_CPSW_getPortControlReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_PORT_CONTROL *pControlInfo)
Uint32 TxLateColl
Definition: csl_cpsw.h:1429
Uint32 txLpiClkstopEnable
Definition: csl_cpsw.h:1052
Uint32 tsTxHostEnable
Definition: csl_cpsw.h:916
void CSL_CPSW_setAleUnicastAddrEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_UNICASTADDR_ENTRY *pUcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 CSL_CPSW_getCppiDstTxThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri)
Uint32 vlanAware
Definition: csl_cpsw.h:146
Uint32 ts129Enable
Definition: csl_cpsw.h:987
Uint32 id
Definition: csl_cpsw.h:457
Uint32 AlePolMatch
Definition: csl_cpsw.h:1501
Uint32 CSL_CPSW_isAleVID0ModeEnabled(CSL_AleRegs *hCpswAleRegs)
Holds CSL_CPSW_CPPI_P0_HOSTBLKSPRI register contents. This is not used for 2 port switch.
Definition: csl_cpsw.h:372
Uint32 CSL_CPSW_isPort0PassPriTagEnabled(CSL_Xge_cpswRegs *hCpswRegs)
Uint32 idle2lpi
Definition: csl_cpsw.h:1115
void CSL_CPSW_enablePortPassPriTag(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 polRedhit
Definition: csl_cpsw.h:1564
void CSL_CPSW_setAlePolicerControlReg(CSL_AleRegs *hCpswAleRegs, CSL_CPSW_ALE_POLICER_CONTROL *policerCntrlCfg)
Holds Port Time Sync Control register contents.
Definition: csl_cpsw.h:884
bool ipPktFltEnableDefNxtHdrLimit
Definition: csl_cpsw.h:1213
Uint32 p0PassPriTag
Definition: csl_cpsw.h:152
Holds the ALE OUI Unicast Address Table entry configuration.
Definition: csl_cpsw.h:688
void CSL_CPSW_setAleCtrl2MirrorMatchIndex(CSL_AleRegs *hCpswAleRegs, Uint32 mirrorMatchIndex)
Uint32 RxDropBottom
Definition: csl_cpsw.h:1462
Uint32 CSL_CPSW_getTxDstThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri)
void CSL_CPSW_disableAle(CSL_AleRegs *hCpswAleRegs)
Uint32 mcastFwdState
Definition: csl_cpsw.h:614
void CSL_CPSW_setTxDstThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri, Uint32 setVal)
Uint32 RxFragments
Definition: csl_cpsw.h:1390
Uint32 p0TxPriActivePri0
Definition: csl_cpsw.h:314
Uint32 forceUntaggedEgress
Definition: csl_cpsw.h:751
void CSL_CPSW_setAleUnknwnVlanRegMcastReg(CSL_AleRegs *hCpswAleRegs, Uint32 aleUnknwnVlanRegMcastVal)
Definition: csl_cpsw.h:466
Holds the Enet_Pn_FIFO_Status register contents.
Definition: csl_cpsw.h:1651
Uint32 macOnlyCafEnable
Definition: csl_cpsw.h:528
Uint32 noLearnMask
Definition: csl_cpsw.h:757
void CSL_CPSW_disableAleTxRateLimit(CSL_AleRegs *hCpswAleRegs)
Uint32 CSL_CPSW_getAleIPv6HighEntryOffset(CSL_AleRegs *hCpswAleRegs)
Uint32 unRegMcastFloodIndex
Definition: csl_cpsw.h:741
Uint32 p0RxEccErrEn
Definition: csl_cpsw.h:236
Uint32 p0HostBlksPri3
Definition: csl_cpsw.h:392
Definition: csl_cpsw.h:601
CSL_CPSW_ALE_POLICER_CONTROL_POLICING_MATCH_MODE policeMatchMode
Definition: csl_cpsw.h:1543
void CSL_CPSW_getAleVlanUnicastAddrEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_VLANUNICASTADDR_ENTRY *pVlanUcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 CSL_CPSW_getTxGlobalOutFlowThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri)
void CSL_CPSW_getAleOutVlanEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_OUTER_VLAN_ENTRY *pOutVlanCfg, CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 mcastLimit
Definition: csl_cpsw.h:531
Uint32 tsLType2Enable
Definition: csl_cpsw.h:966
Uint32 p0StatEnable
Definition: csl_cpsw.h:852
Uint32 dscpIpv4Enable
Definition: csl_cpsw.h:1058
Uint32 tsRxAnnexDEnable
Definition: csl_cpsw.h:933
Holds the ALE IPv6 Address Table entry configuration.
Definition: csl_cpsw.h:802
void CSL_CPSW_setTxGlobalOutFlowThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal)
Uint32 AleVidDrop
Definition: csl_cpsw.h:1474
void CSL_CPSW_setPortMACAddress(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint8 *pMacAddress)
Holds the ALE Unicast Address Table entry configuration.
Definition: csl_cpsw.h:656
Uint32 CSL_CPSW_getGapThreshold(CSL_Xge_cpswRegs *hCpswRegs)
void CSL_CPSW_setPort0FlowIdOffset(CSL_Xge_cpswRegs *hCpswRegs, Uint32 flowIdOffset)
void CSL_CPSW_getEmulationControlReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 *pFree, Uint32 *pSoft)
Uint32 tsMsgTypeEnable
Definition: csl_cpsw.h:922
Holds flow control register contents.
Definition: csl_cpsw.h:412
Uint32 RxAleOverrunDrop
Definition: csl_cpsw.h:1396
Int32 CSL_CPSW_getAleVlanMaskMuxEntryReg(CSL_AleRegs *hCpswAleRegs, Uint32 maskMuxIndex, Uint32 *vlanMaskMuxPtr)
Uint32 majorVer
Definition: csl_cpsw.h:451
Uint32 tsRxAnnexDEnable
Definition: csl_cpsw.h:886
Uint32 tsTxAnnexFEnable
Definition: csl_cpsw.h:907
void CSL_CPSW_setCppiTxGlobalBufThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal)
Uint32 RxOctets
Definition: csl_cpsw.h:1399
Definition: csl_cpsw.h:841
bool trunkEnableInnerVLAN
Definition: csl_cpsw.h:1205
void CSL_CPSW_getAleUnicastAddrEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_UNICASTADDR_ENTRY *pUcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 ageable
Definition: csl_cpsw.h:661
Definition: csl_cpsw.h:1552
CSL_CPSW_ALE_POLICER_CONTROL_POLICING_MATCH_MODE
Definition: csl_cpsw.h:1523
void CSL_CPSW_setTxDstBasedOutFlowAddValX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri, Uint32 addVal)
bool trunkEnableSrcIP
Definition: csl_cpsw.h:1204
void CSL_CPSW_clearAleTable(CSL_AleRegs *hCpswAleRegs)
Definition: csl_cpsw.h:600
Uint32 TxExcessiveColl
Definition: csl_cpsw.h:1426
Uint32 dropUntaggedEnable
Definition: csl_cpsw.h:489
Uint32 majorVer
Definition: csl_cpsw.h:128
void CSL_CPSW_setEmulationControlReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 free, Uint32 soft)
void CSL_CPSW_setAleUnknwnVlanMemberReg(CSL_AleRegs *hCpswAleRegs, Uint32 aleUnknwnVlanMemberVal)
CSL_CPSW_ALE_ENTRYTYPE
Defines ALE Table Entry types.
Definition: csl_cpsw.h:551
Uint32 tsMcastTypeEnable
Definition: csl_cpsw.h:1014
Uint32 ts131Enable
Definition: csl_cpsw.h:999
Uint32 tsTxHostEnable
Definition: csl_cpsw.h:963
Uint32 limitIPNxtHdr
Definition: csl_cpsw.h:760
CSL_CPSW_ALE_PORTSTATE
Defines ALE port states.
Definition: csl_cpsw.h:473
void CSL_CPSW_getAlePolicerGlobConfig(CSL_AleRegs *hCpswAleRegs, CSL_CPSW_ALE_POLICER_GLOB_CONFIG *pGlobConfig)
Uint32 CSL_CPSW_isPort1PassPriTagEnabled(CSL_Xge_cpswRegs *hCpswRegs)
Uint32 CSL_CPSW_isAleUVLANNoLearnEnabled(CSL_AleRegs *hCpswAleRegs)
void CSL_CPSW_setAleEthertypeEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_ETHERTYPE_ENTRY *pEthertypeCfg, CSL_CPSW_ALETABLE_TYPE aleType)
void CSL_CPSW_getP0HostBlksPri(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_CPPI_P0_HOSTBLKSPRI *pCppiHostBlksPri)
Uint32 tsRxVlanLType2Enable
Definition: csl_cpsw.h:945
Uint32 tsTxVlanLType1Enable
Definition: csl_cpsw.h:957
Holds the ALE VLAN/Multicast Address Table entry configuration.
Definition: csl_cpsw.h:631
Definition: csl_cpsw.h:553
Uint32 CSL_CPSW_isAleMacAuthModeEnabled(CSL_AleRegs *hCpswAleRegs)
Uint32 RxDropTop
Definition: csl_cpsw.h:1468
Uint32 CSL_CPSW_getTxStartWords(CSL_Xge_cpswRegs *hCpswRegs)
void CSL_CPSW_setPortRxMaxLen(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 rxMaxLen)
void CSL_CPSW_clearAleEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index)
Uint32 vidIngressCheckEnable
Definition: csl_cpsw.h:492
void CSL_CPSW_getAleVlanEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_VLAN_ENTRY *pVlanCfg, CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 tsUniEnable
Definition: csl_cpsw.h:975
void CSL_CPSW_getEEEPortConfig(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_EEE_PORT_CONFIG *pPortConfig)
Uint32 p1FlowEnable
Definition: csl_cpsw.h:417
Uint32 port2PriorityTypeEscalateEnable
Definition: csl_cpsw.h:1580
Uint32 CSL_CPSW_getCppiTxGlobalBufThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri)
Definition: csl_cpsw.h:1172
void CSL_CPSW_disableAleUVLANNoLearn(CSL_AleRegs *hCpswAleRegs)
Holds the ALE IPv4 Address Table entry configuration.
Definition: csl_cpsw.h:789
Uint32 rxGapEnPri3
Definition: csl_cpsw.h:289
Uint32 polClrselAll
Definition: csl_cpsw.h:1557
void CSL_CPSW_getAleVersionInfo(CSL_AleRegs *hCpswAleRegs, CSL_CPSW_ALE_VERSION *pVersionInfo)
Uint32 rxFifoEmpty
Definition: csl_cpsw.h:1152
Uint32 escPriLoadVal
Definition: csl_cpsw.h:1608
Uint32 ouiIdx
Definition: csl_cpsw.h:1287
void CSL_CPSW_setAleTableEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, Uint32 aleInfoWd0, Uint32 aleInfoWd1, Uint32 aleInfoWd2)
Uint32 txPriActive
Definition: csl_cpsw.h:1683
Uint32 rxGapCnt
Definition: csl_cpsw.h:274
Uint32 decrementTtl
Definition: csl_cpsw.h:1629
void CSL_CPSW_getPortTimeSyncConfig(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_TSCONFIG *pTimeSyncConfig)
void CSL_CPSW_setTxHostBlksRem(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 txBlksRem)
void CSL_CPSW_getAleStatusVlanMask(CSL_AleRegs *hCpswAleRegs, bool *vlanMsk08, bool *vlanMsk12)
Uint32 noSaUpdateEnable
Definition: csl_cpsw.h:498
Definition: csl_cpsw.h:575
Uint32 portMask
Definition: csl_cpsw.h:620
void CSL_CPSW_disableAleBypass(CSL_AleRegs *hCpswAleRegs)
Uint32 p6PassPriTag
Definition: csl_cpsw.h:170
Uint32 CSL_CPSW_getAleIPv6LowEntryIndex(CSL_AleRegs *hCpswAleRegs, Uint32 entryIndex)
Definition: csl_cpsw.h:1217
Uint32 AleRateLimitDrop
Definition: csl_cpsw.h:1471
void CSL_CPSW_getAleAgingTimerReg(CSL_AleRegs *hCpswAleRegs, Uint32 *pAgingPrescale, Uint32 *pAgingPeriod)
Uint32 p0RxRemapDscpIpv4
Definition: csl_cpsw.h:228
Uint32 RxPauseFrames
Definition: csl_cpsw.h:1372
Uint32 TxMultiColl
Definition: csl_cpsw.h:1423
Uint32 CSL_CPSW_isAleEnabled(CSL_AleRegs *hCpswAleRegs)
Uint32 p5PassPriTag
Definition: csl_cpsw.h:167
Uint32 CSL_CPSW_isAleUUNIToHostEnabled(CSL_AleRegs *hCpswAleRegs)
Definition: csl_cpsw.h:832
void CSL_CPSW_setCppiRxPType(CSL_Xge_cpswRegs *hCpswRegs, Uint32 p0RxPtype)
Uint32 CSL_CPSW_getCppiRxPType(CSL_Xge_cpswRegs *hCpswRegs)
Uint32 p8StatEnable
Definition: csl_cpsw.h:876
Uint32 CSL_CPSW_getAlePrescaleReg(CSL_AleRegs *hCpswAleRegs)
Uint32 p7FlowEnable
Definition: csl_cpsw.h:435
Definition: csl_cpsw.h:833
CSL_CPSW_ALE_UCASTTYPE
Defines ALE Unicast types.
Definition: csl_cpsw.h:574
void CSL_CPSW_enablePort0PassPriTag(CSL_Xge_cpswRegs *hCpswRegs)
void CSL_CPSW_getAleStatusNumPolicers(CSL_AleRegs *hCpswAleRegs, Uint32 *pNumPolicers)
Uint32 txLpi
Definition: csl_cpsw.h:1141
Uint32 id
Definition: csl_cpsw.h:134
Uint32 port7PriorityTypeEscalateEnable
Definition: csl_cpsw.h:1595
Uint32 p0TxPriActivePri5
Definition: csl_cpsw.h:349
Uint32 prescale
Definition: csl_cpsw.h:1092
Uint32 CSL_CPSW_getAleControlReg(CSL_AleRegs *hCpswAleRegs)
void CSL_CPSW_getEEEGlobConfig(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_EEE_GLOB_CONFIG *pGlobConfig)
void CSL_CPSW_enableVlanAware(CSL_Xge_cpswRegs *hCpswRegs)
Definition: csl_cpsw.h:555
Holds the Port intervlan configuration info.
Definition: csl_cpsw.h:1615
Uint32 p0HostBlksPri0
Definition: csl_cpsw.h:404
void CSL_CPSW_enableAleUUNIToHost(CSL_AleRegs *hCpswAleRegs)
void CSL_CPSW_setAleIPv4Entry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_IPv4_ENTRY *pIPv4Cfg, CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 tsLType2
Definition: csl_cpsw.h:1023
Uint32 Frame128t255
Definition: csl_cpsw.h:1447
Uint32 CSL_CPSW_getPort0RxMaxLen(CSL_Xge_cpswRegs *hCpswRegs)
Uint32 AleUnKnMulti
Definition: csl_cpsw.h:1489
CPSW_THRU_RATE register.
Definition: csl_cpsw.h:201
Uint32 estBufAct
Definition: csl_cpsw.h:1657
void CSL_CPSW_setEEEPortConfig(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_EEE_PORT_CONFIG *pPortConfig)
Holds CPSW EEE (Energy Efficient Ethernet) Per-Port STATUS.
Definition: csl_cpsw.h:1133
void CSL_CPSW_getCppiSourceIdReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 *pTxSrcId)
Uint32 RxMCastFrames
Definition: csl_cpsw.h:1369
Uint32 Frame256t511
Definition: csl_cpsw.h:1450
Uint32 p0TxPriActivePri7
Definition: csl_cpsw.h:363
Uint32 p8PassPriTag
Definition: csl_cpsw.h:176
CSL_CPSW_ALE_PORTSTATE portState
Definition: csl_cpsw.h:486
Uint32 ethertype
Definition: csl_cpsw.h:779
Uint32 CSL_CPSW_getCppiTxBlksPri(CSL_Xge_cpswRegs *hCpswRegs, Uint8 pri)
void CSL_CPSW_enableAleVlanAware(CSL_AleRegs *hCpswAleRegs)
void CSL_CPSW_setPortStatsEnableReg(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_PORTSTAT *pPortStatsCfg)
void CSL_CPSW_setAlePolicerTestControlReg(CSL_AleRegs *hCpswAleRegs, CSL_CPSW_ALE_POLICER_TEST_CONTROL *policerTestCntrlCfg)
Uint32 macAuthDisable
Definition: csl_cpsw.h:519
void CSL_CPSW_setPort0RxMaxLen(CSL_Xge_cpswRegs *hCpswRegs, Uint32 rxMaxLen)
Uint32 p0RxRemapVlan
Definition: csl_cpsw.h:231
void CSL_CPSW_getPort0RxPriMapReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 *pPortRxPriMap)
Uint32 p0Enable
Definition: csl_cpsw.h:149
Definition: csl_cpsw.h:597
void CSL_CPSW_enableAleVID0Mode(CSL_AleRegs *hCpswAleRegs)
void CSL_CPSW_setTxGlobalBufThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri, Uint32 setVal)
Uint32 fifoLb
Definition: csl_cpsw.h:143
void CSL_CPSW_disableAlePolicerThread(CSL_AleRegs *hCpswAleRegs, Uint32 index)
Uint32 TxOctets
Definition: csl_cpsw.h:1438
Holds Port Time Sync Configuration contents.
Definition: csl_cpsw.h:931
Uint32 TxBCastFrames
Definition: csl_cpsw.h:1405
CSL_CPSW_ALE_UPD_BW
Defines ALE Update Bandwidth Control Value: The upd_bw_ctrl field within ALE control register specifi...
Definition: csl_cpsw.h:1171
void CSL_CPSW_enableAleLearnNoVID(CSL_AleRegs *hCpswAleRegs)
Uint32 polHit
Definition: csl_cpsw.h:1563
Uint32 p0HostBlksPri4
Definition: csl_cpsw.h:388
Uint32 tsRxVlanLType1Enable
Definition: csl_cpsw.h:895
Uint32 ageable
Definition: csl_cpsw.h:693
Uint32 validBitmap
Definition: csl_cpsw.h:1278
Uint32 p0TxCrcRemove
Definition: csl_cpsw.h:179
Uint32 superEnable
Definition: csl_cpsw.h:617
Uint32 redDropEnable
Definition: csl_cpsw.h:1546
CSL_CPSW_ALE_ADDRTYPE
Defines ALE Address types.
Definition: csl_cpsw.h:585
Uint32 rxGapEnPri7
Definition: csl_cpsw.h:277
Uint32 egressTrunkIndex
Definition: csl_cpsw.h:1338
void CSL_CPSW_getAleIPv4Entry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_IPv4_ENTRY *pIPv4Cfg, CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 TxGoodFrames
Definition: csl_cpsw.h:1402
void CSL_CPSW_setCppiTxDstThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal)
void CSL_CPSW_setCpswControlReg(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_CONTROL *pControlRegInfo)
void CSL_CPSW_setCpswTxGlobalBufThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal)
Uint32 secureEnable
Definition: csl_cpsw.h:718
Uint32 port1PriorityTypeEscalateEnable
Definition: csl_cpsw.h:1577
void CSL_CPSW_setCppiPriCirEir(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 cir, Uint32 eir)
Uint32 cppiRxThruRate
Definition: csl_cpsw.h:216
Uint32 destPortMask
Definition: csl_cpsw.h:1349
void CSL_CPSW_disablePort0PassPriTag(CSL_Xge_cpswRegs *hCpswRegs)
Uint32 TxPauseFrames
Definition: csl_cpsw.h:1411
Uint32 polClrallRedhit
Definition: csl_cpsw.h:1555
void CSL_CPSW_getAleOUIAddrEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_OUIADDR_ENTRY *pOUIAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 CSL_CPSW_getTxDstBasedOutFlowAddValX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri)
Holds CPSW Port Control contents.
Definition: csl_cpsw.h:1044
void CSL_CPSW_disableVlanAware(CSL_Xge_cpswRegs *hCpswRegs)
Uint32 CSL_CPSW_extractVid(Uint32 word1, CSL_CPSW_ALETABLE_TYPE aleType)
void CSL_CPSW_getPortRxDscpMap(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pRxDscpPriMap)
Holds CPPI P0 Control register contents.
Definition: csl_cpsw.h:223
Uint32 touched
Definition: csl_cpsw.h:715
Uint32 vid
Definition: csl_cpsw.h:1644
Uint32 CSL_CPSW_getEthertypeMax(CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 txExpressMacAllow
Definition: csl_cpsw.h:1678
void CSL_CPSW_enableAle(CSL_AleRegs *hCpswAleRegs)
Uint8 CSL_CPSW_getRxPriFlowControl(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo)
Uint32 port3PriorityTypeEscalateEnable
Definition: csl_cpsw.h:1583
Uint32 estAddErr
Definition: csl_cpsw.h:1663
Uint32 RxAleDrop
Definition: csl_cpsw.h:1393
Uint32 TxMemProtectErr
Definition: csl_cpsw.h:1507
Uint32 Frame65t127
Definition: csl_cpsw.h:1444
Uint32 port5PriorityTypeEscalateEnable
Definition: csl_cpsw.h:1589
Uint32 p0DscpIpv6En
Definition: csl_cpsw.h:247
void CSL_CPSW_setAleUnknwnVlanUntagReg(CSL_AleRegs *hCpswAleRegs, Uint32 aleUnknwnVlanUntagVal)
Uint32 RxUndersized
Definition: csl_cpsw.h:1387
Uint32 portMask
Definition: csl_cpsw.h:645
Holds CPSW Policer Global Configuration.
Definition: csl_cpsw.h:1186
Uint32 TxDeferred
Definition: csl_cpsw.h:1414
Uint32 p0HostBlksPri7
Definition: csl_cpsw.h:376
Uint32 tsLType2Enable
Definition: csl_cpsw.h:919
bool trunkEnableDst
Definition: csl_cpsw.h:1208
void CSL_CPSW_getPortVlanReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pPortVID, Uint32 *pPortCFI, Uint32 *pPortPRI)
void CSL_CPSW_setTxMaxLenPerPriority(CSL_Xge_cpswRegs *hCpswRegs, Uint32 priority, Uint32 maxLen)
Uint32 replaceDaSa
Definition: csl_cpsw.h:1638
Uint32 ageable
Definition: csl_cpsw.h:712
Definition: csl_cpsw.h:475
Uint32 p0RxPad
Definition: csl_cpsw.h:187
void CSL_CPSW_enableAleUVLANNoLearn(CSL_AleRegs *hCpswAleRegs)
Uint32 CSL_CPSW_getCpswTxGlobalBufThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri)
Uint32 cirIdleIncVal
Definition: csl_cpsw.h:1323
Uint32 dropDualVlan
Definition: csl_cpsw.h:538
void CSL_CPSW_setPortTimeSyncCntlReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_TSCNTL *pTimeSyncCntlCfg)
Uint32 p7StatEnable
Definition: csl_cpsw.h:873
void CSL_CPSW_getStats(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_STATS *pCpswStats)
Uint32 tsRxAnnexFEnable
Definition: csl_cpsw.h:939
void CSL_CPSW_enableAleBypass(CSL_AleRegs *hCpswAleRegs)
Uint32 defThreadEnable
Definition: csl_cpsw.h:1194
Uint32 wait_idle2lpi
Definition: csl_cpsw.h:1135
Uint32 p0TxPriActivePri3
Definition: csl_cpsw.h:335
Uint32 p3StatEnable
Definition: csl_cpsw.h:861
Uint32 CSL_CPSW_isAleBypassEnabled(CSL_AleRegs *hCpswAleRegs)
void CSL_CPSW_getAleStatusNumAleEntries(CSL_AleRegs *hCpswAleRegs, Uint32 *pNumEntries)
void CSL_CPSW_setAleVlanMcastAddrEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_VLANMCASTADDR_ENTRY *pVlanMcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType)
void CSL_CPSW_setPortRxDscpMap(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pRxDscpPriMap)
void CSL_CPSW_setCppiRxGapReg(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_CPPI_P0_RXGAP *pCppiRxGap)
Uint32 ovlanIdx
Definition: csl_cpsw.h:1296
void CSL_CPSW_setAleAgingTimerReg(CSL_AleRegs *hCpswAleRegs, Uint32 agingPrescale, Uint32 agingPeriod)
Uint32 ethertypeIdx
Definition: csl_cpsw.h:1302
Uint32 p0DscpIpv4En
Definition: csl_cpsw.h:253
void CSL_CPSW_getCppiPriCirEir(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 *cir, Uint32 *eir)
void CSL_CPSW_getPortStatsEnableReg(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_PORTSTAT *pPortStatsCfg)
Holds the ALE submodule's version info.
Definition: csl_cpsw.h:446
void CSL_CPSW_getAlePolicerControlReg(CSL_AleRegs *hCpswAleRegs, CSL_CPSW_ALE_POLICER_CONTROL *policerCntrlCfg)
void CSL_CPSW_setPortMaxBlksReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 rxMaxBlks, Uint32 txMaxBlks)
Uint32 disableMacPortDefaultThread
Definition: csl_cpsw.h:1549
void CSL_CPSW_mapTableWord2MacAddr(uint32_t word0, uint32_t word1, uint8_t *macAddr, CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 p7PassPriTag
Definition: csl_cpsw.h:173
Uint32 polClrallHit
Definition: csl_cpsw.h:1554
Uint32 Frame512t1023
Definition: csl_cpsw.h:1453
Uint32 p5FlowEnable
Definition: csl_cpsw.h:429
Uint32 tsTxAnnexEEnable
Definition: csl_cpsw.h:951
void CSL_CPSW_EEEPortStatus(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_EEE_PORT_STATUS *pPortStatus)
Uint32 tsLType1
Definition: csl_cpsw.h:1020
Uint32 p0TxPriActivePri2
Definition: csl_cpsw.h:328
Uint32 p2PassPriTag
Definition: csl_cpsw.h:158
Uint32 CSL_CPSW_getCppiTxGlobalBufThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri)
Uint32 p0RxRemapDscpIpv6
Definition: csl_cpsw.h:225
Uint32 vlanId
Definition: csl_cpsw.h:709
void CSL_CPSW_getAleMcastAddrEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_MCASTADDR_ENTRY *pMcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType)
void CSL_CPSW_setAleVlanMaskMuxReg(CSL_AleRegs *hCpswAleRegs, Uint32 *vlanMaskMux)
void CSL_CPSW_startAleAgeOutNow(CSL_AleRegs *hCpswAleRegs)
Holds the ALE (Inner) VLAN Table entry configuration.
Definition: csl_cpsw.h:733
Uint32 p2FlowEnable
Definition: csl_cpsw.h:420
void CSL_CPSW_getPortTimeSyncSeqIdReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pTsLtype, Uint32 *pTsSeqIdOffset)
Uint32 tsTxVlanLType1Enable
Definition: csl_cpsw.h:910
CSL_CPSW_ALE_VLAN_ENTRY CSL_CPSW_ALE_OUTER_VLAN_ENTRY
Holds the ALE Outer VLAN Table entry configuration.
Definition: csl_cpsw.h:771
void CSL_CPSW_setCppiRxPriFlowControl(CSL_Xge_cpswRegs *hCpswRegs, Uint8 pri)
void CSL_CPSW_disableAleLearnNoVID(CSL_AleRegs *hCpswAleRegs)
Uint32 CSL_CPSW_getPort0FlowIdOffset(CSL_Xge_cpswRegs *hCpswRegs)
Holds the ALE Policer Table entry configuration.
Definition: csl_cpsw.h:1276
Uint32 egressOp
Definition: csl_cpsw.h:1329
Uint32 p0HostBlksPri5
Definition: csl_cpsw.h:384
Uint32 regMcastFloodIndex
Definition: csl_cpsw.h:744
Definition: csl_cpsw.h:599
void CSL_CPSW_disableAleMacAuthMode(CSL_AleRegs *hCpswAleRegs)
Uint32 p0HostBlksPri6
Definition: csl_cpsw.h:380
void CSL_CPSW_getCppiP0Control(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_CPPI_P0_CONTROL *pCppiP0ControlCfg)
Uint32 srcMacIdx
Definition: csl_cpsw.h:1293
bool noDropSrcMcast
Definition: csl_cpsw.h:1219
Uint32 noLearnModeEnable
Definition: csl_cpsw.h:495
Uint32 ts320Enable
Definition: csl_cpsw.h:1011
bool trunkEnableSrc
Definition: csl_cpsw.h:1207
void CSL_CPSW_disableAleUUNIToHost(CSL_AleRegs *hCpswAleRegs)
Uint32 CSL_CPSW_getTxGlobalBufThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri)
void CSL_CPSW_getThruRateReg(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_THRURATE *pThruRateCfg)
Uint32 TxMCastFrames
Definition: csl_cpsw.h:1408
void CSL_CPSW_setTxGlobalBufThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri, Uint32 setVal)
void CSL_CPSW_getAleIPv6Entry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_IPv6_ENTRY *pIPv6Cfg, CSL_CPSW_ALETABLE_TYPE aleType)
void CSL_CPSW_setPort0RxPriMapReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 *pPortRxPriMap)
void CSL_CPSW_disableP0TxCastagnoliCRC(CSL_Xge_cpswRegs *hCpswRegs)
Uint32 Frame64
Definition: csl_cpsw.h:1441
Uint32 vlanIdx
Definition: csl_cpsw.h:1299
Uint32 lpi2wake
Definition: csl_cpsw.h:1124
Definition: csl_cpsw.h:1179
Uint32 rxGapEnPri6
Definition: csl_cpsw.h:280
Uint32 minorVer
Definition: csl_cpsw.h:448
Uint32 CSL_CPSW_getTxGlobalBufThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri)
Uint32 AleUnKnBCastBytes
Definition: csl_cpsw.h:1498
Uint32 port
Definition: csl_cpsw.h:1281
Uint32 CSL_CPSW_isPort0Enabled(CSL_Xge_cpswRegs *hCpswRegs)
Uint32 trunkFlag
Definition: csl_cpsw.h:679
Definition: csl_cpsw.h:598
Uint32 p0TxEccErrEn
Definition: csl_cpsw.h:241
CSL_CPSW_ALE_ADDRTYPE CSL_CPSW_getALEAddressType(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 vlanId
Definition: csl_cpsw.h:735
Uint32 minorVer
Definition: csl_cpsw.h:125
Uint32 polYellowhit
Definition: csl_cpsw.h:1565
Uint32 CSL_CPSW_isAleTxRateLimitEnabled(CSL_AleRegs *hCpswAleRegs)
Uint32 trunkFlag
Definition: csl_cpsw.h:726
Uint32 estCntErr
Definition: csl_cpsw.h:1669
Uint32 enableTTLCheck
Definition: csl_cpsw.h:1344
void CSL_CPSW_setAleOUIAddrEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_OUIADDR_ENTRY *pOUIAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 CSL_CPSW_getAleUpdateBW(CSL_AleRegs *hCpswAleRegs)
UInt32 numLSBIgnore
Definition: csl_cpsw.h:793
Definition: csl_cpsw.h:842
Uint32 rtlVer
Definition: csl_cpsw.h:454
Definition: csl_cpsw.h:1201
Uint32 CSL_CPSW_isAleLearnNoVIDEnabled(CSL_AleRegs *hCpswAleRegs)
void CSL_CPSW_getPortTimeSyncVlanLTypeReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pTsVlanLtype1, Uint32 *pTsVlanLtype2)
Definition: csl_cpsw.h:1561
Uint32 rxLpi
Definition: csl_cpsw.h:1138
Uint32 rxGapEnPri5
Definition: csl_cpsw.h:283
Definition: csl_cpsw.h:1177
Uint32 p0RxChksumEn
Definition: csl_cpsw.h:259
Uint32 tsTxAnnexDEnable
Definition: csl_cpsw.h:948
Uint32 dstIpIdx
Definition: csl_cpsw.h:1308
Uint32 txWake
Definition: csl_cpsw.h:1145
Definition: csl_cpsw.h:554
Uint32 CSL_CPSW_isAleVlanAwareEnabled(CSL_AleRegs *hCpswAleRegs)
void CSL_CPSW_disableAleRateLimit(CSL_AleRegs *hCpswAleRegs)
void CSL_CPSW_getAleVlanMaskMuxReg(CSL_AleRegs *hCpswAleRegs, Uint32 *vlanMaskMux)
Uint32 p0TxPriActivePri4
Definition: csl_cpsw.h:342
Uint32 vlanMemList
Definition: csl_cpsw.h:738
void CSL_CPSW_getPortRawStats(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_STATS *pCpswStats)
Definition: csl_cpsw.h:1541
bool trunkEnablePri
Definition: csl_cpsw.h:1206
Uint32 eeeEnable
Definition: csl_cpsw.h:193
void CSL_CPSW_getPortBlockCountReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pRxBlkCnt_e, Uint32 *pRxBlkCnt_p, Uint32 *pTxBlkCnt)
void CSL_CPSW_setAlePortMirrorSouce(CSL_AleRegs *hCpswAleRegs, Uint32 portNo, bool enableMirror)
void CSL_CPSW_setAleCtrl2TrunkParams(CSL_AleRegs *hCpswAleRegs, CSL_CPSW_ALE_CTRL2_TRUNK_CONFIG *trunkCfg)
Uint32 p0HostBlksPri1
Definition: csl_cpsw.h:400
Uint32 numRLimChans
Definition: csl_cpsw.h:1073
void CSL_CPSW_setAleUpdateBW(CSL_AleRegs *hCpswAleRegs, Uint32 aleUpdBW)
CSL_CPSW_ALE_POLICER_CONTROL_YELLOWTHRESH
Definition: csl_cpsw.h:1530
void CSL_CPSW_setAlePolicerEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_POLICER_ENTRY *pPolCfg)
Uint32 rxGapEnPri1
Definition: csl_cpsw.h:295
void CSL_CPSW_setAleOutVlanEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_OUTER_VLAN_ENTRY *pOutVlanCfg, CSL_CPSW_ALETABLE_TYPE aleType)
void CSL_CPSW_enablePort0(CSL_Xge_cpswRegs *hCpswRegs)
Uint32 TxCarrierSLoss
Definition: csl_cpsw.h:1435
void CSL_CPSW_setAleVlanUnicastAddrEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_VLANUNICASTADDR_ENTRY *pVlanUcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 tsTxAnnexFEnable
Definition: csl_cpsw.h:954
void CSL_CPSW_setAleUnknwnVlanUnregMcastReg(CSL_AleRegs *hCpswAleRegs, Uint32 aleUnknwnVlanUnregMcastVal)
Uint32 ts107Enable
Definition: csl_cpsw.h:981
Definition: csl_cpsw.h:831
void CSL_CPSW_setPTypeReg(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_PTYPE *pPtypeCfg)
CSL_CPSW_ALE_POLICER_ENTRYTYPE
Defines ALE Policer Entry types.
Definition: csl_cpsw.h:596
Uint32 dropDoubleVlan
Definition: csl_cpsw.h:543
Definition: csl_cpsw.h:586
void CSL_CPSW_setAleOAMLpbkControl(CSL_AleRegs *hCpswAleRegs, Uint32 lpbkEnablePortMask)
void CSL_CPSW_setAlePolicerGlobConfig(CSL_AleRegs *hCpswAleRegs, CSL_CPSW_ALE_POLICER_GLOB_CONFIG *pGlobConfig)
Holds the ALE Port control register info.
Definition: csl_cpsw.h:484
void CSL_CPSW_getPortMACAddress(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint8 *pMacAddress)
void CSL_CPSW_setTxBlksPri(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint8 pri, Uint32 blks)
void CSL_CPSW_setRxPriFlowControl(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint8 pri)
void CSL_CPSW_setP0HostBlksPri(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_CPPI_P0_HOSTBLKSPRI *pCppiHostBlksPri)
void CSL_CPSW_setAleIPNxtHdrWhitelist(CSL_AleRegs *hCpswAleRegs, Uint8 ipNxtHdr0, Uint8 ipNxtHdr1, Uint8 ipNxtHdr2, Uint8 ipNxtHdr3)
void CSL_CPSW_setPortTxPriMapReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pPortTxPriMap)
Uint32 CSL_CPSW_getTxDstThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri)
Uint32 tsVlanLType1
Definition: csl_cpsw.h:1026
void CSL_CPSW_getRawStats(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_STATS *pCpswStats)
Uint32 trunkBase
Definition: csl_cpsw.h:1202
Holds CPPI_P0_FIFO_Status register contents. This is not applicable for 2 port switch.
Definition: csl_cpsw.h:307
Uint32 ts319Enable
Definition: csl_cpsw.h:1008
Uint32 thread
Definition: csl_cpsw.h:1311
Uint32 CSL_CPSW_isP0TxCastagnoliCRCEnabled(CSL_Xge_cpswRegs *hCpswRegs)
Uint32 CSL_CPSW_isAleAgeOutDone(CSL_AleRegs *hCpswAleRegs)
Uint32 tsTTLNonzeroEnable
Definition: csl_cpsw.h:1017
void CSL_CPSW_setEEEGlobConfig(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_EEE_GLOB_CONFIG *pGlobConfig)
Uint32 enablePriorityOR
Definition: csl_cpsw.h:1548
Uint32 RxGoodFrames
Definition: csl_cpsw.h:1363
void CSL_CPSW_enableAleRateLimit(CSL_AleRegs *hCpswAleRegs)
void CSL_CPSW_setAleIPv6Entry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_IPv6_ENTRY *pIPv6Cfg, CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 txFifoHold
Definition: csl_cpsw.h:1149
Uint32 CSL_CPSW_getIpv4IgnBitsMax(CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 tsMsgTypeEnable
Definition: csl_cpsw.h:969
Uint32 CSL_CPSW_isAleOUIDenyModeEnabled(CSL_AleRegs *hCpswAleRegs)
Uint32 regMcastFloodMask
Definition: csl_cpsw.h:749
Definition: csl_cpsw.h:1173
Uint32 mcastFwdState
Definition: csl_cpsw.h:639
void CSL_CPSW_setGapThreshold(CSL_Xge_cpswRegs *hCpswRegs, Uint32 gapThreshold)
Uint32 portNumber
Definition: csl_cpsw.h:674
Uint32 CSL_CPSW_getCppiTxDstThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri)
Uint32 polTestIdx
Definition: csl_cpsw.h:1558
void CSL_CPSW_disableAleOUIDenyMode(CSL_AleRegs *hCpswAleRegs)
Uint32 p6StatEnable
Definition: csl_cpsw.h:870
Uint32 port4PriorityTypeEscalateEnable
Definition: csl_cpsw.h:1586
Uint32 PortmaskFrop
Definition: csl_cpsw.h:1465
Definition: csl_cpsw.h:476
Uint32 rxGapEnPri4
Definition: csl_cpsw.h:286
Holds the Time sync submodule's version info.
Definition: csl_cpsw.h:123
Uint32 secureEnable
Definition: csl_cpsw.h:668
void CSL_CPSW_setAlePortControlReg(CSL_AleRegs *hCpswAleRegs, Uint32 portNo, CSL_CPSW_ALE_PORTCONTROL *pPortControlInfo)
void CSL_CPSW_enableAleTxRateLimit(CSL_AleRegs *hCpswAleRegs)
Uint32 p0RxPassCrcErr
Definition: csl_cpsw.h:190
Uint32 AleUnKnUniBytes
Definition: csl_cpsw.h:1486