PDK API Guide for AM64x
udma_soc.h
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1 /*
2  * Copyright (c) Texas Instruments Incorporated 2018
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  *
8  * Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
39 #ifndef UDMA_SOC_H_
40 #define UDMA_SOC_H_
41 
42 /* ========================================================================== */
43 /* Include Files */
44 /* ========================================================================== */
45 
46 /* None */
47 
48 #ifdef __cplusplus
49 extern "C" {
50 #endif
51 
52 /* ========================================================================== */
53 /* Macros & Typedefs */
54 /* ========================================================================== */
55 
65 #define UDMA_INST_ID_BCDMA_0 (UDMA_INST_ID_2)
66 
67 #define UDMA_INST_ID_PKTDMA_0 (UDMA_INST_ID_3)
68 
69 #define UDMA_INST_ID_START (UDMA_INST_ID_2)
70 
71 #define UDMA_INST_ID_MAX (UDMA_INST_ID_3)
72 
73 #define UDMA_NUM_INST_ID (UDMA_INST_ID_MAX - UDMA_INST_ID_START + 1U)
74 /* @} */
75 
85 #define UDMA_SOC_CFG_UDMAP_PRESENT (0U)
86 
88 #define UDMA_SOC_CFG_LCDMA_PRESENT (1U)
89 
91 #define UDMA_SOC_CFG_PROXY_PRESENT (0U)
92 
94 #define UDMA_SOC_CFG_CLEC_PRESENT (0U)
95 
97 #define UDMA_SOC_CFG_RA_NORMAL_PRESENT (0U)
98 
100 #define UDMA_SOC_CFG_RA_LCDMA_PRESENT (1U)
101 
103 #define UDMA_SOC_CFG_RING_MON_PRESENT (0U)
104 
106 #define UDMA_SOC_CFG_APPLY_RING_WORKAROUND (0U)
107 /* @} */
108 
118 #define UDMA_TX_UHC_CHANS_FDEPTH (CSL_DMSS_UDMAP_TX_UHC_CHANS_FDEPTH)
119 
120 #define UDMA_TX_HC_CHANS_FDEPTH (CSL_DMSS_UDMAP_TX_HC_CHANS_FDEPTH)
121 
122 #define UDMA_TX_CHANS_FDEPTH (CSL_DMSS_UDMAP_TX_CHANS_FDEPTH)
123 /* @} */
124 
134 #define UDMA_RINGACC_ASEL_ENDPOINT_PHYSADDR (CSL_LCDMA_RINGACC_ASEL_ENDPOINT_PHYSADDR)
135 
136 #define UDMA_RINGACC_ASEL_ENDPOINT_PCIE0 (CSL_LCDMA_RINGACC_ASEL_ENDPOINT_PCIE0)
137 
138 #define UDMA_RINGACC_ASEL_ENDPOINT_ACP_WR_ALLOC (CSL_LCDMA_RINGACC_ASEL_ENDPOINT_ACP_WR_ALLOC)
139 
140 #define UDMA_RINGACC_ASEL_ENDPOINT_ACP_RD_ALLOC (CSL_LCDMA_RINGACC_ASEL_ENDPOINT_ACP_RD_ALLOC)
141 /* @} */
142 
144 #define UDMA_RING_MODE_INVALID (CSL_LCDMA_RINGACC_RING_MODE_INVALID)
145 
147 #define UDMA_NUM_MAPPED_TX_GROUP (4U)
148 
156 #define UDMA_MAPPED_TX_GROUP_CPSW (UDMA_MAPPED_GROUP0)
157 #define UDMA_MAPPED_TX_GROUP_SAUL (UDMA_MAPPED_GROUP1)
158 #define UDMA_MAPPED_TX_GROUP_ICSSG_0 (UDMA_MAPPED_GROUP2)
159 #define UDMA_MAPPED_TX_GROUP_ICSSG_1 (UDMA_MAPPED_GROUP3)
160 /* @} */
161 
163 #define UDMA_NUM_MAPPED_RX_GROUP (4U)
164 
172 #define UDMA_MAPPED_RX_GROUP_CPSW (UDMA_MAPPED_GROUP4)
173 #define UDMA_MAPPED_RX_GROUP_SAUL (UDMA_MAPPED_GROUP5)
174 #define UDMA_MAPPED_RX_GROUP_ICSSG_0 (UDMA_MAPPED_GROUP6)
175 #define UDMA_MAPPED_RX_GROUP_ICSSG_1 (UDMA_MAPPED_GROUP7)
176 /* @} */
177 
179 #define UDMA_NUM_UTC_INSTANCE (CSL_DMSS_UTC_CNT)
180 
188 /* No UTC in AM64x */
189 /* @} */
190 
199 /*
200  * Locally used core ID to define default RM configuration.
201  * Not to be used by caller
202  */
203 #define UDMA_CORE_ID_MPU1_0 (0U)
204 #define UDMA_CORE_ID_MCU2_0 (1U)
205 #define UDMA_CORE_ID_MCU2_1 (2U)
206 #define UDMA_CORE_ID_MCU1_0 (3U)
207 #define UDMA_CORE_ID_MCU1_1 (4U)
208 #define UDMA_CORE_ID_M4F_0 (5U)
209 /* Total number of cores */
210 #define UDMA_NUM_CORE (6U)
211 /* @} */
212 
222 #define UDMA_RM_RES_ID_BC_UHC (0U)
223 
224 #define UDMA_RM_RES_ID_BC_HC (1U)
225 
226 #define UDMA_RM_RES_ID_BC (2U)
227 
228 #define UDMA_RM_RES_ID_TX_UHC (3U)
229 
230 #define UDMA_RM_RES_ID_TX_HC (4U)
231 
232 #define UDMA_RM_RES_ID_TX (5U)
233 
234 #define UDMA_RM_RES_ID_RX_UHC (6U)
235 
236 #define UDMA_RM_RES_ID_RX_HC (7U)
237 
238 #define UDMA_RM_RES_ID_RX (8U)
239 
240 #define UDMA_RM_RES_ID_GLOBAL_EVENT (9U)
241 
242 #define UDMA_RM_RES_ID_VINTR (10U)
243 
244 #define UDMA_RM_RES_ID_MAPPED_TX_CPSW (11U)
245 
246 #define UDMA_RM_RES_ID_MAPPED_TX_SAUL_0 (12U)
247 
248 #define UDMA_RM_RES_ID_MAPPED_TX_SAUL_1 (13U)
249 
250 #define UDMA_RM_RES_ID_MAPPED_TX_ICSSG_0 (14U)
251 
252 #define UDMA_RM_RES_ID_MAPPED_TX_ICSSG_1 (15U)
253 
254 #define UDMA_RM_RES_ID_MAPPED_RX_CPSW (16U)
255 
256 #define UDMA_RM_RES_ID_MAPPED_RX_SAUL_0 (17U)
257 
258 #define UDMA_RM_RES_ID_MAPPED_RX_SAUL_1 (18U)
259 
260 #define UDMA_RM_RES_ID_MAPPED_RX_SAUL_2 (19U)
261 
262 #define UDMA_RM_RES_ID_MAPPED_RX_SAUL_3 (20U)
263 
264 #define UDMA_RM_RES_ID_MAPPED_RX_ICSSG_0 (21U)
265 
266 #define UDMA_RM_RES_ID_MAPPED_RX_ICSSG_1 (22U)
267 
268 #define UDMA_RM_RES_ID_MAPPED_TX_RING_CPSW (23U)
269 
270 #define UDMA_RM_RES_ID_MAPPED_TX_RING_SAUL_0 (24U)
271 
272 #define UDMA_RM_RES_ID_MAPPED_TX_RING_SAUL_1 (25U)
273 
274 #define UDMA_RM_RES_ID_MAPPED_TX_RING_ICSSG_0 (26U)
275 
276 #define UDMA_RM_RES_ID_MAPPED_TX_RING_ICSSG_1 (27U)
277 
278 #define UDMA_RM_RES_ID_MAPPED_RX_RING_CPSW (28U)
279 
280 #define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_0 (29U)
281 
282 #define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_1 (30U)
283 
284 #define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_2 (31U)
285 
286 #define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_3 (32U)
287 
288 #define UDMA_RM_RES_ID_MAPPED_RX_RING_ICSSG_0 (33U)
289 
290 #define UDMA_RM_RES_ID_MAPPED_RX_RING_ICSSG_1 (34U)
291 
292 #define UDMA_RM_NUM_BCDMA_RES (11U)
293 
294 #define UDMA_RM_NUM_PKTDMA_RES (35U)
295 
296 #define UDMA_RM_NUM_RES (35U)
297 /* @} */
298 
301 #define UDMA_RM_NUM_SHARED_RES (2U)
302 
304 #define UDMA_RM_SHARED_RES_MAX_INST (UDMA_NUM_CORE)
305 
315 #define UDMA_PSIL_CH_CPSW2_TX (CSL_PSILCFG_DMSS_CPSW2_PSILD_THREAD_OFFSET)
316 #define UDMA_PSIL_CH_SAUL0_TX (CSL_PSILCFG_DMSS_SAUL0_PSILD_THREAD_OFFSET)
317 #define UDMA_PSIL_CH_ICSS_G0_TX (CSL_PSILCFG_DMSS_ICSS_G0_PSILD_THREAD_OFFSET)
318 #define UDMA_PSIL_CH_ICSS_G1_TX (CSL_PSILCFG_DMSS_ICSS_G1_PSILD_THREAD_OFFSET)
319 
320 #define UDMA_PSIL_CH_CPSW2_RX (CSL_PSILCFG_DMSS_CPSW2_PSILS_THREAD_OFFSET)
321 #define UDMA_PSIL_CH_SAUL0_RX (CSL_PSILCFG_DMSS_SAUL0_PSILS_THREAD_OFFSET)
322 #define UDMA_PSIL_CH_ICSS_G0_RX (CSL_PSILCFG_DMSS_ICSS_G0_PSILS_THREAD_OFFSET)
323 #define UDMA_PSIL_CH_ICSS_G1_RX (CSL_PSILCFG_DMSS_ICSS_G1_PSILS_THREAD_OFFSET)
324 
325 
326 #define UDMA_PSIL_CH_CPSW2_TX_CNT (CSL_PSILCFG_DMSS_CPSW2_PSILD_THREAD_CNT)
327 #define UDMA_PSIL_CH_SAUL0_TX_CNT (CSL_PSILCFG_DMSS_SAUL0_PSILD_THREAD_CNT)
328 #define UDMA_PSIL_CH_ICSS_G0_TX_CNT (CSL_PSILCFG_DMSS_ICSS_G0_PSILD_THREAD_CNT)
329 #define UDMA_PSIL_CH_ICSS_G1_TX_CNT (CSL_PSILCFG_DMSS_ICSS_G1_PSILD_THREAD_CNT)
330 
331 #define UDMA_PSIL_CH_CPSW2_RX_CNT (CSL_PSILCFG_DMSS_CPSW2_PSILS_THREAD_CNT)
332 #define UDMA_PSIL_CH_SAUL0_RX_CNT (CSL_PSILCFG_DMSS_SAUL0_PSILS_THREAD_CNT)
333 #define UDMA_PSIL_CH_ICSS_G0_RX_CNT (CSL_PSILCFG_DMSS_ICSS_G0_PSILS_THREAD_CNT)
334 #define UDMA_PSIL_CH_ICSS_G1_RX_CNT (CSL_PSILCFG_DMSS_ICSS_G1_PSILS_THREAD_CNT)
335 
336 /* @} */
337 
338 
357 /*
358  * PDMA MAIN0 MCSPI TX Channels
359  */
360 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_TX (CSL_PDMA_CH_MAIN0_MCSPI0_CH0_TX)
361 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_TX (CSL_PDMA_CH_MAIN0_MCSPI0_CH1_TX)
362 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_TX (CSL_PDMA_CH_MAIN0_MCSPI0_CH2_TX)
363 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_TX (CSL_PDMA_CH_MAIN0_MCSPI0_CH3_TX)
364 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_TX (CSL_PDMA_CH_MAIN0_MCSPI1_CH0_TX)
365 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_TX (CSL_PDMA_CH_MAIN0_MCSPI1_CH1_TX)
366 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_TX (CSL_PDMA_CH_MAIN0_MCSPI1_CH2_TX)
367 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_TX (CSL_PDMA_CH_MAIN0_MCSPI1_CH3_TX)
368 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_TX (CSL_PDMA_CH_MAIN0_MCSPI2_CH0_TX)
369 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_TX (CSL_PDMA_CH_MAIN0_MCSPI2_CH1_TX)
370 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_TX (CSL_PDMA_CH_MAIN0_MCSPI2_CH2_TX)
371 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_TX (CSL_PDMA_CH_MAIN0_MCSPI2_CH3_TX)
372 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_TX (CSL_PDMA_CH_MAIN0_MCSPI3_CH0_TX)
373 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_TX (CSL_PDMA_CH_MAIN0_MCSPI3_CH1_TX)
374 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_TX (CSL_PDMA_CH_MAIN0_MCSPI3_CH2_TX)
375 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_TX (CSL_PDMA_CH_MAIN0_MCSPI3_CH3_TX)
376 /*
377  * PDMA MAIN0 UART TX Channels
378  */
379 #define UDMA_PDMA_CH_MAIN0_UART0_TX (CSL_PDMA_CH_MAIN0_UART0_CH0_TX)
380 #define UDMA_PDMA_CH_MAIN0_UART1_TX (CSL_PDMA_CH_MAIN0_UART1_CH0_TX)
381 
382 /* @} */
383 
393 /*
394  * PDMA MAIN0 MCSPI RX Channels
395  */
396 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_RX (CSL_PDMA_CH_MAIN0_MCSPI0_CH0_RX)
397 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_RX (CSL_PDMA_CH_MAIN0_MCSPI0_CH1_RX)
398 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_RX (CSL_PDMA_CH_MAIN0_MCSPI0_CH2_RX)
399 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_RX (CSL_PDMA_CH_MAIN0_MCSPI0_CH3_RX)
400 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_RX (CSL_PDMA_CH_MAIN0_MCSPI1_CH0_RX)
401 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_RX (CSL_PDMA_CH_MAIN0_MCSPI1_CH1_RX)
402 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_RX (CSL_PDMA_CH_MAIN0_MCSPI1_CH2_RX)
403 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_RX (CSL_PDMA_CH_MAIN0_MCSPI1_CH3_RX)
404 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_RX (CSL_PDMA_CH_MAIN0_MCSPI2_CH0_RX)
405 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_RX (CSL_PDMA_CH_MAIN0_MCSPI2_CH1_RX)
406 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_RX (CSL_PDMA_CH_MAIN0_MCSPI2_CH2_RX)
407 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_RX (CSL_PDMA_CH_MAIN0_MCSPI2_CH3_RX)
408 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_RX (CSL_PDMA_CH_MAIN0_MCSPI3_CH0_RX)
409 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_RX (CSL_PDMA_CH_MAIN0_MCSPI3_CH1_RX)
410 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_RX (CSL_PDMA_CH_MAIN0_MCSPI3_CH2_RX)
411 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_RX (CSL_PDMA_CH_MAIN0_MCSPI3_CH3_RX)
412 /*
413  * PDMA MAIN0 UART RX Channels
414  */
415 #define UDMA_PDMA_CH_MAIN0_UART0_RX (CSL_PDMA_CH_MAIN0_UART0_CH0_RX)
416 #define UDMA_PDMA_CH_MAIN0_UART1_RX (CSL_PDMA_CH_MAIN0_UART1_CH0_RX)
417 
418 /* @} */
419 
429 /*
430  * PDMA MAIN1 MCSPI TX Channels
431  */
432 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_TX (CSL_PDMA_CH_MAIN1_MCSPI4_CH0_TX)
433 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_TX (CSL_PDMA_CH_MAIN1_MCSPI4_CH1_TX)
434 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_TX (CSL_PDMA_CH_MAIN1_MCSPI4_CH2_TX)
435 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_TX (CSL_PDMA_CH_MAIN1_MCSPI4_CH3_TX)
436 /*
437  * PDMA MAIN1 UART TX Channels
438  */
439 #define UDMA_PDMA_CH_MAIN1_UART2_TX (CSL_PDMA_CH_MAIN1_UART2_CH0_TX)
440 #define UDMA_PDMA_CH_MAIN1_UART3_TX (CSL_PDMA_CH_MAIN1_UART3_CH0_TX)
441 #define UDMA_PDMA_CH_MAIN1_UART4_TX (CSL_PDMA_CH_MAIN1_UART4_CH0_TX)
442 #define UDMA_PDMA_CH_MAIN1_UART5_TX (CSL_PDMA_CH_MAIN1_UART5_CH0_TX)
443 #define UDMA_PDMA_CH_MAIN1_UART6_TX (CSL_PDMA_CH_MAIN1_UART6_CH0_TX)
444 /*
445  * PDMA MAIN1 MCAN TX Channels
446  */
447 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH0_TX (CSL_PDMA_CH_MAIN1_MCAN0_CH0_TX)
448 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH1_TX (CSL_PDMA_CH_MAIN1_MCAN0_CH1_TX)
449 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH2_TX (CSL_PDMA_CH_MAIN1_MCAN0_CH2_TX)
450 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH0_TX (CSL_PDMA_CH_MAIN1_MCAN1_CH0_TX)
451 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH1_TX (CSL_PDMA_CH_MAIN1_MCAN1_CH1_TX)
452 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH2_TX (CSL_PDMA_CH_MAIN1_MCAN1_CH2_TX)
453 
454 /* @} */
455 
465 /*
466  * PDMA MAIN1 MCSPI RX Channels
467  */
468 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_RX (CSL_PDMA_CH_MAIN1_MCSPI4_CH0_RX)
469 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_RX (CSL_PDMA_CH_MAIN1_MCSPI4_CH1_RX)
470 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_RX (CSL_PDMA_CH_MAIN1_MCSPI4_CH2_RX)
471 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_RX (CSL_PDMA_CH_MAIN1_MCSPI4_CH3_RX)
472 /*
473  * PDMA MAIN1 UART RX Channels
474  */
475 #define UDMA_PDMA_CH_MAIN1_UART2_RX (CSL_PDMA_CH_MAIN1_UART2_CH0_RX)
476 #define UDMA_PDMA_CH_MAIN1_UART3_RX (CSL_PDMA_CH_MAIN1_UART3_CH0_RX)
477 #define UDMA_PDMA_CH_MAIN1_UART4_RX (CSL_PDMA_CH_MAIN1_UART4_CH0_RX)
478 #define UDMA_PDMA_CH_MAIN1_UART5_RX (CSL_PDMA_CH_MAIN1_UART5_CH0_RX)
479 #define UDMA_PDMA_CH_MAIN1_UART6_RX (CSL_PDMA_CH_MAIN1_UART6_CH0_RX)
480 /*
481  * PDMA MAIN1 MCAN RX Channels
482  */
483 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH0_RX (CSL_PDMA_CH_MAIN1_MCAN0_CH0_RX)
484 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH1_RX (CSL_PDMA_CH_MAIN1_MCAN0_CH1_RX)
485 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH2_RX (CSL_PDMA_CH_MAIN1_MCAN0_CH2_RX)
486 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH0_RX (CSL_PDMA_CH_MAIN1_MCAN1_CH0_RX)
487 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH1_RX (CSL_PDMA_CH_MAIN1_MCAN1_CH1_RX)
488 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH2_RX (CSL_PDMA_CH_MAIN1_MCAN1_CH2_RX)
489 /*
490  * PDMA MAIN1 ADC RX Channels
491  */
492 #define UDMA_PDMA_CH_MAIN1_ADC0_CH0_RX (CSL_PDMA_CH_MAIN1_ADC0_CH0_RX)
493 #define UDMA_PDMA_CH_MAIN1_ADC0_CH1_RX (CSL_PDMA_CH_MAIN1_ADC0_CH1_RX)
494 
495 /* @} */
496 
497 /* @} */
498 
502 typedef struct
503 {
504  uint32_t defaultRing;
506  uint32_t startFreeRing;
508  uint32_t numFreeRing;
511 
512 /* ========================================================================== */
513 /* Structure Declarations */
514 /* ========================================================================== */
515 
516 /* None */
517 
518 /* ========================================================================== */
519 /* Function Declarations */
520 /* ========================================================================== */
521 
527 uint32_t Udma_getCoreId(void);
528 
534 uint16_t Udma_getCoreSciDevId(void);
535 
541 uint32_t Udma_isCacheCoherent(void);
542 
543 /* ========================================================================== */
544 /* Static Function Definitions */
545 /* ========================================================================== */
546 
547 /* None */
548 
549 #ifdef __cplusplus
550 }
551 #endif
552 
553 #endif /* #ifndef UDMA_SOC_H_ */
uint32_t Udma_isCacheCoherent(void)
Returns TRUE if the memory is cache coherent.
uint32_t numFreeRing
Definition: udma_soc.h:508
uint32_t Udma_getCoreId(void)
Returns the core ID.
uint32_t startFreeRing
Definition: udma_soc.h:506
UDMA mapped channel ring attributes.
Definition: udma_soc.h:502
uint32_t defaultRing
Definition: udma_soc.h:504
uint16_t Udma_getCoreSciDevId(void)
Returns the core tisci device ID.