42 #ifndef CSL_CPSW_SS_V5_0_H_ 43 #define CSL_CPSW_SS_V5_0_H_ 50 #include <ti/csl/soc.h> 51 #include <ti/csl/csl.h> 52 #include <ti/csl/cslr_xge_cpsw_ss_s.h> 602 Uint32 qsgmiiControlRdCd);
Definition: csl_cpsw_ss.h:67
void CSL_CPSW_SS_setSerdesResetIsolation(CSL_Xge_cpsw_ss_sRegs *hCpswSsRegs, Uint32 resetIso)
Uint32 CSL_CPSW_SS_getQSGMIIStatusRxSync(CSL_Xge_cpsw_ss_sRegs *hCpswSsRegs, Uint32 qsgmiiId)
void CSL_CPSW_SS_INTD_setEOIVector(CSL_cpswRegs_INTD *hCpswIntDRegs, Uint32 eoiVector)
Uint32 CSL_CPSW_SS_INTD_getEnableIntrCPSWEventInterrupt(CSL_cpswRegs_INTD *hCpswIntDRegs)
Uint32 scheme
Definition: csl_cpsw_ss.h:94
void CSL_CPSW_SS_INTD_getStatusIntr(CSL_cpswRegs_INTD *hCpswIntDRegs, CSL_CPSW_SS_INTD_INTRSTATUS *intrStatus)
Uint32 majorRevision
Definition: csl_cpsw_ss.h:102
Uint32 fullDuplex
Definition: csl_cpsw_ss.h:132
Uint32 bu
Definition: csl_cpsw_ss.h:96
Uint32 custom
Definition: csl_cpsw_ss.h:104
void CSL_CPSW_SS_INTD_setEnableIntrCPSWEventInterrupt(CSL_cpswRegs_INTD *hCpswIntDRegs, Uint32 enable)
Uint32 mdioInterruptActive
Definition: csl_cpsw_ss.h:117
Uint32 majorVer
Definition: csl_cpsw_ss.h:79
Uint32 speed
Definition: csl_cpsw_ss.h:130
void CSL_CPSW_SS_getVersionInfo(CSL_Xge_cpsw_ss_sRegs *hCpswSsRegs, CSL_CPSW_SS_VERSION *versionInfo)
Holds the CPSW_SS INTD version info.
Definition: csl_cpsw_ss.h:92
void CSL_CPSW_SS_INTD_setClearIntrStatInterrupt(CSL_cpswRegs_INTD *hCpswIntDRegs)
void CSL_CPSW_SS_INTD_setClearIntrMdioInterrupt(CSL_cpswRegs_INTD *hCpswIntDRegs)
Holds the CPSW_SS RGMII STATUS.
Definition: csl_cpsw_ss.h:126
Uint32 CSL_CPSW_SS_getQSGMIIControlRdCd(CSL_Xge_cpsw_ss_sRegs *hCpswSsRegs, Uint32 qsgmiiId)
void CSL_CPSW_SS_setSGMIIMode(CSL_Xge_cpsw_ss_sRegs *hCpswSsRegs, Uint32 macPortNum, CSL_SGMII_MODE sgmiiModeId)
Holds the CPSW_SS INTD interrupt status info.
Definition: csl_cpsw_ss.h:113
Uint32 link
Definition: csl_cpsw_ss.h:128
CSL_SGMII_MODE
SGMII Mode enumerators.
Definition: csl_cpsw_ss.h:61
Definition: csl_cpsw_ss.h:64
Uint32 minorRevision
Definition: csl_cpsw_ss.h:106
Holds the Ethernet switch subsystem's version info.
Definition: csl_cpsw_ss.h:74
Uint32 CSL_CPSW_SS_getXGMIILinkStatus(CSL_Xge_cpsw_ss_sRegs *hCpswSsRegs, Uint32 xgmiiId)
Uint32 CSL_CPSW_SS_getSGMIILinkStatus(CSL_Xge_cpsw_ss_sRegs *hCpswSsRegs, Uint32 sgmiiId)
Uint32 rtlVer
Definition: csl_cpsw_ss.h:100
void CSL_CPSW_SS_getRGMIIStatus(CSL_Xge_cpsw_ss_sRegs *hCpswSsRegs, Uint32 macPortNum, CSL_CPSW_SS_RGMIISTATUS *pRgmiiStatus)
void CSL_CPSW_SS_INTD_setEnableIntrMdioInterrupt(CSL_cpswRegs_INTD *hCpswIntDRegs, Uint32 enable)
Uint32 id
Definition: csl_cpsw_ss.h:85
Uint32 CSL_CPSW_SS_getSerdesResetIsolation(CSL_Xge_cpsw_ss_sRegs *hCpswSsRegs)
Uint32 rtlVer
Definition: csl_cpsw_ss.h:82
void CSL_CPSW_SS_INTD_setClearIntrCPSWEventInterrupt(CSL_cpswRegs_INTD *hCpswIntDRegs)
Uint32 CSL_CPSW_SS_INTD_getEnableIntrStatInterrupt(CSL_cpswRegs_INTD *hCpswIntDRegs)
void CSL_CPSW_SS_INTD_setEnableIntrStatInterrupt(CSL_cpswRegs_INTD *hCpswIntDRegs, Uint32 enable)
Uint32 CSL_CPSW_SS_INTD_getEOIIntrVector(CSL_cpswRegs_INTD *hCpswIntDRegs)
Uint32 CSL_CPSW_SS_INTD_getIntrVectorOutPulse(CSL_cpswRegs_INTD *hCpswIntDRegs)
void CSL_CPSW_SS_INTD_getVersionInfo(CSL_cpswRegs_INTD *hCpswIntDRegs, CSL_CPSW_SS_INTD_VERSION *versionInfo)
Uint32 cpswEventActive
Definition: csl_cpsw_ss.h:115
Uint32 minorVer
Definition: csl_cpsw_ss.h:76
Uint32 CSL_CPSW_SS_INTD_getEOIVector(CSL_cpswRegs_INTD *hCpswIntDRegs)
void CSL_CPSW_SS_setQSGMIIControlRdCd(CSL_Xge_cpsw_ss_sRegs *hCpswSsRegs, Uint32 qsgmiiId, Uint32 qsgmiiControlRdCd)
Uint32 CSL_CPSW_SS_INTD_getEnableIntrMdioInterrupt(CSL_cpswRegs_INTD *hCpswIntDRegs)
Uint32 statPendInterruptActive
Definition: csl_cpsw_ss.h:119