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PDK API Guide for AM64x
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Holds CPPI_P0_Rx_Gap register contents. This is applicable only for 2 port switch.
Data Fields | |
Uint32 | rxGapCnt |
Uint32 | rxGapEnPri7 |
Uint32 | rxGapEnPri6 |
Uint32 | rxGapEnPri5 |
Uint32 | rxGapEnPri4 |
Uint32 | rxGapEnPri3 |
Uint32 | rxGapEnPri2 |
Uint32 | rxGapEnPri1 |
Uint32 | rxGapEnPri0 |
Uint32 CSL_CPSW_CPPI_P0_RXGAP::rxGapCnt |
Receive Gap Count - This is the number of clocks that will in the gap between received packet on port 0 when a priority has rxGapEnPri[7-0] set
Uint32 CSL_CPSW_CPPI_P0_RXGAP::rxGapEnPri7 |
Receive Gap Enable for Priority 7
Uint32 CSL_CPSW_CPPI_P0_RXGAP::rxGapEnPri6 |
Receive Gap Enable for Priority 6
Uint32 CSL_CPSW_CPPI_P0_RXGAP::rxGapEnPri5 |
Receive Gap Enable for Priority 5
Uint32 CSL_CPSW_CPPI_P0_RXGAP::rxGapEnPri4 |
Receive Gap Enable for Priority 4
Uint32 CSL_CPSW_CPPI_P0_RXGAP::rxGapEnPri3 |
Receive Gap Enable for Priority 3
Uint32 CSL_CPSW_CPPI_P0_RXGAP::rxGapEnPri2 |
Receive Gap Enable for Priority 2
Uint32 CSL_CPSW_CPPI_P0_RXGAP::rxGapEnPri1 |
Receive Gap Enable for Priority 1
Uint32 CSL_CPSW_CPPI_P0_RXGAP::rxGapEnPri0 |
Receive Gap Enable for Priority 0