42 #ifndef CSL_CPSW_V5_H_ 43 #define CSL_CPSW_V5_H_ 50 #include <ti/csl/soc.h> 51 #include <ti/csl/csl.h> 52 #include <ti/csl/cslr_ale.h> 53 #include <ti/csl/cslr_xge_cpsw.h> 61 #define CSL_CPSW_ALECONTROL_RATELIMIT_EN (1 << 0u) 64 #define CSL_CPSW_ALECONTROL_AUTHMODE_EN (1 << 1u) 67 #define CSL_CPSW_ALECONTROL_VLANAWARE_EN (1 << 2u) 70 #define CSL_CPSW_ALECONTROL_RATELIMIT_TX_EN (1 << 3u) 73 #define CSL_CPSW_ALECONTROL_OUIDENY_EN (1 << 5u) 76 #define CSL_CPSW_ALECONTROL_VID0MODE_EN (1 << 6u) 79 #define CSL_CPSW_ALECONTROL_LEARN_NO_VID_EN (1 << 7u) 82 #define CSL_CPSW_ALECONTROL_AGEOUT_NOW_EN (1 << 29u) 85 #define CSL_CPSW_ALECONTROL_CLRTABLE_EN (1 << 30u) 88 #define CSL_CPSW_ALECONTROL_ALE_EN (1 << 31u) 93 #define CSL_CPSW_PORTMASK_PORT0_EN (1 << 0u) 96 #define CSL_CPSW_PORTMASK_PORT1_EN (1 << 1u) 99 #define CSL_CPSW_PORTMASK_PORT2_EN (1 << 2u) 102 #define CSL_CPSW_PORTMASK_PORT3_EN (1 << 3u) 105 #define CSL_CPSW_PORTMASK_PORT4_EN (1 << 4u) 108 #define CSL_CPSW_PORTMASK_PORT5_EN (1 << 5u) 111 #define CSL_CPSW_PORTMASK_PORT6_EN (1 << 6u) 114 #define CSL_CPSW_PORTMASK_PORT7_EN (1 << 7u) 117 #define CSL_CPSW_PORTMASK_PORT8_EN (1 << 8u) 562 #define CSL_ALE_ENTRYTYPE_MAC_ADDR CSL_ALE_ENTRYTYPE_ADDRESS 568 #define CSL_ALE_ENTRYTYPE_POLICER CSL_ALE_ENTRYTYPE_VLAN 611 Uint8 macAddress [6];
633 Uint8 macAddress [6];
658 Uint8 macAddress [6];
690 Uint8 ouiAddress [3];
706 Uint8 macAddress [6];
811 #define CSL_CPSW_NUMALE_ENTRIES_MIN (64) 813 #define CSL_CPSW_NUMSTATBLOCKS (9) 1222 #define CSL_ALE_TABLE_POLICER_ENUM2REG(policerType) ((policerType) << 0x1) 1227 #define CSL_CPSW_ALE_POLICER_PORT_VALID (1 << 0u) 1230 #define CSL_CPSW_ALE_POLICER_PRI_VALID (1 << 1u) 1233 #define CSL_CPSW_ALE_POLICER_OUI_VALID (1 << 2u) 1236 #define CSL_CPSW_ALE_POLICER_DST_MAC_VALID (1 << 3u) 1239 #define CSL_CPSW_ALE_POLICER_SRC_MAC_VALID (1 << 4u) 1242 #define CSL_CPSW_ALE_POLICER_OVLAN_VALID (1 << 5u) 1245 #define CSL_CPSW_ALE_POLICER_VLAN_VALID (1 << 6u) 1248 #define CSL_CPSW_ALE_POLICER_ETHERTYPE_VALID (1 << 7u) 1251 #define CSL_CPSW_ALE_POLICER_SRC_IP_VALID ( 1 << 8u) 1254 #define CSL_CPSW_ALE_POLICER_DST_IP_VALID (1 << 9u) 1258 #define CSL_CPSW_ALE_POLICER_THREAD_VALID ( 1 << 10u) 1261 #define CSL_CPSW_ALE_POLICER_PIR_VALID ( 1 << 11u) 1264 #define CSL_CPSW_ALE_POLICER_CIR_VALID ( 1 << 12u) 1267 #define CSL_CPSW_ALE_POLICER_PORT_TRUNK_VALID (1 << 13u) 1270 #define CSL_CPSW_ALE_POLICER_EGRESSOP_VALID (1 << 14u) 1510 Uint32 TxPriPktCnt[8];
1513 Uint32 TxPriByteCnt[8];
1516 Uint32 TxPriDropPktCnt[8];
1519 Uint32 TxPriDropByteCnt[8];
1617 Uint8 dstMacAddress [6];
1619 Uint8 srcMacAddress [6];
2848 Uint32* pPortRxPriMap
2897 Uint32* pPortRxPriMap
3097 Uint32* pRxBlkCnt_e,
3098 Uint32* pRxBlkCnt_p,
3240 CSL_Xge_cpswRegs *hCpswRegs,
3242 Uint32* pPortTxPriMap
3303 CSL_Xge_cpswRegs *hCpswRegs,
3305 Uint32* pPortTxPriMap
3366 Uint32* pPortRxPriMap
3428 Uint32* pPortRxPriMap
3489 Uint32* pRxDscpPriMap
3554 Uint32* pRxDscpPriMap
4290 Uint32* pTsSeqIdOffset
4295 Uint32* pVlanLtypeInner,
4296 Uint32* pVlanLtypeOuter
4337 Uint32 pVlanLtypeInner,
4338 Uint32 pVlanLtypeOuter
4385 Uint32 tsSeqIdOffset
4428 Uint32* pTsVlanLtype1,
4429 Uint32* pTsVlanLtype2
4474 Uint32 tsVlanLtype1,
6079 (CSL_AleRegs *hCpswAleRegs,
6357 (CSL_AleRegs *hCpswAleRegs,
6398 (CSL_AleRegs *hCpswAleRegs,
6399 Uint32* pNumPolicers,
6484 (CSL_AleRegs *hCpswAleRegs,
6485 Uint32 alePrescaleVal
6531 (CSL_AleRegs *hCpswAleRegs,
6532 Uint32* pAgingPrescale,
6533 Uint32* pAgingPeriod
6582 (CSL_AleRegs *hCpswAleRegs,
6583 Uint32 agingPrescale,
6630 (CSL_AleRegs *hCpswAleRegs,
6631 Uint32* pUnVlanMemList,
6632 Uint32* pUnMcastFloodMask,
6633 Uint32* pUnRegMcastFloodMask,
6634 Uint32* pUnForceUntagEgress
6685 (CSL_AleRegs *hCpswAleRegs,
6686 Uint32 unVlanMemList,
6687 Uint32 unMcastFloodMask,
6688 Uint32 unRegMcastFloodMask,
6689 Uint32 unForceUntagEgress
6733 (CSL_AleRegs *hCpswAleRegs,
6781 (CSL_AleRegs *hCpswAleRegs,
6827 CSL_AleRegs *hCpswAleRegs,
6828 Uint32 maskMuxIndex,
6829 Uint32* vlanMaskMuxPtr
6878 CSL_AleRegs *hCpswAleRegs,
6879 Uint32 maskMuxIndex,
6880 Uint32 vlanMaskMuxVal
6935 (CSL_AleRegs *hCpswAleRegs,
6937 Uint32* pAleInfoWd0,
6938 Uint32* pAleInfoWd1,
6996 (CSL_AleRegs *hCpswAleRegs,
8506 (CSL_AleRegs *hCpswAleRegs,
8561 (CSL_AleRegs *hCpswAleRegs,
8618 (CSL_AleRegs *hCpswAleRegs,
8626 CSL_AleRegs *hCpswAleRegs,
8639 CSL_AleRegs *hCpswAleRegs,
8652 CSL_AleRegs *hCpswAleRegs,
8674 Uint32 mirrorMatchIndex);
8869 (CSL_AleRegs *hCpswAleRegs,
8940 (CSL_AleRegs *hCpswAleRegs,
8989 CSL_AleRegs *hCpswAleRegs,
8990 Uint32 aleUnknwnVlanMemberVal
9032 CSL_AleRegs *hCpswAleRegs,
9033 Uint32 aleUnknwnVlanUntagVal
9056 CSL_AleRegs *hCpswAleRegs,
9057 Uint32 aleUnknwnVlanUnregMcastVal
9063 CSL_AleRegs *hCpswAleRegs,
9064 Uint32 aleUnknwnVlanRegMcastVal
9087 Uint32 lpbkEnablePortMask);
9099 void CSL_CPSW_setPriCirEir(CSL_Xge_cpswRegs *hCpswRegs,Uint32 portNo, Uint32 pri, Uint32 cir, Uint32 eir);
9102 void CSL_CPSW_getPriCirEir(CSL_Xge_cpswRegs *hCpswRegs,Uint32 portNo, Uint32 pri, Uint32 *cir, Uint32 *eir);
CSL_CPSW_ALE_RAMDEPTH_E CSL_CPSW_getAleStatusRamDepth(CSL_AleRegs *hCpswAleRegs)
Uint32 tsVlanLType2
Definition: csl_cpsw.h:1029
Holds CPSW EEE (Energy Efficient Ethernet) Per-Port Configuration.
Definition: csl_cpsw.h:1100
Uint32 rtlVer
Definition: csl_cpsw.h:131
void CSL_CPSW_getAleStatusReg(CSL_AleRegs *hCpswAleRegs, Uint32 *pNumPolicers, Uint32 *pNumEntries)
void CSL_CPSW_getPortTxPriMapReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pPortTxPriMap)
Uint32 p3PassPriTag
Definition: csl_cpsw.h:161
Uint32 touched
Definition: csl_cpsw.h:696
Holds CPSW EEE (Energy Efficient Ethernet) Global Configuration.
Definition: csl_cpsw.h:1087
uint16_t index
Definition: tisci_rm_proxy.h:153
Uint32 p0TxPriActivePri6
Definition: csl_cpsw.h:356
void CSL_CPSW_mapMacAddr2TableWord(uint32_t *word0, uint32_t *word1, uint8_t *macAddr, CSL_CPSW_ALETABLE_TYPE aleType)
CSL_CPSW_ALE_AGT_PRESCALE_E
Defines ALE Aging Timer Prescale.
Definition: csl_cpsw.h:840
Definition: csl_cpsw.h:588
Uint32 p0TxPriActivePri1
Definition: csl_cpsw.h:321
Uint32 rxGapEnPri2
Definition: csl_cpsw.h:292
void CSL_CPSW_setCpswTxGlobalBufThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal)
void CSL_CPSW_setTxDstThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri, Uint32 setVal)
void CSL_CPSW_disableSoftIdle(CSL_Xge_cpswRegs *hCpswRegs)
Uint32 AleUnKnUni
Definition: csl_cpsw.h:1483
Uint32 p0HostBlksPri2
Definition: csl_cpsw.h:396
Uint32 tsTxAnnexDEnable
Definition: csl_cpsw.h:901
void CSL_CPSW_setAleCtrl2MalformedFrameConfig(CSL_AleRegs *hCpswAleRegs, CSL_CPSW_ALE_CTRL2_MALFORMEDFRAME_CONFIG *badFrmCfg)
Uint32 RxCRCErrors
Definition: csl_cpsw.h:1375
Uint32 pri
Definition: csl_cpsw.h:1284
void CSL_CPSW_getCpswVersionInfo(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_VERSION *pVersionInfo)
Holds CPSW priority type register contents.
Definition: csl_cpsw.h:1572
Definition: csl_cpsw.h:843
Definition: csl_cpsw.h:552
Definition: csl_cpsw.h:577
Uint32 p0FlowEnable
Definition: csl_cpsw.h:414
Uint32 RxIpgError
Definition: csl_cpsw.h:1432
Uint32 p6FlowEnable
Definition: csl_cpsw.h:432
bool ipPktFltEnableDefNoFrag
Definition: csl_cpsw.h:1214
void CSL_CPSW_setCppiTxGlobalBufThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal)
Definition: csl_cpsw.h:1538
CSL_CPSW_ALE_POLICER_CONTROL_YELLOWTHRESH yellowDropThresh
Definition: csl_cpsw.h:1544
Uint32 dstMacIdx
Definition: csl_cpsw.h:1290
Uint32 tsRxAnnexFEnable
Definition: csl_cpsw.h:892
Definition: csl_cpsw.h:1176
void CSL_CPSW_setAleControlReg(CSL_AleRegs *hCpswAleRegs, Uint32 aleCtrlVal)
Uint32 tsTxVlanLType2Enable
Definition: csl_cpsw.h:960
Uint32 Frame1024tUp
Definition: csl_cpsw.h:1456
void CSL_CPSW_enableAleOUIDenyMode(CSL_AleRegs *hCpswAleRegs)
void CSL_CPSW_enableAleMacAuthMode(CSL_AleRegs *hCpswAleRegs)
Definition: csl_cpsw.h:477
Uint32 blockEnable
Definition: csl_cpsw.h:721
Uint32 port6PriorityTypeEscalateEnable
Definition: csl_cpsw.h:1592
Holds CPSW control register contents.
Definition: csl_cpsw.h:141
void CSL_CPSW_getPortTimeSyncCntlReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_TSCNTL *pTimeSyncCntlCfg)
void CSL_CPSW_getVlanLTypeReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 *pVlanLtypeInner, Uint32 *pVlanLtypeOuter)
void CSL_CPSW_setTxPriFlowControl(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint8 pri)
Uint32 yellowDropEnable
Definition: csl_cpsw.h:1545
void CSL_CPSW_getAlePolicerEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_POLICER_ENTRY *pPolCfg)
void CSL_CPSW_getAlePortControlReg(CSL_AleRegs *hCpswAleRegs, Uint32 portNo, CSL_CPSW_ALE_PORTCONTROL *pPortControlInfo)
Uint8 CSL_CPSW_getTxPriFlowControl(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo)
void CSL_CPSW_setPriCirEir(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri, Uint32 cir, Uint32 eir)
Uint32 unRegMcastFloodMask
Definition: csl_cpsw.h:746
Uint32 bcastLimit
Definition: csl_cpsw.h:534
void CSL_CPSW_disablePortPassPriTag(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 tsRxAnnexEEnable
Definition: csl_cpsw.h:889
void CSL_CPSW_setAlePortState(CSL_AleRegs *hCpswAleRegs, Uint32 portNo, CSL_CPSW_ALE_PORTSTATE portState)
Uint32 AleUnKnMultiBytes
Definition: csl_cpsw.h:1492
Uint32 RxJabber
Definition: csl_cpsw.h:1384
Definition: csl_cpsw.h:587
Uint32 CSL_CPSW_getCppiRxPacketsPriority(CSL_Xge_cpswRegs *hCpswRegs, Uint32 priority)
Uint32 AleUnKnBCast
Definition: csl_cpsw.h:1495
Uint32 AleAddrEqDrop
Definition: csl_cpsw.h:1477
Uint32 pirIdleIncVal
Definition: csl_cpsw.h:1317
void CSL_CPSW_getCpswControlReg(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_CONTROL *pControlRegInfo)
Definition: csl_cpsw.h:1527
Uint32 tsRxAnnexEEnable
Definition: csl_cpsw.h:936
Uint32 p8FlowEnable
Definition: csl_cpsw.h:438
Definition: csl_cpsw.h:474
Uint32 RxAlignCodeErrors
Definition: csl_cpsw.h:1378
Uint32 CSL_CPSW_getAleIPv6HighEntryIndex(CSL_AleRegs *hCpswAleRegs, Uint32 entryIndex)
void CSL_CPSW_setPortRxPriMapReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pPortRxPriMap)
Uint32 CSL_CPSW_getCpswTxGlobalBufThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri)
Definition: csl_cpsw.h:578
void CSL_CPSW_setcppiTxBlksPri(CSL_Xge_cpswRegs *hCpswRegs, Uint8 pri, Uint32 blks)
void CSL_CPSW_getP0FifoStatus(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_CPPI_P0_FIFOSTATUS *pCppiFifoStats)
void CSL_CPSW_setVlanLTypeReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pVlanLtypeInner, Uint32 pVlanLtypeOuter)
CSL_CPSW_ALE_RAMDEPTH_E
Number of statistic blocks.
Definition: csl_cpsw.h:830
void CSL_CPSW_setAlePortControlTrunk(CSL_AleRegs *hCpswAleRegs, Uint32 portNo, bool trunkEnable, Uint32 trunkNum)
Int32 CSL_CPSW_setAleVlanMaskMuxEntryReg(CSL_AleRegs *hCpswAleRegs, Uint32 maskMuxIndex, Uint32 vlanMaskMuxVal)
CSL_CPSW_ALE_ENTRYTYPE CSL_CPSW_getALEEntryType(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALETABLE_TYPE aleType)
void CSL_CPSW_getCppiRxGapReg(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_CPPI_P0_RXGAP *pCppiRxGap)
Definition: csl_cpsw.h:1175
Uint32 ingressCheckFlag
Definition: csl_cpsw.h:754
bool trunkEnableDestIP
Definition: csl_cpsw.h:1203
void CSL_CPSW_setPortTimeSyncConfig(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_TSCONFIG *pTimeSyncConfig)
Uint32 CSL_CPSW_getTxHostBlksRem(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo)
Uint32 CSL_CPSW_getTxMaxLenPerPriority(CSL_Xge_cpswRegs *hCpswRegs, Uint32 priority)
Definition: csl_cpsw.h:1212
void CSL_CPSW_getPortRxPriMapReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pPortRxPriMap)
Uint32 blockEnable
Definition: csl_cpsw.h:671
Definition: csl_cpsw.h:465
CSL_CPSW_ALE_POLICER_ENTRYTYPE CSL_CPSW_getALEPolicerEntryType(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALETABLE_TYPE aleType)
CSL_CPSW_ALETABLE_TYPE
Defines ALE table types support.
Definition: csl_cpsw.h:464
Uint32 txLpiClkstopEnable
Definition: csl_cpsw.h:1108
void CSL_CPSW_setAleMcastAddrEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_MCASTADDR_ENTRY *pMcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 TxSingleColl
Definition: csl_cpsw.h:1420
Uint32 RxOversized
Definition: csl_cpsw.h:1381
Uint32 CSL_CPSW_getTxBlksPri(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint8 pri)
Holds CPPI_P0_Rx_Gap register contents. This is applicable only for 2 port switch.
Definition: csl_cpsw.h:268
Uint32 destForceUntaggedEgress
Definition: csl_cpsw.h:1633
Uint32 p1StatEnable
Definition: csl_cpsw.h:855
Uint8 CSL_CPSW_getCppiRxPriFlowControl(CSL_Xge_cpswRegs *hCpswRegs)
Uint32 p1PassPriTag
Definition: csl_cpsw.h:155
void CSL_CPSW_setPortTimeSyncSeqIdReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 tsLtype, Uint32 tsSeqIdOffset)
Holds the ALE Ethertype Table entry configuration.
Definition: csl_cpsw.h:777
Uint32 CSL_CPSW_getPortRxMaxLen(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 txFifoEmpty
Definition: csl_cpsw.h:1155
void CSL_CPSW_disableAleVID0Mode(CSL_AleRegs *hCpswAleRegs)
void CSL_CPSW_setVlanType(CSL_Xge_cpswRegs *hCpswRegs, Uint32 vlanType)
Holds Port Statistics Enable register contents.
Definition: csl_cpsw.h:850
Uint32 tsRxVlanLType1Enable
Definition: csl_cpsw.h:942
Uint32 enable
Definition: csl_cpsw.h:1089
Uint32 tsSeqIdOffset
Definition: csl_cpsw.h:1032
void CSL_CPSW_getAleUnkownVlanReg(CSL_AleRegs *hCpswAleRegs, Uint32 *pUnVlanMemList, Uint32 *pUnMcastFloodMask, Uint32 *pUnRegMcastFloodMask, Uint32 *pUnForceUntagEgress)
Uint32 ignMBits
Definition: csl_cpsw.h:648
void CSL_CPSW_setAleCtrl2IPPktFilterConfig(CSL_AleRegs *hCpswAleRegs, CSL_CPSW_ALE_CTRL2_IPPKTFLT_CONFIG *ipPktFltCfg)
Uint32 p2StatEnable
Definition: csl_cpsw.h:858
Holds CPSW Port Rx Rate Limit Configuration for CPPI Port Ingress Rate Limitaion Operation.
Definition: csl_cpsw.h:1067
Definition: csl_cpsw.h:1178
Holds the EMAC statistics.
Definition: csl_cpsw.h:1361
Uint32 rxGapEnPri0
Definition: csl_cpsw.h:298
Uint32 superEnable
Definition: csl_cpsw.h:642
Holds the ALE VLAN Unicast Address Table entry configuration.
Definition: csl_cpsw.h:704
Uint32 ts132Enable
Definition: csl_cpsw.h:1005
Uint32 policingEnable
Definition: csl_cpsw.h:1547
void CSL_CPSW_getAlePolicerHstatReg(CSL_AleRegs *hCpswAleRegs, CSL_CPSW_ALE_POLICER_HSTAT *policerHStatCfg)
void CSL_CPSW_setPortControlReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_PORT_CONTROL *pControlInfo)
Uint32 p3FlowEnable
Definition: csl_cpsw.h:423
Uint32 port0PriorityTypeEscalateEnable
Definition: csl_cpsw.h:1574
Uint32 portNumber
Definition: csl_cpsw.h:724
void CSL_CPSW_getAleTableEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, Uint32 *pAleInfoWd0, Uint32 *pAleInfoWd1, Uint32 *pAleInfoWd2)
Uint32 tsRxVlanLType2Enable
Definition: csl_cpsw.h:898
UInt32 numLSBIgnore
Definition: csl_cpsw.h:806
Uint32 polClrallYellowhit
Definition: csl_cpsw.h:1556
Uint32 ts130Enable
Definition: csl_cpsw.h:993
Uint32 enetRxThruRate
Definition: csl_cpsw.h:209
void CSL_CPSW_setPortTimeSyncVlanLTypeReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 tsVlanLtype1, Uint32 tsVlanLtype2)
Definition: csl_cpsw.h:1535
void CSL_CPSW_getPortMaxBlksReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pRxMaxBlks, Uint32 *pTxMaxBlks)
Uint32 tsTxVlanLType2Enable
Definition: csl_cpsw.h:913
void CSL_CPSW_getAleEthertypeEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_ETHERTYPE_ENTRY *pEthertypeCfg, CSL_CPSW_ALETABLE_TYPE aleType)
void CSL_CPSW_getPort0VlanReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 *pPortVID, Uint32 *pPortCFI, Uint32 *pPortPRI)
void CSL_CPSW_getAlePortState(CSL_AleRegs *hCpswAleRegs, Uint32 portNo, CSL_CPSW_ALE_PORTSTATE *pPortState)
void CSL_CPSW_setAleVlanEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_VLAN_ENTRY *pVlanCfg, CSL_CPSW_ALETABLE_TYPE aleType)
void CSL_CPSW_getAleVlanMcastAddrEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_VLANMCASTADDR_ENTRY *pVlanMcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 tsTxAnnexEEnable
Definition: csl_cpsw.h:904
Uint32 vlanId
Definition: csl_cpsw.h:636
void CSL_CPSW_setPortVlanReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 portVID, Uint32 portCFI, Uint32 portPRI)
Uint32 ignMBits
Definition: csl_cpsw.h:623
Uint32 CSL_CPSW_isSoftIdle(CSL_Xge_cpswRegs *hCpswRegs)
void CSL_CPSW_enableSoftIdle(CSL_Xge_cpswRegs *hCpswRegs)
void CSL_CPSW_setPort0VlanReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portVID, Uint32 portCFI, Uint32 portPRI)
Uint32 p4PassPriTag
Definition: csl_cpsw.h:164
Uint32 defThread
Definition: csl_cpsw.h:1197
void CSL_CPSW_disableAleVlanAware(CSL_AleRegs *hCpswAleRegs)
Definition: csl_cpsw.h:1533
Uint32 disallowIPFragmentation
Definition: csl_cpsw.h:763
Uint32 touched
Definition: csl_cpsw.h:664
void CSL_CPSW_setTxGlobalOutFlowThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal)
void CSL_CPSW_enableP0TxCastagnoliCRC(CSL_Xge_cpswRegs *hCpswRegs)
Uint32 NetOctets
Definition: csl_cpsw.h:1459
Uint32 CSL_CPSW_getIpv6IgnBitsMax(CSL_CPSW_ALETABLE_TYPE aleType)
Definition: csl_cpsw.h:1531
void CSL_CPSW_setAleUnkownVlanReg(CSL_AleRegs *hCpswAleRegs, Uint32 unVlanMemList, Uint32 unMcastFloodMask, Uint32 unRegMcastFloodMask, Uint32 unForceUntagEgress)
void CSL_CPSW_setCppiP0Control(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_CPPI_P0_CONTROL *pCppiP0ControlCfg)
void CSL_CPSW_setAlePrescaleReg(CSL_AleRegs *hCpswAleRegs, Uint32 alePrescaleVal)
Uint32 TxCollision
Definition: csl_cpsw.h:1417
Uint32 dscpIpv6Enable
Definition: csl_cpsw.h:1055
void CSL_CPSW_setCppiTxDstThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal)
Uint32 CSL_CPSW_getTxGlobalOutFlowThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri)
Uint32 srcIpIdx
Definition: csl_cpsw.h:1305
Uint32 p4StatEnable
Definition: csl_cpsw.h:864
void CSL_CPSW_setCppiSourceIdReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 *pTxSrcId)
void CSL_CPSW_disablePort0(CSL_Xge_cpswRegs *hCpswRegs)
Holds the ALE Multicast Address Table entry configuration.
Definition: csl_cpsw.h:609
void CSL_CPSW_getPortStats(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_STATS *pCpswStats)
void CSL_CPSW_getPTypeReg(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_PTYPE *pPtypeCfg)
Uint32 macOnlyEnable
Definition: csl_cpsw.h:513
Uint32 replaceVid
Definition: csl_cpsw.h:1642
Definition: csl_cpsw.h:1534
Definition: csl_cpsw.h:1174
void CSL_CPSW_getPriCirEir(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri, Uint32 *cir, Uint32 *eir)
Definition: csl_cpsw.h:576
Uint32 p4FlowEnable
Definition: csl_cpsw.h:426
Uint32 RxBCastFrames
Definition: csl_cpsw.h:1366
Uint32 CSL_CPSW_isVlanAwareEnabled(CSL_Xge_cpswRegs *hCpswRegs)
Uint32 tsDomainOffset
Definition: csl_cpsw.h:1035
Uint32 p5StatEnable
Definition: csl_cpsw.h:867
Uint32 port8PriorityTypeEscalateEnable
Definition: csl_cpsw.h:1598
void CSL_CPSW_setCppiRxPacketsPriority(CSL_Xge_cpswRegs *hCpswRegs, Uint32 priority, Uint32 rxPackets)
Uint32 CSL_CPSW_isAleRateLimitEnabled(CSL_AleRegs *hCpswAleRegs)
void CSL_CPSW_getPortControlReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_PORT_CONTROL *pControlInfo)
Uint32 TxLateColl
Definition: csl_cpsw.h:1429
Uint32 txLpiClkstopEnable
Definition: csl_cpsw.h:1052
Uint32 tsTxHostEnable
Definition: csl_cpsw.h:916
void CSL_CPSW_setAleUnicastAddrEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_UNICASTADDR_ENTRY *pUcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 CSL_CPSW_getCppiDstTxThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri)
Uint32 vlanAware
Definition: csl_cpsw.h:146
Uint32 ts129Enable
Definition: csl_cpsw.h:987
Uint32 id
Definition: csl_cpsw.h:457
Uint32 AlePolMatch
Definition: csl_cpsw.h:1501
Uint32 CSL_CPSW_isAleVID0ModeEnabled(CSL_AleRegs *hCpswAleRegs)
Holds CSL_CPSW_CPPI_P0_HOSTBLKSPRI register contents. This is not used for 2 port switch.
Definition: csl_cpsw.h:372
Uint32 CSL_CPSW_isPort0PassPriTagEnabled(CSL_Xge_cpswRegs *hCpswRegs)
Uint32 idle2lpi
Definition: csl_cpsw.h:1115
void CSL_CPSW_enablePortPassPriTag(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)
Uint32 polRedhit
Definition: csl_cpsw.h:1564
Definition: csl_cpsw.h:1532
void CSL_CPSW_setAlePolicerControlReg(CSL_AleRegs *hCpswAleRegs, CSL_CPSW_ALE_POLICER_CONTROL *policerCntrlCfg)
Holds Port Time Sync Control register contents.
Definition: csl_cpsw.h:884
bool ipPktFltEnableDefNxtHdrLimit
Definition: csl_cpsw.h:1213
Uint32 p0PassPriTag
Definition: csl_cpsw.h:152
Holds the ALE OUI Unicast Address Table entry configuration.
Definition: csl_cpsw.h:688
void CSL_CPSW_setAleCtrl2MirrorMatchIndex(CSL_AleRegs *hCpswAleRegs, Uint32 mirrorMatchIndex)
Uint32 RxDropBottom
Definition: csl_cpsw.h:1462
Uint32 CSL_CPSW_getTxDstThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri)
void CSL_CPSW_disableAle(CSL_AleRegs *hCpswAleRegs)
Uint32 mcastFwdState
Definition: csl_cpsw.h:614
void CSL_CPSW_setTxDstThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri, Uint32 setVal)
Uint32 RxFragments
Definition: csl_cpsw.h:1390
Uint32 p0TxPriActivePri0
Definition: csl_cpsw.h:314
Uint32 forceUntaggedEgress
Definition: csl_cpsw.h:751
void CSL_CPSW_setAleUnknwnVlanRegMcastReg(CSL_AleRegs *hCpswAleRegs, Uint32 aleUnknwnVlanRegMcastVal)
Definition: csl_cpsw.h:466
Holds the Enet_Pn_FIFO_Status register contents.
Definition: csl_cpsw.h:1651
Uint32 macOnlyCafEnable
Definition: csl_cpsw.h:528
Uint32 noLearnMask
Definition: csl_cpsw.h:757
void CSL_CPSW_disableAleTxRateLimit(CSL_AleRegs *hCpswAleRegs)
Uint32 CSL_CPSW_getAleIPv6HighEntryOffset(CSL_AleRegs *hCpswAleRegs)
Uint32 unRegMcastFloodIndex
Definition: csl_cpsw.h:741
Uint32 p0RxEccErrEn
Definition: csl_cpsw.h:236
Uint32 p0HostBlksPri3
Definition: csl_cpsw.h:392
Definition: csl_cpsw.h:601
CSL_CPSW_ALE_POLICER_CONTROL_POLICING_MATCH_MODE policeMatchMode
Definition: csl_cpsw.h:1543
void CSL_CPSW_getAleVlanUnicastAddrEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_VLANUNICASTADDR_ENTRY *pVlanUcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 CSL_CPSW_getTxGlobalOutFlowThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri)
void CSL_CPSW_getAleOutVlanEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_OUTER_VLAN_ENTRY *pOutVlanCfg, CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 mcastLimit
Definition: csl_cpsw.h:531
Uint32 tsLType2Enable
Definition: csl_cpsw.h:966
Uint32 p0StatEnable
Definition: csl_cpsw.h:852
Uint32 dscpIpv4Enable
Definition: csl_cpsw.h:1058
Uint32 tsRxAnnexDEnable
Definition: csl_cpsw.h:933
Holds the ALE IPv6 Address Table entry configuration.
Definition: csl_cpsw.h:802
void CSL_CPSW_setTxGlobalOutFlowThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal)
Uint32 AleVidDrop
Definition: csl_cpsw.h:1474
void CSL_CPSW_setPortMACAddress(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint8 *pMacAddress)
Holds the ALE Unicast Address Table entry configuration.
Definition: csl_cpsw.h:656
Uint32 CSL_CPSW_getGapThreshold(CSL_Xge_cpswRegs *hCpswRegs)
void CSL_CPSW_setPort0FlowIdOffset(CSL_Xge_cpswRegs *hCpswRegs, Uint32 flowIdOffset)
void CSL_CPSW_getEmulationControlReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 *pFree, Uint32 *pSoft)
Uint32 tsMsgTypeEnable
Definition: csl_cpsw.h:922
Holds flow control register contents.
Definition: csl_cpsw.h:412
Uint32 RxAleOverrunDrop
Definition: csl_cpsw.h:1396
Int32 CSL_CPSW_getAleVlanMaskMuxEntryReg(CSL_AleRegs *hCpswAleRegs, Uint32 maskMuxIndex, Uint32 *vlanMaskMuxPtr)
Uint32 majorVer
Definition: csl_cpsw.h:451
Uint32 tsRxAnnexDEnable
Definition: csl_cpsw.h:886
Uint32 tsTxAnnexFEnable
Definition: csl_cpsw.h:907
void CSL_CPSW_setCppiTxGlobalBufThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal)
Uint32 RxOctets
Definition: csl_cpsw.h:1399
Definition: csl_cpsw.h:841
bool trunkEnableInnerVLAN
Definition: csl_cpsw.h:1205
void CSL_CPSW_getAleUnicastAddrEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_UNICASTADDR_ENTRY *pUcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType)
Definition: csl_cpsw.h:1525
Uint32 ageable
Definition: csl_cpsw.h:661
Definition: csl_cpsw.h:1552
CSL_CPSW_ALE_POLICER_CONTROL_POLICING_MATCH_MODE
Definition: csl_cpsw.h:1523
void CSL_CPSW_setTxDstBasedOutFlowAddValX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri, Uint32 addVal)
bool trunkEnableSrcIP
Definition: csl_cpsw.h:1204
void CSL_CPSW_clearAleTable(CSL_AleRegs *hCpswAleRegs)
Definition: csl_cpsw.h:600
Uint32 TxExcessiveColl
Definition: csl_cpsw.h:1426
Uint32 dropUntaggedEnable
Definition: csl_cpsw.h:489
Uint32 majorVer
Definition: csl_cpsw.h:128
void CSL_CPSW_setEmulationControlReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 free, Uint32 soft)
void CSL_CPSW_setAleUnknwnVlanMemberReg(CSL_AleRegs *hCpswAleRegs, Uint32 aleUnknwnVlanMemberVal)
CSL_CPSW_ALE_ENTRYTYPE
Defines ALE Table Entry types.
Definition: csl_cpsw.h:551
Uint32 tsMcastTypeEnable
Definition: csl_cpsw.h:1014
Uint32 ts131Enable
Definition: csl_cpsw.h:999
Uint32 tsTxHostEnable
Definition: csl_cpsw.h:963
Uint32 limitIPNxtHdr
Definition: csl_cpsw.h:760
CSL_CPSW_ALE_PORTSTATE
Defines ALE port states.
Definition: csl_cpsw.h:473
void CSL_CPSW_getAlePolicerGlobConfig(CSL_AleRegs *hCpswAleRegs, CSL_CPSW_ALE_POLICER_GLOB_CONFIG *pGlobConfig)
Uint32 CSL_CPSW_isPort1PassPriTagEnabled(CSL_Xge_cpswRegs *hCpswRegs)
Uint32 CSL_CPSW_isAleUVLANNoLearnEnabled(CSL_AleRegs *hCpswAleRegs)
void CSL_CPSW_setAleEthertypeEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_ETHERTYPE_ENTRY *pEthertypeCfg, CSL_CPSW_ALETABLE_TYPE aleType)
void CSL_CPSW_getP0HostBlksPri(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_CPPI_P0_HOSTBLKSPRI *pCppiHostBlksPri)
Uint32 tsRxVlanLType2Enable
Definition: csl_cpsw.h:945
Uint32 tsTxVlanLType1Enable
Definition: csl_cpsw.h:957
Holds the ALE VLAN/Multicast Address Table entry configuration.
Definition: csl_cpsw.h:631
Definition: csl_cpsw.h:553
Uint32 CSL_CPSW_isAleMacAuthModeEnabled(CSL_AleRegs *hCpswAleRegs)
Uint32 RxDropTop
Definition: csl_cpsw.h:1468
Uint32 CSL_CPSW_getTxStartWords(CSL_Xge_cpswRegs *hCpswRegs)
void CSL_CPSW_setPortRxMaxLen(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 rxMaxLen)
void CSL_CPSW_clearAleEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index)
Uint32 vidIngressCheckEnable
Definition: csl_cpsw.h:492
void CSL_CPSW_getAleVlanEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_VLAN_ENTRY *pVlanCfg, CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 tsUniEnable
Definition: csl_cpsw.h:975
void CSL_CPSW_getEEEPortConfig(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_EEE_PORT_CONFIG *pPortConfig)
Uint32 p1FlowEnable
Definition: csl_cpsw.h:417
Uint32 port2PriorityTypeEscalateEnable
Definition: csl_cpsw.h:1580
Uint32 CSL_CPSW_getCppiTxGlobalBufThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri)
Definition: csl_cpsw.h:1172
void CSL_CPSW_disableAleUVLANNoLearn(CSL_AleRegs *hCpswAleRegs)
Holds the ALE IPv4 Address Table entry configuration.
Definition: csl_cpsw.h:789
Uint32 rxGapEnPri3
Definition: csl_cpsw.h:289
Uint32 polClrselAll
Definition: csl_cpsw.h:1557
void CSL_CPSW_getAleVersionInfo(CSL_AleRegs *hCpswAleRegs, CSL_CPSW_ALE_VERSION *pVersionInfo)
Uint32 rxFifoEmpty
Definition: csl_cpsw.h:1152
Uint32 escPriLoadVal
Definition: csl_cpsw.h:1608
Uint32 ouiIdx
Definition: csl_cpsw.h:1287
void CSL_CPSW_setAleTableEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, Uint32 aleInfoWd0, Uint32 aleInfoWd1, Uint32 aleInfoWd2)
Uint32 txPriActive
Definition: csl_cpsw.h:1683
Uint32 rxGapCnt
Definition: csl_cpsw.h:274
Uint32 decrementTtl
Definition: csl_cpsw.h:1629
void CSL_CPSW_getPortTimeSyncConfig(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_TSCONFIG *pTimeSyncConfig)
void CSL_CPSW_setTxHostBlksRem(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 txBlksRem)
void CSL_CPSW_getAleStatusVlanMask(CSL_AleRegs *hCpswAleRegs, bool *vlanMsk08, bool *vlanMsk12)
Uint32 noSaUpdateEnable
Definition: csl_cpsw.h:498
Definition: csl_cpsw.h:575
Uint32 portMask
Definition: csl_cpsw.h:620
void CSL_CPSW_disableAleBypass(CSL_AleRegs *hCpswAleRegs)
Uint32 p6PassPriTag
Definition: csl_cpsw.h:170
Uint32 CSL_CPSW_getAleIPv6LowEntryIndex(CSL_AleRegs *hCpswAleRegs, Uint32 entryIndex)
Uint32 AleRateLimitDrop
Definition: csl_cpsw.h:1471
void CSL_CPSW_getAleAgingTimerReg(CSL_AleRegs *hCpswAleRegs, Uint32 *pAgingPrescale, Uint32 *pAgingPeriod)
Uint32 p0RxRemapDscpIpv4
Definition: csl_cpsw.h:228
Uint32 RxPauseFrames
Definition: csl_cpsw.h:1372
Uint32 TxMultiColl
Definition: csl_cpsw.h:1423
Uint32 CSL_CPSW_isAleEnabled(CSL_AleRegs *hCpswAleRegs)
Uint32 p5PassPriTag
Definition: csl_cpsw.h:167
Uint32 CSL_CPSW_isAleUUNIToHostEnabled(CSL_AleRegs *hCpswAleRegs)
Definition: csl_cpsw.h:832
void CSL_CPSW_setCppiRxPType(CSL_Xge_cpswRegs *hCpswRegs, Uint32 p0RxPtype)
Uint32 CSL_CPSW_getCppiRxPType(CSL_Xge_cpswRegs *hCpswRegs)
Uint32 p8StatEnable
Definition: csl_cpsw.h:876
Uint32 CSL_CPSW_getAlePrescaleReg(CSL_AleRegs *hCpswAleRegs)
Uint32 p7FlowEnable
Definition: csl_cpsw.h:435
Definition: csl_cpsw.h:833
CSL_CPSW_ALE_UCASTTYPE
Defines ALE Unicast types.
Definition: csl_cpsw.h:574
void CSL_CPSW_enablePort0PassPriTag(CSL_Xge_cpswRegs *hCpswRegs)
Definition: csl_cpsw.h:1526
void CSL_CPSW_getAleStatusNumPolicers(CSL_AleRegs *hCpswAleRegs, Uint32 *pNumPolicers)
Uint32 txLpi
Definition: csl_cpsw.h:1141
Uint32 id
Definition: csl_cpsw.h:134
Uint32 port7PriorityTypeEscalateEnable
Definition: csl_cpsw.h:1595
Uint32 p0TxPriActivePri5
Definition: csl_cpsw.h:349
Uint32 prescale
Definition: csl_cpsw.h:1092
Uint32 CSL_CPSW_getAleControlReg(CSL_AleRegs *hCpswAleRegs)
void CSL_CPSW_getEEEGlobConfig(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_EEE_GLOB_CONFIG *pGlobConfig)
void CSL_CPSW_enableVlanAware(CSL_Xge_cpswRegs *hCpswRegs)
Definition: csl_cpsw.h:555
Holds the Port intervlan configuration info.
Definition: csl_cpsw.h:1615
Uint32 p0HostBlksPri0
Definition: csl_cpsw.h:404
void CSL_CPSW_enableAleUUNIToHost(CSL_AleRegs *hCpswAleRegs)
void CSL_CPSW_setAleIPv4Entry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_IPv4_ENTRY *pIPv4Cfg, CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 tsLType2
Definition: csl_cpsw.h:1023
Uint32 Frame128t255
Definition: csl_cpsw.h:1447
Uint32 CSL_CPSW_getPort0RxMaxLen(CSL_Xge_cpswRegs *hCpswRegs)
Uint32 AleUnKnMulti
Definition: csl_cpsw.h:1489
CPSW_THRU_RATE register.
Definition: csl_cpsw.h:201
Definition: csl_cpsw.h:1536
Uint32 estBufAct
Definition: csl_cpsw.h:1657
void CSL_CPSW_setEEEPortConfig(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_EEE_PORT_CONFIG *pPortConfig)
Holds CPSW EEE (Energy Efficient Ethernet) Per-Port STATUS.
Definition: csl_cpsw.h:1133
void CSL_CPSW_getCppiSourceIdReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 *pTxSrcId)
Uint32 RxMCastFrames
Definition: csl_cpsw.h:1369
Uint32 Frame256t511
Definition: csl_cpsw.h:1450
Uint32 p0TxPriActivePri7
Definition: csl_cpsw.h:363
Uint32 p8PassPriTag
Definition: csl_cpsw.h:176
CSL_CPSW_ALE_PORTSTATE portState
Definition: csl_cpsw.h:486
Uint32 ethertype
Definition: csl_cpsw.h:779
Uint32 CSL_CPSW_getCppiTxBlksPri(CSL_Xge_cpswRegs *hCpswRegs, Uint8 pri)
void CSL_CPSW_enableAleVlanAware(CSL_AleRegs *hCpswAleRegs)
void CSL_CPSW_setPortStatsEnableReg(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_PORTSTAT *pPortStatsCfg)
void CSL_CPSW_setAlePolicerTestControlReg(CSL_AleRegs *hCpswAleRegs, CSL_CPSW_ALE_POLICER_TEST_CONTROL *policerTestCntrlCfg)
Uint32 macAuthDisable
Definition: csl_cpsw.h:519
void CSL_CPSW_setPort0RxMaxLen(CSL_Xge_cpswRegs *hCpswRegs, Uint32 rxMaxLen)
Uint32 p0RxRemapVlan
Definition: csl_cpsw.h:231
Definition: csl_cpsw.h:1537
void CSL_CPSW_getPort0RxPriMapReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 *pPortRxPriMap)
Uint32 p0Enable
Definition: csl_cpsw.h:149
Definition: csl_cpsw.h:597
void CSL_CPSW_enableAleVID0Mode(CSL_AleRegs *hCpswAleRegs)
void CSL_CPSW_setTxGlobalBufThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri, Uint32 setVal)
Uint32 fifoLb
Definition: csl_cpsw.h:143
void CSL_CPSW_disableAlePolicerThread(CSL_AleRegs *hCpswAleRegs, Uint32 index)
Uint32 TxOctets
Definition: csl_cpsw.h:1438
Holds Port Time Sync Configuration contents.
Definition: csl_cpsw.h:931
Uint32 TxBCastFrames
Definition: csl_cpsw.h:1405
CSL_CPSW_ALE_UPD_BW
Defines ALE Update Bandwidth Control Value: The upd_bw_ctrl field within ALE control register specifi...
Definition: csl_cpsw.h:1171
void CSL_CPSW_enableAleLearnNoVID(CSL_AleRegs *hCpswAleRegs)
Uint32 polHit
Definition: csl_cpsw.h:1563
Uint32 p0HostBlksPri4
Definition: csl_cpsw.h:388
Uint32 tsRxVlanLType1Enable
Definition: csl_cpsw.h:895
Uint32 ageable
Definition: csl_cpsw.h:693
Uint32 validBitmap
Definition: csl_cpsw.h:1278
Uint32 p0TxCrcRemove
Definition: csl_cpsw.h:179
Uint32 superEnable
Definition: csl_cpsw.h:617
Uint32 redDropEnable
Definition: csl_cpsw.h:1546
CSL_CPSW_ALE_ADDRTYPE
Defines ALE Address types.
Definition: csl_cpsw.h:585
Uint32 rxGapEnPri7
Definition: csl_cpsw.h:277
Uint32 egressTrunkIndex
Definition: csl_cpsw.h:1338
void CSL_CPSW_getAleIPv4Entry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_IPv4_ENTRY *pIPv4Cfg, CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 TxGoodFrames
Definition: csl_cpsw.h:1402
void CSL_CPSW_setCppiTxDstThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal)
void CSL_CPSW_setCpswControlReg(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_CONTROL *pControlRegInfo)
void CSL_CPSW_setCpswTxGlobalBufThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal)
Uint32 secureEnable
Definition: csl_cpsw.h:718
Uint32 port1PriorityTypeEscalateEnable
Definition: csl_cpsw.h:1577
void CSL_CPSW_setCppiPriCirEir(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 cir, Uint32 eir)
Uint32 cppiRxThruRate
Definition: csl_cpsw.h:216
Uint32 destPortMask
Definition: csl_cpsw.h:1349
void CSL_CPSW_disablePort0PassPriTag(CSL_Xge_cpswRegs *hCpswRegs)
Uint32 TxPauseFrames
Definition: csl_cpsw.h:1411
Uint32 polClrallRedhit
Definition: csl_cpsw.h:1555
void CSL_CPSW_getAleOUIAddrEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_OUIADDR_ENTRY *pOUIAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 CSL_CPSW_getTxDstBasedOutFlowAddValX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri)
Holds CPSW Port Control contents.
Definition: csl_cpsw.h:1044
void CSL_CPSW_disableVlanAware(CSL_Xge_cpswRegs *hCpswRegs)
Uint32 CSL_CPSW_extractVid(Uint32 word1, CSL_CPSW_ALETABLE_TYPE aleType)
void CSL_CPSW_getPortRxDscpMap(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pRxDscpPriMap)
Holds CPPI P0 Control register contents.
Definition: csl_cpsw.h:223
Uint32 touched
Definition: csl_cpsw.h:715
Uint32 vid
Definition: csl_cpsw.h:1644
Uint32 CSL_CPSW_getEthertypeMax(CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 txExpressMacAllow
Definition: csl_cpsw.h:1678
void CSL_CPSW_enableAle(CSL_AleRegs *hCpswAleRegs)
Uint8 CSL_CPSW_getRxPriFlowControl(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo)
Uint32 port3PriorityTypeEscalateEnable
Definition: csl_cpsw.h:1583
Uint32 estAddErr
Definition: csl_cpsw.h:1663
Uint32 RxAleDrop
Definition: csl_cpsw.h:1393
Uint32 TxMemProtectErr
Definition: csl_cpsw.h:1507
Uint32 Frame65t127
Definition: csl_cpsw.h:1444
Uint32 port5PriorityTypeEscalateEnable
Definition: csl_cpsw.h:1589
Uint32 p0DscpIpv6En
Definition: csl_cpsw.h:247
void CSL_CPSW_setAleUnknwnVlanUntagReg(CSL_AleRegs *hCpswAleRegs, Uint32 aleUnknwnVlanUntagVal)
Uint32 RxUndersized
Definition: csl_cpsw.h:1387
Uint32 portMask
Definition: csl_cpsw.h:645
Holds CPSW Policer Global Configuration.
Definition: csl_cpsw.h:1186
Uint32 TxDeferred
Definition: csl_cpsw.h:1414
Uint32 p0HostBlksPri7
Definition: csl_cpsw.h:376
Uint32 tsLType2Enable
Definition: csl_cpsw.h:919
bool trunkEnableDst
Definition: csl_cpsw.h:1208
void CSL_CPSW_getPortVlanReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pPortVID, Uint32 *pPortCFI, Uint32 *pPortPRI)
void CSL_CPSW_setTxMaxLenPerPriority(CSL_Xge_cpswRegs *hCpswRegs, Uint32 priority, Uint32 maxLen)
Uint32 replaceDaSa
Definition: csl_cpsw.h:1638
Uint32 ageable
Definition: csl_cpsw.h:712
Definition: csl_cpsw.h:475
Uint32 p0RxPad
Definition: csl_cpsw.h:187
void CSL_CPSW_enableAleUVLANNoLearn(CSL_AleRegs *hCpswAleRegs)
Uint32 CSL_CPSW_getCpswTxGlobalBufThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri)
Uint32 cirIdleIncVal
Definition: csl_cpsw.h:1323
Uint32 dropDualVlan
Definition: csl_cpsw.h:538
void CSL_CPSW_setPortTimeSyncCntlReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_TSCNTL *pTimeSyncCntlCfg)
Uint32 p7StatEnable
Definition: csl_cpsw.h:873
void CSL_CPSW_getStats(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_STATS *pCpswStats)
Uint32 tsRxAnnexFEnable
Definition: csl_cpsw.h:939
void CSL_CPSW_enableAleBypass(CSL_AleRegs *hCpswAleRegs)
Uint32 defThreadEnable
Definition: csl_cpsw.h:1194
Uint32 wait_idle2lpi
Definition: csl_cpsw.h:1135
Uint32 p0TxPriActivePri3
Definition: csl_cpsw.h:335
Uint32 p3StatEnable
Definition: csl_cpsw.h:861
Uint32 CSL_CPSW_isAleBypassEnabled(CSL_AleRegs *hCpswAleRegs)
void CSL_CPSW_getAleStatusNumAleEntries(CSL_AleRegs *hCpswAleRegs, Uint32 *pNumEntries)
void CSL_CPSW_setAleVlanMcastAddrEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_VLANMCASTADDR_ENTRY *pVlanMcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType)
void CSL_CPSW_setPortRxDscpMap(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pRxDscpPriMap)
void CSL_CPSW_setCppiRxGapReg(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_CPPI_P0_RXGAP *pCppiRxGap)
Uint32 ovlanIdx
Definition: csl_cpsw.h:1296
void CSL_CPSW_setAleAgingTimerReg(CSL_AleRegs *hCpswAleRegs, Uint32 agingPrescale, Uint32 agingPeriod)
Uint32 ethertypeIdx
Definition: csl_cpsw.h:1302
Uint32 p0DscpIpv4En
Definition: csl_cpsw.h:253
void CSL_CPSW_getCppiPriCirEir(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 *cir, Uint32 *eir)
void CSL_CPSW_getPortStatsEnableReg(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_PORTSTAT *pPortStatsCfg)
Holds the ALE submodule's version info.
Definition: csl_cpsw.h:446
void CSL_CPSW_getAlePolicerControlReg(CSL_AleRegs *hCpswAleRegs, CSL_CPSW_ALE_POLICER_CONTROL *policerCntrlCfg)
void CSL_CPSW_setPortMaxBlksReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 rxMaxBlks, Uint32 txMaxBlks)
Uint32 disableMacPortDefaultThread
Definition: csl_cpsw.h:1549
void CSL_CPSW_mapTableWord2MacAddr(uint32_t word0, uint32_t word1, uint8_t *macAddr, CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 p7PassPriTag
Definition: csl_cpsw.h:173
Uint32 polClrallHit
Definition: csl_cpsw.h:1554
Uint32 Frame512t1023
Definition: csl_cpsw.h:1453
Uint32 p5FlowEnable
Definition: csl_cpsw.h:429
Uint32 tsTxAnnexEEnable
Definition: csl_cpsw.h:951
void CSL_CPSW_EEEPortStatus(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_EEE_PORT_STATUS *pPortStatus)
Uint32 tsLType1
Definition: csl_cpsw.h:1020
Uint32 p0TxPriActivePri2
Definition: csl_cpsw.h:328
Uint32 p2PassPriTag
Definition: csl_cpsw.h:158
Uint32 CSL_CPSW_getCppiTxGlobalBufThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri)
Uint32 p0RxRemapDscpIpv6
Definition: csl_cpsw.h:225
Uint32 vlanId
Definition: csl_cpsw.h:709
void CSL_CPSW_getAleMcastAddrEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_MCASTADDR_ENTRY *pMcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType)
void CSL_CPSW_setAleVlanMaskMuxReg(CSL_AleRegs *hCpswAleRegs, Uint32 *vlanMaskMux)
void CSL_CPSW_startAleAgeOutNow(CSL_AleRegs *hCpswAleRegs)
Holds the ALE (Inner) VLAN Table entry configuration.
Definition: csl_cpsw.h:733
Uint32 p2FlowEnable
Definition: csl_cpsw.h:420
void CSL_CPSW_getPortTimeSyncSeqIdReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pTsLtype, Uint32 *pTsSeqIdOffset)
Uint32 tsTxVlanLType1Enable
Definition: csl_cpsw.h:910
CSL_CPSW_ALE_VLAN_ENTRY CSL_CPSW_ALE_OUTER_VLAN_ENTRY
Holds the ALE Outer VLAN Table entry configuration.
Definition: csl_cpsw.h:771
void CSL_CPSW_setCppiRxPriFlowControl(CSL_Xge_cpswRegs *hCpswRegs, Uint8 pri)
void CSL_CPSW_disableAleLearnNoVID(CSL_AleRegs *hCpswAleRegs)
Uint32 CSL_CPSW_getPort0FlowIdOffset(CSL_Xge_cpswRegs *hCpswRegs)
Holds the ALE Policer Table entry configuration.
Definition: csl_cpsw.h:1276
Uint32 egressOp
Definition: csl_cpsw.h:1329
Uint32 p0HostBlksPri5
Definition: csl_cpsw.h:384
Uint32 regMcastFloodIndex
Definition: csl_cpsw.h:744
Definition: csl_cpsw.h:599
void CSL_CPSW_disableAleMacAuthMode(CSL_AleRegs *hCpswAleRegs)
Uint32 p0HostBlksPri6
Definition: csl_cpsw.h:380
void CSL_CPSW_getCppiP0Control(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_CPPI_P0_CONTROL *pCppiP0ControlCfg)
Uint32 srcMacIdx
Definition: csl_cpsw.h:1293
Uint32 noLearnModeEnable
Definition: csl_cpsw.h:495
Uint32 ts320Enable
Definition: csl_cpsw.h:1011
bool trunkEnableSrc
Definition: csl_cpsw.h:1207
void CSL_CPSW_disableAleUUNIToHost(CSL_AleRegs *hCpswAleRegs)
Uint32 CSL_CPSW_getTxGlobalBufThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri)
void CSL_CPSW_getThruRateReg(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_THRURATE *pThruRateCfg)
Uint32 TxMCastFrames
Definition: csl_cpsw.h:1408
void CSL_CPSW_setTxGlobalBufThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri, Uint32 setVal)
Definition: csl_cpsw.h:1524
void CSL_CPSW_getAleIPv6Entry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_IPv6_ENTRY *pIPv6Cfg, CSL_CPSW_ALETABLE_TYPE aleType)
void CSL_CPSW_setPort0RxPriMapReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 *pPortRxPriMap)
void CSL_CPSW_disableP0TxCastagnoliCRC(CSL_Xge_cpswRegs *hCpswRegs)
Uint32 Frame64
Definition: csl_cpsw.h:1441
Uint32 vlanIdx
Definition: csl_cpsw.h:1299
Uint32 lpi2wake
Definition: csl_cpsw.h:1124
Definition: csl_cpsw.h:1179
Uint32 rxGapEnPri6
Definition: csl_cpsw.h:280
Uint32 minorVer
Definition: csl_cpsw.h:448
Uint32 CSL_CPSW_getTxGlobalBufThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri)
Uint32 AleUnKnBCastBytes
Definition: csl_cpsw.h:1498
Uint32 port
Definition: csl_cpsw.h:1281
Uint32 CSL_CPSW_isPort0Enabled(CSL_Xge_cpswRegs *hCpswRegs)
Uint32 trunkFlag
Definition: csl_cpsw.h:679
Definition: csl_cpsw.h:598
Uint32 p0TxEccErrEn
Definition: csl_cpsw.h:241
CSL_CPSW_ALE_ADDRTYPE CSL_CPSW_getALEAddressType(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 vlanId
Definition: csl_cpsw.h:735
Uint32 minorVer
Definition: csl_cpsw.h:125
Uint32 polYellowhit
Definition: csl_cpsw.h:1565
Uint32 CSL_CPSW_isAleTxRateLimitEnabled(CSL_AleRegs *hCpswAleRegs)
Uint32 trunkFlag
Definition: csl_cpsw.h:726
Uint32 estCntErr
Definition: csl_cpsw.h:1669
Uint32 enableTTLCheck
Definition: csl_cpsw.h:1344
void CSL_CPSW_setAleOUIAddrEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_OUIADDR_ENTRY *pOUIAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 CSL_CPSW_getAleUpdateBW(CSL_AleRegs *hCpswAleRegs)
UInt32 numLSBIgnore
Definition: csl_cpsw.h:793
Definition: csl_cpsw.h:842
Uint32 rtlVer
Definition: csl_cpsw.h:454
Definition: csl_cpsw.h:1201
Uint32 CSL_CPSW_isAleLearnNoVIDEnabled(CSL_AleRegs *hCpswAleRegs)
void CSL_CPSW_getPortTimeSyncVlanLTypeReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pTsVlanLtype1, Uint32 *pTsVlanLtype2)
Definition: csl_cpsw.h:1561
Uint32 rxLpi
Definition: csl_cpsw.h:1138
Uint32 rxGapEnPri5
Definition: csl_cpsw.h:283
Definition: csl_cpsw.h:1177
Uint32 p0RxChksumEn
Definition: csl_cpsw.h:259
Uint32 tsTxAnnexDEnable
Definition: csl_cpsw.h:948
Uint32 dstIpIdx
Definition: csl_cpsw.h:1308
Uint32 txWake
Definition: csl_cpsw.h:1145
Definition: csl_cpsw.h:554
Uint32 CSL_CPSW_isAleVlanAwareEnabled(CSL_AleRegs *hCpswAleRegs)
void CSL_CPSW_disableAleRateLimit(CSL_AleRegs *hCpswAleRegs)
void CSL_CPSW_getAleVlanMaskMuxReg(CSL_AleRegs *hCpswAleRegs, Uint32 *vlanMaskMux)
Uint32 p0TxPriActivePri4
Definition: csl_cpsw.h:342
Uint32 vlanMemList
Definition: csl_cpsw.h:738
void CSL_CPSW_getPortRawStats(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_STATS *pCpswStats)
Definition: csl_cpsw.h:1541
bool trunkEnablePri
Definition: csl_cpsw.h:1206
Uint32 eeeEnable
Definition: csl_cpsw.h:193
void CSL_CPSW_getPortBlockCountReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pRxBlkCnt_e, Uint32 *pRxBlkCnt_p, Uint32 *pTxBlkCnt)
void CSL_CPSW_setAlePortMirrorSouce(CSL_AleRegs *hCpswAleRegs, Uint32 portNo, bool enableMirror)
void CSL_CPSW_setAleCtrl2TrunkParams(CSL_AleRegs *hCpswAleRegs, CSL_CPSW_ALE_CTRL2_TRUNK_CONFIG *trunkCfg)
Uint32 p0HostBlksPri1
Definition: csl_cpsw.h:400
Uint32 numRLimChans
Definition: csl_cpsw.h:1073
void CSL_CPSW_setAleUpdateBW(CSL_AleRegs *hCpswAleRegs, Uint32 aleUpdBW)
CSL_CPSW_ALE_POLICER_CONTROL_YELLOWTHRESH
Definition: csl_cpsw.h:1530
void CSL_CPSW_setAlePolicerEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_POLICER_ENTRY *pPolCfg)
Uint32 rxGapEnPri1
Definition: csl_cpsw.h:295
void CSL_CPSW_setAleOutVlanEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_OUTER_VLAN_ENTRY *pOutVlanCfg, CSL_CPSW_ALETABLE_TYPE aleType)
void CSL_CPSW_enablePort0(CSL_Xge_cpswRegs *hCpswRegs)
Uint32 TxCarrierSLoss
Definition: csl_cpsw.h:1435
void CSL_CPSW_setAleVlanUnicastAddrEntry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_VLANUNICASTADDR_ENTRY *pVlanUcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 tsTxAnnexFEnable
Definition: csl_cpsw.h:954
void CSL_CPSW_setAleUnknwnVlanUnregMcastReg(CSL_AleRegs *hCpswAleRegs, Uint32 aleUnknwnVlanUnregMcastVal)
Uint32 ts107Enable
Definition: csl_cpsw.h:981
Definition: csl_cpsw.h:831
void CSL_CPSW_setPTypeReg(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_PTYPE *pPtypeCfg)
CSL_CPSW_ALE_POLICER_ENTRYTYPE
Defines ALE Policer Entry types.
Definition: csl_cpsw.h:596
Uint32 dropDoubleVlan
Definition: csl_cpsw.h:543
Definition: csl_cpsw.h:586
void CSL_CPSW_setAleOAMLpbkControl(CSL_AleRegs *hCpswAleRegs, Uint32 lpbkEnablePortMask)
void CSL_CPSW_setAlePolicerGlobConfig(CSL_AleRegs *hCpswAleRegs, CSL_CPSW_ALE_POLICER_GLOB_CONFIG *pGlobConfig)
Holds the ALE Port control register info.
Definition: csl_cpsw.h:484
void CSL_CPSW_getPortMACAddress(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint8 *pMacAddress)
void CSL_CPSW_setTxBlksPri(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint8 pri, Uint32 blks)
void CSL_CPSW_setRxPriFlowControl(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint8 pri)
void CSL_CPSW_setP0HostBlksPri(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_CPPI_P0_HOSTBLKSPRI *pCppiHostBlksPri)
void CSL_CPSW_setAleIPNxtHdrWhitelist(CSL_AleRegs *hCpswAleRegs, Uint8 ipNxtHdr0, Uint8 ipNxtHdr1, Uint8 ipNxtHdr2, Uint8 ipNxtHdr3)
void CSL_CPSW_setPortTxPriMapReg(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pPortTxPriMap)
Uint32 CSL_CPSW_getTxDstThresholdClrX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri)
Uint32 tsVlanLType1
Definition: csl_cpsw.h:1026
void CSL_CPSW_getRawStats(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_STATS *pCpswStats)
Uint32 trunkBase
Definition: csl_cpsw.h:1202
Holds CPPI_P0_FIFO_Status register contents. This is not applicable for 2 port switch.
Definition: csl_cpsw.h:307
Uint32 ts319Enable
Definition: csl_cpsw.h:1008
Uint32 thread
Definition: csl_cpsw.h:1311
Uint32 CSL_CPSW_isP0TxCastagnoliCRCEnabled(CSL_Xge_cpswRegs *hCpswRegs)
Uint32 CSL_CPSW_isAleAgeOutDone(CSL_AleRegs *hCpswAleRegs)
Uint32 tsTTLNonzeroEnable
Definition: csl_cpsw.h:1017
void CSL_CPSW_setEEEGlobConfig(CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_EEE_GLOB_CONFIG *pGlobConfig)
Uint32 enablePriorityOR
Definition: csl_cpsw.h:1548
Uint32 RxGoodFrames
Definition: csl_cpsw.h:1363
void CSL_CPSW_enableAleRateLimit(CSL_AleRegs *hCpswAleRegs)
void CSL_CPSW_setAleIPv6Entry(CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_IPv6_ENTRY *pIPv6Cfg, CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 txFifoHold
Definition: csl_cpsw.h:1149
Uint32 CSL_CPSW_getIpv4IgnBitsMax(CSL_CPSW_ALETABLE_TYPE aleType)
Uint32 tsMsgTypeEnable
Definition: csl_cpsw.h:969
Uint32 CSL_CPSW_isAleOUIDenyModeEnabled(CSL_AleRegs *hCpswAleRegs)
Uint32 regMcastFloodMask
Definition: csl_cpsw.h:749
Definition: csl_cpsw.h:1173
Uint32 mcastFwdState
Definition: csl_cpsw.h:639
void CSL_CPSW_setGapThreshold(CSL_Xge_cpswRegs *hCpswRegs, Uint32 gapThreshold)
Uint32 portNumber
Definition: csl_cpsw.h:674
Uint32 CSL_CPSW_getCppiTxDstThresholdSetX(CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri)
Uint32 polTestIdx
Definition: csl_cpsw.h:1558
void CSL_CPSW_disableAleOUIDenyMode(CSL_AleRegs *hCpswAleRegs)
Uint32 p6StatEnable
Definition: csl_cpsw.h:870
Uint32 port4PriorityTypeEscalateEnable
Definition: csl_cpsw.h:1586
Uint32 PortmaskFrop
Definition: csl_cpsw.h:1465
Definition: csl_cpsw.h:476
Uint32 rxGapEnPri4
Definition: csl_cpsw.h:286
Holds the Time sync submodule's version info.
Definition: csl_cpsw.h:123
Uint32 secureEnable
Definition: csl_cpsw.h:668
void CSL_CPSW_setAlePortControlReg(CSL_AleRegs *hCpswAleRegs, Uint32 portNo, CSL_CPSW_ALE_PORTCONTROL *pPortControlInfo)
void CSL_CPSW_enableAleTxRateLimit(CSL_AleRegs *hCpswAleRegs)
Uint32 p0RxPassCrcErr
Definition: csl_cpsw.h:190
Uint32 AleUnKnUniBytes
Definition: csl_cpsw.h:1486