PDK API Guide for AM64x
CSL_CPSW_RX_RATE_LIMIT_CONFIG Struct Reference

Detailed Description

Holds CPSW Port Rx Rate Limit Configuration for CPPI Port Ingress Rate Limitaion Operation.

Data Fields

Uint32 numRLimChans
 
Uint32 idleStep [8]
 
Uint32 sendStep [8]
 

Field Documentation

◆ numRLimChans

Uint32 CSL_CPSW_RX_RATE_LIMIT_CONFIG::numRLimChans

Number of Rate Limitaion Channels. Rate limited channels must be the highest priority channels. For example, if two rate limited channels are required then they must be channel with priority 7 and 6 respectively. The BW of rate limitation channel is calcualted as idleStep/(idleStep + sendStep)*Frequemcy*256 where frequency = the VBUSP_GCLK frequency (350 for 350Mhz)

◆ idleStep

Uint32 CSL_CPSW_RX_RATE_LIMIT_CONFIG::idleStep[8]

Rate Limitaion Idle Step Array

◆ sendStep

Uint32 CSL_CPSW_RX_RATE_LIMIT_CONFIG::sendStep[8]

Rate Limitaion Send Step Array