Introduction

Macros
#define	SDL_ECC_BUS_SAFETY_MSS_BUS_CFG (uint32_t)SDL_MSS_CTRL_U_BASE

#define	DWORD (0x20U)

#define	SDL_MSS_CTRL_R5SS0_CORE0_AHB_BASE (0x000000A0U)

#define	SDL_MSS_CTRL_R5SS1_CORE0_AHB_BASE (0x000000A4U)

#define	SDL_MSS_CTRL_R5SS0_CORE1_AHB_BASE (0x000000B0U)

#define	SDL_MSS_CTRL_R5SS1_CORE1_AHB_BASE (0x000000B4U)

#define	SDL_MSS_CTRL_R5SS0_CORE0_AHB_END (SDL_MSS_CTRL_R5SS0_CORE0_AHB_BASE + SDL_MSS_CTRL_R5SS0_CORE0_AHB_SIZE)

#define	SDL_MSS_CTRL_R5SS1_CORE0_AHB_END (SDL_MSS_CTRL_R5SS1_CORE0_AHB_BASE + SDL_MSS_CTRL_R5SS1_CORE0_AHB_SIZE)

#define	SDL_MSS_CTRL_R5SS0_CORE1_AHB_END (SDL_MSS_CTRL_R5SS0_CORE1_AHB_BASE + SDL_MSS_CTRL_R5SS0_CORE1_AHB_SIZE)

#define	SDL_MSS_CTRL_R5SS1_CORE1_AHB_END (SDL_MSS_CTRL_R5SS1_CORE1_AHB_BASE + SDL_MSS_CTRL_R5SS1_CORE1_AHB_SIZE)

#define	SDL_R5SS0_CORE0_TCMA_U_SIZE (0x000000020U)

#define	SDL_R5SS0_CORE0_TCMB_U_SIZE (0x000000020U)

#define	SDL_MSS_CR5A_TCM_U_BASE (SDL_R5SS0_CORE0_TCMA_U_BASE )

#define	SDL_MSS_CR5B_TCM_U_BASE (SDL_R5SS0_CORE0_TCMB_U_BASE )

#define	SDL_MSS_CR5A_TCM_U_END (SDL_R5SS0_CORE0_TCMA_U_BASE + SDL_R5SS0_CORE0_TCMA_U_SIZE)

#define	SDL_MSS_CR5B_TCM_U_END (SDL_R5SS0_CORE0_TCMB_U_BASE + SDL_R5SS0_CORE0_TCMB_U_SIZE)

#define	SDL_MBOX_SRAM_U_BASE_END (SDL_MBOX_SRAM_U_BASE + 100U)

#define	SDL_MMC0_U_BASE_END (SDL_MMC0_U_BASE + 0X1FFCU-DWORD)

#define	SDL_GPMC0_CFG_U_BASE_END (SDL_GPMC0_CFG_U_BASE + 0X3FCU-DWORD)

#define	SDL_CORE_VBUSP_START (0x50800000U)

#define	SDL_CORE_VBUSP_START_END (SDL_CORE_VBUSP_START + 0X1FFCU)

#define	SDL_PERI_VBUSP_START (0x50200000)

#define	SDL_PERI_VBUSP_START_END (SDL_PERI_VBUSP_START + 0X7FFFFCU)

#define	SDL_L2OCRAM_BANK0 (SDL_L2OCRAM_U_BASE)

#define	SDL_L2OCRAM_BANK0_END (SDL_L2OCRAM_U_BASE + 0x80000U)

#define	SDL_L2OCRAM_BANK1 (SDL_L2OCRAM_U_BASE + 0x80000U)

#define	SDL_L2OCRAM_BANK1_END (SDL_L2OCRAM_U_BASE + 0x100000U)

#define	SDL_L2OCRAM_BANK2 (SDL_L2OCRAM_U_BASE + 0x100000U)

#define	SDL_L2OCRAM_BANK2_END (SDL_L2OCRAM_U_BASE + 0x180000U)

#define	SDL_L2OCRAM_BANK3 (SDL_L2OCRAM_U_BASE + 0x180000U)

#define	SDL_L2OCRAM_BANK3_END (SDL_L2OCRAM_U_BASE + 0x200000U)

#define	SDL_MSS_QSPI_U_BASE (SDL_QSPI0_U_BASE)

#define	SDL_MSS_QSPI_U_SIZE (0x000001D8U)

#define	SDL_MSS_QSPI_U_END (SDL_MSS_QSPI_U_BASE + SDL_MSS_QSPI_U_SIZE)

#define	SDL_MSS_MCRC_U_BASE (SDL_MCRC0_U_BASE)

#define	SDL_MSS_MCRC_U_SIZE (0x000001E4U)

#define	SDL_MSS_MCRC_U_END (SDL_MSS_MCRC_U_BASE + SDL_MSS_MCRC_U_SIZE)

#define	SDL_MSS_STM_STIM_U_BASE (SDL_STM_STIM_U_BASE)

#define	SDL_MSS_STM_STIM_U_SIZE (0x00FFFFFFU)

#define	SDL_MSS_STM_STIM_U_END (SDL_MSS_STM_STIM_U_BASE + SDL_MSS_STM_STIM_U_SIZE)

#define	SDL_MSS_CR5A_AXI_RD_START (0x35000000U)

#define	SDL_MSS_CR5A_AXI_RD_END (0x350003FFU-8U)

#define	SDL_MSS_CR5A_AXI_WR_START (0x35000000U)

#define	SDL_MSS_CR5A_AXI_WR_END (0x350003FFU-8U)

#define	SDL_MSS_CR5A_AXI_S_START SDL_R5SS0_CORE0_TCMB_U_BASE

#define	SDL_MSS_CR5A_AXI_S_END (SDL_R5SS0_CORE0_TCMB_U_BASE + 0xFFFFU)

#define	SDL_MSS_CR5B_AXI_RD_START (0x35000000U)

#define	SDL_MSS_CR5B_AXI_RD_END (0x350003FFU-8U)

#define	SDL_MSS_CR5B_AXI_WR_START (0x35000000U)

#define	SDL_MSS_CR5B_AXI_WR_END (0x350003FFU-8U)

#define	SDL_MSS_CR5B_AXI_S_START SDL_R5SS1_CORE0_TCMB_U_BASE

#define	SDL_MSS_CR5B_AXI_S_END (SDL_R5SS1_CORE0_TCMB_U_BASE + 0xFFFFU)

#define	SDL_MSS_CR5C_AXI_RD_START (0x35000000U)

#define	SDL_MSS_CR5C_AXI_RD_END (0x350003FFU-8U)

#define	SDL_MSS_CR5C_AXI_WR_START (0x35000000U)

#define	SDL_MSS_CR5C_AXI_WR_END (0x350003FFU-8U)

#define	SDL_MSS_CR5C_AXI_S_START SDL_R5SS0_CORE1_TCMB_U_BASE

#define	SDL_MSS_CR5C_AXI_S_END (SDL_R5SS0_CORE1_TCMB_U_BASE + 0x7FFFU)

#define	SDL_MSS_CR5D_AXI_RD_START (0x35000000U)

#define	SDL_MSS_CR5D_AXI_RD_END (0x350003FFU-8U)

#define	SDL_MSS_CR5D_AXI_WR_START (0x35000000U)

#define	SDL_MSS_CR5D_AXI_WR_END (0x350003FFU-8U)

#define	SDL_MSS_CR5D_AXI_S_START SDL_R5SS1_CORE1_TCMB_U_BASE

#define	SDL_MSS_CR5D_AXI_S_END (SDL_R5SS1_CORE1_TCMB_U_BASE + 0x7FFFU)

#define	SDL_MSS_CTRL_TPCC_A0_WR_BASE (0x52A40000U)

#define	SDL_MSS_CTRL_TPCC_A0_WR_END (0x52A40400U-8U)

#define	SDL_MSS_CTRL_TPCC_A1_WR_BASE (0x52A60000U)

#define	SDL_MSS_CTRL_TPCC_A1_WR_END (0x52A60400U-8U)

#define	SDL_MSS_CTRL_TPCC_A0_RD_BASE (0x52A40000U)

#define	SDL_MSS_CTRL_TPCC_A0_RD_END (0x52A40400U-8U)

#define	SDL_MSS_CTRL_TPCC_A1_RD_BASE (0x52A60000U)

#define	SDL_MSS_CTRL_TPCC_A1_RD_END (0x52A60400U-8U)

#define	SDL_MSS_VBUSP_BASE (0x35000000U)

#define	SDL_MSS_VBUSP_BASE_END (0x350003FFU-8U)

#define	SDL_MSS_VBUSP_PERI_BASE (0x35000000U)

#define	SDL_MSS_VBUSP_PERI_BASE_END (0x350003FFU-8U)

#define	SDL_MSS_CPSW_BASE (0x52800000U)

#define	SDL_MSS_CPSW_BASE_END (0x52800400U-8U)

#define	SDL_QSPI_U_BASE (0x48200000U)

#define	SDL_QSPI_U_BASE_END (0x482001FFU-8U)

#define	SDL_MCRC_U_BASE (0x35000000U)

#define	SDL_MCRC_U_BASE_END (0x350003FFU-8U)

#define	SDL_STIM_U_BASE (0x53500000U)

#define	SDL_STIM_U_BASE_END (0x535001FFU-8U)

#define	SDL_SCRP0_U_BASE (0x48000000U)

#define	SDL_SCRP0_U_BASE_END (0x4803FFFFU-8U)

#define	SDL_SCRP1_U_BASE (0x48000000U)

#define	SDL_SCRP1_U_BASE_END (0x4803FFFFU-8U)

#define	SDL_ICSSM_PDSP0_U_BASE (0x48000000U)

#define	SDL_ICSSM_PDSP0_U_BASE_END (0x4803FFFFU-8U)

#define	SDL_ICSSM_PDSP1_U_BASE (0x48000000U)

#define	SDL_ICSSM_PDSP1_U_BASE_END (0x4803FFFFU-8U)

#define	SDL_ICSSM_S_BASE (0x48000000U)

#define	SDL_ICSSM_S_BASE_END (0x4803FFFFU-8U)

#define	SDL_DAP_U_BASE SDL_TOP_RCM_U_BASE

#define	SDL_DAP_U_BASE_END (SDL_TOP_RCM_U_BASE + (0x1FFFU-8U))

#define	SDL_ECC_BUS_SAFETY_MSS_READABLE_NODE 1U

#define	SDL_ECC_BUS_SAFETY_MSS_WRITABLE_NODE 0U

#define	SDL_MSS_CTRL_MSS_VBUSP_SAFETY_H_ERRAGG_SIZE 6U

#define	SDL_MSS_CTRL_MSS_VBUSM_SAFETY_ERRAGG0_SIZE 32U

#define	SDL_MSS_CTRL_MSS_VBUSM_SAFETY_ERRAGG1_SIZE 10U

#define	SDL_MSS_CTRL_MSS_VBUSP_VBUSM_ERRAGG0_SIZE

#define	SDL_ECC_BUS_SAFETY_MSS_NODE_READABLE_1_MASK 0x041030C0U

#define	SDL_ECC_BUS_SAFETY_MSS_NODE_READABLE_2_MASK 0x00000100U

#define	SDL_ECC_BUS_SAFETY_MSS_CR5A_AHB 0U

#define	SDL_ECC_BUS_SAFETY_MSS_CR5B_AHB 1U

#define	SDL_ECC_BUS_SAFETY_MSS_CR5C_AHB 2U

#define	SDL_ECC_BUS_SAFETY_MSS_CR5D_AHB 3U

#define	SDL_ECC_BUS_SAFETY_MSS_MAIN_VBUSP 4U

#define	SDL_ECC_BUS_SAFETY_MSS_PERI_VBUSP 5U

#define	SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_RD 6U

#define	SDL_ECC_BUS_SAFETY_MSS_CR5B_AXI_RD 7U

#define	SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_WR 8U

#define	SDL_ECC_BUS_SAFETY_MSS_CR5B_AXI_WR 9U

#define	SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_S 10U

#define	SDL_ECC_BUS_SAFETY_MSS_CR5B_AXI_S 11U

#define	SDL_ECC_BUS_SAFETY_MSS_CR5C_AXI_RD 12U

#define	SDL_ECC_BUS_SAFETY_MSS_CR5D_AXI_RD 13U

#define	SDL_ECC_BUS_SAFETY_MSS_CR5C_AXI_WR 14U

#define	SDL_ECC_BUS_SAFETY_MSS_CR5D_AXI_WR 15U

#define	SDL_ECC_BUS_SAFETY_MSS_CR5C_AXI_S 16U

#define	SDL_ECC_BUS_SAFETY_MSS_CR5D_AXI_S 17U

#define	SDL_ECC_BUS_SAFETY_DAP 18U

#define	SDL_ECC_BUS_SAFETY_HSM_M 19U

#define	SDL_ECC_BUS_SAFETY_MSS_CPSW 20U

#define	SDL_ECC_BUS_SAFETY_MSS_L2_A 21U

#define	SDL_ECC_BUS_SAFETY_MSS_L2_B 22U

#define	SDL_ECC_BUS_SAFETY_MSS_L2_C 23U

#define	SDL_ECC_BUS_SAFETY_MSS_L2_D 24U

#define	SDL_ECC_BUS_SAFETY_MSS_TPTC_A0_RD 25U

#define	SDL_ECC_BUS_SAFETY_MSS_TPTC_A1_RD 26U

#define	SDL_ECC_BUS_SAFETY_MSS_TPTC_A0_WR 27U

#define	SDL_ECC_BUS_SAFETY_MSS_TPTC_A1_WR 28U

#define	SDL_ECC_BUS_SAFETY_HSM_TPTC0_RD 29U

#define	SDL_ECC_BUS_SAFETY_HSM_TPTC0_WR 30U

#define	SDL_ECC_BUS_SAFETY_HSM_TPTC1_RD 31U

#define	SDL_ECC_BUS_SAFETY_HSM_TPTC1_WR 32U

#define	SDL_ECC_BUS_SAFETY_ICSSM_PDSP0 33U

#define	SDL_ECC_BUS_SAFETY_ICSSM_PDSP1 34U

#define	SDL_ECC_BUS_SAFETY_MSS_QSPI 35U

#define	SDL_ECC_BUS_SAFETY_MSS_MCRC 36U

#define	SDL_ECC_BUS_SAFETY_HSM_DTHE 37U

#define	SDL_ECC_BUS_SAFETY_MSS_SCRP0 38U

#define	SDL_ECC_BUS_SAFETY_MSS_SCRP1 39U

#define	SDL_ECC_BUS_SAFETY_HSM_S 40U

#define	SDL_ECC_BUS_SAFETY_ICSSM_S 41U

#define	SDL_ECC_BUS_SAFETY_MSS_MBOX 42U

#define	SDL_ECC_BUS_SAFETY_MSS_STM_STIM 43U

#define	SDL_ECC_BUS_SAFETY_MSS_MMC 44U

#define	SDL_ECC_BUS_SAFETY_MSS_GPMC 45U

#define	SDL_ECC_BUS_SAFETY_SEC_START_NODE (SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_RD)

#define	SDL_ECC_BUS_SAFETY_SEC_END_NODE (SDL_ECC_BUS_SAFETY_MSS_GPMC)

#define	SDL_ECC_BUS_SAFETY_DED_START_NODE (SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_RD)

#define	SDL_ECC_BUS_SAFETY_DED_END_NODE (SDL_ECC_BUS_SAFETY_MSS_GPMC)

Macro Definition Documentation

◆ SDL_ECC_BUS_SAFETY_MSS_BUS_CFG

#define SDL_ECC_BUS_SAFETY_MSS_BUS_CFG (uint32_t)SDL_MSS_CTRL_U_BASE

◆ DWORD

#define DWORD (0x20U)

◆ SDL_MSS_CTRL_R5SS0_CORE0_AHB_BASE

#define SDL_MSS_CTRL_R5SS0_CORE0_AHB_BASE (0x000000A0U)

◆ SDL_MSS_CTRL_R5SS1_CORE0_AHB_BASE

#define SDL_MSS_CTRL_R5SS1_CORE0_AHB_BASE (0x000000A4U)

◆ SDL_MSS_CTRL_R5SS0_CORE1_AHB_BASE

#define SDL_MSS_CTRL_R5SS0_CORE1_AHB_BASE (0x000000B0U)

◆ SDL_MSS_CTRL_R5SS1_CORE1_AHB_BASE

#define SDL_MSS_CTRL_R5SS1_CORE1_AHB_BASE (0x000000B4U)

◆ SDL_MSS_CTRL_R5SS0_CORE0_AHB_END

#define SDL_MSS_CTRL_R5SS0_CORE0_AHB_END (SDL_MSS_CTRL_R5SS0_CORE0_AHB_BASE + SDL_MSS_CTRL_R5SS0_CORE0_AHB_SIZE)

◆ SDL_MSS_CTRL_R5SS1_CORE0_AHB_END

#define SDL_MSS_CTRL_R5SS1_CORE0_AHB_END (SDL_MSS_CTRL_R5SS1_CORE0_AHB_BASE + SDL_MSS_CTRL_R5SS1_CORE0_AHB_SIZE)

◆ SDL_MSS_CTRL_R5SS0_CORE1_AHB_END

#define SDL_MSS_CTRL_R5SS0_CORE1_AHB_END (SDL_MSS_CTRL_R5SS0_CORE1_AHB_BASE + SDL_MSS_CTRL_R5SS0_CORE1_AHB_SIZE)

◆ SDL_MSS_CTRL_R5SS1_CORE1_AHB_END

#define SDL_MSS_CTRL_R5SS1_CORE1_AHB_END (SDL_MSS_CTRL_R5SS1_CORE1_AHB_BASE + SDL_MSS_CTRL_R5SS1_CORE1_AHB_SIZE)

◆ SDL_R5SS0_CORE0_TCMA_U_SIZE

#define SDL_R5SS0_CORE0_TCMA_U_SIZE (0x000000020U)

◆ SDL_R5SS0_CORE0_TCMB_U_SIZE

#define SDL_R5SS0_CORE0_TCMB_U_SIZE (0x000000020U)

◆ SDL_MSS_CR5A_TCM_U_BASE

#define SDL_MSS_CR5A_TCM_U_BASE (SDL_R5SS0_CORE0_TCMA_U_BASE )

◆ SDL_MSS_CR5B_TCM_U_BASE

#define SDL_MSS_CR5B_TCM_U_BASE (SDL_R5SS0_CORE0_TCMB_U_BASE )

◆ SDL_MSS_CR5A_TCM_U_END

#define SDL_MSS_CR5A_TCM_U_END (SDL_R5SS0_CORE0_TCMA_U_BASE + SDL_R5SS0_CORE0_TCMA_U_SIZE)

◆ SDL_MSS_CR5B_TCM_U_END

#define SDL_MSS_CR5B_TCM_U_END (SDL_R5SS0_CORE0_TCMB_U_BASE + SDL_R5SS0_CORE0_TCMB_U_SIZE)

◆ SDL_MBOX_SRAM_U_BASE_END

#define SDL_MBOX_SRAM_U_BASE_END (SDL_MBOX_SRAM_U_BASE + 100U)

◆ SDL_MMC0_U_BASE_END

#define SDL_MMC0_U_BASE_END (SDL_MMC0_U_BASE + 0X1FFCU-DWORD)

◆ SDL_GPMC0_CFG_U_BASE_END

#define SDL_GPMC0_CFG_U_BASE_END (SDL_GPMC0_CFG_U_BASE + 0X3FCU-DWORD)

◆ SDL_CORE_VBUSP_START

#define SDL_CORE_VBUSP_START (0x50800000U)

◆ SDL_CORE_VBUSP_START_END

#define SDL_CORE_VBUSP_START_END (SDL_CORE_VBUSP_START + 0X1FFCU)

◆ SDL_PERI_VBUSP_START

#define SDL_PERI_VBUSP_START (0x50200000)

◆ SDL_PERI_VBUSP_START_END

#define SDL_PERI_VBUSP_START_END (SDL_PERI_VBUSP_START + 0X7FFFFCU)

◆ SDL_L2OCRAM_BANK0

#define SDL_L2OCRAM_BANK0 (SDL_L2OCRAM_U_BASE)

◆ SDL_L2OCRAM_BANK0_END

#define SDL_L2OCRAM_BANK0_END (SDL_L2OCRAM_U_BASE + 0x80000U)

◆ SDL_L2OCRAM_BANK1

#define SDL_L2OCRAM_BANK1 (SDL_L2OCRAM_U_BASE + 0x80000U)

◆ SDL_L2OCRAM_BANK1_END

#define SDL_L2OCRAM_BANK1_END (SDL_L2OCRAM_U_BASE + 0x100000U)

◆ SDL_L2OCRAM_BANK2

#define SDL_L2OCRAM_BANK2 (SDL_L2OCRAM_U_BASE + 0x100000U)

◆ SDL_L2OCRAM_BANK2_END

#define SDL_L2OCRAM_BANK2_END (SDL_L2OCRAM_U_BASE + 0x180000U)

◆ SDL_L2OCRAM_BANK3

#define SDL_L2OCRAM_BANK3 (SDL_L2OCRAM_U_BASE + 0x180000U)

◆ SDL_L2OCRAM_BANK3_END

#define SDL_L2OCRAM_BANK3_END (SDL_L2OCRAM_U_BASE + 0x200000U)

◆ SDL_MSS_QSPI_U_BASE

#define SDL_MSS_QSPI_U_BASE (SDL_QSPI0_U_BASE)

◆ SDL_MSS_QSPI_U_SIZE

#define SDL_MSS_QSPI_U_SIZE (0x000001D8U)

◆ SDL_MSS_QSPI_U_END

#define SDL_MSS_QSPI_U_END (SDL_MSS_QSPI_U_BASE + SDL_MSS_QSPI_U_SIZE)

◆ SDL_MSS_MCRC_U_BASE

#define SDL_MSS_MCRC_U_BASE (SDL_MCRC0_U_BASE)

◆ SDL_MSS_MCRC_U_SIZE

#define SDL_MSS_MCRC_U_SIZE (0x000001E4U)

◆ SDL_MSS_MCRC_U_END

#define SDL_MSS_MCRC_U_END (SDL_MSS_MCRC_U_BASE + SDL_MSS_MCRC_U_SIZE)

◆ SDL_MSS_STM_STIM_U_BASE

#define SDL_MSS_STM_STIM_U_BASE (SDL_STM_STIM_U_BASE)

◆ SDL_MSS_STM_STIM_U_SIZE

#define SDL_MSS_STM_STIM_U_SIZE (0x00FFFFFFU)

◆ SDL_MSS_STM_STIM_U_END

#define SDL_MSS_STM_STIM_U_END (SDL_MSS_STM_STIM_U_BASE + SDL_MSS_STM_STIM_U_SIZE)

◆ SDL_MSS_CR5A_AXI_RD_START

#define SDL_MSS_CR5A_AXI_RD_START (0x35000000U)

◆ SDL_MSS_CR5A_AXI_RD_END

#define SDL_MSS_CR5A_AXI_RD_END (0x350003FFU-8U)

◆ SDL_MSS_CR5A_AXI_WR_START

#define SDL_MSS_CR5A_AXI_WR_START (0x35000000U)

◆ SDL_MSS_CR5A_AXI_WR_END

#define SDL_MSS_CR5A_AXI_WR_END (0x350003FFU-8U)

◆ SDL_MSS_CR5A_AXI_S_START

#define SDL_MSS_CR5A_AXI_S_START SDL_R5SS0_CORE0_TCMB_U_BASE

◆ SDL_MSS_CR5A_AXI_S_END

#define SDL_MSS_CR5A_AXI_S_END (SDL_R5SS0_CORE0_TCMB_U_BASE + 0xFFFFU)

◆ SDL_MSS_CR5B_AXI_RD_START

#define SDL_MSS_CR5B_AXI_RD_START (0x35000000U)

◆ SDL_MSS_CR5B_AXI_RD_END

#define SDL_MSS_CR5B_AXI_RD_END (0x350003FFU-8U)

◆ SDL_MSS_CR5B_AXI_WR_START

#define SDL_MSS_CR5B_AXI_WR_START (0x35000000U)

◆ SDL_MSS_CR5B_AXI_WR_END

#define SDL_MSS_CR5B_AXI_WR_END (0x350003FFU-8U)

◆ SDL_MSS_CR5B_AXI_S_START

#define SDL_MSS_CR5B_AXI_S_START SDL_R5SS1_CORE0_TCMB_U_BASE

◆ SDL_MSS_CR5B_AXI_S_END

#define SDL_MSS_CR5B_AXI_S_END (SDL_R5SS1_CORE0_TCMB_U_BASE + 0xFFFFU)

◆ SDL_MSS_CR5C_AXI_RD_START

#define SDL_MSS_CR5C_AXI_RD_START (0x35000000U)

◆ SDL_MSS_CR5C_AXI_RD_END

#define SDL_MSS_CR5C_AXI_RD_END (0x350003FFU-8U)

◆ SDL_MSS_CR5C_AXI_WR_START

#define SDL_MSS_CR5C_AXI_WR_START (0x35000000U)

◆ SDL_MSS_CR5C_AXI_WR_END

#define SDL_MSS_CR5C_AXI_WR_END (0x350003FFU-8U)

◆ SDL_MSS_CR5C_AXI_S_START

#define SDL_MSS_CR5C_AXI_S_START SDL_R5SS0_CORE1_TCMB_U_BASE

◆ SDL_MSS_CR5C_AXI_S_END

#define SDL_MSS_CR5C_AXI_S_END (SDL_R5SS0_CORE1_TCMB_U_BASE + 0x7FFFU)

◆ SDL_MSS_CR5D_AXI_RD_START

#define SDL_MSS_CR5D_AXI_RD_START (0x35000000U)

◆ SDL_MSS_CR5D_AXI_RD_END

#define SDL_MSS_CR5D_AXI_RD_END (0x350003FFU-8U)

◆ SDL_MSS_CR5D_AXI_WR_START

#define SDL_MSS_CR5D_AXI_WR_START (0x35000000U)

◆ SDL_MSS_CR5D_AXI_WR_END

#define SDL_MSS_CR5D_AXI_WR_END (0x350003FFU-8U)

◆ SDL_MSS_CR5D_AXI_S_START

#define SDL_MSS_CR5D_AXI_S_START SDL_R5SS1_CORE1_TCMB_U_BASE

◆ SDL_MSS_CR5D_AXI_S_END

#define SDL_MSS_CR5D_AXI_S_END (SDL_R5SS1_CORE1_TCMB_U_BASE + 0x7FFFU)

◆ SDL_MSS_CTRL_TPCC_A0_WR_BASE

#define SDL_MSS_CTRL_TPCC_A0_WR_BASE (0x52A40000U)

◆ SDL_MSS_CTRL_TPCC_A0_WR_END

#define SDL_MSS_CTRL_TPCC_A0_WR_END (0x52A40400U-8U)

◆ SDL_MSS_CTRL_TPCC_A1_WR_BASE

#define SDL_MSS_CTRL_TPCC_A1_WR_BASE (0x52A60000U)

◆ SDL_MSS_CTRL_TPCC_A1_WR_END

#define SDL_MSS_CTRL_TPCC_A1_WR_END (0x52A60400U-8U)

◆ SDL_MSS_CTRL_TPCC_A0_RD_BASE

#define SDL_MSS_CTRL_TPCC_A0_RD_BASE (0x52A40000U)

◆ SDL_MSS_CTRL_TPCC_A0_RD_END

#define SDL_MSS_CTRL_TPCC_A0_RD_END (0x52A40400U-8U)

◆ SDL_MSS_CTRL_TPCC_A1_RD_BASE

#define SDL_MSS_CTRL_TPCC_A1_RD_BASE (0x52A60000U)

◆ SDL_MSS_CTRL_TPCC_A1_RD_END

#define SDL_MSS_CTRL_TPCC_A1_RD_END (0x52A60400U-8U)

◆ SDL_MSS_VBUSP_BASE

#define SDL_MSS_VBUSP_BASE (0x35000000U)

◆ SDL_MSS_VBUSP_BASE_END

#define SDL_MSS_VBUSP_BASE_END (0x350003FFU-8U)

◆ SDL_MSS_VBUSP_PERI_BASE

#define SDL_MSS_VBUSP_PERI_BASE (0x35000000U)

◆ SDL_MSS_VBUSP_PERI_BASE_END

#define SDL_MSS_VBUSP_PERI_BASE_END (0x350003FFU-8U)

◆ SDL_MSS_CPSW_BASE

#define SDL_MSS_CPSW_BASE (0x52800000U)

◆ SDL_MSS_CPSW_BASE_END

#define SDL_MSS_CPSW_BASE_END (0x52800400U-8U)

◆ SDL_QSPI_U_BASE

#define SDL_QSPI_U_BASE (0x48200000U)

◆ SDL_QSPI_U_BASE_END

#define SDL_QSPI_U_BASE_END (0x482001FFU-8U)

◆ SDL_MCRC_U_BASE

#define SDL_MCRC_U_BASE (0x35000000U)

◆ SDL_MCRC_U_BASE_END

#define SDL_MCRC_U_BASE_END (0x350003FFU-8U)

◆ SDL_STIM_U_BASE

#define SDL_STIM_U_BASE (0x53500000U)

◆ SDL_STIM_U_BASE_END

#define SDL_STIM_U_BASE_END (0x535001FFU-8U)

◆ SDL_SCRP0_U_BASE

#define SDL_SCRP0_U_BASE (0x48000000U)

◆ SDL_SCRP0_U_BASE_END

#define SDL_SCRP0_U_BASE_END (0x4803FFFFU-8U)

◆ SDL_SCRP1_U_BASE

#define SDL_SCRP1_U_BASE (0x48000000U)

◆ SDL_SCRP1_U_BASE_END

#define SDL_SCRP1_U_BASE_END (0x4803FFFFU-8U)

◆ SDL_ICSSM_PDSP0_U_BASE

#define SDL_ICSSM_PDSP0_U_BASE (0x48000000U)

◆ SDL_ICSSM_PDSP0_U_BASE_END

#define SDL_ICSSM_PDSP0_U_BASE_END (0x4803FFFFU-8U)

◆ SDL_ICSSM_PDSP1_U_BASE

#define SDL_ICSSM_PDSP1_U_BASE (0x48000000U)

◆ SDL_ICSSM_PDSP1_U_BASE_END

#define SDL_ICSSM_PDSP1_U_BASE_END (0x4803FFFFU-8U)

◆ SDL_ICSSM_S_BASE

#define SDL_ICSSM_S_BASE (0x48000000U)

◆ SDL_ICSSM_S_BASE_END

#define SDL_ICSSM_S_BASE_END (0x4803FFFFU-8U)

◆ SDL_DAP_U_BASE

#define SDL_DAP_U_BASE SDL_TOP_RCM_U_BASE

◆ SDL_DAP_U_BASE_END

#define SDL_DAP_U_BASE_END (SDL_TOP_RCM_U_BASE + (0x1FFFU-8U))

◆ SDL_ECC_BUS_SAFETY_MSS_READABLE_NODE

#define SDL_ECC_BUS_SAFETY_MSS_READABLE_NODE 1U

◆ SDL_ECC_BUS_SAFETY_MSS_WRITABLE_NODE

#define SDL_ECC_BUS_SAFETY_MSS_WRITABLE_NODE 0U

◆ SDL_MSS_CTRL_MSS_VBUSP_SAFETY_H_ERRAGG_SIZE

#define SDL_MSS_CTRL_MSS_VBUSP_SAFETY_H_ERRAGG_SIZE 6U

◆ SDL_MSS_CTRL_MSS_VBUSM_SAFETY_ERRAGG0_SIZE

#define SDL_MSS_CTRL_MSS_VBUSM_SAFETY_ERRAGG0_SIZE 32U

◆ SDL_MSS_CTRL_MSS_VBUSM_SAFETY_ERRAGG1_SIZE

#define SDL_MSS_CTRL_MSS_VBUSM_SAFETY_ERRAGG1_SIZE 10U

◆ SDL_MSS_CTRL_MSS_VBUSP_VBUSM_ERRAGG0_SIZE

#define SDL_MSS_CTRL_MSS_VBUSP_VBUSM_ERRAGG0_SIZE

Value:

(SDL_MSS_CTRL_MSS_VBUSP_SAFETY_H_ERRAGG_SIZE + \

SDL_MSS_CTRL_MSS_VBUSM_SAFETY_ERRAGG0_SIZE)

◆ SDL_ECC_BUS_SAFETY_MSS_NODE_READABLE_1_MASK

#define SDL_ECC_BUS_SAFETY_MSS_NODE_READABLE_1_MASK 0x041030C0U

◆ SDL_ECC_BUS_SAFETY_MSS_NODE_READABLE_2_MASK

#define SDL_ECC_BUS_SAFETY_MSS_NODE_READABLE_2_MASK 0x00000100U

◆ SDL_ECC_BUS_SAFETY_MSS_CR5A_AHB

#define SDL_ECC_BUS_SAFETY_MSS_CR5A_AHB 0U

◆ SDL_ECC_BUS_SAFETY_MSS_CR5B_AHB

#define SDL_ECC_BUS_SAFETY_MSS_CR5B_AHB 1U

◆ SDL_ECC_BUS_SAFETY_MSS_CR5C_AHB

#define SDL_ECC_BUS_SAFETY_MSS_CR5C_AHB 2U

◆ SDL_ECC_BUS_SAFETY_MSS_CR5D_AHB

#define SDL_ECC_BUS_SAFETY_MSS_CR5D_AHB 3U

◆ SDL_ECC_BUS_SAFETY_MSS_MAIN_VBUSP

#define SDL_ECC_BUS_SAFETY_MSS_MAIN_VBUSP 4U

◆ SDL_ECC_BUS_SAFETY_MSS_PERI_VBUSP

#define SDL_ECC_BUS_SAFETY_MSS_PERI_VBUSP 5U

◆ SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_RD

#define SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_RD 6U

◆ SDL_ECC_BUS_SAFETY_MSS_CR5B_AXI_RD

#define SDL_ECC_BUS_SAFETY_MSS_CR5B_AXI_RD 7U

◆ SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_WR

#define SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_WR 8U

◆ SDL_ECC_BUS_SAFETY_MSS_CR5B_AXI_WR

#define SDL_ECC_BUS_SAFETY_MSS_CR5B_AXI_WR 9U

◆ SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_S

#define SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_S 10U

◆ SDL_ECC_BUS_SAFETY_MSS_CR5B_AXI_S

#define SDL_ECC_BUS_SAFETY_MSS_CR5B_AXI_S 11U

◆ SDL_ECC_BUS_SAFETY_MSS_CR5C_AXI_RD

#define SDL_ECC_BUS_SAFETY_MSS_CR5C_AXI_RD 12U

◆ SDL_ECC_BUS_SAFETY_MSS_CR5D_AXI_RD

#define SDL_ECC_BUS_SAFETY_MSS_CR5D_AXI_RD 13U

◆ SDL_ECC_BUS_SAFETY_MSS_CR5C_AXI_WR

#define SDL_ECC_BUS_SAFETY_MSS_CR5C_AXI_WR 14U

◆ SDL_ECC_BUS_SAFETY_MSS_CR5D_AXI_WR

#define SDL_ECC_BUS_SAFETY_MSS_CR5D_AXI_WR 15U

◆ SDL_ECC_BUS_SAFETY_MSS_CR5C_AXI_S

#define SDL_ECC_BUS_SAFETY_MSS_CR5C_AXI_S 16U

◆ SDL_ECC_BUS_SAFETY_MSS_CR5D_AXI_S

#define SDL_ECC_BUS_SAFETY_MSS_CR5D_AXI_S 17U

◆ SDL_ECC_BUS_SAFETY_DAP

#define SDL_ECC_BUS_SAFETY_DAP 18U

◆ SDL_ECC_BUS_SAFETY_HSM_M

#define SDL_ECC_BUS_SAFETY_HSM_M 19U

◆ SDL_ECC_BUS_SAFETY_MSS_CPSW

#define SDL_ECC_BUS_SAFETY_MSS_CPSW 20U

◆ SDL_ECC_BUS_SAFETY_MSS_L2_A

#define SDL_ECC_BUS_SAFETY_MSS_L2_A 21U

◆ SDL_ECC_BUS_SAFETY_MSS_L2_B

#define SDL_ECC_BUS_SAFETY_MSS_L2_B 22U

◆ SDL_ECC_BUS_SAFETY_MSS_L2_C

#define SDL_ECC_BUS_SAFETY_MSS_L2_C 23U

◆ SDL_ECC_BUS_SAFETY_MSS_L2_D

#define SDL_ECC_BUS_SAFETY_MSS_L2_D 24U

◆ SDL_ECC_BUS_SAFETY_MSS_TPTC_A0_RD

#define SDL_ECC_BUS_SAFETY_MSS_TPTC_A0_RD 25U

◆ SDL_ECC_BUS_SAFETY_MSS_TPTC_A1_RD

#define SDL_ECC_BUS_SAFETY_MSS_TPTC_A1_RD 26U

◆ SDL_ECC_BUS_SAFETY_MSS_TPTC_A0_WR

#define SDL_ECC_BUS_SAFETY_MSS_TPTC_A0_WR 27U

◆ SDL_ECC_BUS_SAFETY_MSS_TPTC_A1_WR

#define SDL_ECC_BUS_SAFETY_MSS_TPTC_A1_WR 28U

◆ SDL_ECC_BUS_SAFETY_HSM_TPTC0_RD

#define SDL_ECC_BUS_SAFETY_HSM_TPTC0_RD 29U

◆ SDL_ECC_BUS_SAFETY_HSM_TPTC0_WR

#define SDL_ECC_BUS_SAFETY_HSM_TPTC0_WR 30U

◆ SDL_ECC_BUS_SAFETY_HSM_TPTC1_RD

#define SDL_ECC_BUS_SAFETY_HSM_TPTC1_RD 31U

◆ SDL_ECC_BUS_SAFETY_HSM_TPTC1_WR

#define SDL_ECC_BUS_SAFETY_HSM_TPTC1_WR 32U

◆ SDL_ECC_BUS_SAFETY_ICSSM_PDSP0

#define SDL_ECC_BUS_SAFETY_ICSSM_PDSP0 33U

◆ SDL_ECC_BUS_SAFETY_ICSSM_PDSP1

#define SDL_ECC_BUS_SAFETY_ICSSM_PDSP1 34U

◆ SDL_ECC_BUS_SAFETY_MSS_QSPI

#define SDL_ECC_BUS_SAFETY_MSS_QSPI 35U

◆ SDL_ECC_BUS_SAFETY_MSS_MCRC

#define SDL_ECC_BUS_SAFETY_MSS_MCRC 36U

◆ SDL_ECC_BUS_SAFETY_HSM_DTHE

#define SDL_ECC_BUS_SAFETY_HSM_DTHE 37U

◆ SDL_ECC_BUS_SAFETY_MSS_SCRP0

#define SDL_ECC_BUS_SAFETY_MSS_SCRP0 38U

◆ SDL_ECC_BUS_SAFETY_MSS_SCRP1

#define SDL_ECC_BUS_SAFETY_MSS_SCRP1 39U

◆ SDL_ECC_BUS_SAFETY_HSM_S

#define SDL_ECC_BUS_SAFETY_HSM_S 40U

◆ SDL_ECC_BUS_SAFETY_ICSSM_S

#define SDL_ECC_BUS_SAFETY_ICSSM_S 41U

◆ SDL_ECC_BUS_SAFETY_MSS_MBOX

#define SDL_ECC_BUS_SAFETY_MSS_MBOX 42U

◆ SDL_ECC_BUS_SAFETY_MSS_STM_STIM

#define SDL_ECC_BUS_SAFETY_MSS_STM_STIM 43U

◆ SDL_ECC_BUS_SAFETY_MSS_MMC

#define SDL_ECC_BUS_SAFETY_MSS_MMC 44U

◆ SDL_ECC_BUS_SAFETY_MSS_GPMC

#define SDL_ECC_BUS_SAFETY_MSS_GPMC 45U

◆ SDL_ECC_BUS_SAFETY_SEC_START_NODE

#define SDL_ECC_BUS_SAFETY_SEC_START_NODE (SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_RD)

◆ SDL_ECC_BUS_SAFETY_SEC_END_NODE

#define SDL_ECC_BUS_SAFETY_SEC_END_NODE (SDL_ECC_BUS_SAFETY_MSS_GPMC)

◆ SDL_ECC_BUS_SAFETY_DED_START_NODE

#define SDL_ECC_BUS_SAFETY_DED_START_NODE (SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_RD)

◆ SDL_ECC_BUS_SAFETY_DED_END_NODE

#define SDL_ECC_BUS_SAFETY_DED_END_NODE (SDL_ECC_BUS_SAFETY_MSS_GPMC)