AM263x MCU+ SDK  11.00.00
sdl_ecc_soc.h
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1 /*
2  * SDL ECC
3  *
4  * Software Diagnostics Library module for ECC
5  *
6  * Copyright (c) Texas Instruments Incorporated 2022-2023
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  *
12  * Redistributions of source code must retain the above copyright
13  * notice, this list of conditions and the following disclaimer.
14  *
15  * Redistributions in binary form must reproduce the above copyright
16  * notice, this list of conditions and the following disclaimer in the
17  * documentation and/or other materials provided with the
18  * distribution.
19  *
20  * Neither the name of Texas Instruments Incorporated nor the names of
21  * its contributors may be used to endorse or promote products derived
22  * from this software without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35  *
36  */
37 
52  #ifndef INCLUDE_SDL_ECC_SOC_H_
53  #define INCLUDE_SDL_ECC_SOC_H_
54 
55  #include <stdint.h>
56  #include <sdl/sdl_ecc.h>
57  #include <sdl/ecc/sdl_ip_ecc.h>
58  #include <sdl/include/sdl_types.h>
59  #include <sdl/esm/soc/am263x/sdl_esm_core.h>
60  #include <sdl/ecc/sdl_ecc_priv.h>
61  #include <sdl/include/am263x/sdlr_soc_ecc_aggr.h>
62  #include <sdl/include/am263x/soc_config.h>
63  #include <sdl/include/am263x/sdlr_intr_esm0.h>
64  #include <sdl/include/am263x/sdlr_soc_baseaddress.h>
65  #include <sdl/include/am263x/sdlr_intr_r5fss0_core0.h>
66  #include <sdl/include/am263x/sdlr_intr_r5fss0_core1.h>
67  #include <sdl/include/am263x/sdlr_intr_r5fss1_core0.h>
68  #include <sdl/include/am263x/sdlr_intr_r5fss1_core1.h>
69  #include <sdl/include/am263x/sdlr_param_regs.h>
70 
71 #define SDL_ECC_WIDTH_UNDEFINED 0x1
72 
73 /* define Max memEntries for each aggregator (i.e. the number of RAM ID's with * Wrapper type) */
74 #define SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (7U)
75 #define SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (28U)
76 #define SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (28U)
77 #define SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (28U)
78 #define SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (28U)
79 #define SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (10U)
80 #define SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (5U)
81 #define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
82 #define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
83 #define SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
84 #define SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
85 #define SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (8U)
86 #define SDL_ECC_Base_Address_TOTAL_ENTRIES (12U)
87 
88 #define SDL_CPSW0_ECC_U_BASE (SDL_CPSW0_U_BASE + 0x3f000u)
89 
90 /* define parity control register addresses */
91 /* R5FSS0 */
92 #define SDL_R5FSS0_CORE0_TCM_ERR_STATUS (0x50D18104U)
93 #define SDL_R5FSS0_CORE0_TCM_ERR_STATUS_RAW (0x50D18108U)
94 #define SDL_R5SS0_TCM_ADDRPARITY_ERRFORCE (0x50D1813CU)
95 
96 #define SDL_R5FSS0_CORE1_TCM_ERR_STATUS (0x50D18114U)
97 #define SDL_R5FSS0_CORE1_TCM_ERR_STATUS_RAW (0x50D18118U)
98 /* R5FSS1 */
99 #define SDL_R5FSS1_CORE0_TCM_ERR_STATUS (0x50D18144U)
100 #define SDL_R5FSS1_CORE0_TCM_ERR_STATUS_RAW (0x50D18148U)
101 #define SDL_R5SS1_TCM_ADDRPARITY_ERRFORCE (0x50D1817CU)
102 
103 #define SDL_R5FSS1_CORE1_TCM_ERR_STATUS (0x50D18154U)
104 #define SDL_R5FSS1_CORE1_TCM_ERR_STATUS_RAW (0x50D18158U)
105 
106 /* TPCC */
107 #define SDL_R5FSS0_CORE0_TPCC0_PARITY_CTRL (0x50D18180U)
108 #define SDL_R5FSS0_CORE0_TPCC0_PARITY_STATUS (0x50D18184U)
109 
110 #define SDL_TPCC0_ERRAGG_STATUS (0x50D18004U)
111 #define SDL_TPCC0_ERRAGG_MASK (0x50D18000U)
112 /*param registers */
113 #define SDL_PARAM_REG_1 (SDL_PARAM_REG_SET0 + 0x20U)
114 #define SDL_PARAM_REG_2 (SDL_PARAM_REG_SET0 + 0x30U)
115 
119 static const SDL_MemConfig_t SDL_SOC_ECC_AGGR_MemEntries[SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
120 {
121  { SDL_SOC_ECC_AGGR_MSS_L2_SLV0_ECC_RAM_ID, 0x70000000u,
122  SDL_SOC_ECC_AGGR_MSS_L2_SLV0_ECC_RAM_SIZE, 8u,
123  SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
124  { SDL_SOC_ECC_AGGR_MSS_L2_SLV1_ECC_RAM_ID, 0x70080000u,
125  SDL_SOC_ECC_AGGR_MSS_L2_SLV1_ECC_RAM_SIZE, 8u,
126  SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
127  { SDL_SOC_ECC_AGGR_MSS_L2_SLV2_ECC_RAM_ID, 0x70100000u,
128  SDL_SOC_ECC_AGGR_MSS_L2_SLV2_ECC_RAM_SIZE, 8u,
129  SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
130  { SDL_SOC_ECC_AGGR_MSS_L2_SLV3_ECC_RAM_ID, 0x70180000u,
131  SDL_SOC_ECC_AGGR_MSS_L2_SLV3_ECC_RAM_SIZE, 8u,
132  SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
133  { SDL_SOC_ECC_AGGR_MAILBOX_ECC_RAM_ID, 0x72000000u,
134  SDL_SOC_ECC_AGGR_MAILBOX_ECC_RAM_SIZE, 8u,
135  SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
136  { SDL_SOC_ECC_AGGR_TPTC_A0_ECC_RAM_ID, 0u,
137  SDL_SOC_ECC_AGGR_TPTC_A0_ECC_RAM_SIZE, 8u,
138  SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
139  { SDL_SOC_ECC_AGGR_TPTC_A1_ECC_RAM_ID, 0u,
140  SDL_SOC_ECC_AGGR_TPTC_A1_ECC_RAM_SIZE, 8u,
141  SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
142 };
143 
148 static const SDL_MemConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
149 {
150  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID, 0u,
151  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_SIZE, 4u,
152  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
153  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID, 0u,
154  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_SIZE, 4u,
155  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
156  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID, 0u,
157  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_SIZE, 4u,
158  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
159  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID, 0u,
160  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_SIZE, 4u,
161  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
162  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID, 0u,
163  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_SIZE, 8u,
164  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_WIDTH, ((bool)false) },
165  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID, 0u,
166  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_SIZE, 8u,
167  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_WIDTH, ((bool)false) },
168  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID, 0u,
169  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_SIZE, 8u,
170  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_WIDTH, ((bool)false) },
171  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID, 0u,
172  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_SIZE, 8u,
173  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_WIDTH, ((bool)false) },
174  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID, 0u,
175  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_SIZE, 4u,
176  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
177  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID, 0u,
178  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_SIZE, 4u,
179  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
180  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID, 0u,
181  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_SIZE, 4u,
182  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
183  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID, 0u,
184  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_SIZE, 4u,
185  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
186  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID, 0u,
187  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_SIZE, 4u,
188  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
189  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID, 0u,
190  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_SIZE, 4u,
191  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_WIDTH, ((bool)false) },
192  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID, 0u,
193  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_SIZE, 4u,
194  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_WIDTH, ((bool)false) },
195  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID, 0u,
196  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_SIZE, 4u,
197  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_WIDTH, ((bool)false) },
198  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID, 0u,
199  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_SIZE, 4u,
200  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_WIDTH, ((bool)false) },
201  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID, 0u,
202  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_SIZE, 4u,
203  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_WIDTH, ((bool)false) },
204  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID, 0u,
205  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_SIZE, 4u,
206  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_WIDTH, ((bool)false) },
207  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID, 0u,
208  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_SIZE, 4u,
209  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_WIDTH, ((bool)false) },
210  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID, 0u,
211  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_SIZE, 4u,
212  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_WIDTH, ((bool)false) },
213  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID, 0x0u,
214  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_SIZE, 4u,
215  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ROW_WIDTH, ((bool)true) },
216  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID, 0x0u,
217  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_SIZE, 4u,
218  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ROW_WIDTH, ((bool)true) },
219  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID, 0x00080000u,
220  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_SIZE, 4u,
221  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ROW_WIDTH, ((bool)true) },
222  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID, 0x00080000u,
223  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_SIZE, 4u,
224  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ROW_WIDTH, ((bool)true) },
225  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID, 0x00080000u,
226  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_SIZE, 4u,
227  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ROW_WIDTH, ((bool)true) },
228  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID, 0x00080000u,
229  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_SIZE, 4u,
230  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ROW_WIDTH, ((bool)true) },
231  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID, 0x50f02000u,
232  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_SIZE, 4u,
233  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH, ((bool)true) },
234 };
235 
240 static const SDL_MemConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
241 {
242  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID, 0u,
243  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_SIZE, 4u,
244  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
245  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID, 0u,
246  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_SIZE, 4u,
247  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
248  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID, 0u,
249  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_SIZE, 4u,
250  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
251  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID, 0u,
252  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_SIZE, 4u,
253  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
254  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID, 0u,
255  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_SIZE, 8u,
256  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_ROW_WIDTH, ((bool)false) },
257  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID, 0u,
258  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_SIZE, 8u,
259  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_ROW_WIDTH, ((bool)false) },
260  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID, 0u,
261  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_SIZE, 8u,
262  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_ROW_WIDTH, ((bool)false) },
263  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID, 0u,
264  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_SIZE, 8u,
265  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_ROW_WIDTH, ((bool)false) },
266  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID, 0u,
267  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_SIZE, 4u,
268  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
269  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID, 0u,
270  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_SIZE, 4u,
271  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
272  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID, 0u,
273  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_SIZE, 4u,
274  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
275  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID, 0u,
276  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_SIZE, 4u,
277  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
278  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID, 0u,
279  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_SIZE, 4u,
280  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
281  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID, 0u,
282  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_SIZE, 4u,
283  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_ROW_WIDTH, ((bool)false) },
284  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID, 0u,
285  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_SIZE, 4u,
286  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_ROW_WIDTH, ((bool)false) },
287  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID, 0u,
288  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_SIZE, 4u,
289  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_ROW_WIDTH, ((bool)false) },
290  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID, 0u,
291  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_SIZE, 4u,
292  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_ROW_WIDTH, ((bool)false) },
293  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID, 0u,
294  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_SIZE, 4u,
295  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_ROW_WIDTH, ((bool)false) },
296  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID, 0u,
297  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_SIZE, 4u,
298  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_ROW_WIDTH, ((bool)false) },
299  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID, 0u,
300  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_SIZE, 4u,
301  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_ROW_WIDTH, ((bool)false) },
302  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID, 0u,
303  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_SIZE, 4u,
304  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_ROW_WIDTH, ((bool)false) },
305  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_ID, 0x00008000u,
306  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_SIZE, 4u,
307  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_ROW_WIDTH, ((bool)true) },
308  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_ID, 0x00008000u,
309  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_SIZE, 4u,
310  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_ROW_WIDTH, ((bool)true) },
311  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_ID, 0x00088000u,
312  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_SIZE, 4u,
313  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_ROW_WIDTH, ((bool)true) },
314  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_ID, 0x00088000u,
315  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_SIZE, 4u,
316  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_ROW_WIDTH, ((bool)true) },
317  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_ID, 0x00088000u,
318  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_SIZE, 4u,
319  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_ROW_WIDTH, ((bool)true) },
320  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_ID, 0x00088000u,
321  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_SIZE, 4u,
322  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_ROW_WIDTH, ((bool)true) },
323  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID, 0x50f02000u,
324  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_SIZE, 4u,
325  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ROW_WIDTH, ((bool)true) },
326 };
327 
332 static const SDL_MemConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_MemEntries[SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
333 {
334  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID, 0u,
335  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_SIZE, 4u,
336  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
337  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID, 0u,
338  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_SIZE, 4u,
339  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
340  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID, 0u,
341  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_SIZE, 4u,
342  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
343  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID, 0u,
344  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_SIZE, 4u,
345  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
346  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID, 0u,
347  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_SIZE, 8u,
348  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_WIDTH, ((bool)false) },
349  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID, 0u,
350  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_SIZE, 8u,
351  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_WIDTH, ((bool)false) },
352  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID, 0u,
353  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_SIZE, 8u,
354  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_WIDTH, ((bool)false) },
355  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID, 0u,
356  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_SIZE, 8u,
357  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_WIDTH, ((bool)false) },
358  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID, 0u,
359  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_SIZE, 4u,
360  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
361  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID, 0u,
362  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_SIZE, 4u,
363  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
364  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID, 0u,
365  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_SIZE, 4u,
366  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
367  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID, 0u,
368  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_SIZE, 4u,
369  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
370  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID, 0u,
371  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_SIZE, 4u,
372  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
373  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID, 0u,
374  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_SIZE, 4u,
375  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_WIDTH, ((bool)false) },
376  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID, 0u,
377  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_SIZE, 4u,
378  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_WIDTH, ((bool)false) },
379  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID, 0u,
380  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_SIZE, 4u,
381  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_WIDTH, ((bool)false) },
382  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID, 0u,
383  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_SIZE, 4u,
384  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_WIDTH, ((bool)false) },
385  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID, 0u,
386  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_SIZE, 4u,
387  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_WIDTH, ((bool)false) },
388  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID, 0u,
389  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_SIZE, 4u,
390  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_WIDTH, ((bool)false) },
391  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID, 0u,
392  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_SIZE, 4u,
393  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_WIDTH, ((bool)false) },
394  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID, 0u,
395  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_SIZE, 4u,
396  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_WIDTH, ((bool)false) },
397  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID, 0x0u,
398  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_SIZE, 4u,
399  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ROW_WIDTH, ((bool)true) },
400  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID, 0x0u,
401  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_SIZE, 4u,
402  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ROW_WIDTH, ((bool)true) },
403  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID, 0x00080000u,
404  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_SIZE, 4u,
405  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ROW_WIDTH, ((bool)true) },
406  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID, 0x00080000u,
407  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_SIZE, 4u,
408  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ROW_WIDTH, ((bool)true) },
409  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID, 0x00080000u,
410  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_SIZE, 4u,
411  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ROW_WIDTH, ((bool)true) },
412  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID, 0x00080000u,
413  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_SIZE, 4u,
414  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ROW_WIDTH, ((bool)true) },
415  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID, 0x50f02000u,
416  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_SIZE, 4u,
417  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH, ((bool)true) },
418 };
419 
424 static const SDL_MemConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_MemEntries[SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
425 {
426  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID, 0u,
427  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_SIZE, 4u,
428  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
429  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID, 0u,
430  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_SIZE, 4u,
431  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
432  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID, 0u,
433  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_SIZE, 4u,
434  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
435  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID, 0u,
436  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_SIZE, 4u,
437  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
438  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID, 0u,
439  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_SIZE, 8u,
440  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_ROW_WIDTH, ((bool)false) },
441  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID, 0u,
442  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_SIZE, 8u,
443  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_ROW_WIDTH, ((bool)false) },
444  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID, 0u,
445  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_SIZE, 8u,
446  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_ROW_WIDTH, ((bool)false) },
447  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID, 0u,
448  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_SIZE, 8u,
449  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_ROW_WIDTH, ((bool)false) },
450  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID, 0u,
451  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_SIZE, 4u,
452  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
453  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID, 0u,
454  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_SIZE, 4u,
455  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
456  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID, 0u,
457  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_SIZE, 4u,
458  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
459  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID, 0u,
460  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_SIZE, 4u,
461  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
462  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID, 0u,
463  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_SIZE, 4u,
464  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
465  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID, 0u,
466  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_SIZE, 4u,
467  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_ROW_WIDTH, ((bool)false) },
468  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID, 0u,
469  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_SIZE, 4u,
470  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_ROW_WIDTH, ((bool)false) },
471  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID, 0u,
472  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_SIZE, 4u,
473  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_ROW_WIDTH, ((bool)false) },
474  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID, 0u,
475  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_SIZE, 4u,
476  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_ROW_WIDTH, ((bool)false) },
477  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID, 0u,
478  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_SIZE, 4u,
479  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_ROW_WIDTH, ((bool)false) },
480  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID, 0u,
481  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_SIZE, 4u,
482  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_ROW_WIDTH, ((bool)false) },
483  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID, 0u,
484  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_SIZE, 4u,
485  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_ROW_WIDTH, ((bool)false) },
486  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID, 0u,
487  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_SIZE, 4u,
488  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_ROW_WIDTH, ((bool)false) },
489  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_ID, 0x00008000u,
490  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_SIZE, 4u,
491  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_ROW_WIDTH, ((bool)true) },
492  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_ID, 0x00008000u,
493  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_SIZE, 4u,
494  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_ROW_WIDTH, ((bool)true) },
495  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_ID, 0x00088000u,
496  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_SIZE, 4u,
497  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_ROW_WIDTH, ((bool)true) },
498  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_ID, 0x00088000u,
499  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_SIZE, 4u,
500  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_ROW_WIDTH, ((bool)true) },
501  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_ID, 0x00088000u,
502  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_SIZE, 4u,
503  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_ROW_WIDTH, ((bool)true) },
504  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_ID, 0x00088000u,
505  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_SIZE, 4u,
506  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_ROW_WIDTH, ((bool)true) },
507  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID, 0x50f02000u,
508  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_SIZE, 4u,
509  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ROW_WIDTH, ((bool)true) },
510 };
511 
516 static const SDL_MemConfig_t SDL_HSM_ECC_AGGR_MemEntries[SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
517 {
518  { SDL_HSM_ECC_AGGR_RAMB0_RAM_ID, 0u,
519  SDL_HSM_ECC_AGGR_RAMB0_RAM_SIZE, 4u,
520  SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
521  { SDL_HSM_ECC_AGGR_RAMB1_RAM_ID, 0u,
522  SDL_HSM_ECC_AGGR_RAMB1_RAM_SIZE, 4u,
523  SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
524  { SDL_HSM_ECC_AGGR_RAMB2_RAM_ID, 0u,
525  SDL_HSM_ECC_AGGR_RAMB2_RAM_SIZE, 4u,
526  SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
527  { SDL_HSM_ECC_AGGR_RAMB3_RAM_ID, 0u,
528  SDL_HSM_ECC_AGGR_RAMB3_RAM_SIZE, 4u,
529  SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
530  { SDL_HSM_ECC_AGGR_SECUREB4_RAM_ID, 0u,
531  SDL_HSM_ECC_AGGR_SECUREB4_RAM_SIZE, 4u,
532  SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
533  { SDL_HSM_ECC_AGGR_MBOX_RAM_ID, 0u,
534  SDL_HSM_ECC_AGGR_MBOX_RAM_SIZE, 4u,
535  SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
536  { SDL_HSM_ECC_AGGR_SECURE_RAM_ID, 0u,
537  SDL_HSM_ECC_AGGR_SECURE_RAM_SIZE, 4u,
538  SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
539  { SDL_HSM_ECC_AGGR_ROM_RAM_ID, 0u,
540  SDL_HSM_ECC_AGGR_ROM_RAM_SIZE, 4u,
541  SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
542  { SDL_HSM_ECC_AGGR_TPTC_A0_RAM_ID, 0u,
543  SDL_HSM_ECC_AGGR_TPTC_A0_RAM_SIZE, 8u,
544  SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
545  { SDL_HSM_ECC_AGGR_TPTC_A1_RAM_ID, 0u,
546  SDL_HSM_ECC_AGGR_TPTC_A1_RAM_SIZE, 8u,
547  SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
548 };
549 
554 static const SDL_MemConfig_t SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries[SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
555 {
556  { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_ID, 0x48000000u,
557  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_SIZE, 4u,
558  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_ROW_WIDTH, ((bool)true) },
559  { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_ID, 0x48002000u,
560  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_SIZE, 4u,
561  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_ROW_WIDTH, ((bool)true) },
562  { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID, 0x48034000u,
563  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_SIZE, 4u,
564  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_ROW_WIDTH, ((bool)true) },
565  { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID, 0x48038000u,
566  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_SIZE, 4u,
567  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_ROW_WIDTH, ((bool)true) },
568  { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_ID, 0x48010000u,
569  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_SIZE, 4u,
570  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_ROW_WIDTH, ((bool)true) },
571 };
572 
577 static const SDL_MemConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
578 {
579  { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x52600000u,
580  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
581  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
582 };
583 
588 static const SDL_MemConfig_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
589 {
590  { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x52610000u,
591  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
592  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
593 };
594 
599 static const SDL_MemConfig_t SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
600 {
601  { SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x52620000u,
602  SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
603  SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
604 };
605 
610 static const SDL_MemConfig_t SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
611 {
612  { SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x52630000u,
613  SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
614  SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
615 };
616 
621 static const SDL_MemConfig_t SDL_CPSW3GCSS_ECC_AGGR_MemEntries[SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
622 {
623  { SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_RAM_ID, 0x5283E000u,
624  SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_RAM_SIZE, 71u,
625  SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_ROW_WIDTH, ((bool)true) },
626  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_RAM_ID, 0u,
627  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_RAM_SIZE, 32u,
628  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_ROW_WIDTH, ((bool)false) },
629  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_RAM_ID, 0u,
630  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_RAM_SIZE, 32u,
631  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_ROW_WIDTH, ((bool)false) },
632  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_RAM_ID, 0u,
633  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_RAM_SIZE, 32u,
634  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_ROW_WIDTH, ((bool)false) },
635  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_RAM_ID, 0u,
636  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_RAM_SIZE, 32u,
637  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_ROW_WIDTH, ((bool)false) },
638  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_RAM_ID, 0u,
639  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_RAM_SIZE, 32u,
640  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_ROW_WIDTH, ((bool)false) },
641  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_RAM_ID, 0u,
642  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_RAM_SIZE, 32u,
643  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_ROW_WIDTH, ((bool)false) },
644  { SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_RAM_ID, 0x52832000u,
645  SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_RAM_SIZE, 4u,
646  SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
647 };
652 static const SDL_RAMIdEntry_t SDL_SOC_ECC_AGGR_RamIdTable[SDL_SOC_ECC_AGGR_NUM_RAMS] =
653 {
654  { SDL_SOC_ECC_AGGR_MSS_L2_SLV0_ECC_RAM_ID,
655  SDL_SOC_ECC_AGGR_MSS_L2_SLV0_ECC_INJECT_TYPE,
656  SDL_SOC_ECC_AGGR_MSS_L2_SLV0_ECC_ECC_TYPE,
657  0u,
658  NULL },
659  { SDL_SOC_ECC_AGGR_MSS_L2_SLV1_ECC_RAM_ID,
660  SDL_SOC_ECC_AGGR_MSS_L2_SLV1_ECC_INJECT_TYPE,
661  SDL_SOC_ECC_AGGR_MSS_L2_SLV1_ECC_ECC_TYPE,
662  0u,
663  NULL },
664  { SDL_SOC_ECC_AGGR_MSS_L2_SLV2_ECC_RAM_ID,
665  SDL_SOC_ECC_AGGR_MSS_L2_SLV2_ECC_INJECT_TYPE,
666  SDL_SOC_ECC_AGGR_MSS_L2_SLV2_ECC_ECC_TYPE,
667  0u,
668  NULL },
669  { SDL_SOC_ECC_AGGR_MSS_L2_SLV3_ECC_RAM_ID,
670  SDL_SOC_ECC_AGGR_MSS_L2_SLV3_ECC_INJECT_TYPE,
671  SDL_SOC_ECC_AGGR_MSS_L2_SLV3_ECC_ECC_TYPE,
672  0u,
673  NULL },
674  { SDL_SOC_ECC_AGGR_MAILBOX_ECC_RAM_ID,
675  SDL_SOC_ECC_AGGR_MAILBOX_ECC_INJECT_TYPE,
676  SDL_SOC_ECC_AGGR_MAILBOX_ECC_ECC_TYPE,
677  0u,
678  NULL },
679  { SDL_SOC_ECC_AGGR_TPTC_A0_ECC_RAM_ID,
680  SDL_SOC_ECC_AGGR_TPTC_A0_ECC_INJECT_TYPE,
681  SDL_SOC_ECC_AGGR_TPTC_A0_ECC_ECC_TYPE,
682  0u,
683  NULL },
684  { SDL_SOC_ECC_AGGR_TPTC_A1_ECC_RAM_ID,
685  SDL_SOC_ECC_AGGR_TPTC_A1_ECC_INJECT_TYPE,
686  SDL_SOC_ECC_AGGR_TPTC_A1_ECC_ECC_TYPE,
687  0u,
688  NULL },
689 };
690 
695 static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS] =
696 {
697  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID,
698  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
699  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE,
700  0u,
701  NULL },
702  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID,
703  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
704  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE,
705  0u,
706  NULL },
707  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID,
708  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
709  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE,
710  0u,
711  NULL },
712  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID,
713  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
714  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE,
715  0u,
716  NULL },
717  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID,
718  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
719  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE,
720  0u,
721  NULL },
722  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID,
723  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
724  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE,
725  0u,
726  NULL },
727  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID,
728  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
729  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE,
730  0u,
731  NULL },
732  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID,
733  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
734  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE,
735  0u,
736  NULL },
737  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID,
738  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
739  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE,
740  0u,
741  NULL },
742  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID,
743  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
744  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE,
745  0u,
746  NULL },
747  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID,
748  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
749  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE,
750  0u,
751  NULL },
752  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID,
753  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
754  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE,
755  0u,
756  NULL },
757  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID,
758  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
759  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE,
760  0u,
761  NULL },
762  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID,
763  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
764  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE,
765  0u,
766  NULL },
767  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID,
768  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
769  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE,
770  0u,
771  NULL },
772  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID,
773  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
774  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE,
775  0u,
776  NULL },
777  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID,
778  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
779  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE,
780  0u,
781  NULL },
782  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID,
783  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
784  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE,
785  0u,
786  NULL },
787  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID,
788  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
789  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE,
790  0u,
791  NULL },
792  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID,
793  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
794  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE,
795  0u,
796  NULL },
797  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID,
798  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
799  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE,
800  0u,
801  NULL },
802  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID,
803  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_INJECT_TYPE,
804  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ECC_TYPE,
805  0u,
806  NULL },
807  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID,
808  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_INJECT_TYPE,
809  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ECC_TYPE,
810  0u,
811  NULL },
812  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID,
813  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_INJECT_TYPE,
814  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ECC_TYPE,
815  0u,
816  NULL },
817  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID,
818  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_INJECT_TYPE,
819  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ECC_TYPE,
820  0u,
821  NULL },
822  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID,
823  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_INJECT_TYPE,
824  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ECC_TYPE,
825  0u,
826  NULL },
827  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID,
828  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_INJECT_TYPE,
829  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ECC_TYPE,
830  0u,
831  NULL },
832  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID,
833  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_INJECT_TYPE,
834  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ECC_TYPE,
835  0u,
836  NULL },
837 };
838 
843 static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS] =
844 {
845  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID,
846  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_INJECT_TYPE,
847  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_ECC_TYPE,
848  0u,
849  NULL },
850  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID,
851  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_INJECT_TYPE,
852  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_ECC_TYPE,
853  0u,
854  NULL },
855  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID,
856  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_INJECT_TYPE,
857  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_ECC_TYPE,
858  0u,
859  NULL },
860  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID,
861  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_INJECT_TYPE,
862  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_ECC_TYPE,
863  0u,
864  NULL },
865  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID,
866  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_INJECT_TYPE,
867  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_ECC_TYPE,
868  0u,
869  NULL },
870  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID,
871  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_INJECT_TYPE,
872  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_ECC_TYPE,
873  0u,
874  NULL },
875  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID,
876  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_INJECT_TYPE,
877  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_ECC_TYPE,
878  0u,
879  NULL },
880  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID,
881  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_INJECT_TYPE,
882  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_ECC_TYPE,
883  0u,
884  NULL },
885  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID,
886  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_INJECT_TYPE,
887  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_ECC_TYPE,
888  0u,
889  NULL },
890  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID,
891  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_INJECT_TYPE,
892  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_ECC_TYPE,
893  0u,
894  NULL },
895  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID,
896  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_INJECT_TYPE,
897  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_ECC_TYPE,
898  0u,
899  NULL },
900  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID,
901  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_INJECT_TYPE,
902  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_ECC_TYPE,
903  0u,
904  NULL },
905  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID,
906  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_INJECT_TYPE,
907  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_ECC_TYPE,
908  0u,
909  NULL },
910  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID,
911  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_INJECT_TYPE,
912  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_ECC_TYPE,
913  0u,
914  NULL },
915  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID,
916  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_INJECT_TYPE,
917  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_ECC_TYPE,
918  0u,
919  NULL },
920  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID,
921  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_INJECT_TYPE,
922  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_ECC_TYPE,
923  0u,
924  NULL },
925  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID,
926  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_INJECT_TYPE,
927  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_ECC_TYPE,
928  0u,
929  NULL },
930  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID,
931  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_INJECT_TYPE,
932  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_ECC_TYPE,
933  0u,
934  NULL },
935  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID,
936  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_INJECT_TYPE,
937  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_ECC_TYPE,
938  0u,
939  NULL },
940  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID,
941  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_INJECT_TYPE,
942  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_ECC_TYPE,
943  0u,
944  NULL },
945  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID,
946  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_INJECT_TYPE,
947  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_ECC_TYPE,
948  0u,
949  NULL },
950  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_ID,
951  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_INJECT_TYPE,
952  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_ECC_TYPE,
953  0u,
954  NULL },
955  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_ID,
956  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_INJECT_TYPE,
957  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_ECC_TYPE,
958  0u,
959  NULL },
960  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_ID,
961  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_INJECT_TYPE,
962  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_ECC_TYPE,
963  0u,
964  NULL },
965  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_ID,
966  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_INJECT_TYPE,
967  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_ECC_TYPE,
968  0u,
969  NULL },
970  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_ID,
971  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_INJECT_TYPE,
972  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_ECC_TYPE,
973  0u,
974  NULL },
975  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_ID,
976  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_INJECT_TYPE,
977  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_ECC_TYPE,
978  0u,
979  NULL },
980  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID,
981  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_INJECT_TYPE,
982  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ECC_TYPE,
983  0u,
984  NULL },
985 };
990 static const SDL_RAMIdEntry_t SDL_R5FSS1_CORE0_ECC_AGGR_RamIdTable[SDL_R5FSS1_CORE0_ECC_AGGR_NUM_RAMS] =
991 {
992  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID,
993  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
994  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE,
995  0u,
996  NULL },
997  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID,
998  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
999  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE,
1000  0u,
1001  NULL },
1002  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID,
1003  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
1004  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE,
1005  0u,
1006  NULL },
1007  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID,
1008  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
1009  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE,
1010  0u,
1011  NULL },
1012  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID,
1013  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
1014  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE,
1015  0u,
1016  NULL },
1017  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID,
1018  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
1019  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE,
1020  0u,
1021  NULL },
1022  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID,
1023  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
1024  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE,
1025  0u,
1026  NULL },
1027  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID,
1028  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
1029  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE,
1030  0u,
1031  NULL },
1032  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID,
1033  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
1034  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE,
1035  0u,
1036  NULL },
1037  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID,
1038  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
1039  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE,
1040  0u,
1041  NULL },
1042  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID,
1043  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
1044  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE,
1045  0u,
1046  NULL },
1047  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID,
1048  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
1049  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE,
1050  0u,
1051  NULL },
1052  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID,
1053  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
1054  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE,
1055  0u,
1056  NULL },
1057  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID,
1058  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
1059  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE,
1060  0u,
1061  NULL },
1062  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID,
1063  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
1064  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE,
1065  0u,
1066  NULL },
1067  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID,
1068  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
1069  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE,
1070  0u,
1071  NULL },
1072  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID,
1073  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
1074  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE,
1075  0u,
1076  NULL },
1077  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID,
1078  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
1079  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE,
1080  0u,
1081  NULL },
1082  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID,
1083  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
1084  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE,
1085  0u,
1086  NULL },
1087  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID,
1088  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
1089  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE,
1090  0u,
1091  NULL },
1092  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID,
1093  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
1094  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE,
1095  0u,
1096  NULL },
1097  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID,
1098  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_INJECT_TYPE,
1099  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ECC_TYPE,
1100  0u,
1101  NULL },
1102  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID,
1103  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_INJECT_TYPE,
1104  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ECC_TYPE,
1105  0u,
1106  NULL },
1107  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID,
1108  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_INJECT_TYPE,
1109  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ECC_TYPE,
1110  0u,
1111  NULL },
1112  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID,
1113  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_INJECT_TYPE,
1114  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ECC_TYPE,
1115  0u,
1116  NULL },
1117  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID,
1118  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_INJECT_TYPE,
1119  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ECC_TYPE,
1120  0u,
1121  NULL },
1122  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID,
1123  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_INJECT_TYPE,
1124  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ECC_TYPE,
1125  0u,
1126  NULL },
1127  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID,
1128  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_INJECT_TYPE,
1129  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ECC_TYPE,
1130  0u,
1131  NULL },
1132 };
1133 
1138 static const SDL_RAMIdEntry_t SDL_R5FSS1_CORE1_ECC_AGGR_RamIdTable[SDL_R5FSS1_CORE1_ECC_AGGR_NUM_RAMS] =
1139 {
1140  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID,
1141  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_INJECT_TYPE,
1142  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_ECC_TYPE,
1143  0u,
1144  NULL },
1145  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID,
1146  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_INJECT_TYPE,
1147  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_ECC_TYPE,
1148  0u,
1149  NULL },
1150  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID,
1151  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_INJECT_TYPE,
1152  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_ECC_TYPE,
1153  0u,
1154  NULL },
1155  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID,
1156  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_INJECT_TYPE,
1157  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_ECC_TYPE,
1158  0u,
1159  NULL },
1160  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID,
1161  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_INJECT_TYPE,
1162  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_ECC_TYPE,
1163  0u,
1164  NULL },
1165  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID,
1166  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_INJECT_TYPE,
1167  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_ECC_TYPE,
1168  0u,
1169  NULL },
1170  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID,
1171  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_INJECT_TYPE,
1172  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_ECC_TYPE,
1173  0u,
1174  NULL },
1175  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID,
1176  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_INJECT_TYPE,
1177  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_ECC_TYPE,
1178  0u,
1179  NULL },
1180  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID,
1181  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_INJECT_TYPE,
1182  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_ECC_TYPE,
1183  0u,
1184  NULL },
1185  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID,
1186  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_INJECT_TYPE,
1187  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_ECC_TYPE,
1188  0u,
1189  NULL },
1190  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID,
1191  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_INJECT_TYPE,
1192  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_ECC_TYPE,
1193  0u,
1194  NULL },
1195  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID,
1196  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_INJECT_TYPE,
1197  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_ECC_TYPE,
1198  0u,
1199  NULL },
1200  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID,
1201  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_INJECT_TYPE,
1202  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_ECC_TYPE,
1203  0u,
1204  NULL },
1205  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID,
1206  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_INJECT_TYPE,
1207  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_ECC_TYPE,
1208  0u,
1209  NULL },
1210  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID,
1211  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_INJECT_TYPE,
1212  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_ECC_TYPE,
1213  0u,
1214  NULL },
1215  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID,
1216  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_INJECT_TYPE,
1217  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_ECC_TYPE,
1218  0u,
1219  NULL },
1220  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID,
1221  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_INJECT_TYPE,
1222  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_ECC_TYPE,
1223  0u,
1224  NULL },
1225  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID,
1226  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_INJECT_TYPE,
1227  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_ECC_TYPE,
1228  0u,
1229  NULL },
1230  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID,
1231  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_INJECT_TYPE,
1232  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_ECC_TYPE,
1233  0u,
1234  NULL },
1235  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID,
1236  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_INJECT_TYPE,
1237  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_ECC_TYPE,
1238  0u,
1239  NULL },
1240  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID,
1241  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_INJECT_TYPE,
1242  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_ECC_TYPE,
1243  0u,
1244  NULL },
1245  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_ID,
1246  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_INJECT_TYPE,
1247  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_ECC_TYPE,
1248  0u,
1249  NULL },
1250  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_ID,
1251  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_INJECT_TYPE,
1252  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_ECC_TYPE,
1253  0u,
1254  NULL },
1255  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_ID,
1256  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_INJECT_TYPE,
1257  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_ECC_TYPE,
1258  0u,
1259  NULL },
1260  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_ID,
1261  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_INJECT_TYPE,
1262  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_ECC_TYPE,
1263  0u,
1264  NULL },
1265  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_ID,
1266  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_INJECT_TYPE,
1267  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_ECC_TYPE,
1268  0u,
1269  NULL },
1270  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_ID,
1271  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_INJECT_TYPE,
1272  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_ECC_TYPE,
1273  0u,
1274  NULL },
1275  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID,
1276  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_INJECT_TYPE,
1277  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ECC_TYPE,
1278  0u,
1279  NULL },
1280 };
1281 
1286 static const SDL_RAMIdEntry_t SDL_HSM_ECC_AGGR_RamIdTable[SDL_HSM_ECC_AGGR_NUM_RAMS] =
1287 {
1288  { SDL_HSM_ECC_AGGR_RAMB0_RAM_ID,
1289  SDL_HSM_ECC_AGGR_RAMB0_INJECT_TYPE,
1290  SDL_HSM_ECC_AGGR_RAMB0_ECC_TYPE,
1291  0u,
1292  NULL },
1293  { SDL_HSM_ECC_AGGR_RAMB1_RAM_ID,
1294  SDL_HSM_ECC_AGGR_RAMB1_INJECT_TYPE,
1295  SDL_HSM_ECC_AGGR_RAMB1_ECC_TYPE,
1296  0u,
1297  NULL },
1298  { SDL_HSM_ECC_AGGR_RAMB2_RAM_ID,
1299  SDL_HSM_ECC_AGGR_RAMB2_INJECT_TYPE,
1300  SDL_HSM_ECC_AGGR_RAMB2_ECC_TYPE,
1301  0u,
1302  NULL },
1303  { SDL_HSM_ECC_AGGR_RAMB3_RAM_ID,
1304  SDL_HSM_ECC_AGGR_RAMB3_INJECT_TYPE,
1305  SDL_HSM_ECC_AGGR_RAMB3_ECC_TYPE,
1306  0u,
1307  NULL },
1308  { SDL_HSM_ECC_AGGR_SECUREB4_RAM_ID,
1309  SDL_HSM_ECC_AGGR_SECUREB4_INJECT_TYPE,
1310  SDL_HSM_ECC_AGGR_SECUREB4_ECC_TYPE,
1311  0u,
1312  NULL },
1313  { SDL_HSM_ECC_AGGR_MBOX_RAM_ID,
1314  SDL_HSM_ECC_AGGR_MBOX_INJECT_TYPE,
1315  SDL_HSM_ECC_AGGR_MBOX_ECC_TYPE,
1316  0u,
1317  NULL },
1318  { SDL_HSM_ECC_AGGR_SECURE_RAM_ID,
1319  SDL_HSM_ECC_AGGR_SECURE_INJECT_TYPE,
1320  SDL_HSM_ECC_AGGR_SECURE_ECC_TYPE,
1321  0u,
1322  NULL },
1323  { SDL_HSM_ECC_AGGR_ROM_RAM_ID,
1324  SDL_HSM_ECC_AGGR_ROM_INJECT_TYPE,
1325  SDL_HSM_ECC_AGGR_ROM_ECC_TYPE,
1326  0u,
1327  NULL },
1328  { SDL_HSM_ECC_AGGR_TPTC_A0_RAM_ID,
1329  SDL_HSM_ECC_AGGR_TPTC_A0_INJECT_TYPE,
1330  SDL_HSM_ECC_AGGR_TPTC_A0_ECC_TYPE,
1331  0u,
1332  NULL },
1333  { SDL_HSM_ECC_AGGR_TPTC_A1_RAM_ID,
1334  SDL_HSM_ECC_AGGR_TPTC_A1_INJECT_TYPE,
1335  SDL_HSM_ECC_AGGR_TPTC_A1_ECC_TYPE,
1336  0u,
1337  NULL },
1338 };
1339 
1344 static const SDL_RAMIdEntry_t SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable[SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS] =
1345 {
1346  { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_ID,
1347  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_INJECT_TYPE,
1348  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_ECC_TYPE,
1349  0u,
1350  NULL },
1351  { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_ID,
1352  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_INJECT_TYPE,
1353  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_ECC_TYPE,
1354  0u,
1355  NULL },
1356  { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID,
1357  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_INJECT_TYPE,
1358  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_ECC_TYPE,
1359  0u,
1360  NULL },
1361  { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID,
1362  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_INJECT_TYPE,
1363  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_ECC_TYPE,
1364  0u,
1365  NULL },
1366  { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_ID,
1367  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_INJECT_TYPE,
1368  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_ECC_TYPE,
1369  0u,
1370  NULL },
1371 };
1372 
1377 static const SDL_RAMIdEntry_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
1378 {
1379  { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
1380  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
1381  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
1382  0u,
1383  NULL }
1384 };
1385 
1390 static const SDL_RAMIdEntry_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
1391 {
1392  { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
1393  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
1394  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
1395  0u,
1396  NULL }
1397 };
1398 
1403 static const SDL_RAMIdEntry_t SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
1404 {
1405  { SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
1406  SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
1407  SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
1408  0u,
1409  NULL }
1410 };
1411 
1416 static const SDL_RAMIdEntry_t SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
1417 {
1418  { SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
1419  SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
1420  SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
1421  0u,
1422  NULL }
1423 };
1424 
1429 static const SDL_RAMIdEntry_t SDL_CPSW3GCSS_ECC_AGGR_RamIdTable[SDL_CPSW3GCSS_ECC_AGGR_NUM_RAMS] =
1430 {
1431  { SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_RAM_ID,
1432  SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_INJECT_TYPE,
1433  SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_ECC_TYPE,
1434  0u,
1435  NULL },
1436  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_RAM_ID,
1437  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_INJECT_TYPE,
1438  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_ECC_TYPE,
1439  0u,
1440  NULL },
1441  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_RAM_ID,
1442  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_INJECT_TYPE,
1443  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_ECC_TYPE,
1444  0u,
1445  NULL },
1446  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_RAM_ID,
1447  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_INJECT_TYPE,
1448  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_ECC_TYPE,
1449  0u,
1450  NULL },
1451  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_RAM_ID,
1452  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_INJECT_TYPE,
1453  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_ECC_TYPE,
1454  0u,
1455  NULL },
1456  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_RAM_ID,
1457  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_INJECT_TYPE,
1458  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_ECC_TYPE,
1459  0u,
1460  NULL },
1461  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_RAM_ID,
1462  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_INJECT_TYPE,
1463  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_ECC_TYPE,
1464  0u,
1465  NULL },
1466  { SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_RAM_ID,
1467  SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_INJECT_TYPE,
1468  SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_ECC_TYPE,
1469  0u,
1470  NULL },
1471 };
1472 
1473 static SDL_ecc_aggrRegs * const SDL_ECC_aggrBaseAddressTable[SDL_ECC_Base_Address_TOTAL_ENTRIES] =
1474 {
1475  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGG_TOP_U_BASE)),
1476  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGG_R5SS0_CORE0_U_BASE)),
1477  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGG_R5SS0_CORE1_U_BASE)),
1478  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGG_R5SS1_CORE0_U_BASE)),
1479  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGG_R5SS1_CORE1_U_BASE )),
1480  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_HSM_ECC_AGGR_U_BASE)),
1481  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ICSSM0_ECC_U_BASE)),
1482  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN0_ECC_U_BASE)),
1483  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN1_ECC_U_BASE)),
1484  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN2_ECC_U_BASE)),
1485  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN3_ECC_U_BASE)),
1486  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_CPSW0_ECC_U_BASE)),
1487 
1488 };
1489 
1490 SDL_ecc_aggrRegs * SDL_ECC_aggrTransBaseAddressTable[SDL_ECC_MEMTYPE_MAX];
1493 static const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX] =
1494 {
1495 
1496  /* Index: SDL_SOC_ECC_AGGR (0) */
1497  {
1498  SDL_SOC_ECC_AGGR_NUM_RAMS,
1499  SDL_SOC_ECC_AGGR_RamIdTable,
1500  SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1501  SDL_SOC_ECC_AGGR_MemEntries,
1502  SDL_ESM_INST_MAIN_ESM0,
1503  SDL_ESM0_ECC_AGGREGATOR_SOC_ECCAGG_CORR_LEVEL,
1504  SDL_ESM0_ECC_AGGREGATOR_SOC_ECCAGG_UNCORR_LEVEL
1505  },
1506  /* Index: SDL_R5FSS0_CORE0_ECC_AGGR (1) */
1507  {
1508  SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS,
1509  SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable,
1510  SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1511  SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries,
1512  SDL_ESM_INST_MAIN_ESM0,
1513  SDL_ESM0_R5FSS0_CORE0_R5FSS0_CORE0_ECC_CORRECTED_LEVEL_0,
1514  SDL_ESM0_R5FSS0_CORE0_R5FSS0_CORE0_ECC_UNCORRECTED_LEVEL_0
1515  },
1516  /* Index: SDL_R5FSS0_CORE1_ECC_AGGR (2) */
1517  {
1518  SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS,
1519  SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable,
1520  SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1521  SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries,
1522  SDL_ESM_INST_MAIN_ESM0,
1523  SDL_ESM0_R5FSS0_CORE1_R5FSS0_CORE1_ECC_CORRECTED_LEVEL_0,
1524  SDL_ESM0_R5FSS0_CORE1_R5FSS0_CORE1_ECC_UNCORRECTED_LEVEL_0
1525  },
1526  /* Index: SDL_R5FSS1_CORE0_ECC_AGGR (3) */
1527  {
1528  SDL_R5FSS1_CORE0_ECC_AGGR_NUM_RAMS,
1529  SDL_R5FSS1_CORE0_ECC_AGGR_RamIdTable,
1530  SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1531  SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries,
1532  SDL_ESM_INST_MAIN_ESM0,
1533  SDL_ESM0_R5FSS1_CORE0_R5FSS1_CORE0_ECC_CORRECTED_LEVEL_0,
1534  SDL_ESM0_R5FSS1_CORE0_R5FSS1_CORE0_ECC_UNCORRECTED_LEVEL_0
1535  },
1536  /* Index: SDL_R5FSS1_CORE1_ECC_AGGR (4) */
1537  {
1538  SDL_R5FSS1_CORE1_ECC_AGGR_NUM_RAMS,
1539  SDL_R5FSS1_CORE1_ECC_AGGR_RamIdTable,
1540  SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1541  SDL_R5FSS1_CORE1_ECC_AGGR_MemEntries,
1542  SDL_ESM_INST_MAIN_ESM0,
1543  SDL_ESM0_R5FSS1_CORE1_R5FSS1_CORE1_ECC_CORRECTED_LEVEL_0,
1544  SDL_ESM0_R5FSS1_CORE1_R5FSS1_CORE1_ECC_UNCORRECTED_LEVEL_0
1545  },
1546  /* Index: SDL_HSM_ECC_AGGR (5) */
1547  {
1548  SDL_HSM_ECC_AGGR_NUM_RAMS,
1549  SDL_HSM_ECC_AGGR_RamIdTable,
1550  SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1551  SDL_HSM_ECC_AGGR_MemEntries,
1552  SDL_ESM_INST_MAIN_ESM0,
1553  SDL_ESM0_HSM_ESM_HIGH_INTR,
1554  SDL_ESM0_HSM_ESM_LOW_INTR
1555  },
1556  /* Index: SDL_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR (6) */
1557  {
1558  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS,
1559  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable,
1560  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1561  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries,
1562  SDL_ESM_INST_MAIN_ESM0,
1563  SDL_ESM0_PRU_ICSSM0_PR1_ECC_SEC_ERR_REQ,
1564  SDL_ESM0_PRU_ICSSM0_PR1_ECC_DED_ERR_REQ
1565  },
1566  /* Index: SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR (7) */
1567  {
1568  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
1569  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
1570  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1571  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
1572  SDL_ESM_INST_MAIN_ESM0,
1573  SDL_ESM0_MCAN0_MCAN0_ECC_CORR_LVL_INT,
1574  SDL_ESM0_MCAN0_MCAN0_ECC_UNCORR_LVL_INT
1575  },
1576  /* Index: SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR (8) */
1577  {
1578  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
1579  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
1580  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1581  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
1582  SDL_ESM_INST_MAIN_ESM0,
1583  SDL_ESM0_MCAN1_MCAN1_ECC_CORR_LVL_INT,
1584  SDL_ESM0_MCAN1_MCAN1_ECC_UNCORR_LVL_INT
1585  },
1586  /* Index: SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR (9) */
1587  {
1588  SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
1589  SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
1590  SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1591  SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
1592  SDL_ESM_INST_MAIN_ESM0,
1593  SDL_ESM0_MCAN2_MCAN2_ECC_CORR_LVL_INT,
1594  SDL_ESM0_MCAN2_MCAN2_ECC_UNCORR_LVL_INT
1595  },
1596  /* Index: SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR (10) */
1597  {
1598  SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
1599  SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
1600  SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1601  SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
1602  SDL_ESM_INST_MAIN_ESM0,
1603  SDL_ESM0_MCAN3_MCAN3_ECC_CORR_LVL_INT,
1604  SDL_ESM0_MCAN3_MCAN3_ECC_UNCORR_LVL_INT
1605  },
1606  /* Index: SDL_CPSW3GCSS_ECC_AGGR (11) */
1607  {
1608  SDL_CPSW3GCSS_ECC_AGGR_NUM_RAMS,
1609  SDL_CPSW3GCSS_ECC_AGGR_RamIdTable,
1610  SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1611  SDL_CPSW3GCSS_ECC_AGGR_MemEntries,
1612  SDL_ESM_INST_MAIN_ESM0,
1613  SDL_ESM0_CPSW3G_CPSW_ECC_SEC_PEND_INTR,
1614  SDL_ESM0_CPSW3G_CPSW_ECC_DED_PEND_INTR
1615  },
1616 
1617 
1618  };
1619 
1621  #endif /* INCLUDE_SDL_ECC_SOC_H_ */
SDL_CPSW0_ECC_U_BASE
#define SDL_CPSW0_ECC_U_BASE
Definition: sdl_ecc_soc.h:88
SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:599
SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:78
SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:75
SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:148
SDL_ecc_aggrRegs
Definition: V1/sdlr_ecc.h:53
SDL_R5FSS1_CORE0_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_R5FSS1_CORE0_ECC_AGGR_RamIdTable[SDL_R5FSS1_CORE0_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:990
SDL_ESM_INST_MAIN_ESM0
@ SDL_ESM_INST_MAIN_ESM0
Definition: sdl_esm_soc.h:66
SDL_ECC_aggrTransBaseAddressTable
SDL_ecc_aggrRegs * SDL_ECC_aggrTransBaseAddressTable[SDL_ECC_MEMTYPE_MAX]
Definition: sdl_ecc_soc.h:1490
SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries[SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:554
SDL_SOC_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_SOC_ECC_AGGR_MemEntries[SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:119
SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:77
SDL_ECC_WIDTH_UNDEFINED
#define SDL_ECC_WIDTH_UNDEFINED
Definition: sdl_ecc_soc.h:71
SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:240
SDL_SOC_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_SOC_ECC_AGGR_RamIdTable[SDL_SOC_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:652
SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:82
SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:83
SDL_CPSW3GCSS_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_CPSW3GCSS_ECC_AGGR_RamIdTable[SDL_CPSW3GCSS_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:1429
SDL_ECC_aggrBaseAddressTable
static SDL_ecc_aggrRegs *const SDL_ECC_aggrBaseAddressTable[SDL_ECC_Base_Address_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:1473
SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:843
SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:1403
sdl_ip_ecc.h
SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:610
SDL_MemConfig_t
Definition: sdl_ecc_priv.h:88
SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:76
SDL_R5FSS1_CORE1_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_MemEntries[SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:424
SDL_HSM_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_HSM_ECC_AGGR_RamIdTable[SDL_HSM_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:1286
sdl_ecc.h
Header file contains enumerations, structure definitions and function.
SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:1390
SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:80
SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:74
SDL_R5FSS1_CORE0_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_MemEntries[SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:332
SDL_HSM_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_HSM_ECC_AGGR_MemEntries[SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:516
SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable[SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:1344
SDL_RAMIdEntry_t
Definition: sdl_ecc_priv.h:63
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:81
SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:588
SDL_ECC_aggrTable
static const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX]
Definition: sdl_ecc_soc.h:1493
SDL_EccAggrEntry_t
Definition: sdl_ecc_priv.h:104
SDL_R5FSS1_CORE1_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_R5FSS1_CORE1_ECC_AGGR_RamIdTable[SDL_R5FSS1_CORE1_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:1138
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:1377
SDL_CPSW3GCSS_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_CPSW3GCSS_ECC_AGGR_MemEntries[SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:621
SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:1416
SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:79
SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:695
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:577
sdl_ecc_priv.h
SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:85
SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:84
SDL_ECC_Base_Address_TOTAL_ENTRIES
#define SDL_ECC_Base_Address_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:86