etpwm.h

Go to the documentation of this file.

/*
 * Copyright (C) 2021-2023 Texas Instruments Incorporated
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *   Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 *
 *   Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the
 *   distribution.
 *
 *   Neither the name of Texas Instruments Incorporated nor the names of
 *   its contributors may be used to endorse or promote products derived
 *   from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef EPWM_V1_H_
#define EPWM_V1_H_
 
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
 
//*****************************************************************************
//
// Header Files
//
//*****************************************************************************
#include <stdbool.h>
#include <stdint.h>
#include <drivers/hw_include/hw_types.h>
#include <drivers/hw_include/cslr_soc.h>
#include <kernel/dpl/DebugP.h>
#include <drivers/hw_include/cslr_epwm.h>
 
//*****************************************************************************
//
// Defines for the API.
//
//*****************************************************************************
//*****************************************************************************
//
// Define to specify mask for source parameter for
// EPWM_enableSyncOutPulseSource() & EPWM_disableSyncOutPulseSource()
//
//*****************************************************************************
#define EPWM_SYNC_OUT_SOURCE_M ((uint16_t)CSL_EPWM_EPWMSYNCOUTEN_SWEN_MASK   |\
                             (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_ZEROEN_MASK    |\
                             (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_CMPBEN_MASK    |\
                             (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_CMPCEN_MASK    |\
                             (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_CMPDEN_MASK    |\
                             (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_DCAEVT1EN_MASK |\
                             (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_DCBEVT1EN_MASK)
 
//*****************************************************************************
//
// Values that can be passed to EPWM_enableSyncOutPulseSource() &
// EPWM_disableSyncOutPulseSource() as the \e mode parameter.
//
//*****************************************************************************
#define EPWM_SYNC_OUT_PULSE_ON_SOFTWARE  CSL_EPWM_EPWMSYNCOUTEN_SWEN_MASK
#define EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO  CSL_EPWM_EPWMSYNCOUTEN_ZEROEN_MASK
#define EPWM_SYNC_OUT_PULSE_ON_CNTR_COMPARE_B  CSL_EPWM_EPWMSYNCOUTEN_CMPBEN_MASK
#define EPWM_SYNC_OUT_PULSE_ON_CNTR_COMPARE_C  CSL_EPWM_EPWMSYNCOUTEN_CMPCEN_MASK
#define EPWM_SYNC_OUT_PULSE_ON_CNTR_COMPARE_D  CSL_EPWM_EPWMSYNCOUTEN_CMPDEN_MASK
#define EPWM_SYNC_OUT_PULSE_ON_DCA_EVT1_SYNC  CSL_EPWM_EPWMSYNCOUTEN_DCAEVT1EN_MASK
#define EPWM_SYNC_OUT_PULSE_ON_DCB_EVT1_SYNC  CSL_EPWM_EPWMSYNCOUTEN_DCBEVT1EN_MASK
#define EPWM_SYNC_OUT_PULSE_ON_ALL  EPWM_SYNC_OUT_SOURCE_M
 
//
// Time Base Module
//
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
   EPWM_EMULATION_STOP_AFTER_NEXT_TB = 0,
   EPWM_EMULATION_STOP_AFTER_FULL_CYCLE = 1,
   EPWM_EMULATION_FREE_RUN = 2
} EPWM_EmulationMode;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
   EPWM_COUNT_MODE_DOWN_AFTER_SYNC = 0,  
   EPWM_COUNT_MODE_UP_AFTER_SYNC = 1  
} EPWM_SyncCountMode;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_CLOCK_DIVIDER_1 = 0,  
    EPWM_CLOCK_DIVIDER_2 = 1,  
    EPWM_CLOCK_DIVIDER_4 = 2,  
    EPWM_CLOCK_DIVIDER_8 = 3,  
    EPWM_CLOCK_DIVIDER_16 = 4,  
    EPWM_CLOCK_DIVIDER_32 = 5,  
    EPWM_CLOCK_DIVIDER_64 = 6,  
    EPWM_CLOCK_DIVIDER_128 = 7  
} EPWM_ClockDivider;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_HSCLOCK_DIVIDER_1 = 0,  
    EPWM_HSCLOCK_DIVIDER_2 = 1,  
    EPWM_HSCLOCK_DIVIDER_4 = 2,  
    EPWM_HSCLOCK_DIVIDER_6 = 3,  
    EPWM_HSCLOCK_DIVIDER_8 = 4,  
    EPWM_HSCLOCK_DIVIDER_10 = 5,  
    EPWM_HSCLOCK_DIVIDER_12 = 6,  
    EPWM_HSCLOCK_DIVIDER_14 = 7   
} EPWM_HSClockDivider;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_SYNC_IN_PULSE_SRC_DISABLE = 0x0,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM0 = 0x1,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1 = 0x2,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM2 = 0x3,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM3 = 0x4,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM4 = 0x5,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM5 = 0x6,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM6 = 0x7,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM7 = 0x8,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM8 = 0x9,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM9 = 0xA,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM10 = 0xB,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM11 = 0xC,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM12 = 0xD,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM13 = 0xE,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM14 = 0xF,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM15 = 0x10,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM16 = 0x11,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM17 = 0x12,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM18 = 0x13,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM19 = 0x14,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM20 = 0x15,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM21 = 0x16,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM22 = 0x17,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM23 = 0x18,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM24 = 0x19,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM25 = 0x1A,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM26 = 0x1B,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM27 = 0x1C,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM28 = 0x1D,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM29 = 0x1E,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM30 = 0x1F,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM31 = 0x20,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP0 = 0x40,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP1 = 0x41,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP2 = 0x42,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP3 = 0x43,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP4 = 0x44,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP5 = 0x45,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP6 = 0x46,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP7 = 0x47,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP8 = 0x48,
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP9 = 0x49,
    EPWM_SYNC_IN_PULSE_SRC_INPUTXBAR_OUT4 = 0x50,
    EPWM_SYNC_IN_PULSE_SRC_INPUTXBAR_OUT20 = 0x51,
    EPWM_SYNC_IN_PULSE_SRC_C2K_TIMESYNC_XBAR_PWM_OUT0 = 0x58,
    EPWM_SYNC_IN_PULSE_SRC_C2K_TIMESYNC_XBAR_PWM_OUT1 = 0x59,
    EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG0 = 0x60,
    EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG1 = 0x61,
    EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG2 = 0x62,
    EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG3 = 0x63,
    EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG0 = 0x64,
    EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG1 = 0x65,
    EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG2 = 0x66,
    EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG3 = 0x67,
    EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG0 = 0x68,
    EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG1 = 0x69,
    EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG2 = 0x6A,
    EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG3 = 0x6B,
    EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG0 = 0x6C,
    EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG1 = 0x6D,
    EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG2 = 0x6E,
    EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG3 = 0x6F
} EPWM_SyncInPulseSource;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_OSHT_SYNC_OUT_TRIG_SYNC = 0x0, 
    EPWM_OSHT_SYNC_OUT_TRIG_RELOAD = 0x1  
} EPWM_OneShotSyncOutTrigger;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_PERIOD_SHADOW_LOAD = 0,
    EPWM_PERIOD_DIRECT_LOAD = 1
} EPWM_PeriodLoadMode;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_COUNTER_MODE_UP = 0,         
    EPWM_COUNTER_MODE_DOWN = 1,       
    EPWM_COUNTER_MODE_UP_DOWN = 2,    
    EPWM_COUNTER_MODE_STOP_FREEZE = 3 
} EPWM_TimeBaseCountMode;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_SHADOW_LOAD_MODE_COUNTER_ZERO = 0,
    EPWM_SHADOW_LOAD_MODE_COUNTER_SYNC = 1,
    EPWM_SHADOW_LOAD_MODE_SYNC = 2
} EPWM_PeriodShadowLoadMode;
 
//*****************************************************************************
//
// Values that can be returned by the EPWM_getTimeBaseCounterDirection()
//
//*****************************************************************************
#define EPWM_TIME_BASE_STATUS_COUNT_DOWN   (0U)
#define EPWM_TIME_BASE_STATUS_COUNT_UP     (1U)
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_LINK_WITH_EPWM_0 = 0,   
    EPWM_LINK_WITH_EPWM_1 = 1,   
    EPWM_LINK_WITH_EPWM_2 = 2,   
    EPWM_LINK_WITH_EPWM_3 = 3,   
    EPWM_LINK_WITH_EPWM_4 = 4,   
    EPWM_LINK_WITH_EPWM_5 = 5,   
    EPWM_LINK_WITH_EPWM_6 = 6,   
    EPWM_LINK_WITH_EPWM_7 = 7,   
    EPWM_LINK_WITH_EPWM_8 = 8,   
    EPWM_LINK_WITH_EPWM_9 = 9,   
    EPWM_LINK_WITH_EPWM_10 = 10,   
    EPWM_LINK_WITH_EPWM_11 = 11,   
    EPWM_LINK_WITH_EPWM_12 = 12,   
    EPWM_LINK_WITH_EPWM_13 = 13,   
    EPWM_LINK_WITH_EPWM_14 = 14,   
    EPWM_LINK_WITH_EPWM_15 = 15,   
    EPWM_LINK_WITH_EPWM_16 = 16,   
    EPWM_LINK_WITH_EPWM_17 = 17,   
    EPWM_LINK_WITH_EPWM_18 = 18,   
    EPWM_LINK_WITH_EPWM_19 = 19,   
    EPWM_LINK_WITH_EPWM_20 = 20,   
    EPWM_LINK_WITH_EPWM_21 = 21,   
    EPWM_LINK_WITH_EPWM_22 = 22,   
    EPWM_LINK_WITH_EPWM_23 = 23,   
    EPWM_LINK_WITH_EPWM_24 = 24,   
    EPWM_LINK_WITH_EPWM_25 = 25,   
    EPWM_LINK_WITH_EPWM_26 = 26,   
    EPWM_LINK_WITH_EPWM_27 = 27,   
    EPWM_LINK_WITH_EPWM_28 = 28,   
    EPWM_LINK_WITH_EPWM_29 = 29,   
    EPWM_LINK_WITH_EPWM_30 = 30,   
    EPWM_LINK_WITH_EPWM_31 = 31,   
} EPWM_CurrentLink;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_LINK_TBPRD = 0,  
    EPWM_LINK_COMP_A = 5,  
    EPWM_LINK_COMP_B = 10,  
    EPWM_LINK_COMP_C = 16, 
    EPWM_LINK_COMP_D = 21, 
    EPWM_LINK_GLDCTL2 = 26,  
    EPWM_LINK_DBRED = 1,    
    EPWM_LINK_DBFED = 6,    
    EPWM_LINK_XLOAD = 2      
} EPWM_LinkComponent;
 
//
// Counter Compare Module
//
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_COUNTER_COMPARE_A = 0, 
    EPWM_COUNTER_COMPARE_B = 4, 
    EPWM_COUNTER_COMPARE_C = 10, 
    EPWM_COUNTER_COMPARE_D = 14  
} EPWM_CounterCompareModule;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_COMP_LOAD_ON_CNTR_ZERO = 0,
    EPWM_COMP_LOAD_ON_CNTR_PERIOD = 1,
    EPWM_COMP_LOAD_ON_CNTR_ZERO_PERIOD = 2,
    EPWM_COMP_LOAD_FREEZE = 3,
    EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO = 4,
    EPWM_COMP_LOAD_ON_SYNC_CNTR_PERIOD = 5,
    EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO_PERIOD = 6,
    EPWM_COMP_LOAD_ON_SYNC_ONLY = 8
} EPWM_CounterCompareLoadMode;
 
//
// Action Qualifier Module
//
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_ACTION_QUALIFIER_A = 0, 
    EPWM_ACTION_QUALIFIER_B = 2  
} EPWM_ActionQualifierModule;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_AQ_LOAD_ON_CNTR_ZERO = 0,
    EPWM_AQ_LOAD_ON_CNTR_PERIOD = 1,
    EPWM_AQ_LOAD_ON_CNTR_ZERO_PERIOD = 2,
    EPWM_AQ_LOAD_FREEZE = 3,
    EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO = 4,
    EPWM_AQ_LOAD_ON_SYNC_CNTR_PERIOD = 5,
    EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO_PERIOD = 6,
    EPWM_AQ_LOAD_ON_SYNC_ONLY = 8
} EPWM_ActionQualifierLoadMode;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1 = 0, 
    EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2 = 1, 
    EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1 = 2, 
    EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_2 = 3, 
    EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_1 = 4, 
    EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_2 = 5, 
    EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_3 = 6, 
    EPWM_AQ_TRIGGER_EVENT_TRIG_EPWM_SYNCIN = 7, 
    EPWM_AQ_TRIGGER_EVENT_TRIG_DC_EVTFILT = 8 
} EPWM_ActionQualifierTriggerSource;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO = 0,
    EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD = 2,
    EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA = 4,
    EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA = 6,
    EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB = 8,
    EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB = 10,
    EPWM_AQ_OUTPUT_ON_T1_COUNT_UP = 1,
    EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN = 3,
    EPWM_AQ_OUTPUT_ON_T2_COUNT_UP = 5,
    EPWM_AQ_OUTPUT_ON_T2_COUNT_DOWN = 7
} EPWM_ActionQualifierOutputEvent;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_AQ_OUTPUT_NO_CHANGE = 0,  
    EPWM_AQ_OUTPUT_LOW = 1,  
    EPWM_AQ_OUTPUT_HIGH = 2,  
    EPWM_AQ_OUTPUT_TOGGLE = 3   
} EPWM_ActionQualifierOutput;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_AQ_SW_DISABLED = 0,  
    EPWM_AQ_SW_OUTPUT_LOW = 1,  
    EPWM_AQ_SW_OUTPUT_HIGH = 2  
} EPWM_ActionQualifierSWOutput;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_AQ_OUTPUT_NO_CHANGE_ZERO = 0x0,
    EPWM_AQ_OUTPUT_LOW_ZERO = 0x1,
    EPWM_AQ_OUTPUT_HIGH_ZERO = 0x2,
    EPWM_AQ_OUTPUT_TOGGLE_ZERO = 0x3,
    EPWM_AQ_OUTPUT_NO_CHANGE_PERIOD = 0x0,
    EPWM_AQ_OUTPUT_LOW_PERIOD = 0x4,
    EPWM_AQ_OUTPUT_HIGH_PERIOD = 0x8,
    EPWM_AQ_OUTPUT_TOGGLE_PERIOD = 0xC,
    EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPA = 0x00,
    EPWM_AQ_OUTPUT_LOW_UP_CMPA = 0x10,
    EPWM_AQ_OUTPUT_HIGH_UP_CMPA = 0x20,
    EPWM_AQ_OUTPUT_TOGGLE_UP_CMPA = 0x30,
    EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPA = 0x00,
    EPWM_AQ_OUTPUT_LOW_DOWN_CMPA = 0x40,
    EPWM_AQ_OUTPUT_HIGH_DOWN_CMPA = 0x80,
    EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPA = 0xC0,
    EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPB = 0x000,
    EPWM_AQ_OUTPUT_LOW_UP_CMPB = 0x100,
    EPWM_AQ_OUTPUT_HIGH_UP_CMPB = 0x200,
    EPWM_AQ_OUTPUT_TOGGLE_UP_CMPB = 0x300,
    EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPB = 0x000,
    EPWM_AQ_OUTPUT_LOW_DOWN_CMPB = 0x400,
    EPWM_AQ_OUTPUT_HIGH_DOWN_CMPB = 0x800,
    EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPB = 0xC00
} EPWM_ActionQualifierEventAction;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_AQ_OUTPUT_NO_CHANGE_UP_T1 = 0x0,
    EPWM_AQ_OUTPUT_LOW_UP_T1 = 0x1,
    EPWM_AQ_OUTPUT_HIGH_UP_T1 = 0x2,
    EPWM_AQ_OUTPUT_TOGGLE_UP_T1 = 0x3,
    EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T1 = 0x0,
    EPWM_AQ_OUTPUT_LOW_DOWN_T1 = 0x4,
    EPWM_AQ_OUTPUT_HIGH_DOWN_T1 = 0x8,
    EPWM_AQ_OUTPUT_TOGGLE_DOWN_T1 = 0xC,
    EPWM_AQ_OUTPUT_NO_CHANGE_UP_T2 = 0x00,
    EPWM_AQ_OUTPUT_LOW_UP_T2 = 0x10,
    EPWM_AQ_OUTPUT_HIGH_UP_T2 = 0x20,
    EPWM_AQ_OUTPUT_TOGGLE_UP_T2 = 0x30,
    EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T2 = 0x00,
    EPWM_AQ_OUTPUT_LOW_DOWN_T2 = 0x40,
    EPWM_AQ_OUTPUT_HIGH_DOWN_T2 = 0x80,
    EPWM_AQ_OUTPUT_TOGGLE_DOWN_T2 = 0xC0
} EPWM_AdditionalActionQualifierEventAction;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_AQ_OUTPUT_A = 0, 
    EPWM_AQ_OUTPUT_B = 4  
} EPWM_ActionQualifierOutputModule;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO = 0,
    EPWM_AQ_SW_SH_LOAD_ON_CNTR_PERIOD = 1,
    EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO_PERIOD = 2,
    EPWM_AQ_SW_IMMEDIATE_LOAD = 3
} EPWM_ActionQualifierContForce;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_DB_OUTPUT_A = 1, 
    EPWM_DB_OUTPUT_B = 0  
} EPWM_DeadBandOutput;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_DB_RED = 1, 
    EPWM_DB_FED = 0  
} EPWM_DeadBandDelayMode;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_DB_POLARITY_ACTIVE_HIGH = 0, 
    EPWM_DB_POLARITY_ACTIVE_LOW  = 1  
} EPWM_DeadBandPolarity;
 
//*****************************************************************************
//
// Values that can be passed to EPWM_setRisingEdgeDeadBandDelayInput(),
// EPWM_setFallingEdgeDeadBandDelayInput() as the input parameter.
//
//*****************************************************************************
#define EPWM_DB_INPUT_EPWMA       (0U)
#define EPWM_DB_INPUT_EPWMB       (1U)
#define EPWM_DB_INPUT_DB_RED      (2U)
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_DB_LOAD_ON_CNTR_ZERO = 0,
    EPWM_DB_LOAD_ON_CNTR_PERIOD = 1,
    EPWM_DB_LOAD_ON_CNTR_ZERO_PERIOD = 2,
    EPWM_DB_LOAD_FREEZE = 3
} EPWM_DeadBandControlLoadMode;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_RED_LOAD_ON_CNTR_ZERO = 0,
    EPWM_RED_LOAD_ON_CNTR_PERIOD = 1,
    EPWM_RED_LOAD_ON_CNTR_ZERO_PERIOD = 2,
    EPWM_RED_LOAD_FREEZE = 3
} EPWM_RisingEdgeDelayLoadMode;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_FED_LOAD_ON_CNTR_ZERO = 0,
    EPWM_FED_LOAD_ON_CNTR_PERIOD = 1,
    EPWM_FED_LOAD_ON_CNTR_ZERO_PERIOD = 2,
    EPWM_FED_LOAD_FREEZE = 3
} EPWM_FallingEdgeDelayLoadMode;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_DB_COUNTER_CLOCK_FULL_CYCLE = 0,
    EPWM_DB_COUNTER_CLOCK_HALF_CYCLE = 1
} EPWM_DeadBandClockMode;
 
//
// Trip Zone
//
//*****************************************************************************
//
// Values that can be passed to EPWM_enableTripZoneSignals() and
// EPWM_disableTripZoneSignals() as the tzSignal parameter.
//
//*****************************************************************************
#define EPWM_TZ_SIGNAL_CBC1          (0x1U)
#define EPWM_TZ_SIGNAL_CBC2          (0x2U)
#define EPWM_TZ_SIGNAL_CBC3          (0x4U)
#define EPWM_TZ_SIGNAL_CBC4          (0x8U)
#define EPWM_TZ_SIGNAL_CBC5          (0x10U)
#define EPWM_TZ_SIGNAL_CBC6          (0x20U)
#define EPWM_TZ_SIGNAL_DCAEVT2       (0x40U)
#define EPWM_TZ_SIGNAL_DCBEVT2       (0x80U)
#define EPWM_TZ_SIGNAL_OSHT1         (0x100U)
#define EPWM_TZ_SIGNAL_OSHT2         (0x200U)
#define EPWM_TZ_SIGNAL_OSHT3         (0x400U)
#define EPWM_TZ_SIGNAL_OSHT4         (0x800U)
#define EPWM_TZ_SIGNAL_OSHT5         (0x1000U)
#define EPWM_TZ_SIGNAL_OSHT6         (0x2000U)
#define EPWM_TZ_SIGNAL_DCAEVT1       (0x4000U)
#define EPWM_TZ_SIGNAL_DCBEVT1       (0x8000U)
#define EPWM_TZ_SIGNAL_CAPEVT_OST    (0x10000U)
#define EPWM_TZ_SIGNAL_CAPEVT_CBC    (0x1000000U)
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_TZ_DC_OUTPUT_A1 = 0, 
    EPWM_TZ_DC_OUTPUT_A2 = 3, 
    EPWM_TZ_DC_OUTPUT_B1 = 6, 
    EPWM_TZ_DC_OUTPUT_B2 = 9  
} EPWM_TripZoneDigitalCompareOutput;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_TZ_EVENT_DC_DISABLED = 0,  
    EPWM_TZ_EVENT_DCXH_LOW = 1,  
    EPWM_TZ_EVENT_DCXH_HIGH = 2,  
    EPWM_TZ_EVENT_DCXL_LOW = 3,  
    EPWM_TZ_EVENT_DCXL_HIGH = 4,  
    EPWM_TZ_EVENT_DCXL_HIGH_DCXH_LOW = 5  
} EPWM_TripZoneDigitalCompareOutputEvent;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_TZ_ACTION_EVENT_TZA = 0,     
    EPWM_TZ_ACTION_EVENT_TZB = 2,     
    EPWM_TZ_ACTION_EVENT_DCAEVT1 = 4, 
    EPWM_TZ_ACTION_EVENT_DCAEVT2 = 6, 
    EPWM_TZ_ACTION_EVENT_DCBEVT1 = 8, 
    EPWM_TZ_ACTION_EVENT_DCBEVT2 = 10 
} EPWM_TripZoneEvent;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_TZ_ACTION_HIGH_Z = 0,  
    EPWM_TZ_ACTION_HIGH = 1,  
    EPWM_TZ_ACTION_LOW = 2,  
    EPWM_TZ_ACTION_DISABLE = 3  
} EPWM_TripZoneAction;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_TZ_ADV_ACTION_EVENT_TZB_D = 9,
    EPWM_TZ_ADV_ACTION_EVENT_TZB_U = 6,
    EPWM_TZ_ADV_ACTION_EVENT_TZA_D = 3,
    EPWM_TZ_ADV_ACTION_EVENT_TZA_U = 0
} EPWM_TripZoneAdvancedEvent;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_TZ_ADV_ACTION_HIGH_Z = 0,  
    EPWM_TZ_ADV_ACTION_HIGH = 1,  
    EPWM_TZ_ADV_ACTION_LOW = 2,  
    EPWM_TZ_ADV_ACTION_TOGGLE = 3,  
    EPWM_TZ_ADV_ACTION_DISABLE = 7  
} EPWM_TripZoneAdvancedAction;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_U = 0,
    EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_D = 3,
    EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U = 6,
    EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D = 9
} EPWM_TripZoneAdvDigitalCompareEvent;
 
//*****************************************************************************
//
// Values that can be passed to EPWM_enableTripZoneInterrupt()and
// EPWM_disableTripZoneInterrupt() as the tzInterrupt parameter .
//
//*****************************************************************************
#define EPWM_TZ_INTERRUPT_CBC      (0x2U)
#define EPWM_TZ_INTERRUPT_OST      (0x4U)
#define EPWM_TZ_INTERRUPT_DCAEVT1  (0x8U)
#define EPWM_TZ_INTERRUPT_DCAEVT2  (0x10U)
#define EPWM_TZ_INTERRUPT_DCBEVT1  (0x20U)
#define EPWM_TZ_INTERRUPT_DCBEVT2  (0x40U)
#define EPWM_TZ_INTERRUPT_CAPEVT   (0x80U)
 
//*****************************************************************************
//
// Values that can be returned by EPWM_getTripZoneFlagStatus() .
//
//*****************************************************************************
#define EPWM_TZ_FLAG_CBC      (0x2U)
#define EPWM_TZ_FLAG_OST      (0x4U)
#define EPWM_TZ_FLAG_DCAEVT1  (0x8U)
#define EPWM_TZ_FLAG_DCAEVT2  (0x10U)
#define EPWM_TZ_FLAG_DCBEVT1  (0x20U)
#define EPWM_TZ_FLAG_DCBEVT2  (0x40U)
#define EPWM_TZ_FLAG_CAPEVT   (0x80U)
 
//*****************************************************************************
//
// Value can be passed to EPWM_clearTripZoneFlag() as the
// tzInterrupt parameter and returned by EPWM_getTripZoneFlagStatus().
//
//*****************************************************************************
#define EPWM_TZ_INTERRUPT     (0x1U)
 
//*****************************************************************************
//
// Values that can be passed to EPWM_clearCycleByCycleTripZoneFlag()
// as the tzCbcFlag parameter and returned by
// EPWM_getCycleByCycleTripZoneFlagStatus().
//
//*****************************************************************************
#define EPWM_TZ_CBC_FLAG_1        (0x1U)
#define EPWM_TZ_CBC_FLAG_2        (0x2U)
#define EPWM_TZ_CBC_FLAG_3        (0x4U)
#define EPWM_TZ_CBC_FLAG_4        (0x8U)
#define EPWM_TZ_CBC_FLAG_5        (0x10U)
#define EPWM_TZ_CBC_FLAG_6        (0x20U)
#define EPWM_TZ_CBC_FLAG_DCAEVT2  (0x40U)
#define EPWM_TZ_CBC_FLAG_DCBEVT2  (0x80U)
#define EPWM_TZ_CBC_FLAG_CAPEVT   (0x100U)
 
//*****************************************************************************
//
// Values that can be passed to EPWM_clearOneShotTripZoneFlag() as
// the tzCbcFlag parameter and returned by the
// EPWM_getOneShotTripZoneFlagStatus() .
//
//*****************************************************************************
#define EPWM_TZ_OST_FLAG_OST1      (0x1U)
#define EPWM_TZ_OST_FLAG_OST2      (0x2U)
#define EPWM_TZ_OST_FLAG_OST3      (0x4U)
#define EPWM_TZ_OST_FLAG_OST4      (0x8U)
#define EPWM_TZ_OST_FLAG_OST5      (0x10U)
#define EPWM_TZ_OST_FLAG_OST6      (0x20U)
#define EPWM_TZ_OST_FLAG_DCAEVT1   (0x40U)
#define EPWM_TZ_OST_FLAG_DCBEVT1   (0x80U)
#define EPWM_TZ_OST_FLAG_CAPEVT    (0x100U)
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO = 0,
    EPWM_TZ_CBC_PULSE_CLR_CNTR_PERIOD = 1,
    EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD = 2
} EPWM_CycleByCycleTripZoneClearMode;
 
//*****************************************************************************
//
// Values that can be passed to EPWM_forceTripZoneEvent() as the
// tzForceEvent parameter.
//
//*****************************************************************************
#define EPWM_TZ_FORCE_EVENT_CBC      (0x2U)
#define EPWM_TZ_FORCE_EVENT_OST      (0x4U)
#define EPWM_TZ_FORCE_EVENT_DCAEVT1  (0x8U)
#define EPWM_TZ_FORCE_EVENT_DCAEVT2  (0x10U)
#define EPWM_TZ_FORCE_EVENT_DCBEVT1  (0x20U)
#define EPWM_TZ_FORCE_EVENT_DCBEVT2  (0x40U)
#define EPWM_TZ_FORCE_EVENT_CAPEVT   (0x80U)
 
//*****************************************************************************
//
// Values that can be passed to EPWM_enableTripZoneOutput() and
// EPWM_disableTripZoneOutput as the tzOutput parameter.
//
//*****************************************************************************
#define EPWM_TZ_SELECT_TRIPOUT_OST        (0x1)
#define EPWM_TZ_SELECT_TRIPOUT_CBC        (0x2)
#define EPWM_TZ_SELECT_TRIPOUT_TZ1        (0x4)
#define EPWM_TZ_SELECT_TRIPOUT_TZ2        (0x8)
#define EPWM_TZ_SELECT_TRIPOUT_TZ3        (0x10)
#define EPWM_TZ_SELECT_TRIPOUT_TZ4        (0x20)
#define EPWM_TZ_SELECT_TRIPOUT_TZ5        (0x40)
#define EPWM_TZ_SELECT_TRIPOUT_TZ6        (0x80)
#define EPWM_TZ_SELECT_TRIPOUT_DCAEVT1    (0x100)
#define EPWM_TZ_SELECT_TRIPOUT_DCAEVT2    (0x200)
#define EPWM_TZ_SELECT_TRIPOUT_DCBEVT1    (0x400)
#define EPWM_TZ_SELECT_TRIPOUT_DCBEVT2    (0x800)
#define EPWM_TZ_SELECT_TRIPOUT_CAPEVT     (0x1000)
 
//*****************************************************************************
//
// Values that can be passed to EPWM_setInterruptSource() as the
// interruptSource parameter.
//
//*****************************************************************************
#define EPWM_INT_TBCTR_ZERO            (1U)
#define EPWM_INT_TBCTR_PERIOD          (2U)
#define EPWM_INT_TBCTR_ETINTMIX        (3U)
#define EPWM_INT_TBCTR_U_CMPA          (4U)
#define EPWM_INT_TBCTR_U_CMPC          (8U)
#define EPWM_INT_TBCTR_D_CMPA          (5U)
#define EPWM_INT_TBCTR_D_CMPC          (10U)
#define EPWM_INT_TBCTR_U_CMPB          (6U)
#define EPWM_INT_TBCTR_U_CMPD          (12U)
#define EPWM_INT_TBCTR_D_CMPB          (7U)
#define EPWM_INT_TBCTR_D_CMPD          (14U)
 
//*****************************************************************************
//
// Values that can be passed to EPWM_setInterruptSource() and
// EPWM_setADCTriggerSource() as the mixedSource parameter.
//
//*****************************************************************************
#define EPWM_INT_MIX_TBCTR_ZERO            (0x1)
#define EPWM_INT_MIX_TBCTR_PERIOD          (0x2)
#define EPWM_INT_MIX_TBCTR_U_CMPA          (0x4)
#define EPWM_INT_MIX_TBCTR_D_CMPA          (0x8)
#define EPWM_INT_MIX_TBCTR_U_CMPB          (0x10)
#define EPWM_INT_MIX_TBCTR_D_CMPB          (0x20)
#define EPWM_INT_MIX_TBCTR_U_CMPC          (0x40)
#define EPWM_INT_MIX_TBCTR_D_CMPC          (0x80)
#define EPWM_INT_MIX_TBCTR_U_CMPD          (0x100)
#define EPWM_INT_MIX_TBCTR_D_CMPD          (0x200)
#define EPWM_INT_MIX_DCAEVT1               (0x400)
 
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_SOC_A = 0,  
    EPWM_SOC_B = 1   
} EPWM_ADCStartOfConversionType;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_SOC_DCxEVT1 = 0,
    EPWM_SOC_TBCTR_ZERO = 1,
    EPWM_SOC_TBCTR_PERIOD = 2,
    EPWM_SOC_TBCTR_MIXED_EVENT = 3,
    EPWM_SOC_TBCTR_U_CMPA = 4,
    EPWM_SOC_TBCTR_U_CMPC = 8,
    EPWM_SOC_TBCTR_D_CMPA = 5,
    EPWM_SOC_TBCTR_D_CMPC = 10,
    EPWM_SOC_TBCTR_U_CMPB = 6,
    EPWM_SOC_TBCTR_U_CMPD = 12,
    EPWM_SOC_TBCTR_D_CMPB = 7,
    EPWM_SOC_TBCTR_D_CMPD = 14
} EPWM_ADCStartOfConversionSource;
 
//
// Digital Compare Module
//
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_DC_TYPE_DCAH = 0,  
    EPWM_DC_TYPE_DCAL = 1,  
    EPWM_DC_TYPE_DCBH = 2,  
    EPWM_DC_TYPE_DCBL = 3   
} EPWM_DigitalCompareType;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_DC_TRIP_TRIPIN1 = 0,  
    EPWM_DC_TRIP_TRIPIN2 = 1,  
    EPWM_DC_TRIP_TRIPIN3 = 2,  
    EPWM_DC_TRIP_TRIPIN4 = 3,  
    EPWM_DC_TRIP_TRIPIN5 = 4,  
    EPWM_DC_TRIP_TRIPIN6 = 5,  
    EPWM_DC_TRIP_TRIPIN7 = 6,  
    EPWM_DC_TRIP_TRIPIN8 = 7,  
    EPWM_DC_TRIP_TRIPIN9 = 8,  
    EPWM_DC_TRIP_TRIPIN10 = 9,  
    EPWM_DC_TRIP_TRIPIN11 = 10,  
    EPWM_DC_TRIP_TRIPIN12 = 11,  
    EPWM_DC_TRIP_TRIPIN13 = 12,  
    EPWM_DC_TRIP_TRIPIN14 = 13,  
    EPWM_DC_TRIP_TRIPIN15 = 14,  
    EPWM_DC_TRIP_COMBINATION = 15 
} EPWM_DigitalCompareTripInput;
 
//*****************************************************************************
//
// Values that can be passed to EPWM_enableDigitalCompareTripCombinationInput()
// EPWM_disableDigitalCompareTripCombinationInput() as the tripInput
// parameter.
//
//*****************************************************************************
#define EPWM_DC_COMBINATIONAL_TRIPIN1   (0x1U)
#define EPWM_DC_COMBINATIONAL_TRIPIN2   (0x2U)
#define EPWM_DC_COMBINATIONAL_TRIPIN3   (0x4U)
#define EPWM_DC_COMBINATIONAL_TRIPIN4   (0x8U)
#define EPWM_DC_COMBINATIONAL_TRIPIN5   (0x10U)
#define EPWM_DC_COMBINATIONAL_TRIPIN6   (0x20U)
#define EPWM_DC_COMBINATIONAL_TRIPIN7   (0x40U)
#define EPWM_DC_COMBINATIONAL_TRIPIN8   (0x80U)
#define EPWM_DC_COMBINATIONAL_TRIPIN9   (0x100U)
#define EPWM_DC_COMBINATIONAL_TRIPIN10  (0x200U)
#define EPWM_DC_COMBINATIONAL_TRIPIN11  (0x400U)
#define EPWM_DC_COMBINATIONAL_TRIPIN12  (0x800U)
#define EPWM_DC_COMBINATIONAL_TRIPIN13  (0x1000U)
#define EPWM_DC_COMBINATIONAL_TRIPIN14  (0x2000U)
#define EPWM_DC_COMBINATIONAL_TRIPIN15  (0x4000U)
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_DC_WINDOW_START_TBCTR_PERIOD = 0,
    EPWM_DC_WINDOW_START_TBCTR_ZERO = 1,
    EPWM_DC_WINDOW_START_TBCTR_ZERO_PERIOD = 2,
    EPWM_DC_WINDOW_START_TBCTR_BLANK_PULSE_MIX = 3
} EPWM_DigitalCompareBlankingPulse;
 
//*****************************************************************************
//
// Values that can be passed to EPWM_setDigitalCompareBlankingEvent()
// as the mixedSource parameter.
//
//*****************************************************************************
#define EPWM_DC_TBCTR_ZERO            (0x1)
#define EPWM_DC_TBCTR_PERIOD          (0x2)
#define EPWM_DC_TBCTR_U_CMPA          (0x4)
#define EPWM_DC_TBCTR_D_CMPA          (0x8)
#define EPWM_DC_TBCTR_U_CMPB          (0x10)
#define EPWM_DC_TBCTR_D_CMPB          (0x20)
#define EPWM_DC_TBCTR_U_CMPC          (0x40)
#define EPWM_DC_TBCTR_D_CMPC          (0x80)
#define EPWM_DC_TBCTR_U_CMPD          (0x100)
#define EPWM_DC_TBCTR_D_CMPD          (0x200)
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_DC_WINDOW_SOURCE_DCAEVT1 = 0, 
    EPWM_DC_WINDOW_SOURCE_DCAEVT2 = 1, 
    EPWM_DC_WINDOW_SOURCE_DCBEVT1 = 2, 
    EPWM_DC_WINDOW_SOURCE_DCBEVT2 = 3  
} EPWM_DigitalCompareFilterInput;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_DC_MODULE_A = 0,  
    EPWM_DC_MODULE_B = 1   
} EPWM_DigitalCompareModule;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_DC_EVENT_1 = 0,  
    EPWM_DC_EVENT_2 = 1   
} EPWM_DigitalCompareEvent;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL = 0,
    EPWM_DC_EVENT_SOURCE_FILT_SIGNAL = 1
} EPWM_DigitalCompareEventSource;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_DC_EVENT_INPUT_SYNCED = 0,
    EPWM_DC_EVENT_INPUT_NOT_SYNCED = 1
} EPWM_DigitalCompareSyncMode;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_DC_CBC_LATCH_DISABLED = 0x0,
    EPWM_DC_CBC_LATCH_ENABLED = 0x1
} EPWM_DigitalCompareCBCLatchMode;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_DC_CBC_LATCH_CLR_CNTR_ZERO = 0x0,
    EPWM_DC_CBC_LATCH_CLR_ON_CNTR_PERIOD = 0x1,
    EPWM_DC_CBC_LATCH_CLR_ON_CNTR_ZERO_PERIOD = 0x2
} EPWM_DigitalCompareCBCLatchClearEvent;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_GL_LOAD_PULSE_CNTR_ZERO = 0x0,
    EPWM_GL_LOAD_PULSE_CNTR_PERIOD = 0x1,
    EPWM_GL_LOAD_PULSE_CNTR_ZERO_PERIOD = 0x2,
    EPWM_GL_LOAD_PULSE_SYNC = 0x3,
    EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_ZERO = 0x4,
    EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_PERIOD = 0x5,
    EPWM_GL_LOAD_PULSE_SYNC_CNTR_ZERO_PERIOD = 0x6,
    EPWM_GL_LOAD_PULSE_CNTR_CMPC_U = 0x8,
    EPWM_GL_LOAD_PULSE_CNTR_CMPC_D = 0x9,
    EPWM_GL_LOAD_PULSE_CNTR_CMPD_U = 0xA,
    EPWM_GL_LOAD_PULSE_CNTR_CMPD_D = 0xB,
    EPWM_GL_LOAD_PULSE_GLOBAL_FORCE = 0xF
} EPWM_GlobalLoadTrigger;
 
//*****************************************************************************
//
// Values that can be passed to EPWM_enableGlobalLoadRegisters(),
// EPWM_disableGlobalLoadRegisters() as theloadRegister parameter.
//
//*****************************************************************************
#define EPWM_GL_REGISTER_TBPRD_TBPRDHR  (0x1U)
#define EPWM_GL_REGISTER_CMPA_CMPAHR  (0x2U)
#define EPWM_GL_REGISTER_CMPB_CMPBHR  (0x4U)
#define EPWM_GL_REGISTER_CMPC  (0x8U)
#define EPWM_GL_REGISTER_CMPD  (0x10U)
#define EPWM_GL_REGISTER_DBRED_DBREDHR  (0x20U)
#define EPWM_GL_REGISTER_DBFED_DBFEDHR  (0x40U)
#define EPWM_GL_REGISTER_DBCTL  (0x80U)
#define EPWM_GL_REGISTER_AQCTLA_AQCTLA2  (0x100U)
#define EPWM_GL_REGISTER_AQCTLB_AQCTLB2  (0x200U)
#define EPWM_GL_REGISTER_AQCSFRC  (0x400U)
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_VALLEY_TRIGGER_EVENT_SOFTWARE = 0U,
    EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO = 1U,
    EPWM_VALLEY_TRIGGER_EVENT_CNTR_PERIOD = 2U,
    EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO_PERIOD = 3U,
    EPWM_VALLEY_TRIGGER_EVENT_DCAEVT1 = 4U,
    EPWM_VALLEY_TRIGGER_EVENT_DCAEVT2 = 5U,
    EPWM_VALLEY_TRIGGER_EVENT_DCBEVT1 = 6U,
    EPWM_VALLEY_TRIGGER_EVENT_DCBEVT2 = 7U
} EPWM_ValleyTriggerSource;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_VALLEY_COUNT_START_EDGE = 0,  
    EPWM_VALLEY_COUNT_STOP_EDGE = 1  
} EPWM_ValleyCounterEdge;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_VALLEY_DELAY_MODE_SW_DELAY = 0U,
    EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SW_DELAY = 1U,
    EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_1_SW_DELAY = 2U,
    EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_2_SW_DELAY = 3U,
    EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_4_SW_DELAY = 4U
} EPWM_ValleyDelayMode;
 
//
// DC Edge Filter
//
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_DC_EDGEFILT_MODE_RISING = 0,
    EPWM_DC_EDGEFILT_MODE_FALLING = 1,
    EPWM_DC_EDGEFILT_MODE_BOTH = 2
} EPWM_DigitalCompareEdgeFilterMode;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_DC_EDGEFILT_EDGECNT_0 = 0,
    EPWM_DC_EDGEFILT_EDGECNT_1 = 1,
    EPWM_DC_EDGEFILT_EDGECNT_2 = 2,
    EPWM_DC_EDGEFILT_EDGECNT_3 = 3,
    EPWM_DC_EDGEFILT_EDGECNT_4 = 4,
    EPWM_DC_EDGEFILT_EDGECNT_5 = 5,
    EPWM_DC_EDGEFILT_EDGECNT_6 = 6,
    EPWM_DC_EDGEFILT_EDGECNT_7 = 7
} EPWM_DigitalCompareEdgeFilterEdgeCount;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_REGISTER_GROUP_HR = 0x1,  
    EPWM_REGISTER_GROUP_GLOBAL_LOAD = 0x2,  
    EPWM_REGISTER_GROUP_TRIP_ZONE = 0x4,  
    EPWM_REGISTER_GROUP_TRIP_ZONE_CLEAR = 0x8,  
    EPWM_REGISTER_GROUP_DIGITAL_COMPARE = 0x10  
} EPWM_LockRegisterGroup;
 
//
// Minimum Dead Band
//
//*****************************************************************************
//
//
//*****************************************************************************
#define EPWM_MINDB_BLOCK_A    (0x0)
#define EPWM_MINDB_BLOCK_B    (0x1)
 
//*****************************************************************************
//
//
//*****************************************************************************
#define EPWM_MINDB_NO_INVERT    (0x0)
#define EPWM_MINDB_INVERT       (0x1)
 
//*****************************************************************************
//
//
//*****************************************************************************
#define EPWM_MINDB_INVERT_LOGICAL_AND    (0x0)
#define EPWM_MINDB_LOGICAL_OR            (0x1)
 
//*****************************************************************************
//
//
//*****************************************************************************
#define EPWM_MINDB_PWMB                 (0x0)
#define EPWM_MINDB_PWM_OUTXBAR_OUT1     (0x1)
#define EPWM_MINDB_PWM_OUTXBAR_OUT2     (0x2)
#define EPWM_MINDB_PWM_OUTXBAR_OUT3     (0x3)
#define EPWM_MINDB_PWM_OUTXBAR_OUT4     (0x4)
#define EPWM_MINDB_PWM_OUTXBAR_OUT5     (0x5)
#define EPWM_MINDB_PWM_OUTXBAR_OUT6     (0x6)
#define EPWM_MINDB_PWM_OUTXBAR_OUT7     (0x7)
#define EPWM_MINDB_PWM_OUTXBAR_OUT8     (0x8)
#define EPWM_MINDB_PWM_OUTXBAR_OUT9     (0x9)
#define EPWM_MINDB_PWM_OUTXBAR_OUT10    (0xA)
#define EPWM_MINDB_PWM_OUTXBAR_OUT11    (0xB)
#define EPWM_MINDB_PWM_OUTXBAR_OUT12    (0xC)
#define EPWM_MINDB_PWM_OUTXBAR_OUT13    (0xD)
#define EPWM_MINDB_PWM_OUTXBAR_OUT14    (0xE)
#define EPWM_MINDB_PWM_OUTXBAR_OUT15    (0xF)
 
//*****************************************************************************
//
//
//*****************************************************************************
#define EPWM_MINDB_BLOCKING_SIGNAL_SAME    (0x0)
#define EPWM_MINDB_BLOCKING_SIGNAL_DIFF    (0x1)
 
//*****************************************************************************
//
//
//*****************************************************************************
#define EPWM_MINDB_ICSS_XBAR_OUT0     (0x0)
#define EPWM_MINDB_ICSS_XBAR_OUT1     (0x1)
#define EPWM_MINDB_ICSS_XBAR_OUT2     (0x2)
#define EPWM_MINDB_ICSS_XBAR_OUT3     (0x3)
#define EPWM_MINDB_ICSS_XBAR_OUT4     (0x4)
#define EPWM_MINDB_ICSS_XBAR_OUT5     (0x5)
#define EPWM_MINDB_ICSS_XBAR_OUT6     (0x6)
#define EPWM_MINDB_ICSS_XBAR_OUT7     (0x7)
#define EPWM_MINDB_ICSS_XBAR_OUT8     (0x8)
#define EPWM_MINDB_ICSS_XBAR_OUT9     (0x9)
#define EPWM_MINDB_ICSS_XBAR_OUT10    (0xA)
#define EPWM_MINDB_ICSS_XBAR_OUT11    (0xB)
#define EPWM_MINDB_ICSS_XBAR_OUT12    (0xC)
#define EPWM_MINDB_ICSS_XBAR_OUT13    (0xD)
#define EPWM_MINDB_ICSS_XBAR_OUT14    (0xE)
#define EPWM_MINDB_ICSS_XBAR_OUT15    (0xF)
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    HRPWM_CHANNEL_A = 0, 
    HRPWM_CHANNEL_B = 8  
} HRPWM_Channel;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    HRPWM_MEP_CTRL_DISABLE = 0,
    HRPWM_MEP_CTRL_RISING_EDGE = 1,
    HRPWM_MEP_CTRL_FALLING_EDGE = 2,
    HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE = 3
} HRPWM_MEPEdgeMode;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    HRPWM_MEP_DUTY_PERIOD_CTRL = 0,
    HRPWM_MEP_PHASE_CTRL = 1
} HRPWM_MEPCtrlMode;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    HRPWM_LOAD_ON_CNTR_ZERO = 0,
    HRPWM_LOAD_ON_CNTR_PERIOD = 1,
    HRPWM_LOAD_ON_CNTR_ZERO_PERIOD = 2,
    HRPWM_LOAD_ON_CMPB_EQ = 3
} HRPWM_LoadMode;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    HRPWM_OUTPUT_ON_B_NORMAL = 0,
    HRPWM_OUTPUT_ON_B_INV_A  = 1
} HRPWM_ChannelBOutput;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    HRPWM_PWMSYNC_SOURCE_PERIOD = 0,
    HRPWM_PWMSYNC_SOURCE_ZERO = 1,
    HRPWM_PWMSYNC_SOURCE_COMPC_UP = 4,
    HRPWM_PWMSYNC_SOURCE_COMPC_DOWN = 5,
    HRPWM_PWMSYNC_SOURCE_COMPD_UP = 6,
    HRPWM_PWMSYNC_SOURCE_COMPD_DOWN = 7
} HRPWM_SyncPulseSource;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    HRPWM_COUNTER_COMPARE_A = 0, 
    HRPWM_COUNTER_COMPARE_B = 4  
} HRPWM_CounterCompareModule;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    HRPWM_DB_MEP_CTRL_DISABLE = 0,
    HRPWM_DB_MEP_CTRL_RED = 1,
    HRPWM_DB_MEP_CTRL_FED = 2,
    HRPWM_DB_MEP_CTRL_RED_FED = 3
} HRPWM_MEPDeadBandEdgeMode;
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    HRPWM_XCMP1_ACTIVE = 0,
    HRPWM_XCMP2_ACTIVE = 4,
    HRPWM_XCMP3_ACTIVE = 8,
    HRPWM_XCMP4_ACTIVE = 12,
    HRPWM_XCMP5_ACTIVE = 16,
    HRPWM_XCMP6_ACTIVE = 20,
    HRPWM_XCMP7_ACTIVE = 24,
    HRPWM_XCMP8_ACTIVE = 28,
    HRPWM_XTBPRD_ACTIVE = 32,
 
    HRPWM_XCMP1_SHADOW1 = 128,
    HRPWM_XCMP2_SHADOW1 = 132,
    HRPWM_XCMP3_SHADOW1 = 136,
    HRPWM_XCMP4_SHADOW1 = 140,
    HRPWM_XCMP5_SHADOW1 = 144,
    HRPWM_XCMP6_SHADOW1 = 148,
    HRPWM_XCMP7_SHADOW1 = 152,
    HRPWM_XCMP8_SHADOW1 = 156,
    HRPWM_XTBPRD_SHADOW1 = 160,
 
    HRPWM_XCMP1_SHADOW2 = 256,
    HRPWM_XCMP2_SHADOW2 = 260,
    HRPWM_XCMP3_SHADOW2 = 264,
    HRPWM_XCMP4_SHADOW2 = 268,
    HRPWM_XCMP5_SHADOW2 = 272,
    HRPWM_XCMP6_SHADOW2 = 276,
    HRPWM_XCMP7_SHADOW2 = 280,
    HRPWM_XCMP8_SHADOW2 = 284,
    HRPWM_XTBPRD_SHADOW2 = 288,
 
    HRPWM_XCMP1_SHADOW3 = 384,
    HRPWM_XCMP2_SHADOW3 = 388,
    HRPWM_XCMP3_SHADOW3 = 392,
    HRPWM_XCMP4_SHADOW3 = 396,
    HRPWM_XCMP5_SHADOW3 = 400,
    HRPWM_XCMP6_SHADOW3 = 404,
    HRPWM_XCMP7_SHADOW3 = 408,
    HRPWM_XCMP8_SHADOW3 = 412,
    HRPWM_XTBPRD_SHADOW3 = 416,
}HRPWM_XCMPReg;
//
//
//*****************************************************************************
#define EPWM_XCMP_ACTIVE   (0x0)
#define EPWM_XCMP_SHADOW1    (0x1)
#define EPWM_XCMP_SHADOW2    (0x2)
#define EPWM_XCMP_SHADOW3    (0x3)
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_XCMP1_ACTIVE = 0,
    EPWM_XCMP2_ACTIVE = 4,
    EPWM_XCMP3_ACTIVE = 8,
    EPWM_XCMP4_ACTIVE = 12,
    EPWM_XCMP5_ACTIVE = 16,
    EPWM_XCMP6_ACTIVE = 20,
    EPWM_XCMP7_ACTIVE = 24,
    EPWM_XCMP8_ACTIVE = 28,
    EPWM_XTBPRD_ACTIVE = 32,
 
    EPWM_XCMP1_SHADOW1 = 128,
    EPWM_XCMP2_SHADOW1 = 132,
    EPWM_XCMP3_SHADOW1 = 136,
    EPWM_XCMP4_SHADOW1 = 140,
    EPWM_XCMP5_SHADOW1 = 144,
    EPWM_XCMP6_SHADOW1 = 148,
    EPWM_XCMP7_SHADOW1 = 152,
    EPWM_XCMP8_SHADOW1 = 156,
    EPWM_XTBPRD_SHADOW1 = 160,
 
    EPWM_XCMP1_SHADOW2 = 256,
    EPWM_XCMP2_SHADOW2 = 260,
    EPWM_XCMP3_SHADOW2 = 264,
    EPWM_XCMP4_SHADOW2 = 268,
    EPWM_XCMP5_SHADOW2 = 272,
    EPWM_XCMP6_SHADOW2 = 276,
    EPWM_XCMP7_SHADOW2 = 280,
    EPWM_XCMP8_SHADOW2 = 284,
    EPWM_XTBPRD_SHADOW2 = 288,
 
    EPWM_XCMP1_SHADOW3 = 384,
    EPWM_XCMP2_SHADOW3 = 388,
    EPWM_XCMP3_SHADOW3 = 392,
    EPWM_XCMP4_SHADOW3 = 396,
    EPWM_XCMP5_SHADOW3 = 400,
    EPWM_XCMP6_SHADOW3 = 404,
    EPWM_XCMP7_SHADOW3 = 408,
    EPWM_XCMP8_SHADOW3 = 412,
    EPWM_XTBPRD_SHADOW3 = 416,
 
}EPWM_XCMPReg;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_CMPC_SHADOW1 = 0x0U,
    EPWM_CMPD_SHADOW1 = 0x4U,
    EPWM_CMPC_SHADOW2 = 0x80U,
    EPWM_CMPD_SHADOW2 = 0x84U,
    EPWM_CMPC_SHADOW3 = 0x100U,
    EPWM_CMPD_SHADOW3 = 0x104U
 
}EPWM_XCompareReg;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_XMAX_ACTIVE = 0x0U,
    EPWM_XMIN_ACTIVE = 0x2U,
    EPWM_XMAX_SHADOW1 = 0x80U,
    EPWM_XMIN_SHADOW1 = 0x82U,
    EPWM_XMAX_SHADOW2 = 0x100U,
    EPWM_XMIN_SHADOW2 = 0x102U,
    EPWM_XMAX_SHADOW3 = 0x180U,
    EPWM_XMIN_SHADOW3 = 0x182U,
 
}EPWM_XMinMaxReg;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP1 = 0,
    EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP2 = 2,
    EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP3 = 4,
    EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP4 = 6,
    EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5 = 8,
    EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6 = 10,
    EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7 = 12,
    EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8 = 14
} EPWM_XCMPActionQualifierOutputEvent;
 
//*****************************************************************************
//
//
//*****************************************************************************
 
typedef enum
{
    EPWM_XCMP_NONE_CMPA = 0,
    EPWM_XCMP_1_CMPA = 1,
    EPWM_XCMP_2_CMPA = 2,
    EPWM_XCMP_3_CMPA = 3,
    EPWM_XCMP_4_CMPA = 4,
    EPWM_XCMP_5_CMPA = 5,
    EPWM_XCMP_6_CMPA = 6,
    EPWM_XCMP_7_CMPA = 7,
    EPWM_XCMP_8_CMPA = 8
}EPWM_XCMP_ALLOC_CMPA;
 
//*****************************************************************************
//
//
//*****************************************************************************
 
typedef enum
{
    EPWM_XCMP_1_CMPB = 5,
    EPWM_XCMP_2_CMPB = 6,
    EPWM_XCMP_3_CMPB = 7,
    EPWM_XCMP_4_CMPB = 8
}EPWM_XCMP_ALLOC_CMPB;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EPWM_XCMP_XLOADCTL_LOADMODE_LOADONCE = 0,
    EPWM_XCMP_XLOADCTL_LOADMODE_LOADMULTIPLE = 1
}EPWM_XCMPXloadCtlLoadMode;
 
//*****************************************************************************
//
//
//*****************************************************************************
 
typedef enum
{
    EPWM_XCMP_XLOADCTL_SHDWLEVEL_0 = 0,
    EPWM_XCMP_XLOADCTL_SHDWLEVEL_1 = 1,
    EPWM_XCMP_XLOADCTL_SHDWLEVEL_2 = 2,
    EPWM_XCMP_XLOADCTL_SHDWLEVEL_3 = 3
}EPWM_XCMP_XLOADCTL_SHDWLEVEL;
 
//*****************************************************************************
//
//
//*****************************************************************************
 
typedef enum
{
    EPWM_XCMP_XLOADCTL_SHDWBUFPTR_NULL = 0,
    EPWM_XCMP_XLOADCTL_SHDWBUFPTR_ONE =  1,
    EPWM_XCMP_XLOADCTL_SHDWBUFPTR_TWO =  2,
    EPWM_XCMP_XLOADCTL_SHDWBUFPTR_THREE =3
}EPWM_XCMP_XLOADCTL_SHDWBUFPTR;
 
//
// Diode Emulation Logic
//
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum{
    EPWM_DIODE_EMULATION_CBC = 0,
    EPWM_DIODE_EMULATION_OST = 1
}EPWM_DiodeEmulationMode;
 
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum{
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT0 = 0x01,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT1 = 0x02,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT2 = 0x03,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT3 = 0x04,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT4 = 0x05,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT5 = 0x06,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT6 = 0x07,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT7 = 0x08,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT8 = 0x09,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT9 = 0x0A,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT10 = 0x0B,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT11 = 0x0C,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT12 = 0x0D,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT13 = 0x0E,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT14 = 0x0F,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT15 = 0x10,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT16 = 0x11,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT17 = 0x12,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT18 = 0x13,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT19 = 0x14,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT20 = 0x15,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT21 = 0x16,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT22 = 0x17,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT23 = 0x18,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT24 = 0x19,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT25 = 0x1A,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT26 = 0x1B,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT27 = 0x1C,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT28 = 0x1D,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT29 = 0x1E,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT30 = 0x1F,
    EPWM_DE_TRIP_SRC_INPUTXBAR_OUT31 = 0x20,
    EPWM_DE_TRIP_SRC_CMPSSA0 = 0x21,
    EPWM_DE_TRIP_SRC_CMPSSA1 = 0x22,
    EPWM_DE_TRIP_SRC_CMPSSA2 = 0x23,
    EPWM_DE_TRIP_SRC_CMPSSA3 = 0x24,
    EPWM_DE_TRIP_SRC_CMPSSA4 = 0x25,
    EPWM_DE_TRIP_SRC_CMPSSA5 = 0x26,
    EPWM_DE_TRIP_SRC_CMPSSA6 = 0x27,
    EPWM_DE_TRIP_SRC_CMPSSA7 = 0x28,
    EPWM_DE_TRIP_SRC_CMPSSA8 = 0x29,
    EPWM_DE_TRIP_SRC_CMPSSA9 = 0x2A,
    EPWM_DE_TRIP_SRC_CMPSSB0 = 0x31,
    EPWM_DE_TRIP_SRC_CMPSSB1 = 0x32,
    EPWM_DE_TRIP_SRC_CMPSSB2 = 0x33,
    EPWM_DE_TRIP_SRC_CMPSSB3 = 0x34,
    EPWM_DE_TRIP_SRC_CMPSSB4 = 0x35,
    EPWM_DE_TRIP_SRC_CMPSSB5 = 0x36,
    EPWM_DE_TRIP_SRC_CMPSSB6 = 0x37,
    EPWM_DE_TRIP_SRC_CMPSSB7 = 0x38,
    EPWM_DE_TRIP_SRC_CMPSSB8 = 0x39,
    EPWM_DE_TRIP_SRC_CMPSSB9 = 0x3A
}EPWM_DiodeEmulationTripSource;
 
 
typedef enum{
 
    EPWM_DE_SYNC_TRIPHorL = 0x00,
    EPWM_DE_SYNC_INV_TRIPHorL = 0x01,
    EPWM_DE_LOW = 0x10,
    EPWM_DE_HIGH = 0x11
}EPWM_DiodeEmulationSignal;
//*****************************************************************************
//
//
//*****************************************************************************
#define EPWM_DE_CHANNEL_A    (0x0)
#define EPWM_DE_CHANNEL_B    (0x1)
 
//*****************************************************************************
//
//
//*****************************************************************************
 
#define EPWM_DE_COUNT_UP    (0x0)
#define EPWM_DE_COUNT_DOWN    (0x1)
 
//*****************************************************************************
//
//
//*****************************************************************************
 
#define EPWM_DE_TRIPL    (0x1)
#define EPWM_DE_TRIPH    (0x0)
 
 
 
//*****************************************************************************
//
//
//*****************************************************************************
#define EPWM_DCxCTL_STEP (CSL_EPWM_DCBCTL - CSL_EPWM_DCACTL)
#define EPWM_DCxxTRIPSEL (CSL_EPWM_DCALTRIPSEL - CSL_EPWM_DCAHTRIPSEL)
#define EPWM_XREGSHDWxSTS_STEP (CSL_EPWM_XREGSHDW2STS-CSL_EPWM_XREGSHDW1STS)
#define EPWM_XCMPx_ACTIVE_STEP (CSL_EPWM_XCMP2_ACTIVE-CSL_EPWM_XCMP1_ACTIVE)
#define EPWM_XCMPx_STEP (CSL_EPWM_XCMP1_SHDW2-CSL_EPWM_XCMP1_SHDW1)
#define EPWM_XCMPx_SHDWx_STEP (CSL_EPWM_XCMP2_SHDW1-CSL_EPWM_XCMP1_SHDW1)
#define EPWM_LOCK_KEY (0xA5A50000U)
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef struct
{
    Float32                freqInHz;    
    Float32                dutyValA;    
    Float32                dutyValB;    
    bool                   invertSignalB; 
    Float32                sysClkInHz;  
    EPWM_TimeBaseCountMode tbCtrMode;   
    EPWM_ClockDivider      tbClkDiv;    
    EPWM_HSClockDivider    tbHSClkDiv;  
} EPWM_SignalParams;
 
//
// Time Base Sub Module related APIs
//
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setTimeBaseCounter(uint32_t base, uint16_t count)
{
    //
    // Write to TBCTR register
    //
    HW_WR_REG16(base + CSL_EPWM_TBCTR, count);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setCountModeAfterSync(uint32_t base, EPWM_SyncCountMode mode)
{
    if(mode == EPWM_COUNT_MODE_UP_AFTER_SYNC)
    {
        //
        // Set PHSDIR bit
        //
        HW_WR_REG16(base + CSL_EPWM_TBCTL,
            (HW_RD_REG16(base + CSL_EPWM_TBCTL) |
            CSL_EPWM_TBCTL_PHSDIR_MASK));
    }
    else
    {
        //
        // Clear PHSDIR bit
        //
        HW_WR_REG16(base + CSL_EPWM_TBCTL,
            (HW_RD_REG16(base + CSL_EPWM_TBCTL) &
            ~CSL_EPWM_TBCTL_PHSDIR_MASK));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setClockPrescaler(uint32_t base, EPWM_ClockDivider prescaler,
                       EPWM_HSClockDivider highSpeedPrescaler)
{
    //
    // Write to CLKDIV and HSPCLKDIV bit
    //
    HW_WR_REG16(base + CSL_EPWM_TBCTL,
        ((HW_RD_REG16(base + CSL_EPWM_TBCTL) &
        ~(CSL_EPWM_TBCTL_CLKDIV_MASK | CSL_EPWM_TBCTL_HSPCLKDIV_MASK)) |
        (((uint16_t)prescaler << CSL_EPWM_TBCTL_CLKDIV_SHIFT) |
        ((uint16_t)highSpeedPrescaler << CSL_EPWM_TBCTL_HSPCLKDIV_SHIFT))));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_forceSyncPulse(uint32_t base)
{
    //
    // Set SWFSYNC bit
    //
    HW_WR_REG16(base + CSL_EPWM_TBCTL,
        HW_RD_REG16(base + CSL_EPWM_TBCTL) | CSL_EPWM_TBCTL_SWFSYNC_MASK);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setSyncInPulseSource(uint32_t base, EPWM_SyncInPulseSource source)
{
    //
    // Set EPWM Sync-In Source Mode.
    //
    HW_WR_REG16(base + CSL_EPWM_EPWMSYNCINSEL,
        ((HW_RD_REG16(base + CSL_EPWM_EPWMSYNCINSEL) &
        (~CSL_EPWM_EPWMSYNCINSEL_SEL_MASK)) |
        ((uint16_t)source & CSL_EPWM_EPWMSYNCINSEL_SEL_MASK)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_enableSyncOutPulseSource(uint32_t base, uint16_t source)
{
    //
    // Check the arguments
    //
    DebugP_assert(source <= EPWM_SYNC_OUT_SOURCE_M);
 
    //
    // Enable selected EPWM Sync-Out Sources.
    //
    HW_WR_REG16(base + CSL_EPWM_EPWMSYNCOUTEN,
        (HW_RD_REG16(base + CSL_EPWM_EPWMSYNCOUTEN) |
        (uint16_t)source));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disableSyncOutPulseSource(uint32_t base, uint16_t source)
{
    //
    // Check the arguments
    //
    DebugP_assert(source <= EPWM_SYNC_OUT_SOURCE_M);
 
    //
    // Disable EPWM Sync-Out Sources.
    //
    HW_WR_REG16(base + CSL_EPWM_EPWMSYNCOUTEN,
        (HW_RD_REG16(base + CSL_EPWM_EPWMSYNCOUTEN) &
        ~((uint16_t)source)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setOneShotSyncOutTrigger(uint32_t base,
                              EPWM_OneShotSyncOutTrigger trigger)
{
    //
    // Set source for One-Shot Sync-Out Pulse.
    //
    HW_WR_REG16(base + CSL_EPWM_TBCTL3,
        ((HW_RD_REG16(base + CSL_EPWM_TBCTL3) &
        ~(CSL_EPWM_TBCTL3_OSSFRCEN_MASK)) |
        (uint16_t)trigger));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setPeriodLoadMode(uint32_t base, EPWM_PeriodLoadMode loadMode)
{
    if(loadMode == EPWM_PERIOD_SHADOW_LOAD)
    {
        //
        // Clear PRDLD
        //
        HW_WR_REG16(base + CSL_EPWM_TBCTL,
            (HW_RD_REG16(base + CSL_EPWM_TBCTL) & ~CSL_EPWM_TBCTL_PRDLD_MASK));
    }
    else
    {
        //
        // Set PRDLD
        //
        HW_WR_REG16(base + CSL_EPWM_TBCTL,
            (HW_RD_REG16(base + CSL_EPWM_TBCTL) | CSL_EPWM_TBCTL_PRDLD_MASK));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_enablePhaseShiftLoad(uint32_t base)
{
    //
    // Set PHSEN bit
    //
    HW_WR_REG16(base + CSL_EPWM_TBCTL,
        (HW_RD_REG16(base + CSL_EPWM_TBCTL) | CSL_EPWM_TBCTL_PHSEN_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disablePhaseShiftLoad(uint32_t base)
{
    //
    // Clear PHSEN bit
    //
    HW_WR_REG16(base + CSL_EPWM_TBCTL,
        (HW_RD_REG16(base + CSL_EPWM_TBCTL) & ~CSL_EPWM_TBCTL_PHSEN_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setTimeBaseCounterMode(uint32_t base, EPWM_TimeBaseCountMode counterMode)
{
    //
    // Write to CTRMODE bit
    //
    HW_WR_REG16(base + CSL_EPWM_TBCTL,
        ((HW_RD_REG16(base + CSL_EPWM_TBCTL) &
        ~(CSL_EPWM_TBCTL_CTRMODE_MASK)) | ((uint16_t)counterMode)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_selectPeriodLoadEvent(uint32_t base,
                           EPWM_PeriodShadowLoadMode shadowLoadMode)
{
    //
    // Write to PRDLDSYNC bit
    //
    HW_WR_REG16(base + CSL_EPWM_TBCTL2,
        ((HW_RD_REG16(base + CSL_EPWM_TBCTL2) &
        ~(CSL_EPWM_TBCTL2_PRDLDSYNC_MASK)) |
        ((uint16_t)shadowLoadMode << CSL_EPWM_TBCTL2_PRDLDSYNC_SHIFT)));
}
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_enableOneShotSync(uint32_t base)
{
    //
    // Set OSHTSYNCMODE bit
    //
    HW_WR_REG16(base + CSL_EPWM_TBCTL2,
        (HW_RD_REG16(base + CSL_EPWM_TBCTL2) |
        CSL_EPWM_TBCTL2_OSHTSYNCMODE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disableOneShotSync(uint32_t base)
{
    //
    // Clear OSHTSYNCMODE bit
    //
    HW_WR_REG16(base + CSL_EPWM_TBCTL2,
        (HW_RD_REG16(base + CSL_EPWM_TBCTL2) &
        ~CSL_EPWM_TBCTL2_OSHTSYNCMODE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_startOneShotSync(uint32_t base)
{
    //
    // Set OSHTSYNC bit
    //
    HW_WR_REG16(base + CSL_EPWM_TBCTL2,
        (HW_RD_REG16(base + CSL_EPWM_TBCTL2) | CSL_EPWM_TBCTL2_OSHTSYNC_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t
EPWM_getTimeBaseCounterValue(uint32_t base)
{
    //
    // Returns TBCTR value
    //
    return(HW_RD_REG16(base + CSL_EPWM_TBCTR));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline bool
EPWM_getTimeBaseCounterOverflowStatus(uint32_t base)
{
    //
    // Return true if CTRMAX bit is set, false otherwise
    //
    return(((HW_RD_REG16(base + CSL_EPWM_TBSTS) &
            CSL_EPWM_TBSTS_CTRMAX_MASK) ==
            CSL_EPWM_TBSTS_CTRMAX_MASK) ? true : false);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_clearTimeBaseCounterOverflowEvent(uint32_t base)
{
    //
    // Set CTRMAX bit
    //
    HW_WR_REG16(base + CSL_EPWM_TBSTS,
        (HW_RD_REG16(base + CSL_EPWM_TBSTS) | CSL_EPWM_TBSTS_CTRMAX_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline bool
EPWM_getSyncStatus(uint32_t base)
{
    //
    // Return true if SYNCI bit is set, false otherwise
    //
    return(((HW_RD_REG16(base + CSL_EPWM_TBSTS) & CSL_EPWM_TBSTS_SYNCI_MASK) ==
            CSL_EPWM_TBSTS_SYNCI_MASK) ? true : false);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_clearSyncEvent(uint32_t base)
{
    //
    // Set SYNCI bit
    //
    HW_WR_REG16(base + CSL_EPWM_TBSTS,
        (HW_RD_REG16(base + CSL_EPWM_TBSTS) | CSL_EPWM_TBSTS_SYNCI_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t
EPWM_getTimeBaseCounterDirection(uint32_t base)
{
    //
    // Return CTRDIR bit
    //
    return(HW_RD_REG16(base + CSL_EPWM_TBSTS) & CSL_EPWM_TBSTS_CTRDIR_MASK);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setPhaseShift(uint32_t base, uint16_t phaseCount)
{
    //
    // Write to TBPHS bit
    //
    HW_WR_REG32(base + CSL_EPWM_TBPHS,
        ((HW_RD_REG32(base + CSL_EPWM_TBPHS) &
        ~((uint32_t)CSL_EPWM_TBPHS_TBPHS_MASK)) |
        ((uint32_t)phaseCount << CSL_EPWM_TBPHS_TBPHS_SHIFT)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setTimeBasePeriod(uint32_t base, uint16_t periodCount)
{
    //
    // Write to TBPRD bit
    //
    HW_WR_REG16(base + CSL_EPWM_TBPRD, periodCount);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t
EPWM_getTimeBasePeriod(uint32_t base)
{
    //
    // Read from TBPRD bit
    //
    return(HW_RD_REG16(base + CSL_EPWM_TBPRD));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setupEPWMLinks(uint32_t base, EPWM_CurrentLink epwmLink,
                    EPWM_LinkComponent linkComp)
{
    uint32_t registerOffset;
 
    if((linkComp == EPWM_LINK_DBRED) || (linkComp == EPWM_LINK_DBFED))
    {
        registerOffset = base + CSL_EPWM_EPWMXLINK2;
        linkComp = (EPWM_LinkComponent) (linkComp - 1);
    }
    else if (linkComp == EPWM_LINK_XLOAD)
    {
         registerOffset = base + CSL_EPWM_EPWMXLINKXLOAD;
         linkComp = (EPWM_LinkComponent) (linkComp - 2);
    }
    else
    {
        registerOffset = base + CSL_EPWM_EPWMXLINK;
    }
 
    //
    // Configure EPWM links
    //
    HW_WR_REG32(registerOffset,
        ((HW_RD_REG32(registerOffset) &
        ~((uint32_t)CSL_EPWM_EPWMXLINK_TBPRDLINK_MASK << linkComp)) |
        ((uint32_t)epwmLink << linkComp)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setCounterCompareShadowLoadMode(uint32_t base,
                                     EPWM_CounterCompareModule compModule,
                                     EPWM_CounterCompareLoadMode loadMode)
{
    uint16_t syncModeOffset;
    uint16_t loadModeOffset;
    uint16_t shadowModeOffset;
    uint32_t registerOffset;
 
    if((compModule == EPWM_COUNTER_COMPARE_A) ||
       (compModule == EPWM_COUNTER_COMPARE_C))
    {
        syncModeOffset = CSL_EPWM_CMPCTL_LOADASYNC_SHIFT;
        loadModeOffset = CSL_EPWM_CMPCTL_LOADAMODE_SHIFT;
        shadowModeOffset = CSL_EPWM_CMPCTL_SHDWAMODE_SHIFT;
    }
    else
    {
        syncModeOffset = CSL_EPWM_CMPCTL_LOADBSYNC_SHIFT;
        loadModeOffset = CSL_EPWM_CMPCTL_LOADBMODE_SHIFT;
        shadowModeOffset = CSL_EPWM_CMPCTL_SHDWBMODE_SHIFT;
    }
 
    //
    // Get the register offset.  CSL_EPWM_CMPCTL for A&B or
    // CSL_EPWM_CMPCTL2 for C&D
    //
    if((compModule == EPWM_COUNTER_COMPARE_A) ||
       (compModule == EPWM_COUNTER_COMPARE_B))
    {
        registerOffset = base + CSL_EPWM_CMPCTL;
    }
    else
    {
        registerOffset = base + CSL_EPWM_CMPCTL2;
    }
 
    //
    // Set the appropriate sync and load mode bits and also enable shadow
    // load mode. Shadow to active load can also be frozen.
    //
    HW_WR_REG16(registerOffset,
        ((HW_RD_REG16(registerOffset) &
        ~((CSL_EPWM_CMPCTL_LOADASYNC_MAX << syncModeOffset) |
        (CSL_EPWM_CMPCTL_LOADAMODE_MAX << loadModeOffset) |
        (CSL_EPWM_CMPCTL_SHDWAMODE_MAX << shadowModeOffset))) |
        ((((uint16_t)loadMode >> 2U) << syncModeOffset) |
        (((uint16_t)loadMode & CSL_EPWM_CMPCTL_LOADASYNC_MAX) <<
        loadModeOffset))));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disableCounterCompareShadowLoadMode(uint32_t base,
                                         EPWM_CounterCompareModule compModule)
{
    uint16_t shadowModeOffset;
    uint32_t registerOffset;
 
    if((compModule == EPWM_COUNTER_COMPARE_A) ||
       (compModule == EPWM_COUNTER_COMPARE_C))
    {
        shadowModeOffset = CSL_EPWM_CMPCTL_SHDWAMODE_SHIFT;
    }
    else
    {
        shadowModeOffset = CSL_EPWM_CMPCTL_SHDWBMODE_SHIFT;
    }
 
    //
    // Get the register offset.  CSL_EPWM_CMPCTL for A&B or
    // CSL_EPWM_CMPCTL2 for C&D
    //
    if((compModule == EPWM_COUNTER_COMPARE_A) ||
       (compModule == EPWM_COUNTER_COMPARE_B))
    {
        registerOffset = base + CSL_EPWM_CMPCTL;
    }
    else
    {
        registerOffset = base + CSL_EPWM_CMPCTL2;
    }
 
    //
    // Disable shadow load mode.
    //
    HW_WR_REG16(registerOffset,
        (HW_RD_REG16(registerOffset) |
        (CSL_EPWM_CMPCTL_SHDWAMODE_MAX << shadowModeOffset)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setCounterCompareValue(uint32_t base, EPWM_CounterCompareModule compModule,
                            uint16_t compCount)
{
    uint32_t registerOffset;
 
    //
    // Get the register offset for the Counter compare
    //
    registerOffset = base + CSL_EPWM_CMPA + (uint16_t)compModule;
 
    //
    // Write to the counter compare registers.
    //
    if((compModule == EPWM_COUNTER_COMPARE_A) ||
        (compModule == EPWM_COUNTER_COMPARE_B))
    {
        //
        // Write to COMPA or COMPB bits
        //
        HW_WR_REG16(registerOffset + 0x2U, compCount);
    }
    else
    {
        //
        // Write to COMPC or COMPD bits
        //
        HW_WR_REG16(registerOffset, compCount);
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t
EPWM_getCounterCompareValue(uint32_t base, EPWM_CounterCompareModule compModule)
{
    uint32_t registerOffset;
    uint16_t compCount;
 
    //
    // Get the register offset for the Counter compare
    //
    registerOffset = base + CSL_EPWM_CMPA + (uint16_t)compModule;
 
    //
    // Read from the counter compare registers.
    //
    if((compModule == EPWM_COUNTER_COMPARE_A) ||
        (compModule == EPWM_COUNTER_COMPARE_B))
    {
        //
        // Read COMPA or COMPB bits
        //
        compCount = (uint16_t)((HW_RD_REG32(registerOffset) &
                    (uint32_t)CSL_EPWM_CMPA_CMPA_MASK) >>
                    CSL_EPWM_CMPA_CMPA_SHIFT);
    }
    else
    {
        //
        // Read COMPC or COMPD bits
        //
        compCount = HW_RD_REG16(registerOffset);
    }
    return(compCount);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline bool
EPWM_getCounterCompareShadowStatus(uint32_t base,
                                   EPWM_CounterCompareModule compModule)
{
    //
    // Check the arguments
    //
    DebugP_assert((compModule == EPWM_COUNTER_COMPARE_A) ||
                  (compModule == EPWM_COUNTER_COMPARE_B));
 
    //
    // Read the value of SHDWAFULL or SHDWBFULL bit
    //
    return((((HW_RD_REG32(base + CSL_EPWM_CMPCTL) >>
            ((((uint16_t)compModule >> 1U) & 0x2U) +
            CSL_EPWM_CMPCTL_SHDWAFULL_SHIFT)) &
            0x1U) == 0x1U) ? true:false);
}
 
//
// Action Qualifier module related APIs
//
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setActionQualifierShadowLoadMode(uint32_t base,
                                      EPWM_ActionQualifierModule aqModule,
                                      EPWM_ActionQualifierLoadMode loadMode)
{
    uint16_t syncModeOffset;
    uint16_t shadowModeOffset;
 
    syncModeOffset = CSL_EPWM_AQCTL_LDAQASYNC_SHIFT + (uint16_t)aqModule;
    shadowModeOffset = CSL_EPWM_AQCTL_SHDWAQAMODE_SHIFT + (uint16_t)aqModule;
 
    //
    // Set the appropriate sync and load mode bits and also enable shadow
    // load mode. Shadow to active load can also be frozen.
    //
    HW_WR_REG16(base + CSL_EPWM_AQCTL,
        ((HW_RD_REG16(base + CSL_EPWM_AQCTL) &
        (~((CSL_EPWM_AQCTL_LDAQAMODE_MASK << (uint16_t)aqModule) |
        (CSL_EPWM_AQCTL_LDAQASYNC_MAX << (uint16_t)syncModeOffset))) |
        (CSL_EPWM_AQCTL_SHDWAQAMODE_MAX << shadowModeOffset)) |
        ((((uint16_t)loadMode >> 2U) << syncModeOffset) |
        (((uint16_t)loadMode & CSL_EPWM_AQCTL_LDAQAMODE_MASK) <<
        (uint16_t)aqModule))));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disableActionQualifierShadowLoadMode(uint32_t base,
                                          EPWM_ActionQualifierModule aqModule)
{
    uint16_t shadowModeOffset;
 
    shadowModeOffset = CSL_EPWM_AQCTL_SHDWAQAMODE_SHIFT + (uint16_t)aqModule;
 
    //
    // Disable shadow load mode. Action qualifier is loaded on
    // immediate mode only.
    //
    HW_WR_REG16(base + CSL_EPWM_AQCTL,
        (HW_RD_REG16(base + CSL_EPWM_AQCTL) &
        ~(CSL_EPWM_AQCTL_SHDWAQAMODE_MAX << shadowModeOffset)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setActionQualifierT1TriggerSource(uint32_t base,
                                     EPWM_ActionQualifierTriggerSource trigger)
{
    //
    // Set T1 trigger source
    //
    HW_WR_REG16(base + CSL_EPWM_AQTSRCSEL,
        ((HW_RD_REG16(base + CSL_EPWM_AQTSRCSEL) &
        (~CSL_EPWM_AQTSRCSEL_T1SEL_MASK)) |
        ((uint16_t)trigger)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setActionQualifierT2TriggerSource(uint32_t base,
                                      EPWM_ActionQualifierTriggerSource trigger)
{
    //
    // Set T2 trigger source
    //
    HW_WR_REG16(base + CSL_EPWM_AQTSRCSEL,
        ((HW_RD_REG16(base + CSL_EPWM_AQTSRCSEL) &
        (~CSL_EPWM_AQTSRCSEL_T2SEL_MASK)) |
        ((uint16_t)trigger << CSL_EPWM_AQTSRCSEL_T2SEL_SHIFT)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setActionQualifierAction(uint32_t base,
                              EPWM_ActionQualifierOutputModule epwmOutput,
                              EPWM_ActionQualifierOutput output,
                              EPWM_ActionQualifierOutputEvent event)
{
    uint32_t registerOffset;
    uint32_t registerTOffset;
 
    //
    // Get the register offset
    //
    registerOffset = CSL_EPWM_AQCTLA + (uint16_t)epwmOutput;
    registerTOffset = CSL_EPWM_AQCTLA2 + (uint16_t)epwmOutput;
 
    //
    // If the event occurs on T1 or T2 events
    //
    if(((uint16_t)event & 0x1U) == 1U)
    {
        //
        // Write to T1U,T1D,T2U or T2D of AQCTLA2 register
        //
        HW_WR_REG16(base + registerTOffset,
            ((HW_RD_REG16(base + registerTOffset) &
            ~(CSL_EPWM_AQCTLA_ZRO_MAX << ((uint16_t)event - 1U))) |
            ((uint16_t)output << ((uint16_t)event - 1U))));
    }
    else
    {
        //
        // Write to ZRO,PRD,CAU,CAD,CBU or CBD bits of AQCTLA register
        //
        HW_WR_REG16(base + registerOffset,
            ((HW_RD_REG16(base + registerOffset) &
            ~(CSL_EPWM_AQCTLA_ZRO_MAX << (uint16_t)event)) |
            ((uint16_t)output << (uint16_t)event)));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setActionQualifierActionComplete(uint32_t base,
                                EPWM_ActionQualifierOutputModule epwmOutput,
                                EPWM_ActionQualifierEventAction action)
{
    uint32_t registerOffset;
 
    //
    // Get the register offset
    //
    registerOffset = CSL_EPWM_AQCTLA + (uint16_t)epwmOutput;
 
    //
    // Write to ZRO, PRD, CAU, CAD, CBU or CBD bits of AQCTLA register
    //
    HW_WR_REG16(base + registerOffset, action);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setAdditionalActionQualifierActionComplete(uint32_t base,
                            EPWM_ActionQualifierOutputModule epwmOutput,
                            EPWM_AdditionalActionQualifierEventAction action)
{
    uint32_t registerTOffset;
 
    //
    // Get the register offset
    //
    registerTOffset = CSL_EPWM_AQCTLA2 + (uint16_t)epwmOutput;
 
    //
    // Write to T1U, T1D, T2U or T2D of AQCTLA2 register
    //
    HW_WR_REG16(base + registerTOffset, action);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setActionQualifierContSWForceShadowMode(uint32_t base,
                                            EPWM_ActionQualifierContForce mode)
{
    //
    // Set the Action qualifier software action reload mode.
    // Write to RLDCSF bit
    //
    HW_WR_REG16(base + CSL_EPWM_AQSFRC,
        ((HW_RD_REG16(base + CSL_EPWM_AQSFRC) &
        ~CSL_EPWM_AQSFRC_RLDCSF_MASK) |
        ((uint16_t)mode << CSL_EPWM_AQSFRC_RLDCSF_SHIFT)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setActionQualifierContSWForceAction(uint32_t base,
                                EPWM_ActionQualifierOutputModule epwmOutput,
                                EPWM_ActionQualifierSWOutput output)
{
    //
    // Initiate a continuous software forced output
    //
    if(epwmOutput == EPWM_AQ_OUTPUT_A)
    {
        HW_WR_REG16(base + CSL_EPWM_AQCSFRC,
            ((HW_RD_REG16(base + CSL_EPWM_AQCSFRC) &
            ~CSL_EPWM_AQCSFRC_CSFA_MASK) |
            ((uint16_t)output)));
    }
    else
    {
        HW_WR_REG16(base + CSL_EPWM_AQCSFRC,
            ((HW_RD_REG16(base + CSL_EPWM_AQCSFRC) &
            ~CSL_EPWM_AQCSFRC_CSFB_MASK) |
            ((uint16_t)output << CSL_EPWM_AQCSFRC_CSFB_SHIFT)));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setActionQualifierSWAction(uint32_t base,
                                EPWM_ActionQualifierOutputModule epwmOutput,
                                EPWM_ActionQualifierOutput output)
{
    //
    // Set the one time software forced action
    //
    if(epwmOutput == EPWM_AQ_OUTPUT_A)
    {
        HW_WR_REG16(base + CSL_EPWM_AQSFRC,
            ((HW_RD_REG16(base + CSL_EPWM_AQSFRC) &
            ~CSL_EPWM_AQSFRC_ACTSFA_MASK) |
            ((uint16_t)output)));
    }
    else
    {
        HW_WR_REG16(base + CSL_EPWM_AQSFRC,
            ((HW_RD_REG16(base + CSL_EPWM_AQSFRC) &
            ~CSL_EPWM_AQSFRC_ACTSFB_MASK) |
            ((uint16_t)output << CSL_EPWM_AQSFRC_ACTSFB_SHIFT)));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_forceActionQualifierSWAction(uint32_t base,
                                  EPWM_ActionQualifierOutputModule epwmOutput)
{
    //
    // Initiate a software forced event
    //
    if(epwmOutput == EPWM_AQ_OUTPUT_A)
    {
        HW_WR_REG16(base + CSL_EPWM_AQSFRC,
            (HW_RD_REG16(base + CSL_EPWM_AQSFRC) |
            CSL_EPWM_AQSFRC_OTSFA_MASK));
    }
    else
    {
        HW_WR_REG16(base + CSL_EPWM_AQSFRC,
            (HW_RD_REG16(base + CSL_EPWM_AQSFRC) |
            CSL_EPWM_AQSFRC_OTSFB_MASK));
    }
}
 
//
// Dead Band Module related APIs
//
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setDeadBandOutputSwapMode(uint32_t base, EPWM_DeadBandOutput output,
                               bool enableSwapMode)
{
    uint16_t mask;
 
    mask = (uint16_t)1U << ((uint16_t)output + CSL_EPWM_DBCTL_OUTSWAP_SHIFT);
 
    if(enableSwapMode)
    {
        //
        // Set the appropriate outswap bit to swap output
        //
        HW_WR_REG16(base + CSL_EPWM_DBCTL,
            (HW_RD_REG16(base + CSL_EPWM_DBCTL) | mask));
    }
    else
    {
        //
        // Clear the appropriate outswap bit to disable output swap
        //
        HW_WR_REG16(base + CSL_EPWM_DBCTL,
            (HW_RD_REG16(base + CSL_EPWM_DBCTL) & ~mask));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setDeadBandDelayMode(uint32_t base, EPWM_DeadBandDelayMode delayMode,
                          bool enableDelayMode)
{
    uint16_t mask;
 
    mask = 1U << ((uint16_t)(delayMode + CSL_EPWM_DBCTL_OUT_MODE_SHIFT));
 
    if(enableDelayMode)
    {
        //
        // Set the appropriate outmode bit to enable Dead Band delay
        //
        HW_WR_REG16(base + CSL_EPWM_DBCTL,
            (HW_RD_REG16(base + CSL_EPWM_DBCTL) | mask));
    }
    else
    {
        //
        // Clear the appropriate outswap bit to disable output swap
        //
        HW_WR_REG16(base + CSL_EPWM_DBCTL,
            (HW_RD_REG16(base + CSL_EPWM_DBCTL) & ~mask));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setDeadBandDelayPolarity(uint32_t base,
                              EPWM_DeadBandDelayMode delayMode,
                              EPWM_DeadBandPolarity polarity)
{
    uint16_t shift;
 
    shift = (((uint16_t)delayMode ^ 0x1U) + CSL_EPWM_DBCTL_POLSEL_SHIFT);
 
    //
    // Set the appropriate polsel bits for dead band polarity
    //
    HW_WR_REG16(base + CSL_EPWM_DBCTL,
        ((HW_RD_REG16(base + CSL_EPWM_DBCTL) & ~ (1U << shift)) |
        ((uint16_t)polarity << shift)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setRisingEdgeDeadBandDelayInput(uint32_t base, uint16_t input)
{
    //
    // Check the arguments
    //
    DebugP_assert((input == EPWM_DB_INPUT_EPWMA) ||
           (input == EPWM_DB_INPUT_EPWMB));
 
    //
    // Set the Rising Edge Delay input
    //
    HW_WR_REG16(base + CSL_EPWM_DBCTL,
        ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
        ~(1U << (CSL_EPWM_DBCTL_IN_MODE_SHIFT))) |
        (input << CSL_EPWM_DBCTL_IN_MODE_SHIFT)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setFallingEdgeDeadBandDelayInput(uint32_t base, uint16_t input)
{
    //
    // Check the arguments
    //
    DebugP_assert((input == EPWM_DB_INPUT_EPWMA) ||
           (input == EPWM_DB_INPUT_EPWMB) ||
           (input == EPWM_DB_INPUT_DB_RED));
 
    if(input == EPWM_DB_INPUT_DB_RED)
    {
        //
        // Set the Falling Edge Delay input
        //
        HW_WR_REG16(base + CSL_EPWM_DBCTL,
            (HW_RD_REG16(base + CSL_EPWM_DBCTL) |
            CSL_EPWM_DBCTL_DEDB_MODE_MASK));
    }
    else
    {
        //
        // Set the Falling Edge Delay input
        //
        HW_WR_REG16(base + CSL_EPWM_DBCTL,
            (HW_RD_REG16(base + CSL_EPWM_DBCTL) &
            ~CSL_EPWM_DBCTL_DEDB_MODE_MASK));
 
        //
        // Set the Rising Edge Delay input
        //
        HW_WR_REG16(base + CSL_EPWM_DBCTL,
            ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
            ~(1U << (CSL_EPWM_DBCTL_IN_MODE_SHIFT + 1U))) |
            (input << (CSL_EPWM_DBCTL_IN_MODE_SHIFT + 1U))));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setDeadBandControlShadowLoadMode(uint32_t base,
                                      EPWM_DeadBandControlLoadMode loadMode)
{
    //
    // Enable the shadow mode and setup the load event
    //
    HW_WR_REG16(base + CSL_EPWM_DBCTL2,
        ((HW_RD_REG16(base + CSL_EPWM_DBCTL2) &
        ~CSL_EPWM_DBCTL2_LOADDBCTLMODE_MASK) |
        (CSL_EPWM_DBCTL2_LOADDBCTLMODE_MASK | (uint16_t)loadMode)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disableDeadBandControlShadowLoadMode(uint32_t base)
{
    //
    // Disable the shadow load mode. Only immediate load mode only.
    //
    HW_WR_REG16(base + CSL_EPWM_DBCTL2,
        (HW_RD_REG16(base + CSL_EPWM_DBCTL2) &
        ~CSL_EPWM_DBCTL2_SHDWDBCTLMODE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setRisingEdgeDelayCountShadowLoadMode(uint32_t base,
                                         EPWM_RisingEdgeDelayLoadMode loadMode)
{
    //
    // Enable the shadow mode. Set-up the load mode
    //
    HW_WR_REG16(base + CSL_EPWM_DBCTL,
        ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
        ~CSL_EPWM_DBCTL_LOADREDMODE_MASK) |
        ((uint16_t)CSL_EPWM_DBCTL_SHDWDBREDMODE_MASK |
        ((uint16_t)loadMode << CSL_EPWM_DBCTL_LOADREDMODE_SHIFT))));
 
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disableRisingEdgeDelayCountShadowLoadMode(uint32_t base)
{
    //
    // Disable the shadow mode.
    //
    HW_WR_REG16(base + CSL_EPWM_DBCTL,
        (HW_RD_REG16(base + CSL_EPWM_DBCTL) &
        ~CSL_EPWM_DBCTL_SHDWDBREDMODE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setFallingEdgeDelayCountShadowLoadMode(uint32_t base,
                                        EPWM_FallingEdgeDelayLoadMode loadMode)
{
    //
    // Enable the shadow mode. Setup the load mode.
    //
    HW_WR_REG16(base + CSL_EPWM_DBCTL,
        ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
        ~CSL_EPWM_DBCTL_LOADFEDMODE_MASK) |
        (CSL_EPWM_DBCTL_SHDWDBFEDMODE_MASK |
        ((uint16_t)loadMode << CSL_EPWM_DBCTL_LOADFEDMODE_SHIFT))));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disableFallingEdgeDelayCountShadowLoadMode(uint32_t base)
{
    //
    // Disable the shadow mode.
    //
    HW_WR_REG16(base + CSL_EPWM_DBCTL,
        (HW_RD_REG16(base + CSL_EPWM_DBCTL) &
        ~CSL_EPWM_DBCTL_SHDWDBFEDMODE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setDeadBandCounterClock(uint32_t base,
                             EPWM_DeadBandClockMode clockMode)
{
    //
    // Set the DB clock mode
    //
    HW_WR_REG16(base + CSL_EPWM_DBCTL,
        ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
        ~CSL_EPWM_DBCTL_HALFCYCLE_MASK) |
        ((uint16_t)clockMode << CSL_EPWM_DBCTL_HALFCYCLE_SHIFT)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setRisingEdgeDelayCount(uint32_t base, uint16_t redCount)
{
    //
    // Check the arguments
    //
    DebugP_assert(redCount <= CSL_EPWM_DBRED_DBRED_MAX);
 
    //
    // Set the RED (Rising Edge Delay) count
    //
    HW_WR_REG16(base + CSL_EPWM_DBRED, redCount);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setFallingEdgeDelayCount(uint32_t base, uint16_t fedCount)
{
    //
    // Check the arguments
    //
    DebugP_assert(fedCount <= CSL_EPWM_DBFED_DBFED_MAX);
 
    //
    // Set the FED (Falling Edge Delay) count
    //
    HW_WR_REG16(base + CSL_EPWM_DBFED, fedCount);
}
 
//
// Chopper module related APIs
//
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_enableChopper(uint32_t base)
{
    //
    // Set CHPEN bit. Enable Chopper
    //
    HW_WR_REG16(base + CSL_EPWM_PCCTL,
        (HW_RD_REG16(base + CSL_EPWM_PCCTL) | CSL_EPWM_PCCTL_CHPEN_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disableChopper(uint32_t base)
{
    //
    // Clear CHPEN bit. Disable Chopper
    //
    HW_WR_REG16(base + CSL_EPWM_PCCTL,
        (HW_RD_REG16(base + CSL_EPWM_PCCTL) & ~CSL_EPWM_PCCTL_CHPEN_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setChopperDutyCycle(uint32_t base, uint16_t dutyCycleCount)
{
    //
    // Check the arguments
    //
    DebugP_assert(dutyCycleCount < CSL_EPWM_PCCTL_CHPDUTY_MAX);
 
    //
    // Set the chopper duty cycle
    //
    HW_WR_REG16(base + CSL_EPWM_PCCTL,
        ((HW_RD_REG16(base + CSL_EPWM_PCCTL) & ~CSL_EPWM_PCCTL_CHPDUTY_MASK) |
        (dutyCycleCount << CSL_EPWM_PCCTL_CHPDUTY_SHIFT)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setChopperFreq(uint32_t base, uint16_t freqDiv)
{
    //
    // Check the arguments
    //
    DebugP_assert(freqDiv <= CSL_EPWM_PCCTL_CHPFREQ_MAX);
 
    //
    // Set the chopper clock
    //
    HW_WR_REG16(base + CSL_EPWM_PCCTL,
        ((HW_RD_REG16(base + CSL_EPWM_PCCTL) &
        ~(uint16_t)CSL_EPWM_PCCTL_CHPFREQ_MASK) |
        (freqDiv << CSL_EPWM_PCCTL_CHPFREQ_SHIFT)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setChopperFirstPulseWidth(uint32_t base, uint16_t firstPulseWidth)
{
    //
    // Check the arguments
    //
    DebugP_assert(firstPulseWidth <= CSL_EPWM_PCCTL_OSHTWTH_MAX);
 
    //
    // Set the chopper clock
    //
    HW_WR_REG16(base + CSL_EPWM_PCCTL,
        ((HW_RD_REG16(base + CSL_EPWM_PCCTL) &
        ~(uint16_t)CSL_EPWM_PCCTL_OSHTWTH_MASK) |
        (firstPulseWidth << CSL_EPWM_PCCTL_OSHTWTH_SHIFT)));
}
 
//
// Trip Zone module related APIs
//
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_enableTripZoneSignals(uint32_t base, uint32_t tzSignal)
{
    //
    // Set the trip zone bits
    //
    HW_WR_REG32(base + CSL_EPWM_TZSEL,
        (HW_RD_REG32(base + CSL_EPWM_TZSEL) | tzSignal));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disableTripZoneSignals(uint32_t base, uint32_t tzSignal)
{
    //
    // Clear the trip zone bits
    //
    HW_WR_REG32(base + CSL_EPWM_TZSEL,
        (HW_RD_REG32(base + CSL_EPWM_TZSEL) & ~tzSignal));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setTripZoneDigitalCompareEventCondition(uint32_t base,
                                EPWM_TripZoneDigitalCompareOutput dcType,
                                EPWM_TripZoneDigitalCompareOutputEvent dcEvent)
{
    //
    // Set Digital Compare Events conditions that cause a Digital Compare trip
    //
    HW_WR_REG16(base + CSL_EPWM_TZDCSEL,
        ((HW_RD_REG16(base + CSL_EPWM_TZDCSEL) &
        ~(CSL_EPWM_TZDCSEL_DCAEVT1_MASK << (uint16_t)dcType)) |
        ((uint16_t)dcEvent << (uint16_t)dcType)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_enableTripZoneAdvAction(uint32_t base)
{
    //
    // Enable Advanced feature. Set ETZE bit
    //
    HW_WR_REG16(base + CSL_EPWM_TZCTL2,
        (HW_RD_REG16(base + CSL_EPWM_TZCTL2) | CSL_EPWM_TZCTL2_ETZE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disableTripZoneAdvAction(uint32_t base)
{
    //
    // Disable Advanced feature. clear ETZE bit
    //
    HW_WR_REG16(base + CSL_EPWM_TZCTL2,
        (HW_RD_REG16(base + CSL_EPWM_TZCTL2) & ~CSL_EPWM_TZCTL2_ETZE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setTripZoneAction(uint32_t base, EPWM_TripZoneEvent tzEvent,
                       EPWM_TripZoneAction tzAction)
{
    //
    // Set the Action for Trip Zone events
    //
    HW_WR_REG16(base + CSL_EPWM_TZCTL,
        ((HW_RD_REG16(base + CSL_EPWM_TZCTL) &
        ~(CSL_EPWM_TZCTL_TZA_MASK << (uint16_t)tzEvent)) |
        ((uint16_t)tzAction << (uint16_t)tzEvent)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setTripZoneAdvAction(uint32_t base, EPWM_TripZoneAdvancedEvent tzAdvEvent,
                          EPWM_TripZoneAdvancedAction tzAdvAction)
{
    //
    // Set the Advanced Action for Trip Zone events
    //
    HW_WR_REG16(base + CSL_EPWM_TZCTL2,
        ((HW_RD_REG16(base + CSL_EPWM_TZCTL2) &
        ~(CSL_EPWM_TZCTL2_TZAU_MASK << (uint16_t)tzAdvEvent)) |
        ((uint16_t)tzAdvAction << (uint16_t)tzAdvEvent)));
 
    HW_WR_REG16(base + CSL_EPWM_TZCTL2,
        (HW_RD_REG16(base + CSL_EPWM_TZCTL2) | CSL_EPWM_TZCTL2_ETZE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setTripZoneAdvDigitalCompareActionA(uint32_t base,
                              EPWM_TripZoneAdvDigitalCompareEvent tzAdvDCEvent,
                              EPWM_TripZoneAdvancedAction tzAdvDCAction)
{
    //
    // Set the Advanced Action for Trip Zone events
    //
    HW_WR_REG16(base + CSL_EPWM_TZCTLDCA,
        ((HW_RD_REG16(base + CSL_EPWM_TZCTLDCA) &
        ~(CSL_EPWM_TZCTLDCA_DCAEVT1U_MASK << (uint16_t)tzAdvDCEvent)) |
        ((uint16_t)tzAdvDCAction << (uint16_t)tzAdvDCEvent)));
 
    HW_WR_REG16(base + CSL_EPWM_TZCTL2,
        (HW_RD_REG16(base + CSL_EPWM_TZCTL2) | CSL_EPWM_TZCTL2_ETZE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void EPWM_setTripZoneAdvDigitalCompareActionB(uint32_t base,
                              EPWM_TripZoneAdvDigitalCompareEvent tzAdvDCEvent,
                              EPWM_TripZoneAdvancedAction tzAdvDCAction)
{
    //
    // Set the Advanced Action for Trip Zone events
    //
    HW_WR_REG16(base + CSL_EPWM_TZCTLDCB,
        ((HW_RD_REG16(base + CSL_EPWM_TZCTLDCB) &
        ~(CSL_EPWM_TZCTLDCB_DCBEVT1U_MASK << (uint16_t)tzAdvDCEvent)) |
        ((uint16_t)tzAdvDCAction << (uint16_t)tzAdvDCEvent)));
 
    HW_WR_REG16(base + CSL_EPWM_TZCTL2,
        (HW_RD_REG16(base + CSL_EPWM_TZCTL2) | CSL_EPWM_TZCTL2_ETZE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_enableTripZoneInterrupt(uint32_t base, uint16_t tzInterrupt)
{
    //
    // Check the arguments
    //
    DebugP_assert((tzInterrupt >= 0U) && (tzInterrupt < 0x80U));
 
    //
    // Enable Trip zone interrupts
    //
    HW_WR_REG16(base + CSL_EPWM_TZEINT,
        (HW_RD_REG16(base + CSL_EPWM_TZEINT) | tzInterrupt));
}
 
//*****************************************************************************
//
//
//***************************************************************************
static inline void
EPWM_disableTripZoneInterrupt(uint32_t base, uint16_t tzInterrupt)
{
    //
    // Check the arguments
    //
    DebugP_assert((tzInterrupt > 0U) && (tzInterrupt < 0x80U));
 
    //
    // Disable Trip zone interrupts
    //
    HW_WR_REG16(base + CSL_EPWM_TZEINT,
        (HW_RD_REG16(base + CSL_EPWM_TZEINT) & ~tzInterrupt));
}
 
//*****************************************************************************
//
//
//***************************************************************************
static inline uint16_t
EPWM_getTripZoneFlagStatus(uint32_t base)
{
    //
    // Return the Trip zone flag status
    //
    return(HW_RD_REG16(base + CSL_EPWM_TZFLG) & 0xFFU);
}
 
//*****************************************************************************
//
//
//***************************************************************************
static inline uint16_t
EPWM_getCycleByCycleTripZoneFlagStatus(uint32_t base)
{
    //
    // Return the Cycle By Cycle Trip zone flag status
    //
    return(HW_RD_REG16(base + CSL_EPWM_TZCBCFLG) & 0x1FFU);
}
 
//*****************************************************************************
//
//
//***************************************************************************
static inline uint16_t
EPWM_getOneShotTripZoneFlagStatus(uint32_t base)
{
    //
    // Return the One Shot Trip zone flag status
    //
    return(HW_RD_REG16(base + CSL_EPWM_TZOSTFLG) & 0x1FFU);
}
 
//*****************************************************************************
//
//
//**************************************************************************
static inline void
EPWM_selectCycleByCycleTripZoneClearEvent(uint32_t base,
                                 EPWM_CycleByCycleTripZoneClearMode clearEvent)
{
    //
    // Set the Cycle by Cycle Trip Latch mode
    //
    HW_WR_REG16(base + CSL_EPWM_TZCLR,
        ((HW_RD_REG16(base + CSL_EPWM_TZCLR) &
        ~CSL_EPWM_TZCLR_CBCPULSE_MASK) |
        ((uint16_t)clearEvent << CSL_EPWM_TZCLR_CBCPULSE_SHIFT)));
}
 
//*****************************************************************************
//
//
//***************************************************************************
static inline void
EPWM_clearTripZoneFlag(uint32_t base, uint16_t tzFlags)
{
    //
    // Check the arguments
    //
    DebugP_assert((tzFlags < 0x80U) && (tzFlags >= 0x1U));
 
    //
    // Clear Trip zone event flag
    //
    HW_WR_REG16(base + CSL_EPWM_TZCLR,
        (HW_RD_REG16(base + CSL_EPWM_TZCLR) | tzFlags));
}
 
//*****************************************************************************
//
//
//***************************************************************************
static inline void
EPWM_clearCycleByCycleTripZoneFlag(uint32_t base, uint16_t tzCBCFlags)
{
    //
    // Check the arguments
    //
    DebugP_assert(tzCBCFlags < 0x200U);
 
    //
    // Clear the Cycle By Cycle Trip zone flag
    //
    HW_WR_REG16(base + CSL_EPWM_TZCBCCLR,
        (HW_RD_REG16(base + CSL_EPWM_TZCBCCLR) | tzCBCFlags));
}
 
//*****************************************************************************
//
//
//***************************************************************************
static inline void
EPWM_clearOneShotTripZoneFlag(uint32_t base, uint16_t tzOSTFlags)
{
    //
    // Check the arguments
    //
    DebugP_assert(tzOSTFlags < 0x200U);
 
    //
    // Clear the Cycle By Cycle Trip zone flag
    //
    HW_WR_REG16(base + CSL_EPWM_TZOSTCLR,
        (HW_RD_REG16(base + CSL_EPWM_TZOSTCLR) | tzOSTFlags));
}
 
//*****************************************************************************
//
//
//***************************************************************************
static inline void
EPWM_forceTripZoneEvent(uint32_t base, uint16_t tzForceEvent)
{
    //
    // Check the arguments
    //
    DebugP_assert((tzForceEvent & 0xFF01U)== 0U);
 
    //
    // Force a Trip Zone event
    //
    HW_WR_REG16(base + CSL_EPWM_TZFRC,
        (HW_RD_REG16(base + CSL_EPWM_TZFRC) | tzForceEvent));
}
 
//*****************************************************************************
//
//
//***************************************************************************
static inline void
EPWM_enableTripZoneOutput(uint32_t base, uint16_t tzOutput)
{
    //
    // Enable the Trip Zone signals as output
    //
    HW_WR_REG16(base + CSL_EPWM_TZTRIPOUTSEL,
        (HW_RD_REG16(base + CSL_EPWM_TZTRIPOUTSEL) | tzOutput));
}
 
//*****************************************************************************
//
//
//***************************************************************************
static inline void
EPWM_disableTripZoneOutput(uint32_t base, uint16_t tzOutput)
{
    //
    // Disable the Trip Zone signals as output
    //
    HW_WR_REG16(base + CSL_EPWM_TZTRIPOUTSEL,
        (HW_RD_REG16(base + CSL_EPWM_TZTRIPOUTSEL) & ~tzOutput));
}
 
//
// Event Trigger related APIs
//
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_enableInterrupt(uint32_t base)
{
    //
    // Enable ePWM interrupt
    //
    HW_WR_REG16(base + CSL_EPWM_ETSEL,
        (HW_RD_REG16(base + CSL_EPWM_ETSEL) | CSL_EPWM_ETSEL_INTEN_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disableInterrupt(uint32_t base)
{
    //
    // Disable ePWM interrupt
    //
    HW_WR_REG16(base + CSL_EPWM_ETSEL,
        (HW_RD_REG16(base + CSL_EPWM_ETSEL) & ~CSL_EPWM_ETSEL_INTEN_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setInterruptSource(uint32_t base, uint16_t interruptSource,
                        uint16_t mixedSource)
{
    uint16_t intSource;
 
    //
    // Check the arguments
    //
    DebugP_assert(((interruptSource > 0U) && (interruptSource < 9U)) ||
           (interruptSource == 10U) || (interruptSource == 12U) ||
           (interruptSource == 14U));
 
    if((interruptSource == EPWM_INT_TBCTR_U_CMPC) ||
       (interruptSource == EPWM_INT_TBCTR_U_CMPD) ||
       (interruptSource == EPWM_INT_TBCTR_D_CMPC) ||
       (interruptSource == EPWM_INT_TBCTR_D_CMPD))
    {
        //
        // Shift the interrupt source by 1
        //
        intSource = interruptSource >> 1U;
 
        //
        // Enable events based on comp C or comp D
        //
        HW_WR_REG16(base + CSL_EPWM_ETSEL,
            (HW_RD_REG16(base + CSL_EPWM_ETSEL) |
            CSL_EPWM_ETSEL_INTSELCMP_MASK));
    }
    else if((interruptSource == EPWM_INT_TBCTR_U_CMPA) ||
            (interruptSource == EPWM_INT_TBCTR_U_CMPB) ||
            (interruptSource == EPWM_INT_TBCTR_D_CMPA) ||
            (interruptSource == EPWM_INT_TBCTR_D_CMPB))
    {
        intSource = interruptSource;
 
        //
        // Enable events based on comp A or comp B
        //
        HW_WR_REG16(base + CSL_EPWM_ETSEL,
            (HW_RD_REG16(base + CSL_EPWM_ETSEL) &
            ~CSL_EPWM_ETSEL_INTSELCMP_MASK));
    }
    else if(interruptSource == EPWM_INT_TBCTR_ETINTMIX)
    {
        intSource = interruptSource;
 
        //
        // Enable mixed events
        //
        HW_WR_REG16(base + CSL_EPWM_ETINTMIXEN, mixedSource);
    }
    else
    {
        intSource = interruptSource;
    }
 
    //
    // Set the interrupt source
    //
    HW_WR_REG16(base + CSL_EPWM_ETSEL,
        ((HW_RD_REG16(base + CSL_EPWM_ETSEL) &
        ~CSL_EPWM_ETSEL_INTSEL_MASK) | intSource));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setInterruptEventCount(uint32_t base, uint16_t eventCount)
{
    //
    // Check the arguments
    //
    DebugP_assert(eventCount <= CSL_EPWM_ETINTPS_INTPRD2_MAX);
 
    //
    // Enable advanced feature of interrupt every up to 15 events
    //
    HW_WR_REG16(base + CSL_EPWM_ETPS,
        (HW_RD_REG16(base + CSL_EPWM_ETPS) | CSL_EPWM_ETPS_INTPSSEL_MASK));
 
    HW_WR_REG16(base + CSL_EPWM_ETINTPS,
        ((HW_RD_REG16(base + CSL_EPWM_ETINTPS) &
        ~CSL_EPWM_ETINTPS_INTPRD2_MASK) | eventCount));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline bool
EPWM_getEventTriggerInterruptStatus(uint32_t base)
{
    //
    // Return INT bit of ETFLG register
    //
    return(((HW_RD_REG16(base + CSL_EPWM_ETFLG) & 0x1U) ==
            0x1U) ? true : false);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_clearEventTriggerInterruptFlag(uint32_t base)
{
    //
    // Clear INT bit of ETCLR register
    //
    HW_WR_REG16(base + CSL_EPWM_ETCLR,
        (HW_RD_REG16(base + CSL_EPWM_ETCLR) | CSL_EPWM_ETCLR_INT_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_enableInterruptEventCountInit(uint32_t base)
{
    //
    // Enable interrupt event count initializing/loading
    //
    HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
        (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) |
        CSL_EPWM_ETCNTINITCTL_INTINITEN_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disableInterruptEventCountInit(uint32_t base)
{
    //
    // Disable interrupt event count initializing/loading
    //
    HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
        (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) &
        ~CSL_EPWM_ETCNTINITCTL_INTINITEN_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_forceInterruptEventCountInit(uint32_t base)
{
    //
    // Load the Interrupt Event counter value
    //
    HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
        (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) |
        CSL_EPWM_ETCNTINITCTL_INTINITFRC_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setInterruptEventCountInitValue(uint32_t base, uint16_t eventCount)
{
    //
    // Check the arguments
    //
    DebugP_assert(eventCount <= CSL_EPWM_ETCNTINIT_INTINIT_MAX);
 
    //
    // Set the Pre-interrupt event count
    //
    HW_WR_REG16(base + CSL_EPWM_ETCNTINIT,
        ((HW_RD_REG16(base + CSL_EPWM_ETCNTINIT) &
        ~CSL_EPWM_ETCNTINIT_INTINIT_MASK) |
        (uint16_t)(eventCount & CSL_EPWM_ETCNTINIT_INTINIT_MASK)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t
EPWM_getInterruptEventCount(uint32_t base)
{
    //
    // Return the interrupt event count
    //
    return(((HW_RD_REG16(base + CSL_EPWM_ETINTPS) &
            CSL_EPWM_ETINTPS_INTCNT2_MASK) >>
            CSL_EPWM_ETINTPS_INTCNT2_SHIFT));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_forceEventTriggerInterrupt(uint32_t base)
{
    //
    // Set INT bit of ETFRC register
    //
    HW_WR_REG16(base + CSL_EPWM_ETFRC,
        (HW_RD_REG16(base + CSL_EPWM_ETFRC) | CSL_EPWM_ETFRC_INT_MASK));
}
 
//
// ADC SOC configuration related APIs
//
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_enableADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
{
    //
    // Enable an SOC
    //
    if(adcSOCType == EPWM_SOC_A)
    {
        HW_WR_REG16(base + CSL_EPWM_ETSEL,
        (HW_RD_REG16(base + CSL_EPWM_ETSEL) | CSL_EPWM_ETSEL_SOCAEN_MASK));
    }
    else
    {
        HW_WR_REG16(base + CSL_EPWM_ETSEL,
        (HW_RD_REG16(base + CSL_EPWM_ETSEL) | CSL_EPWM_ETSEL_SOCBEN_MASK));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disableADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
{
    //
    // Disable an SOC
    //
    if(adcSOCType == EPWM_SOC_A)
    {
        HW_WR_REG16(base + CSL_EPWM_ETSEL,
        (HW_RD_REG16(base + CSL_EPWM_ETSEL) & ~CSL_EPWM_ETSEL_SOCAEN_MASK));
    }
    else
    {
        HW_WR_REG16(base + CSL_EPWM_ETSEL,
        (HW_RD_REG16(base + CSL_EPWM_ETSEL) & ~CSL_EPWM_ETSEL_SOCBEN_MASK));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setADCTriggerSource(uint32_t base,
                         EPWM_ADCStartOfConversionType adcSOCType,
                         EPWM_ADCStartOfConversionSource socSource,
                         uint16_t mixedSource)
{
    uint16_t source;
 
    if((socSource == EPWM_SOC_TBCTR_U_CMPC) ||
       (socSource == EPWM_SOC_TBCTR_U_CMPD) ||
       (socSource == EPWM_SOC_TBCTR_D_CMPC) ||
       (socSource == EPWM_SOC_TBCTR_D_CMPD))
    {
        source = (uint16_t)socSource >> 1U;
    }
    else
    {
        source = (uint16_t)socSource;
    }
 
    if(adcSOCType == EPWM_SOC_A)
    {
        //
        // Set the SOC source
        //
        HW_WR_REG16(base + CSL_EPWM_ETSEL,
            ((HW_RD_REG16(base + CSL_EPWM_ETSEL) &
            ~CSL_EPWM_ETSEL_SOCASEL_MASK) |
            (source << CSL_EPWM_ETSEL_SOCASEL_SHIFT)));
 
        //
        // Enable the comparator selection
        //
        if((socSource == EPWM_SOC_TBCTR_U_CMPA) ||
           (socSource == EPWM_SOC_TBCTR_U_CMPB) ||
           (socSource == EPWM_SOC_TBCTR_D_CMPA) ||
           (socSource == EPWM_SOC_TBCTR_D_CMPB))
        {
            //
            // Enable events based on comp A or comp B
            //
            HW_WR_REG16(base + CSL_EPWM_ETSEL,
            (HW_RD_REG16(base + CSL_EPWM_ETSEL) &
            ~CSL_EPWM_ETSEL_SOCASELCMP_MASK));
        }
        else if((socSource == EPWM_SOC_TBCTR_U_CMPC) ||
                (socSource == EPWM_SOC_TBCTR_U_CMPD) ||
                (socSource == EPWM_SOC_TBCTR_D_CMPC) ||
                (socSource == EPWM_SOC_TBCTR_D_CMPD))
        {
            //
            // Enable events based on comp C or comp D
            //
            HW_WR_REG16(base + CSL_EPWM_ETSEL,
            (HW_RD_REG16(base + CSL_EPWM_ETSEL) |
            CSL_EPWM_ETSEL_SOCASELCMP_MASK));
        }
        else if(socSource == EPWM_SOC_TBCTR_MIXED_EVENT)
        {
            //
            // Enable mixed events
            //
            HW_WR_REG16(base + CSL_EPWM_ETSOCAMIXEN, mixedSource);
        }
        else
        {
            //
            // No action required for the other socSource options
            //
        }
    }
    else
    {
        //
        // Enable the comparator selection
        //
        HW_WR_REG16(base + CSL_EPWM_ETSEL,
            ((HW_RD_REG16(base + CSL_EPWM_ETSEL) &
            ~CSL_EPWM_ETSEL_SOCBSEL_MASK) |
            (source << CSL_EPWM_ETSEL_SOCBSEL_SHIFT)));
 
        //
        // Enable the comparator selection
        //
        if((socSource == EPWM_SOC_TBCTR_U_CMPA) ||
           (socSource == EPWM_SOC_TBCTR_U_CMPB) ||
           (socSource == EPWM_SOC_TBCTR_D_CMPA) ||
           (socSource == EPWM_SOC_TBCTR_D_CMPB))
        {
            //
            // Enable events based on comp A or comp B
            //
            HW_WR_REG16(base + CSL_EPWM_ETSEL,
                (HW_RD_REG16(base + CSL_EPWM_ETSEL) &
                ~CSL_EPWM_ETSEL_SOCBSELCMP_MASK));
        }
        else if((socSource == EPWM_SOC_TBCTR_U_CMPC) ||
                (socSource == EPWM_SOC_TBCTR_U_CMPD) ||
                (socSource == EPWM_SOC_TBCTR_D_CMPC) ||
                (socSource == EPWM_SOC_TBCTR_D_CMPD))
        {
            //
            // Enable events based on comp C or comp D
            //
            HW_WR_REG16(base + CSL_EPWM_ETSEL,
                (HW_RD_REG16(base + CSL_EPWM_ETSEL) |
                CSL_EPWM_ETSEL_SOCBSELCMP_MASK));
        }
        else if(socSource == EPWM_SOC_TBCTR_MIXED_EVENT)
        {
            //
            // Enable mixed events
            //
            HW_WR_REG16(base + CSL_EPWM_ETSOCBMIXEN, mixedSource);
        }
        else
        {
            //
            // No action required for the other socSource options
            //
        }
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setADCTriggerEventPrescale(uint32_t base,
                                EPWM_ADCStartOfConversionType adcSOCType,
                                uint16_t preScaleCount)
{
    //
    // Check the arguments
    //
    DebugP_assert(preScaleCount <= CSL_EPWM_ETSOCPS_SOCAPRD2_MAX);
 
    //
    // Enable advanced feature of SOC every up to 15 events
    //
    HW_WR_REG16(base + CSL_EPWM_ETPS,
        (HW_RD_REG16(base + CSL_EPWM_ETPS) |
        CSL_EPWM_ETPS_SOCPSSEL_MASK));
 
    if(adcSOCType == EPWM_SOC_A)
    {
        //
        // Set the count for SOC A
        //
        HW_WR_REG16(base + CSL_EPWM_ETSOCPS,
            ((HW_RD_REG16(base + CSL_EPWM_ETSOCPS) &
            ~CSL_EPWM_ETSOCPS_SOCAPRD2_MASK) |
            preScaleCount));
    }
    else
    {
        //
        // Set the count for SOC B
        //
        HW_WR_REG16(base + CSL_EPWM_ETSOCPS,
            ((HW_RD_REG16(base + CSL_EPWM_ETSOCPS) &
            ~CSL_EPWM_ETSOCPS_SOCBPRD2_MASK) |
            (preScaleCount << CSL_EPWM_ETSOCPS_SOCBPRD2_SHIFT)));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline bool
EPWM_getADCTriggerFlagStatus(uint32_t base,
                             EPWM_ADCStartOfConversionType adcSOCType)
{
    //
    // Return the SOC A/ B status
    //
    return((((HW_RD_REG16(base + CSL_EPWM_ETFLG) >>
            ((uint16_t)adcSOCType + CSL_EPWM_ETFLG_SOCA_SHIFT)) &
            0x1U) == 0x1U) ? true : false);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_clearADCTriggerFlag(uint32_t base,
                         EPWM_ADCStartOfConversionType adcSOCType)
{
    //
    // Clear SOC A/B bit of ETCLR register
    //
    HW_WR_REG16(base + CSL_EPWM_ETCLR,
        (HW_RD_REG16(base + CSL_EPWM_ETCLR) |
        1U << ((uint16_t)adcSOCType + CSL_EPWM_ETCLR_SOCA_SHIFT)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_enableADCTriggerEventCountInit(uint32_t base,
                                    EPWM_ADCStartOfConversionType adcSOCType)
{
    //
    // Enable SOC event count initializing/loading
    //
    HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
        (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) | 1U <<
        ((uint16_t)adcSOCType + CSL_EPWM_ETCNTINITCTL_SOCAINITEN_SHIFT)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disableADCTriggerEventCountInit(uint32_t base,
                                     EPWM_ADCStartOfConversionType adcSOCType)
{
    //
    // Disable SOC event count initializing/loading
    //
    HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
        (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) &
        ~(1U << ((uint16_t)adcSOCType +
        CSL_EPWM_ETCNTINITCTL_SOCAINITEN_SHIFT))));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_forceADCTriggerEventCountInit(uint32_t base,
                                   EPWM_ADCStartOfConversionType adcSOCType)
{
    //
    // Load the Interrupt Event counter value
    //
    HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
        (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) |
        1U << ((uint16_t)adcSOCType +
        CSL_EPWM_ETCNTINITCTL_SOCAINITFRC_SHIFT)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setADCTriggerEventCountInitValue(uint32_t base,
                                      EPWM_ADCStartOfConversionType adcSOCType,
                                      uint16_t eventCount)
{
    //
    // Check the arguments
    //
    DebugP_assert(eventCount <= CSL_EPWM_ETCNTINIT_SOCAINIT_MAX);
 
    //
    // Set the ADC Trigger event count
    //
    if(adcSOCType == EPWM_SOC_A)
    {
        HW_WR_REG16(base + CSL_EPWM_ETCNTINIT,
            ((HW_RD_REG16(base + CSL_EPWM_ETCNTINIT) &
            ~CSL_EPWM_ETCNTINIT_SOCAINIT_MASK) |
            (uint16_t)(eventCount << CSL_EPWM_ETCNTINIT_SOCAINIT_SHIFT)));
    }
    else
    {
        HW_WR_REG16(base + CSL_EPWM_ETCNTINIT,
            ((HW_RD_REG16(base + CSL_EPWM_ETCNTINIT) &
            ~CSL_EPWM_ETCNTINIT_SOCBINIT_MASK) |
            (eventCount << CSL_EPWM_ETCNTINIT_SOCBINIT_SHIFT)));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t
EPWM_getADCTriggerEventCount(uint32_t base,
                             EPWM_ADCStartOfConversionType adcSOCType)
{
    uint16_t eventCount;
 
    //
    // Return the SOC event count
    //
    if(adcSOCType == EPWM_SOC_A)
    {
        eventCount = (HW_RD_REG16(base + CSL_EPWM_ETSOCPS) >>
                     CSL_EPWM_ETSOCPS_SOCACNT2_SHIFT) &
                     CSL_EPWM_ETSOCPS_SOCACNT2_MAX;
    }
    else
    {
        eventCount = (HW_RD_REG16(base + CSL_EPWM_ETSOCPS) >>
                     CSL_EPWM_ETSOCPS_SOCBCNT2_SHIFT) &
                     CSL_EPWM_ETSOCPS_SOCBCNT2_MAX;
    }
 
    return(eventCount);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_forceADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
{
    //
    // Set SOC A/B bit of ETFRC register
    //
    HW_WR_REG16(base + CSL_EPWM_ETFRC,
        (HW_RD_REG16(base + CSL_EPWM_ETFRC) |
        1U << ((uint16_t)adcSOCType + CSL_EPWM_ETFRC_SOCA_SHIFT)));
}
 
//
// Digital Compare module related APIs
//
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_selectDigitalCompareTripInput(uint32_t base,
                                   EPWM_DigitalCompareTripInput tripSource,
                                   EPWM_DigitalCompareType dcType)
{
    //
    // Set the DC trip input
    //
    HW_WR_REG16(base + CSL_EPWM_DCTRIPSEL,
        ((HW_RD_REG16(base + CSL_EPWM_DCTRIPSEL) &
        ~(CSL_EPWM_DCTRIPSEL_DCAHCOMPSEL_MASK <<
        ((uint16_t)dcType << 2U))) |
        ((uint16_t)tripSource << ((uint16_t)dcType << 2U))));
}
 
//
// DCFILT
//
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_enableDigitalCompareBlankingWindow(uint32_t base)
{
    //
    // Enable DC filter blanking window
    //
    HW_WR_REG16(base + CSL_EPWM_DCFCTL,
        (HW_RD_REG16(base + CSL_EPWM_DCFCTL) | CSL_EPWM_DCFCTL_BLANKE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disableDigitalCompareBlankingWindow(uint32_t base)
{
    //
    // Disable DC filter blanking window
    //
    HW_WR_REG16(base + CSL_EPWM_DCFCTL,
        (HW_RD_REG16(base + CSL_EPWM_DCFCTL) & ~CSL_EPWM_DCFCTL_BLANKE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_enableDigitalCompareWindowInverseMode(uint32_t base)
{
    //
    // Enable DC window inverse mode.
    //
    HW_WR_REG16(base + CSL_EPWM_DCFCTL,
        (HW_RD_REG16(base + CSL_EPWM_DCFCTL) | CSL_EPWM_DCFCTL_BLANKINV_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disableDigitalCompareWindowInverseMode(uint32_t base)
{
    //
    // Disable DC window inverse mode.
    //
    HW_WR_REG16(base + CSL_EPWM_DCFCTL,
        (HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
        ~CSL_EPWM_DCFCTL_BLANKINV_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setDigitalCompareBlankingEvent(uint32_t base,
                                EPWM_DigitalCompareBlankingPulse blankingPulse,
                                uint16_t mixedSource)
{
    if(blankingPulse == EPWM_DC_WINDOW_START_TBCTR_BLANK_PULSE_MIX)
    {
        //
        // Enable mixed events
        //
        HW_WR_REG16(base + CSL_EPWM_BLANKPULSEMIXSEL, mixedSource);
    }
 
    //
    // Set DC blanking event
    //
    HW_WR_REG16(base + CSL_EPWM_DCFCTL,
        ((HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
        ~CSL_EPWM_DCFCTL_PULSESEL_MASK) |
        ((uint16_t)((uint32_t)blankingPulse <<
        CSL_EPWM_DCFCTL_PULSESEL_SHIFT))));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setDigitalCompareFilterInput(uint32_t base,
                                  EPWM_DigitalCompareFilterInput filterInput)
{
    //
    // Set the signal source that will be filtered
    //
    HW_WR_REG16(base + CSL_EPWM_DCFCTL,
        ((HW_RD_REG16(base + CSL_EPWM_DCFCTL) & ~CSL_EPWM_DCFCTL_SRCSEL_MASK) |
        ((uint16_t)filterInput)));
}
 
//
// DC Edge Filter
//
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_enableDigitalCompareEdgeFilter(uint32_t base)
{
    //
    // Enable DC Edge Filter
    //
    HW_WR_REG16(base + CSL_EPWM_DCFCTL,
        (HW_RD_REG16(base + CSL_EPWM_DCFCTL) |
        CSL_EPWM_DCFCTL_EDGEFILTSEL_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disableDigitalCompareEdgeFilter(uint32_t base)
{
    //
    // Disable DC Edge Filter
    //
    HW_WR_REG16(base + CSL_EPWM_DCFCTL,
        (HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
        ~CSL_EPWM_DCFCTL_EDGEFILTSEL_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setDigitalCompareEdgeFilterMode(uint32_t base,
                                    EPWM_DigitalCompareEdgeFilterMode edgeMode)
{
    //
    // Set DC Edge filter mode
    //
    HW_WR_REG16(base + CSL_EPWM_DCFCTL,
        (HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
        ~CSL_EPWM_DCFCTL_EDGEMODE_MASK) |
        (edgeMode << CSL_EPWM_DCFCTL_EDGEMODE_SHIFT));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setDigitalCompareEdgeFilterEdgeCount(uint32_t base,
                            EPWM_DigitalCompareEdgeFilterEdgeCount edgeCount)
{
    //
    // Set DC Edge filter edge count
    //
    HW_WR_REG16(base + CSL_EPWM_DCFCTL,
        (HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
        ~CSL_EPWM_DCFCTL_EDGECOUNT_MASK) |
        (edgeCount << CSL_EPWM_DCFCTL_EDGECOUNT_SHIFT));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t
EPWM_getDigitalCompareEdgeFilterEdgeCount(uint32_t base)
{
    //
    // Return configured DC edge filter edge count
    //
    return((HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
            CSL_EPWM_DCFCTL_EDGECOUNT_MASK) >>
            CSL_EPWM_DCFCTL_EDGECOUNT_SHIFT);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t
EPWM_getDigitalCompareEdgeFilterEdgeStatus(uint32_t base)
{
    //
    // Return captured edge count by DC Edge filter
    //
    return((HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
            CSL_EPWM_DCFCTL_EDGESTATUS_MASK) >>
            CSL_EPWM_DCFCTL_EDGESTATUS_SHIFT);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setDigitalCompareWindowOffset(uint32_t base, uint16_t windowOffsetCount)
{
    //
    // Set the blanking window offset in TBCLK counts
    //
    HW_WR_REG16(base + CSL_EPWM_DCFOFFSET, windowOffsetCount);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setDigitalCompareWindowLength(uint32_t base, uint16_t windowLengthCount)
{
    //
    // Set the blanking window length in TBCLK counts
    //
    HW_WR_REG16(base + CSL_EPWM_DCFWINDOW, windowLengthCount);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t
EPWM_getDigitalCompareBlankingWindowOffsetCount(uint32_t base)
{
    //
    // Return the Blanking Window Offset count
    //
    return(HW_RD_REG16(base + CSL_EPWM_DCFOFFSETCNT));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t
EPWM_getDigitalCompareBlankingWindowLengthCount(uint32_t base)
{
    //
    // Return the Blanking Window Length count
    //
    return(HW_RD_REG16(base + CSL_EPWM_DCFWINDOWCNT));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setDigitalCompareEventSource(uint32_t base,
                                  EPWM_DigitalCompareModule dcModule,
                                  EPWM_DigitalCompareEvent dcEvent,
                                  EPWM_DigitalCompareEventSource dcEventSource)
{
    uint32_t registerOffset;
 
    registerOffset = CSL_EPWM_DCACTL + (uint16_t)dcModule * EPWM_DCxCTL_STEP;
 
    //
    // Set the DC event 1 source source
    //
    if(dcEvent == EPWM_DC_EVENT_1)
    {
        HW_WR_REG16(base + registerOffset,
            ((HW_RD_REG16(base + registerOffset) &
            ~CSL_EPWM_DCACTL_EVT1SRCSEL_MASK) |
            (uint16_t)dcEventSource));
    }
    else
    {
        HW_WR_REG16(base + registerOffset,
            ((HW_RD_REG16(base + registerOffset) &
            ~CSL_EPWM_DCACTL_EVT2SRCSEL_MASK) |
            ((uint16_t)dcEventSource << CSL_EPWM_DCACTL_EVT2SRCSEL_SHIFT)));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setDigitalCompareEventSyncMode(uint32_t base,
                                    EPWM_DigitalCompareModule dcModule,
                                    EPWM_DigitalCompareEvent dcEvent,
                                    EPWM_DigitalCompareSyncMode syncMode)
{
    uint32_t registerOffset;
 
    registerOffset = CSL_EPWM_DCACTL + (uint16_t)dcModule * EPWM_DCxCTL_STEP;
 
    //
    // Set the DC event sync mode
    //
    if(dcEvent == EPWM_DC_EVENT_1)
    {
        HW_WR_REG16(base + registerOffset,
            ((HW_RD_REG16(base + registerOffset) &
            ~CSL_EPWM_DCACTL_EVT1FRCSYNCSEL_MASK) |
            ((uint16_t)syncMode << CSL_EPWM_DCACTL_EVT1FRCSYNCSEL_SHIFT)));
    }
    else
    {
        HW_WR_REG16(base + registerOffset,
            ((HW_RD_REG16(base + registerOffset) &
            ~CSL_EPWM_DCACTL_EVT2FRCSYNCSEL_MASK) |
            ((uint16_t)syncMode << CSL_EPWM_DCACTL_EVT2FRCSYNCSEL_SHIFT)));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_enableDigitalCompareADCTrigger(uint32_t base,
                                    EPWM_DigitalCompareModule dcModule)
{
    uint32_t registerOffset;
 
    registerOffset = CSL_EPWM_DCACTL + (uint16_t)dcModule * EPWM_DCxCTL_STEP;
 
    //
    // Enable Digital Compare start of conversion generation
    //
    HW_WR_REG16(base + registerOffset,
        (HW_RD_REG16(base + registerOffset) | CSL_EPWM_DCACTL_EVT1SOCE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disableDigitalCompareADCTrigger(uint32_t base,
                                     EPWM_DigitalCompareModule dcModule)
{
    uint32_t registerOffset;
 
    registerOffset = CSL_EPWM_DCACTL + (uint16_t)dcModule * EPWM_DCxCTL_STEP;
 
    //
    // Disable Digital Compare start of conversion generation
    //
    HW_WR_REG16(base + registerOffset,
        (HW_RD_REG16(base + registerOffset) & ~CSL_EPWM_DCACTL_EVT1SOCE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_enableDigitalCompareSyncEvent(uint32_t base,
                                   EPWM_DigitalCompareModule dcModule)
{
    uint32_t registerOffset;
 
    registerOffset = CSL_EPWM_DCACTL + (uint16_t)dcModule * EPWM_DCxCTL_STEP;
 
    //
    // Enable Digital Compare sync out pulse generation
    //
    HW_WR_REG16(base + registerOffset,
        (HW_RD_REG16(base + registerOffset) | CSL_EPWM_DCACTL_EVT1SYNCE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disableDigitalCompareSyncEvent(uint32_t base,
                                    EPWM_DigitalCompareModule dcModule)
{
    uint32_t registerOffset;
 
    registerOffset = CSL_EPWM_DCACTL + (uint16_t)dcModule * EPWM_DCxCTL_STEP;
 
    //
    // Disable Digital Compare sync out pulse generation
    //
    HW_WR_REG16(base + registerOffset,
        (HW_RD_REG16(base + registerOffset) &
        ~CSL_EPWM_DCACTL_EVT1SYNCE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setDigitalCompareCBCLatchMode(uint32_t base,
                                   EPWM_DigitalCompareModule dcModule,
                                   EPWM_DigitalCompareEvent dcEvent,
                                   EPWM_DigitalCompareCBCLatchMode latchMode)
{
    uint32_t registerOffset;
 
    registerOffset = CSL_EPWM_DCACTL + (uint16_t)dcModule * EPWM_DCxCTL_STEP;
 
    //
    // Set the DC CBC Latch Mode
    //
    if(dcEvent == EPWM_DC_EVENT_1)
    {
        HW_WR_REG16(base + registerOffset,
            ((HW_RD_REG16(base + registerOffset) &
            ~CSL_EPWM_DCACTL_EVT1LATSEL_MASK) |
            ((uint16_t)latchMode << CSL_EPWM_DCACTL_EVT1LATSEL_SHIFT)));
    }
    else
    {
        HW_WR_REG16(base + registerOffset,
            ((HW_RD_REG16(base + registerOffset) &
            ~CSL_EPWM_DCACTL_EVT2LATSEL_MASK) |
            ((uint16_t)latchMode << CSL_EPWM_DCACTL_EVT2LATSEL_SHIFT)));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_selectDigitalCompareCBCLatchClearEvent(uint32_t base,
                              EPWM_DigitalCompareModule dcModule,
                              EPWM_DigitalCompareEvent dcEvent,
                              EPWM_DigitalCompareCBCLatchClearEvent clearEvent)
{
    uint32_t registerOffset;
 
    registerOffset = CSL_EPWM_DCACTL + (uint16_t)dcModule * EPWM_DCxCTL_STEP;
 
    //
    // Set the DC CBC Latch Clear Event
    //
    if(dcEvent == EPWM_DC_EVENT_1)
    {
        HW_WR_REG16(base + registerOffset,
            ((HW_RD_REG16(base + registerOffset) &
            ~CSL_EPWM_DCACTL_EVT1LATCLRSEL_MASK) |
            ((uint16_t)clearEvent << CSL_EPWM_DCACTL_EVT1LATCLRSEL_SHIFT)));
    }
    else
    {
        HW_WR_REG16(base + registerOffset,
            ((HW_RD_REG16(base + registerOffset) &
            ~CSL_EPWM_DCACTL_EVT2LATCLRSEL_MASK) |
            ((uint16_t)clearEvent << CSL_EPWM_DCACTL_EVT2LATCLRSEL_SHIFT)));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline bool
EPWM_getDigitalCompareCBCLatchStatus(uint32_t base,
                                     EPWM_DigitalCompareModule dcModule,
                                     EPWM_DigitalCompareEvent dcEvent)
{
    uint32_t registerOffset;
    uint16_t status;
 
    registerOffset = CSL_EPWM_DCACTL + (uint16_t)dcModule * EPWM_DCxCTL_STEP;
 
    //
    // Get DC CBC Latch Clear Event
    //
    if(dcEvent == EPWM_DC_EVENT_1)
    {
        status = HW_RD_REG16(base + registerOffset) &
                 CSL_EPWM_DCACTL_EVT1LAT_MASK;
    }
    else
    {
        status = HW_RD_REG16(base + registerOffset) &
                 CSL_EPWM_DCACTL_EVT2LAT_MASK;
    }
 
    return(status != 0U);
}
 
//
// DC capture mode
//
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_enableDigitalCompareCounterCapture(uint32_t base)
{
    //
    // Enable Time base counter capture
    //
    HW_WR_REG16(base + CSL_EPWM_DCCAPCTL,
        (HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) | CSL_EPWM_DCCAPCTL_CAPE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disableDigitalCompareCounterCapture(uint32_t base)
{
    //
    // Disable Time base counter capture
    //
    HW_WR_REG16(base + CSL_EPWM_DCCAPCTL,
        (HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) &
        ~CSL_EPWM_DCCAPCTL_CAPE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setDigitalCompareCounterShadowMode(uint32_t base, bool enableShadowMode)
{
    if(enableShadowMode)
    {
        //
        // Enable DC counter shadow mode
        //
        HW_WR_REG16(base + CSL_EPWM_DCCAPCTL,
            (HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) &
            ~CSL_EPWM_DCCAPCTL_SHDWMODE_MASK));
    }
    else
    {
       //
       // Disable DC counter shadow mode
       //
       HW_WR_REG16(base + CSL_EPWM_DCCAPCTL,
           (HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) |
           CSL_EPWM_DCCAPCTL_SHDWMODE_MASK));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline bool
EPWM_getDigitalCompareCaptureStatus(uint32_t base)
{
    //
    // Return the DC compare status
    //
    return((HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) &
            CSL_EPWM_DCCAPCTL_CAPSTS_MASK) == CSL_EPWM_DCCAPCTL_CAPSTS_MASK);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t
EPWM_getDigitalCompareCaptureCount(uint32_t base)
{
    //
    // Return the DC Time Base Counter Capture count value
    //
    return(HW_RD_REG16(base + CSL_EPWM_DCCAP));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_enableDigitalCompareTripCombinationInput(uint32_t base,
                                              uint16_t tripInput,
                                              EPWM_DigitalCompareType dcType)
{
    uint32_t registerOffset;
 
    //
    // Get the DCAHTRIPSEL, DCALTRIPSEL, DCBHTRIPSEL, DCBLTRIPSEL register
    // offset with respect to DCAHTRIPSEL
    //
    registerOffset = CSL_EPWM_DCAHTRIPSEL +
                     (uint16_t)dcType * EPWM_DCxxTRIPSEL;
 
    //
    // Set the DC trip input
    //
    HW_WR_REG16(base + registerOffset,
        (HW_RD_REG16(base + registerOffset) | tripInput));
 
    //
    // Enable the combination input
    //
    HW_WR_REG16(base + CSL_EPWM_DCTRIPSEL,
        (HW_RD_REG16(base + CSL_EPWM_DCTRIPSEL) |
        (CSL_EPWM_DCTRIPSEL_DCAHCOMPSEL_MASK << ((uint16_t)dcType << 2U))));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disableDigitalCompareTripCombinationInput(uint32_t base,
                                               uint16_t tripInput,
                                               EPWM_DigitalCompareType dcType)
{
    uint32_t registerOffset;
 
    //
    // Get the DCAHTRIPSEL, DCALTRIPSEL, DCBHTRIPSEL, DCBLTRIPSEL register
    // offset with respect to DCAHTRIPSEL
    //
    registerOffset = CSL_EPWM_DCAHTRIPSEL +
                     (uint16_t)dcType * EPWM_DCxxTRIPSEL;
 
    //
    // Set the DC trip input
    //
    HW_WR_REG16(base + registerOffset,
        (HW_RD_REG16(base + registerOffset) & ~tripInput));
}
 
//
// Valley switching
//
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_enableValleyCapture(uint32_t base)
{
    //
    // Set VCAPE bit
    //
    HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
        (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) | CSL_EPWM_VCAPCTL_VCAPE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disableValleyCapture(uint32_t base)
{
    //
    // Clear VCAPE bit
    //
    HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
        (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) & ~CSL_EPWM_VCAPCTL_VCAPE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_startValleyCapture(uint32_t base)
{
    //
    // Set VCAPSTART bit
    //
    HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
        (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) |
        CSL_EPWM_VCAPCTL_VCAPSTART_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setValleyTriggerSource(uint32_t base, EPWM_ValleyTriggerSource trigger)
{
    //
    // Write to TRIGSEL bits
    //
    HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
        ((HW_RD_REG16(base + CSL_EPWM_VCAPCTL) &
        ~CSL_EPWM_VCAPCTL_TRIGSEL_MASK) |
        ((uint16_t)trigger << CSL_EPWM_VCAPCTL_TRIGSEL_SHIFT)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setValleyTriggerEdgeCounts(uint32_t base, uint16_t startCount,
                                uint16_t stopCount)
{
    //
    // Check the arguments
    //
    DebugP_assert((startCount < 16U) && (stopCount < 16U));
 
    //
    // Write to STARTEDGE and STOPEDGE bits
    //
    HW_WR_REG16(base + CSL_EPWM_VCNTCFG,
        ((HW_RD_REG16(base + CSL_EPWM_VCNTCFG) &
        ~(CSL_EPWM_VCNTCFG_STARTEDGE_MASK | CSL_EPWM_VCNTCFG_STOPEDGE_MASK)) |
        (startCount | (stopCount << CSL_EPWM_VCNTCFG_STOPEDGE_SHIFT))));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_enableValleyHWDelay(uint32_t base)
{
    //
    // Set EDGEFILTDLYSEL bit
    //
    HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
        (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) |
        CSL_EPWM_VCAPCTL_EDGEFILTDLYSEL_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disableValleyHWDelay(uint32_t base)
{
    //
    // Clear EDGEFILTDLYSEL bit
    //
    HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
        (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) &
        ~CSL_EPWM_VCAPCTL_EDGEFILTDLYSEL_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setValleySWDelayValue(uint32_t base, uint16_t delayOffsetValue)
{
    //
    // Write to SWVDELVAL bits
    //
    HW_WR_REG16(base + CSL_EPWM_SWVDELVAL, delayOffsetValue);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setValleyDelayDivider(uint32_t base, EPWM_ValleyDelayMode delayMode)
{
    //
    // Write to VDELAYDIV bits
    //
    HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
        ((HW_RD_REG16(base + CSL_EPWM_VCAPCTL) &
        ~CSL_EPWM_VCAPCTL_VDELAYDIV_MASK) |
        ((uint16_t)delayMode << CSL_EPWM_VCAPCTL_VDELAYDIV_SHIFT)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline bool
EPWM_getValleyEdgeStatus(uint32_t base, EPWM_ValleyCounterEdge edge)
{
    if(edge == EPWM_VALLEY_COUNT_START_EDGE)
    {
        //
        // Returns STARTEDGESTS status
        //
        return(((HW_RD_REG16(base + CSL_EPWM_VCNTCFG) &
               CSL_EPWM_VCNTCFG_STARTEDGESTS_MASK) ==
               CSL_EPWM_VCNTCFG_STARTEDGESTS_MASK) ? true : false);
    }
    else
    {
        //
        // Returns STOPEDGESTS status
        //
        return(((HW_RD_REG16(base + CSL_EPWM_VCNTCFG) &
                CSL_EPWM_VCNTCFG_STOPEDGESTS_MASK) ==
                CSL_EPWM_VCNTCFG_STOPEDGESTS_MASK) ? true : false);
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t
EPWM_getValleyCount(uint32_t base)
{
    //
    // Read VCNTVAL register
    //
    return(HW_RD_REG16(base + CSL_EPWM_VCNTVAL));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t
EPWM_getValleyHWDelay(uint32_t base)
{
    //
    // Read HWVDELVAL  register
    //
    return(HW_RD_REG16(base + CSL_EPWM_HWVDELVAL));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_enableGlobalLoad(uint32_t base)
{
    //
    // Shadow to active load is controlled globally
    //
    HW_WR_REG16(base + CSL_EPWM_GLDCTL,
        (HW_RD_REG16(base + CSL_EPWM_GLDCTL) | CSL_EPWM_GLDCTL_GLD_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disableGlobalLoad(uint32_t base)
{
    //
    // Shadow to active load is controlled individually
    //
    HW_WR_REG16(base + CSL_EPWM_GLDCTL,
        (HW_RD_REG16(base + CSL_EPWM_GLDCTL) & ~CSL_EPWM_GLDCTL_GLD_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setGlobalLoadTrigger(uint32_t base, EPWM_GlobalLoadTrigger loadTrigger)
{
    //
    // Set the Global shadow to active load pulse
    //
    HW_WR_REG16(base + CSL_EPWM_GLDCTL,
        ((HW_RD_REG16(base + CSL_EPWM_GLDCTL) &
        ~CSL_EPWM_GLDCTL_GLDMODE_MASK) |
        ((uint16_t)loadTrigger << CSL_EPWM_GLDCTL_GLDMODE_SHIFT)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setGlobalLoadEventPrescale(uint32_t base, uint16_t prescalePulseCount)
{
    //
    // Check the arguments
    //
    DebugP_assert(prescalePulseCount < 8U);
 
    //
    // Set the number of counts that have to occur before
    // a load strobe is issued
    //
    HW_WR_REG16(base + CSL_EPWM_GLDCTL,
        ((HW_RD_REG16(base + CSL_EPWM_GLDCTL) & ~CSL_EPWM_GLDCTL_GLDPRD_MASK) |
        (prescalePulseCount << CSL_EPWM_GLDCTL_GLDPRD_SHIFT)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t
EPWM_getGlobalLoadEventCount(uint32_t base)
{
    //
    // Return the number of events that have occurred
    //
    return((HW_RD_REG16(base + CSL_EPWM_GLDCTL) >>
            CSL_EPWM_GLDCTL_GLDCNT_SHIFT) & CSL_EPWM_GLDCTL_GLDCNT_MAX);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disableGlobalLoadOneShotMode(uint32_t base)
{
    //
    // Enable global continuous shadow to active load
    //
    HW_WR_REG16(base + CSL_EPWM_GLDCTL,
        (HW_RD_REG16(base + CSL_EPWM_GLDCTL) &
        ~CSL_EPWM_GLDCTL_OSHTMODE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_enableGlobalLoadOneShotMode(uint32_t base)
{
    //
    // Enable global continuous shadow to active load
    //
    HW_WR_REG16(base + CSL_EPWM_GLDCTL,
        (HW_RD_REG16(base + CSL_EPWM_GLDCTL) | CSL_EPWM_GLDCTL_OSHTMODE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setGlobalLoadOneShotLatch(uint32_t base)
{
    //
    // Set a one shot Global shadow load pulse.
    //
    HW_WR_REG16(base + CSL_EPWM_GLDCTL2,
        (HW_RD_REG16(base + CSL_EPWM_GLDCTL2) | CSL_EPWM_GLDCTL2_OSHTLD_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_forceGlobalLoadOneShotEvent(uint32_t base)
{
    //
    // Force a Software Global shadow load pulse
    //
    HW_WR_REG16(base + CSL_EPWM_GLDCTL2,
        (HW_RD_REG16(base + CSL_EPWM_GLDCTL2) | CSL_EPWM_GLDCTL2_GFRCLD_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_enableGlobalLoadRegisters(uint32_t base, uint16_t loadRegister)
{
    //
    // Check the arguments
    //
    DebugP_assert((loadRegister > 0x0000U) && (loadRegister < 0x0800U));
 
    //
    // The register specified by loadRegister is loaded globally
    //
    HW_WR_REG16(base + CSL_EPWM_GLDCFG,
        (HW_RD_REG16(base + CSL_EPWM_GLDCFG) | loadRegister));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disableGlobalLoadRegisters(uint32_t base, uint16_t loadRegister)
{
    //
    // Check the arguments
    //
    DebugP_assert((loadRegister > 0x0000U) && (loadRegister < 0x0800U));
 
    //
    // The register specified by loadRegister is loaded by individual
    // register configuration setting
    //
    HW_WR_REG16(base + CSL_EPWM_GLDCFG,
        (HW_RD_REG16(base + CSL_EPWM_GLDCFG) & ~loadRegister));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_lockRegisters(uint32_t base, EPWM_LockRegisterGroup registerGroup)
{
    //
    // Write the Key to EPWMLOCK register
    //
    HW_WR_REG32(base + CSL_EPWM_EPWMLOCK,
        ((uint32_t)EPWM_LOCK_KEY | ((uint32_t)registerGroup)));
}
 
//
// Minimum Dead Band
//
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_enableMinimumDeadBand(uint32_t base, uint32_t block)
{
    if(block == EPWM_MINDB_BLOCK_A)
    {
        HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
            (HW_RD_REG32(base + CSL_EPWM_MINDBCFG) |
            CSL_EPWM_MINDBCFG_ENABLEA_MASK));
    }
    else
    {
        HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
            (HW_RD_REG32(base + CSL_EPWM_MINDBCFG) |
            CSL_EPWM_MINDBCFG_ENABLEB_MASK));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disableMinimumDeadBand(uint32_t base, uint32_t block)
{
    if(block == EPWM_MINDB_BLOCK_A)
    {
        HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
            (HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
            ~CSL_EPWM_MINDBCFG_ENABLEA_MASK));
    }
    else
    {
        HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
            (HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
            ~CSL_EPWM_MINDBCFG_ENABLEB_MASK));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_invertMinimumDeadBandSignal(uint32_t base, uint32_t block,
                                 uint32_t invert)
{
    if(block == EPWM_MINDB_BLOCK_A)
    {
        HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
            ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
            ~CSL_EPWM_MINDBCFG_INVERTA_MASK) |
            (invert<<CSL_EPWM_MINDBCFG_INVERTA_SHIFT)));
    }
    else
    {
        HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
            ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
            ~CSL_EPWM_MINDBCFG_INVERTB_MASK) |
            (invert<<CSL_EPWM_MINDBCFG_INVERTB_SHIFT)));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_selectMinimumDeadBandAndOrLogic(uint32_t base, uint32_t block,
                                     uint32_t referenceSignal)
{
    if(block == EPWM_MINDB_BLOCK_A)
    {
        HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
            ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
            ~CSL_EPWM_MINDBCFG_POLSELA_MASK) |
            (referenceSignal<<CSL_EPWM_MINDBCFG_POLSELA_SHIFT)));
    }
    else
    {
        HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
            ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
            ~CSL_EPWM_MINDBCFG_POLSELB_MASK) |
            (referenceSignal<<CSL_EPWM_MINDBCFG_POLSELB_SHIFT)));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_selectMinimumDeadBandBlockingSignal(uint32_t base, uint32_t block,
                                         uint32_t blockingSignal)
{
    if(block == EPWM_MINDB_BLOCK_A)
    {
        HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
            ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
            ~CSL_EPWM_MINDBCFG_SELBLOCKA_MASK) |
            (blockingSignal<<CSL_EPWM_MINDBCFG_SELBLOCKA_SHIFT)));
    }
    else
    {
        HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
            ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
            ~CSL_EPWM_MINDBCFG_SELBLOCKB_MASK) |
            (blockingSignal<<CSL_EPWM_MINDBCFG_SELBLOCKB_SHIFT)));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_selectMinimumDeadBandReferenceSignal(uint32_t base, uint32_t block,
                                          uint32_t referenceSignal)
{
    if(block == EPWM_MINDB_BLOCK_A)
    {
        HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
            ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
            ~CSL_EPWM_MINDBCFG_SELA_MASK) |
            (referenceSignal<<CSL_EPWM_MINDBCFG_SELA_SHIFT)));
    }
    else
    {
        HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
            ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
            ~CSL_EPWM_MINDBCFG_SELB_MASK) |
            (referenceSignal<<CSL_EPWM_MINDBCFG_SELB_SHIFT)));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint32_t
EPWM_getMinDeadBandDelay(uint32_t base, uint32_t block)
{
    uint32_t retval;
 
    if(block == EPWM_MINDB_BLOCK_A)
    {
        retval = (HW_RD_REG32(base + CSL_EPWM_MINDBDLY) &
                  CSL_EPWM_MINDBDLY_DELAYA_MASK);
    }
    else
    {
        retval = (HW_RD_REG32(base + CSL_EPWM_MINDBDLY) &
                  CSL_EPWM_MINDBDLY_DELAYB_MASK);
    }
 
    return retval;
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setMinDeadBandDelay(uint32_t base, uint32_t block, uint32_t delay)
{
    if(block == EPWM_MINDB_BLOCK_A)
    {
        HW_WR_REG32(base + CSL_EPWM_MINDBDLY,
            ((HW_RD_REG32(base + CSL_EPWM_MINDBDLY) &
            ~CSL_EPWM_MINDBDLY_DELAYA_MASK) |
            (delay<<CSL_EPWM_MINDBDLY_DELAYA_SHIFT)));
    }
    else
    {
        HW_WR_REG32(base + CSL_EPWM_MINDBDLY,
            ((HW_RD_REG32(base + CSL_EPWM_MINDBDLY) &
            ~CSL_EPWM_MINDBDLY_DELAYB_MASK) |
            (delay<<CSL_EPWM_MINDBDLY_DELAYB_SHIFT)));
    }
}
 
//
// Illegal Combo Logic
//
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_enableIllegalComboLogic(uint32_t base, uint32_t block)
{
    if(block == EPWM_MINDB_BLOCK_A)
    {
        HW_WR_REG32(base + CSL_EPWM_LUTCTLA,
            (HW_RD_REG32(base + CSL_EPWM_LUTCTLA) &
            ~CSL_EPWM_LUTCTLA_BYPASS_MASK));
    }
    else
    {
        HW_WR_REG32(base + CSL_EPWM_LUTCTLB,
            (HW_RD_REG32(base + CSL_EPWM_LUTCTLB) &
            ~CSL_EPWM_LUTCTLB_BYPASS_MASK));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disableIllegalComboLogic(uint32_t base, uint32_t block)
{
    if(block == EPWM_MINDB_BLOCK_A)
    {
        HW_WR_REG32(base + CSL_EPWM_LUTCTLA,
            (HW_RD_REG32(base + CSL_EPWM_LUTCTLA) |
            CSL_EPWM_LUTCTLA_BYPASS_MASK));
    }
    else
    {
        HW_WR_REG32(base + CSL_EPWM_LUTCTLB,
            (HW_RD_REG32(base + CSL_EPWM_LUTCTLB) |
            CSL_EPWM_LUTCTLB_BYPASS_MASK));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_selectXbarInput(uint32_t base, uint32_t block, uint32_t xbarInput)
{
    if(block == EPWM_MINDB_BLOCK_A)
    {
        HW_WR_REG32(base + CSL_EPWM_LUTCTLA,
            ((HW_RD_REG32(base + CSL_EPWM_LUTCTLA) &
            ~CSL_EPWM_LUTCTLA_SELXBAR_MASK) |
            (xbarInput<<CSL_EPWM_LUTCTLA_SELXBAR_SHIFT)));
    }
    else
    {
        HW_WR_REG32(base + CSL_EPWM_LUTCTLB,
            ((HW_RD_REG32(base + CSL_EPWM_LUTCTLB) &
            ~CSL_EPWM_LUTCTLB_SELXBAR_MASK) |
            (xbarInput<<CSL_EPWM_LUTCTLB_SELXBAR_SHIFT)));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setLutDecX(uint32_t base, uint32_t block, uint32_t decx, uint32_t force)
{
    if(block == EPWM_MINDB_BLOCK_A)
    {
        HW_WR_REG32(base + CSL_EPWM_LUTCTLA,
            ((HW_RD_REG32(base + CSL_EPWM_LUTCTLA) &
            ~(CSL_EPWM_LUTCTLA_LUTDEC0_MAX <<
            (CSL_EPWM_LUTCTLA_LUTDEC0_SHIFT+decx))) |
            (force<<(CSL_EPWM_LUTCTLA_LUTDEC0_SHIFT+decx))));
    }
    else if(block == EPWM_MINDB_BLOCK_B)
    {
        HW_WR_REG32(base + CSL_EPWM_LUTCTLB,
            ((HW_RD_REG32(base + CSL_EPWM_LUTCTLB) &
            ~(CSL_EPWM_LUTCTLB_LUTDEC0_MAX <<
            (CSL_EPWM_LUTCTLB_LUTDEC0_SHIFT+decx))) |
            (force<<(CSL_EPWM_LUTCTLB_LUTDEC0_SHIFT+decx))));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
HRPWM_setPhaseShift(uint32_t base, uint32_t phaseCount)
{
    //
    // Check the arguments
    //
    DebugP_assert(phaseCount <= 0xFFFFFFFF);
 
    //
    // Write to TBPHS:TBPHSHR bits
    //
    HW_WR_REG32(base + CSL_EPWM_TBPHS, phaseCount<<8U);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
HRPWM_setHiResPhaseShift(uint32_t base, uint16_t hrPhaseCount)
{
    //
    // Check the arguments
    //
    DebugP_assert(hrPhaseCount <= CSL_EPWM_TBPHS_TBPHSHR_MAX);
 
    //
    // Write to TBPHSHR bits
    //
    HW_WR_REG32(base + CSL_EPWM_TBPHS,
        ((HW_RD_REG32(base + CSL_EPWM_TBPHS) &
        ~((uint32_t)CSL_EPWM_TBPHS_TBPHSHR_MASK)) |
        ((uint32_t)hrPhaseCount << (CSL_EPWM_TBPHS_TBPHSHR_SHIFT + 8U))));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
HRPWM_setHiResTimeBasePeriod(uint32_t base, uint16_t hrPeriodCount)
{
    //
    // Check the arguments
    //
    DebugP_assert(hrPeriodCount <= CSL_EPWM_TBPRDHR_TBPRDHR_MAX);
 
    //
    // Write to TBPRDHR bits
    //
    HW_WR_REG16(base + CSL_EPWM_TBPRDHR, hrPeriodCount << 8);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t
HRPWM_getHiResTimeBasePeriod(uint32_t base)
{
    //
    // Read from TBPRDHR bit
    //
    return(HW_RD_REG16(base + CSL_EPWM_TBPRDHR) >> 8U);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
HRPWM_setMEPEdgeSelect(uint32_t base, HRPWM_Channel channel,
                       HRPWM_MEPEdgeMode mepEdgeMode)
{
    //
    // Set the edge mode
    //
    HW_WR_REG16(base + CSL_EPWM_HRCNFG,
        ((HW_RD_REG16(base + CSL_EPWM_HRCNFG) &
        ~(CSL_EPWM_HRCNFG_EDGMODE_MAX << (uint16_t)channel)) |
        ((uint16_t)mepEdgeMode << (uint16_t)channel)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
HRPWM_setMEPControlMode(uint32_t base, HRPWM_Channel channel,
                        HRPWM_MEPCtrlMode mepCtrlMode)
{
    //
    // Set the MEP control
    //
    HW_WR_REG16(base + CSL_EPWM_HRCNFG,
        ((HW_RD_REG16(base + CSL_EPWM_HRCNFG) &
        ~(CSL_EPWM_HRCNFG_CTLMODE_MAX << ((uint16_t)channel + 2U))) |
        ((uint16_t)mepCtrlMode << ((uint16_t)channel + 2U))));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
HRPWM_setCounterCompareShadowLoadEvent(uint32_t base, HRPWM_Channel channel,
                                       HRPWM_LoadMode loadEvent)
{
    //
    // Set the CMPAHR or CMPBHR load mode
    //
    HW_WR_REG16(base + CSL_EPWM_HRCNFG,
        ((HW_RD_REG16(base + CSL_EPWM_HRCNFG) &
        ~(CSL_EPWM_HRCNFG_HRLOAD_MAX << ((uint16_t)channel + 3U))) |
        ((uint16_t)loadEvent << ((uint16_t)channel + 3U))));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
HRPWM_setOutputSwapMode(uint32_t base, bool enableOutputSwap)
{
    //
    // Set output swap mode
    //
    if(enableOutputSwap)
    {
        HW_WR_REG16(base + CSL_EPWM_HRCNFG,
            HW_RD_REG16(base + CSL_EPWM_HRCNFG) | CSL_EPWM_HRCNFG_SWAPAB_MASK);
    }
    else
    {
        HW_WR_REG16(base + CSL_EPWM_HRCNFG,
            HW_RD_REG16(base + CSL_EPWM_HRCNFG) & ~CSL_EPWM_HRCNFG_SWAPAB_MASK);
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
HRPWM_setChannelBOutputPath(uint32_t base, HRPWM_ChannelBOutput outputOnB)
{
    //
    // Set the output on ePWM B
    //
    HW_WR_REG16(base + CSL_EPWM_HRCNFG,
        ((HW_RD_REG16(base + CSL_EPWM_HRCNFG) & ~(CSL_EPWM_HRCNFG_SELOUTB_MASK)) |
        ((uint16_t)outputOnB << CSL_EPWM_HRCNFG_SELOUTB_SHIFT)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
HRPWM_enableAutoConversion(uint32_t base)
{
    //
    // Enable MEP automatic scale
    //
    HW_WR_REG16(base + CSL_EPWM_HRCNFG,
        HW_RD_REG16(base + CSL_EPWM_HRCNFG) | CSL_EPWM_HRCNFG_AUTOCONV_MASK);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
HRPWM_disableAutoConversion(uint32_t base)
{
    //
    // Disable MEP automatic scale
    //
    HW_WR_REG16(base + CSL_EPWM_HRCNFG,
        HW_RD_REG16(base + CSL_EPWM_HRCNFG) & ~CSL_EPWM_HRCNFG_AUTOCONV_MASK);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
HRPWM_enablePeriodControl(uint32_t base)
{
    //
    // Set HRPE bit
    //
    HW_WR_REG16(base + CSL_EPWM_HRPCTL,
        HW_RD_REG16(base + CSL_EPWM_HRPCTL) | CSL_EPWM_HRPCTL_HRPE_MASK);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
HRPWM_disablePeriodControl(uint32_t base)
{
    //
    // Clear HRPE bit
    //
    HW_WR_REG16(base + CSL_EPWM_HRPCTL,
        HW_RD_REG16(base + CSL_EPWM_HRPCTL) & ~CSL_EPWM_HRPCTL_HRPE_MASK);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
HRPWM_enablePhaseShiftLoad(uint32_t base)
{
    //
    // Set TBPHSHRLOADE bit
    //
    HW_WR_REG16(base + CSL_EPWM_HRPCTL,
        HW_RD_REG16(base + CSL_EPWM_HRPCTL) | CSL_EPWM_HRPCTL_TBPHSHRLOADE_MASK);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
HRPWM_disablePhaseShiftLoad(uint32_t base)
{
    //
    // Clear TBPHSHRLOADE bit
    //
    HW_WR_REG16(base + CSL_EPWM_HRPCTL,
        HW_RD_REG16(base + CSL_EPWM_HRPCTL) & ~CSL_EPWM_HRPCTL_TBPHSHRLOADE_MASK);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
HRPWM_setSyncPulseSource(uint32_t base, HRPWM_SyncPulseSource syncPulseSource)
{
    //
    // Set the PWMSYNC source
    //
 
    //
    // Configuration for sync pulse source equal to HRPWM_PWMSYNC_SOURCE_PERIOD
    // or HRPWM_PWMSYNC_SOURCE_ZERO
    //
    if(syncPulseSource < HRPWM_PWMSYNC_SOURCE_COMPC_UP)
    {
        HW_WR_REG16(base + CSL_EPWM_HRPCTL,
            ((HW_RD_REG16(base + CSL_EPWM_HRPCTL) &
            ~(CSL_EPWM_HRPCTL_PWMSYNCSELX_MASK | CSL_EPWM_HRPCTL_PWMSYNCSEL_MASK)) |
            ((uint16_t)syncPulseSource << 1U)));
    }
    else
    {
        HW_WR_REG16(base + CSL_EPWM_HRPCTL,
            ((HW_RD_REG16(base + CSL_EPWM_HRPCTL) & ~CSL_EPWM_HRPCTL_PWMSYNCSELX_MASK) |
            ((uint16_t)syncPulseSource << CSL_EPWM_HRPCTL_PWMSYNCSELX_SHIFT)));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
HRPWM_setTranslatorRemainder(uint32_t base, uint16_t trremVal)
{
    //
    // Check the arguments
    //
    DebugP_assert(trremVal <= CSL_EPWM_TRREM_TRREM_MAX);
 
    //
    // Set Translator Remainder value
    //
    HW_WR_REG16(base + CSL_EPWM_TRREM, trremVal & CSL_EPWM_TRREM_TRREM_MASK);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
HRPWM_setCounterCompareValue(uint32_t base,
                             HRPWM_CounterCompareModule compModule,
                             uint32_t compCount)
{
    //
    // Check the arguments
    //
    DebugP_assert(compCount <= 0xFFFFFFFF);
 
    //
    // Write to counter compare registers
    //
    if(compModule == HRPWM_COUNTER_COMPARE_A)
    {
        //
        // Write to CMPA:CMPAHR
        //
        HW_WR_REG32(base + CSL_EPWM_CMPA, compCount << 8);
    }
    else
    {
        //
        // Write to CMPB:CMPBHR
        //
        HW_WR_REG32(base + CSL_EPWM_CMPB, compCount << 8);
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint32_t
HRPWM_getCounterCompareValue(uint32_t base,
                             HRPWM_CounterCompareModule compModule)
{
    uint32_t compCount;
 
    //
    // Get counter compare value for selected module
    //
    if(compModule == HRPWM_COUNTER_COMPARE_A)
    {
        //
        // Read from CMPAHR
        //
        compCount = HW_RD_REG32(base + CSL_EPWM_CMPA);
    }
    else
    {
        //
        // Read from CMPBHR
        //
        compCount = HW_RD_REG32(base + CSL_EPWM_CMPB);
    }
 
    return(compCount>>8U);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
HRPWM_setHiResCounterCompareValue(uint32_t base,
                                 HRPWM_CounterCompareModule compModule,
                                 uint16_t hrCompCount)
{
    //
    // Check the arguments
    //
    DebugP_assert(hrCompCount <= CSL_EPWM_CMPA_CMPAHR_MAX);
 
    //
    // Write to the high resolution counter compare registers
    //
    if(compModule == HRPWM_COUNTER_COMPARE_A)
    {
        //
        // Write to CMPAHR
        //
        HW_WR_REG32(base + CSL_EPWM_CMPA,
            HW_RD_REG32(base + CSL_EPWM_CMPA) | ((hrCompCount & CSL_EPWM_CMPA_CMPAHR_MASK) << 8U));
    }
    else
    {
        //
        // Write to CMPBHR
        //
        HW_WR_REG32(base + CSL_EPWM_CMPB,
            HW_RD_REG32(base + CSL_EPWM_CMPB) | ((hrCompCount & CSL_EPWM_CMPB_CMPBHR_MASK) << 8U));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t
HRPWM_getHiResCounterCompareValueOnly(uint32_t base,
                                      HRPWM_CounterCompareModule compModule)
{
    uint16_t hrCompCount;
 
    //
    // Get counter compare value for selected module
    //
    if(compModule == HRPWM_COUNTER_COMPARE_A)
    {
        //
        // Read from CMPAHR
        //
        hrCompCount = (HW_RD_REG16(base + CSL_EPWM_CMPA) & CSL_EPWM_CMPA_CMPAHR_MASK);
    }
    else
    {
        //
        // Read from CMPBHR
        //
        hrCompCount = (HW_RD_REG16(base + CSL_EPWM_CMPB) & CSL_EPWM_CMPB_CMPBHR_MASK);
    }
 
    return(hrCompCount >> 8U);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
HRPWM_setHiResRisingEdgeDelay(uint32_t base, uint16_t hrRedCount)
{
    //
    // Check the arguments
    //
    DebugP_assert(hrRedCount <= CSL_EPWM_DBREDHR_DBREDHR_MAX);
 
    //
    // Set the High Resolution RED (Rising Edge Delay) count only
    //
    HW_WR_REG16(base + CSL_EPWM_DBREDHR,
      HW_RD_REG16(base + CSL_EPWM_DBREDHR) |
      (hrRedCount << CSL_EPWM_DBREDHR_DBREDHR_SHIFT));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
HRPWM_setHiResFallingEdgeDelayOnly(uint32_t base, uint16_t hrFedCount)
{
    //
    // Check the arguments
    //
    DebugP_assert(hrFedCount <= CSL_EPWM_DBFEDHR_DBFEDHR_MAX);
 
    //
    // Set the high resolution FED (Falling Edge Delay) count
    //
    HW_WR_REG16(base + CSL_EPWM_DBFEDHR,
        HW_RD_REG16(base + CSL_EPWM_DBFEDHR) &
        ~CSL_EPWM_DBFEDHR_DBFEDHR_MASK |
        (hrFedCount << CSL_EPWM_DBFEDHR_DBFEDHR_SHIFT));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
HRPWM_setMEPStep(uint32_t base, uint16_t mepCount)
{
    //
    // Check the arguments
    //
    DebugP_assert(mepCount <= CSL_OTTOCAL_HRMSTEP_HRMSTEP_MAX);
 
    //
    // Set HRPWM MEP count
    //
    HW_WR_REG16(base + CSL_OTTOCAL_HRMSTEP,
        ((HW_RD_REG16(base + CSL_OTTOCAL_HRMSTEP) & ~CSL_OTTOCAL_HRMSTEP_HRMSTEP_MASK) |
        mepCount << CSL_OTTOCAL_HRMSTEP_HRMSTEP_SHIFT));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
HRPWM_setDeadbandMEPEdgeSelect(uint32_t base,
                              HRPWM_MEPDeadBandEdgeMode mepDBEdge)
{
    //
    // Set the HRPWM DB edge mode
    //
    HW_WR_REG16(base + CSL_EPWM_HRCNFG2,
        ((HW_RD_REG16(base + CSL_EPWM_HRCNFG2) & ~CSL_EPWM_HRCNFG2_EDGMODEDB_MASK) |
        ((uint16_t)mepDBEdge << CSL_EPWM_HRCNFG2_EDGMODEDB_SHIFT)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
HRPWM_setRisingEdgeDelayLoadMode(uint32_t base,
                                 HRPWM_LoadMode loadEvent)
{
    //
    // Set the HRPWM RED load mode
    //
    HW_WR_REG16(base + CSL_EPWM_HRCNFG2,
        ((HW_RD_REG16(base + CSL_EPWM_HRCNFG2) & ~CSL_EPWM_HRCNFG2_CTLMODEDBRED_MASK) |
        ((uint16_t)loadEvent << CSL_EPWM_HRCNFG2_CTLMODEDBRED_SHIFT)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
HRPWM_setFallingEdgeDelayLoadMode(uint32_t base, HRPWM_LoadMode loadEvent)
{
    //
    // Set the HRPWM FED load mode
    //
    HW_WR_REG16(base + CSL_EPWM_HRCNFG2,
        ((HW_RD_REG16(base + CSL_EPWM_HRCNFG2) & ~CSL_EPWM_HRCNFG2_CTLMODEDBFED_MASK) |
        ((uint16_t)loadEvent << CSL_EPWM_HRCNFG2_CTLMODEDBFED_SHIFT)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
HRPWM_setXCMPRegValue(uint32_t base, HRPWM_XCMPReg xcmpReg,
                            uint16_t xcmpvalue)
{
    uint32_t registerOffset;
 
    //
    // Get the register offset for the Counter compare
    //
    registerOffset = base + CSL_EPWM_XCMP1_ACTIVE + (uint16_t)xcmpReg;
 
    //
    // Write to the xcmp registers.
    //
    HW_WR_REG16(registerOffset, xcmpvalue);
}
//
// XCMP related APIs
//
//*****************************************************************************
//
//
//*****************************************************************************
 
static inline void
EPWM_enableXCMPMode(uint32_t base)
{
    uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
 
    HW_WR_REG32(registerOffset,
        (HW_RD_REG32(registerOffset) | CSL_EPWM_XCMPCTL1_XCMPEN_MAX ));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disableXCMPMode(uint32_t base)
{
    uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
 
    HW_WR_REG32(registerOffset,
        (HW_RD_REG32(registerOffset) & ~CSL_EPWM_XCMPCTL1_XCMPEN_MAX ));
}
 
 
//*****************************************************************************
//
//
//*****************************************************************************
 
static inline void
EPWM_enableSplitXCMP(uint32_t base)
{
    uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
    uint32_t offset = CSL_EPWM_XCMPCTL1_XCMPSPLIT_SHIFT;
 
    HW_WR_REG32(registerOffset,
        (HW_RD_REG32(registerOffset) | ( CSL_EPWM_XCMPCTL1_XCMPSPLIT_MAX << offset )));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
 
static inline void
EPWM_disableSplitXCMP(uint32_t base)
{
    uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
    uint32_t offset = CSL_EPWM_XCMPCTL1_XCMPSPLIT_SHIFT;
 
    HW_WR_REG32(registerOffset,
      (HW_RD_REG32(registerOffset) & ~( CSL_EPWM_XCMPCTL1_XCMPSPLIT_MAX << offset )));
 
}
 
//*****************************************************************************
//
 
//
//*****************************************************************************
 
static inline void
EPWM_allocAXCMP(uint32_t base, EPWM_XCMP_ALLOC_CMPA alloctype)
{
    uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
    uint32_t offset = CSL_EPWM_XCMPCTL1_XCMPA_ALLOC_SHIFT;
 
   HW_WR_REG32(registerOffset,
        ( (HW_RD_REG32(registerOffset) & ~CSL_EPWM_XCMPCTL1_XCMPA_ALLOC_MASK) | ( alloctype << offset )));
}
 
//*****************************************************************************
//
 
//
//*****************************************************************************
 
static inline void
EPWM_allocBXCMP(uint32_t base, EPWM_XCMP_ALLOC_CMPB alloctype)
{
    uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
    uint32_t offset = CSL_EPWM_XCMPCTL1_XCMPB_ALLOC_SHIFT;
 
    HW_WR_REG32(registerOffset,
        ( (HW_RD_REG32(registerOffset) & ~CSL_EPWM_XCMPCTL1_XCMPB_ALLOC_MASK) | ( alloctype << offset )));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
 
static inline void
EPWM_setXCMPRegValue(uint32_t base, EPWM_XCMPReg xcmpReg,
                            uint16_t xcmpvalue)
{
    uint32_t registerOffset;
 
    //
    // Get the register offset for the Counter compare
    //
    registerOffset = base + CSL_EPWM_XCMP1_ACTIVE + (uint16_t)xcmpReg;
 
    //
    // Write to the xcmp registers.
    //
    HW_WR_REG16(registerOffset + 0x2U, xcmpvalue);
}
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setCMPShadowRegValue(uint32_t base, EPWM_XCompareReg cmpReg,
                            uint16_t cmpvalue)
{
    //
    // Check the arguments
    //
    uint32_t registerOffset;
    registerOffset = base + CSL_EPWM_CMPC_SHDW1 + (uint32_t)cmpReg;
 
    //
    // Write to the CMPC/D Shadow registers.
    //
    HW_WR_REG16(registerOffset, cmpvalue);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setXMINMAXRegValue(uint32_t base, EPWM_XMinMaxReg xminmaxReg,
                            uint16_t xcmpvalue)
{
    //
    // Check the arguments
    //
    uint32_t registerOffset;
    registerOffset = base +  CSL_EPWM_XMINMAX_ACTIVE + (uint16_t)xminmaxReg;
 
    //
    // Write to the XMINMAX register.
    //
    HW_WR_REG16(registerOffset, xcmpvalue);
}
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_setXCMPActionQualifierAction(uint32_t base, uint32_t shadowset,
                              EPWM_ActionQualifierOutputModule epwmOutput,
                              EPWM_ActionQualifierOutput output,
                              EPWM_XCMPActionQualifierOutputEvent event)
{
    uint32_t registerOffset;
 
    //
    // Get the register offset
    //
 
    if(shadowset == EPWM_XCMP_ACTIVE)
    {
        registerOffset = CSL_EPWM_XAQCTLA_ACTIVE + (uint16_t)(epwmOutput/2);
 
        HW_WR_REG16(base + registerOffset,
            ((HW_RD_REG16(base + registerOffset) &
            ~(CSL_EPWM_XAQCTLA_ACTIVE_XCMP1_MAX << (uint16_t)event)) |
            ((uint16_t)output << (uint16_t)event)));
    }
    else if(shadowset == EPWM_XCMP_SHADOW1)
    {
        registerOffset = CSL_EPWM_XAQCTLA_SHDW1 + (uint16_t)(epwmOutput/2);
 
        HW_WR_REG16(base + registerOffset,
        ((HW_RD_REG16(base + registerOffset) &
        ~(CSL_EPWM_XAQCTLA_SHDW1_XCMP1_MAX << (uint16_t)event)) |
        ((uint16_t)output << (uint16_t)event)));
    }
    else if(shadowset == EPWM_XCMP_SHADOW2)
    {
        registerOffset = CSL_EPWM_XAQCTLA_SHDW2 + (uint16_t)(epwmOutput/2);
 
        HW_WR_REG16(base + registerOffset,
        ((HW_RD_REG16(base + registerOffset) &
        ~(CSL_EPWM_XAQCTLA_SHDW2_XCMP1_MAX << (uint16_t)event)) |
        ((uint16_t)output << (uint16_t)event)));
    }
    else if(shadowset == EPWM_XCMP_SHADOW3)
    {
        registerOffset = CSL_EPWM_XAQCTLA_SHDW3 + (uint16_t)(epwmOutput/2);
 
        HW_WR_REG16(base + registerOffset,
        ((HW_RD_REG16(base + registerOffset) &
        ~(CSL_EPWM_XAQCTLA_SHDW3_XCMP1_MAX << (uint16_t)event)) |
        ((uint16_t)output << (uint16_t)event)));
    }
 
}
 
//*****************************************************************************
//
//
//*****************************************************************************
 
static inline void
EPWM_enableXLoad(uint32_t base)
{
    uint32_t registerOffset = base + CSL_EPWM_XLOAD;
 
    HW_WR_REG32(registerOffset,
        (HW_RD_REG32(registerOffset) | CSL_EPWM_XLOAD_STARTLD_MASK ));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_disableXLoad(uint32_t base)
{
    uint32_t registerOffset = base + CSL_EPWM_XLOAD;
 
    HW_WR_REG32(registerOffset,
        (HW_RD_REG32(registerOffset) & ~CSL_EPWM_XLOAD_STARTLD_MASK ));
}
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EPWM_forceXLoad(uint32_t base)
{
    //
    // Check the arguments
    //
    uint32_t registerOffset;
    registerOffset = base + CSL_EPWM_XLOAD;
 
    HW_WR_REG32(registerOffset,
        (HW_RD_REG32(registerOffset) | CSL_EPWM_XLOAD_FRCLD_MASK ));
}
//*****************************************************************************
//
 
//
//*****************************************************************************
 
static inline void
EPWM_setXCMPLoadMode(uint32_t base,EPWM_XCMPXloadCtlLoadMode mode)
{
    uint32_t registerOffset;
 
    //
    // Get the register offset
    //
    registerOffset =  base + CSL_EPWM_XLOADCTL;
 
    if(mode == EPWM_XCMP_XLOADCTL_LOADMODE_LOADONCE)
    {
        HW_WR_REG32(registerOffset,
        (HW_RD_REG32(registerOffset) & ~CSL_EPWM_XLOADCTL_LOADMODE_MASK));
    }
    else if(mode == EPWM_XCMP_XLOADCTL_LOADMODE_LOADMULTIPLE)
    {
        HW_WR_REG32(registerOffset,
        (HW_RD_REG32(registerOffset) | CSL_EPWM_XLOADCTL_LOADMODE_MASK));
    }
}
 
//*****************************************************************************
//
 
//
//*****************************************************************************
static inline void
EPWM_setXCMPShadowLevel(uint32_t base, EPWM_XCMP_XLOADCTL_SHDWLEVEL level)
{
    uint32_t registerOffset;
 
    //
    // Get the register offset
    //
    registerOffset =  base + CSL_EPWM_XLOADCTL;
 
    HW_WR_REG32(registerOffset,
        ((HW_RD_REG32(registerOffset) & ~CSL_EPWM_XLOADCTL_SHDWLEVEL_MASK) |
        ((uint16_t)level << CSL_EPWM_XLOADCTL_SHDWLEVEL_SHIFT)));
}
 
//*****************************************************************************
//
 
//
//*****************************************************************************
static inline void
EPWM_setXCMPShadowBufPtrLoadOnce(uint32_t base, EPWM_XCMP_XLOADCTL_SHDWBUFPTR ptr)
{
    uint32_t registerOffset;
 
    //
    // Get the register offset
    //
    registerOffset =  base + CSL_EPWM_XLOADCTL;
 
    HW_WR_REG32(registerOffset,
        ((HW_RD_REG32(registerOffset) & ~CSL_EPWM_XLOADCTL_SHDWBUFPTR_LOADONCE_MASK) |
        ((uint16_t)ptr << CSL_EPWM_XLOADCTL_SHDWBUFPTR_LOADONCE_SHIFT)));
}
 
//*****************************************************************************
//
 
//
//*****************************************************************************
static inline void
EPWM_setXCMPShadowRepeatBufxCount(uint32_t base, uint32_t bufferset, uint8_t count)
{
    uint32_t registerOffset;
    //
    // Get the register offset
    //
    registerOffset =  base + CSL_EPWM_XLOADCTL;
 
    if(bufferset == EPWM_XCMP_SHADOW2)
    {
        HW_WR_REG32(registerOffset,
            ((HW_RD_REG32(registerOffset) & ~(CSL_EPWM_XLOADCTL_RPTBUF2PRD_MASK))
            | (count<<CSL_EPWM_XLOADCTL_RPTBUF2PRD_SHIFT)) );
    }
    else if(bufferset == EPWM_XCMP_SHADOW3)
    {
         HW_WR_REG32(registerOffset,
        ((HW_RD_REG32(registerOffset) & ~(CSL_EPWM_XLOADCTL_RPTBUF3PRD_MASK))
        | (count<<CSL_EPWM_XLOADCTL_RPTBUF3PRD_SHIFT)) );
    }
}
 
//*************************************************
//
// DIODE EMULATION LOGIC APIs
//
 
//*****************************************************************************
//
//
//*****************************************************************************
 
static inline void
EPWM_enableDiodeEmulationMode(uint32_t base)
{
    uint32_t registerOffset;
    //
    // Get the register offset
    //
    registerOffset =  base + CSL_EPWM_DECTL;
 
    HW_WR_REG32(registerOffset,
        (HW_RD_REG32(registerOffset) | CSL_EPWM_DECTL_ENABLE_MAX ));
 
}
 
//*****************************************************************************
//
//
//*****************************************************************************
 
static inline void
EPWM_disableDiodeEmulationMode(uint32_t base)
{
    uint32_t registerOffset;
    //
    // Get the register offset
    //
    registerOffset =  base + CSL_EPWM_DECTL;
 
    HW_WR_REG32(registerOffset,
        (HW_RD_REG32(registerOffset) & ~CSL_EPWM_DECTL_ENABLE_MAX ));
 
}
 
//*****************************************************************************
//
 
//
//*****************************************************************************
 
static inline void
EPWM_setDiodeEmulationMode(uint32_t base,EPWM_DiodeEmulationMode mode)
{
    uint32_t registerOffset;
 
    //
    // Get the register offset
    //
    registerOffset =  base + CSL_EPWM_DECTL;
 
    if(mode == EPWM_DIODE_EMULATION_CBC)
    {
        HW_WR_REG32(registerOffset,
        (HW_RD_REG32(registerOffset) & ~CSL_EPWM_DECTL_MODE_MASK));
    }
    else if(mode == EPWM_DIODE_EMULATION_OST)
    {
        HW_WR_REG32(registerOffset,
        (HW_RD_REG32(registerOffset) | CSL_EPWM_DECTL_MODE_MASK));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
 
static inline void
EPWM_setDiodeEmulationReentryDelay(uint32_t base,uint8_t delay)
{
    uint32_t registerOffset;
    //
    // Get the register offset
    //
    registerOffset =  base + CSL_EPWM_DECTL;
 
     HW_WR_REG32(registerOffset,
        ((HW_RD_REG32(registerOffset) & ~(CSL_EPWM_DECTL_REENTRYDLY_MASK))
        | (delay<<CSL_EPWM_DECTL_REENTRYDLY_SHIFT)) );
}
 
//*****************************************************************************
//
//*****************************************************************************
 
static inline void
EPWM_configureDiodeEmulationTripSources(uint32_t base, EPWM_DiodeEmulationTripSource source,
                                        uint32_t tripLorH)
{
    uint32_t registerOffset;
    //
    // Get the register offset
    //
    registerOffset =  base + CSL_EPWM_DECOMPSEL;
 
    if(tripLorH == EPWM_DE_TRIPL)
    {
        HW_WR_REG32(registerOffset,
            ((HW_RD_REG32(registerOffset) &
            ~CSL_EPWM_DECOMPSEL_TRIPL_MASK) |
            (source<<CSL_EPWM_DECOMPSEL_TRIPL_SHIFT)));
    }
    else if(tripLorH == EPWM_DE_TRIPH)
    {
        HW_WR_REG32(registerOffset,
            ((HW_RD_REG32(registerOffset) &
            ~CSL_EPWM_DECOMPSEL_TRIPH_MASK) |
            (source<<CSL_EPWM_DECOMPSEL_TRIPH_SHIFT)));
    }
 
}
 
//*****************************************************************************
//
//*****************************************************************************
 
static inline void
EPWM_selectDiodeEmulationPWMsignal(uint32_t base,uint32_t channel,
                                   EPWM_DiodeEmulationSignal signal)
{
    uint32_t registerOffset;
    //
    // Get the register offset
    //
    registerOffset =  base + CSL_EPWM_DEACTCTL;
 
    if(channel == EPWM_DE_CHANNEL_A)
    {
        HW_WR_REG32(registerOffset,
            ((HW_RD_REG32(registerOffset) &
            ~CSL_EPWM_DEACTCTL_PWMA_MASK) |
            (signal<<CSL_EPWM_DEACTCTL_PWMA_SHIFT)));
    }
    else
    {
        HW_WR_REG32(registerOffset,
            ((HW_RD_REG32(registerOffset) &
            ~CSL_EPWM_DEACTCTL_PWMB_MASK) |
            (signal<<CSL_EPWM_DEACTCTL_PWMB_SHIFT)));
    }
}
 
//*****************************************************************************
//
//*****************************************************************************
 
static inline void
EPWM_selectDiodeEmulationTripSignal(uint32_t base,uint32_t channel,
                                   uint32_t signal)
{
    uint32_t registerOffset;
    //
    // Get the register offset
    //
    registerOffset =  base + CSL_EPWM_DEACTCTL;
 
    if(channel == EPWM_DE_CHANNEL_A)
    {
        HW_WR_REG32(registerOffset,
            ((HW_RD_REG32(registerOffset) &
            ~CSL_EPWM_DEACTCTL_TRIPSELA_MASK) |
            (signal<<CSL_EPWM_DEACTCTL_TRIPSELA_SHIFT)));
    }
    else
    {
        HW_WR_REG32(registerOffset,
            ((HW_RD_REG32(registerOffset) &
            ~CSL_EPWM_DEACTCTL_TRIPSELB_MASK) |
            (signal<<CSL_EPWM_DEACTCTL_TRIPSELB_SHIFT)));
    }
}
 
//*****************************************************************************
//
//*****************************************************************************
 
static inline void
EPWM_nobypassDiodeEmulationLogic(uint32_t base)
{
    uint32_t registerOffset;
    //
    // Get the register offset
    //
    registerOffset =  base + CSL_EPWM_DEACTCTL;
 
    HW_WR_REG32(registerOffset,
        (HW_RD_REG32(registerOffset) &
        ~(CSL_EPWM_DEACTCTL_TRIPENABLE_MAX << CSL_EPWM_DEACTCTL_TRIPENABLE_SHIFT)));
 
}
 
//*****************************************************************************
//
//*****************************************************************************
 
static inline void
EPWM_bypassDiodeEmulationLogic(uint32_t base)
{
    uint32_t registerOffset;
    //
    // Get the register offset
    //
    registerOffset =  base + CSL_EPWM_DEACTCTL;
 
    HW_WR_REG32(registerOffset,
        (HW_RD_REG32(registerOffset) |
        (CSL_EPWM_DEACTCTL_TRIPENABLE_MAX << CSL_EPWM_DEACTCTL_TRIPENABLE_SHIFT)));
 
}
 
//*****************************************************************************
//
//*****************************************************************************
 
static inline void
EPWM_forceDiodeEmulationActive(uint32_t base)
{
    uint32_t registerOffset;
    //
    // Get the register offset
    //
    registerOffset =  base + CSL_EPWM_DEFRC;
 
     HW_WR_REG32(registerOffset,
        (HW_RD_REG32(registerOffset) | CSL_EPWM_DEFRC_DEACTIVE_MASK));
 
}
 
//*****************************************************************************
//
//*****************************************************************************
 
static inline void
EPWM_clearDiodeEmulationActive(uint32_t base)
{
    uint32_t registerOffset;
    //
    // Get the register offset
    //
    registerOffset =  base + CSL_EPWM_DECLR;
 
     HW_WR_REG32(registerOffset,
        (HW_RD_REG32(registerOffset) | CSL_EPWM_DECLR_DEACTIVE_MASK));
 
}
//*****************************************************************************
//
//*****************************************************************************
 
 
static inline void
EPWM_enableDiodeEmulationMonitorModeControl(uint32_t base)
{
   uint32_t registerOffset;
    //
    // Get the register offset
    //
    registerOffset =  base + CSL_EPWM_DEMONCTL;
 
    HW_WR_REG32(registerOffset,
        (HW_RD_REG32(registerOffset) |
        (CSL_EPWM_DEMONCTL_ENABLE_MAX << CSL_EPWM_DEMONCTL_ENABLE_SHIFT)));
}
 
//*****************************************************************************
//
//*****************************************************************************
 
static inline void
EPWM_disableDiodeEmulationMonitorModeControl(uint32_t base)
{
   uint32_t registerOffset;
    //
    // Get the register offset
    //
    registerOffset =  base + CSL_EPWM_DEMONCTL;
 
    HW_WR_REG32(registerOffset,
        (HW_RD_REG32(registerOffset) &
        ~(CSL_EPWM_DEMONCTL_ENABLE_MAX << CSL_EPWM_DEMONCTL_ENABLE_SHIFT)));
}
 
//*****************************************************************************
//
//*****************************************************************************
 
static inline void
EPWM_setDiodeEmulationMonitorModeStep(uint32_t base,uint32_t direction,
                                   uint8_t stepsize)
{
    uint32_t registerOffset;
    //
    // Get the register offset
    //
    registerOffset =  base + CSL_EPWM_DEMONSTEP;
 
    if(direction == EPWM_DE_COUNT_UP)
    {
        HW_WR_REG32(registerOffset,
        (HW_RD_REG32(registerOffset) & ~CSL_EPWM_DEMONSTEP_INCSTEP_MASK)
        | (stepsize<<CSL_EPWM_DEMONSTEP_INCSTEP_SHIFT));
    }
    else if(direction == EPWM_DE_COUNT_DOWN)
    {
        HW_WR_REG32(registerOffset,
            ((HW_RD_REG32(registerOffset) &
            ~CSL_EPWM_DEMONSTEP_DECSTEP_MASK) |
            (stepsize<<CSL_EPWM_DEMONSTEP_DECSTEP_SHIFT)));
    }
}
 
//*****************************************************************************
//
//*****************************************************************************
static inline void
EPWM_setDiodeEmulationMonitorCounterThreshold(uint32_t base,uint16_t threshold)
{
    uint32_t registerOffset;
    //
    // Get the register offset
    //
    registerOffset =  base + CSL_EPWM_DEMONTHRES;
 
     HW_WR_REG32(registerOffset,
        ((HW_RD_REG32(registerOffset) & ~(CSL_EPWM_DEMONTHRES_THRESHOLD_MASK))
        | (threshold<<CSL_EPWM_DEMONTHRES_THRESHOLD_SHIFT)) );
}
 
 
//*****************************************************************************
//
//
//*****************************************************************************
extern void
EPWM_setEmulationMode(uint32_t base, EPWM_EmulationMode emulationMode);
//*****************************************************************************
//
//
//*****************************************************************************
extern void
EPWM_configureSignal(uint32_t base, const EPWM_SignalParams *signalParams);
//*****************************************************************************
//
// Close the Doxygen group.
//
//*****************************************************************************
 
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
 
#endif // EPWM_V1_H_