diff --git a/source/sdl/.project/project_am243x.js b/source/sdl/.project/project_am243x.js
index a2e66fce72..86faabd948 100644
--- a/source/sdl/.project/project_am243x.js
+++ b/source/sdl/.project/project_am243x.js
@@ -79,6 +79,9 @@ const files_r5f = {
   		"sdl_interrupt_register.c",
   		"sdl_exception.c",
         "sdl_ecc_r5.c",
+        "sdl_r5f_utils.c",
+        "sdl_ip_rom_checksum.c",
+        "sdl_rom_checksum.c"
     ],
 };
 
@@ -122,6 +125,7 @@ const filedirs_r5f = {
         "pbist/v0/soc/am243x",
         "r5",
         "r5/v0",
+        "rom_checksum",
     ],
 };
 
diff --git a/source/sdl/.project/project_am263x.js b/source/sdl/.project/project_am263x.js
index e4fce2adf9..f6677dd81c 100644
--- a/source/sdl/.project/project_am263x.js
+++ b/source/sdl/.project/project_am263x.js
@@ -30,6 +30,7 @@ const files_r5f = {
         "sdl_ccm.c",
         "sdl_mcu_armss_ccmr5.c",
         "sdl_stc_soc.c",
+        "sdl_r5f_utils.c",
 
     ],
 };
diff --git a/source/sdl/.project/project_am273x.js b/source/sdl/.project/project_am273x.js
index 2c77c9a460..fc9fb0b581 100644
--- a/source/sdl/.project/project_am273x.js
+++ b/source/sdl/.project/project_am273x.js
@@ -5,7 +5,6 @@ let device = "am273x";
 const files_r5f = {
     common: [
         "sdl_dpl.c",
-        "sdl_dcc.c",
         "sdl_ip_esm.c",
         "sdl_esm.c",
         "sdl_esm_core.c",
@@ -53,7 +52,6 @@ const asmfiles_r5f = {
 const files_c66 = {
     common: [
         "sdl_dpl.c",
-        "sdl_dcc.c",
         "sdl_ip_esm.c",
         "sdl_esm.c",
         "sdl_esm_core.c",
@@ -73,7 +71,6 @@ const files_c66 = {
 const filedirs = {
     common: [
         "dpl",
-        "dcc/v1",
         "esm",
         "esm/v1",
         "esm/v1/v1_0",
diff --git a/source/sdl/dcc/v1/sdl_dcc.h b/source/sdl/dcc/v1/sdl_dcc.h
index a9ada12078..71a759657f 100644
--- a/source/sdl/dcc/v1/sdl_dcc.h
+++ b/source/sdl/dcc/v1/sdl_dcc.h
@@ -142,7 +142,7 @@ typedef uint32_t SDL_DCC_mode;
 
 #define SDL_DCC_MODE_SINGLE_SHOT     (DCC_DCCGCTRL_SINGLESHOT_MODE)
 /**< Stop counting when counter0 and valid0 both reach zero */
-//#define SDL_DCC_MODE_SINGLE_SHOT_2     (DCC_DCCGCTRL_SINGLESHOT_MODE2) //not applicable for am273x
+
 /**< Stop counting when counter1 reaches zero */
 #define SDL_DCC_MODE_CONTINUOUS        (DCC_DCCGCTRL_SINGLESHOT_DISABLE)
 /**< Continuously repeat (until error) */
diff --git a/source/sdl/dcc/v1/soc/am273x/sdl_soc_dcc.h b/source/sdl/dcc/v1/soc/am273x/sdl_soc_dcc.h
deleted file mode 100644
index 0daa7c1a5d..0000000000
--- a/source/sdl/dcc/v1/soc/am273x/sdl_soc_dcc.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- *   Copyright (c) Texas Instruments Incorporated 2022
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions
- *  are met:
- *
- *    Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *    Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the
- *    distribution.
- *
- *    Neither the name of Texas Instruments Incorporated nor the names of
- *    its contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-#ifndef SDL_SOC_DCC_H_
-#define SDL_SOC_DCC_H_
-
-#include <sdl/include/am273x/sdlr_soc_baseaddress.h>
-
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** ===========================================================================
- *
- * @ingroup  SDL_DCC_MODULE
- * @defgroup SDL_DCC_API SDL Dual Clock Comparator(DCC)
- *
- * ============================================================================
- */
-/**
-@defgroup SDL_DCC_ENUM DCC Enumerated Data Types
-@ingroup SDL_DCC_API
-*/
-
-/*======================================================================================================
-*   Required Macros for Instances config
-======================================================================================================*/
-
-#define SDL_DCC_MAX_INSTANCE    (6U)
-
-/** ===========================================================================
- *  @addtogroup SDL_DCC_ENUM
-    @{
- * ============================================================================
- */
-
-/*************************************************************************************************************
-*  Enum for different DCC module instances
-**************************************************************************************************************/
-
-typedef enum {
-
-   SDL_DCC_INST_MSS_DCCA,
-   /**< MSS DCCA Instance */
-   SDL_DCC_INST_MSS_DCCB,
-   /**< MSS DCCB Instance */
-   SDL_DCC_INST_MSS_DCCC,
-   /**< MSS DCCC Instance */
-   SDL_DCC_INST_MSS_DCCD,
-   /**< MSS DCCD Instance */
-
-   SDL_DCC_INST_DSS_DCCA,
-   /**< DSS DCCA Instance */
-   SDL_DCC_INST_DSS_DCCB,
-   /**< DSS DCCB Instance */
-
-   INVALID_INSTANCE,
-    /**< Invalid Instance */
-
-} SDL_DCC_Inst;
-
-/* @} */
-
-/*======================================================================================================
-*   This is global array gives the BASE ADDRESS of DCC modules
-======================================================================================================*/
-
-static uint32_t SDL_DCC_baseAddress[SDL_DCC_MAX_INSTANCE] = {SDL_MSS_DCCA_U_BASE, SDL_MSS_DCCB_U_BASE, SDL_MSS_DCCC_U_BASE, SDL_MSS_DCCD_U_BASE, SDL_DSS_DCCA_U_BASE,
-                                                                SDL_DSS_DCCB_U_BASE };
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SDL_SOC_DCC_H_ */
diff --git a/source/sdl/dcc/v1/soc/sdl_dcc_soc.h b/source/sdl/dcc/v1/soc/sdl_dcc_soc.h
index e786c32b4f..2b7e0d7459 100644
--- a/source/sdl/dcc/v1/soc/sdl_dcc_soc.h
+++ b/source/sdl/dcc/v1/soc/sdl_dcc_soc.h
@@ -38,9 +38,6 @@
 extern "C" {
 #endif
 
-#if defined (SOC_AM273X)
-#include <sdl/dcc/v1/soc/am273x/sdl_soc_dcc.h>
-#endif /* SOC_AM273X */
 #if defined (SOC_AWR294X)
 #include <sdl/dcc/v1/soc/awr294x/sdl_soc_dcc.h>
 #endif /* SOC_AWR294X */
@@ -49,11 +46,6 @@ extern "C" {
 #include <sdl/dcc/v1/soc/am263x/sdl_soc_dcc.h>
 #endif /* SOC_AM263X */
 
-#if defined (SOC_AM273X)
-#include <sdl/esm/soc/am273x/sdl_esm_soc.h>
-#include <sdl/include/am273x/sdlr_mss_ctrl.h>
-#endif /* SOC_AM273X */
-
 #if defined (SOC_AWR294X)
 #include <sdl/esm/soc/awr294x/sdl_esm_soc.h>
 #include <sdl/include/awr294x/sdlr_mss_ctrl.h>
diff --git a/source/sdl/dpl/sdl_dpl.c b/source/sdl/dpl/sdl_dpl.c
index cd36b2c7a0..6e95d7d07a 100644
--- a/source/sdl/dpl/sdl_dpl.c
+++ b/source/sdl/dpl/sdl_dpl.c
@@ -83,7 +83,9 @@ int32_t SDL_DPL_enableInterrupt(int32_t intNum)
     return ret;
 }
 
-
+/**
+ * Design: PROC_SDL-6203
+ */
 int32_t SDL_DPL_disableInterrupt(int32_t intNum)
 {
     SDL_ErrType_t ret = SDL_PASS;
@@ -102,7 +104,7 @@ int32_t SDL_DPL_disableInterrupt(int32_t intNum)
 }
 
 /**
- * Design: PROC_SDL-1145,PROC_SDL-1146,PROC_SDL-5802
+ * Design: PROC_SDL-5802
  */
 
 int32_t SDL_DPL_registerInterrupt(SDL_DPL_HwipParams *pParams, pSDL_DPL_HwipHandle *handle)
@@ -126,7 +128,9 @@ int32_t SDL_DPL_registerInterrupt(SDL_DPL_HwipParams *pParams, pSDL_DPL_HwipHand
     return ret;
 }
 
-
+/**
+ * Design: PROC_SDL-6206
+ */
 int32_t SDL_DPL_deregisterInterrupt(pSDL_DPL_HwipHandle handle)
 {
     SDL_ErrType_t ret = SDL_PASS;
@@ -178,7 +182,7 @@ void* SDL_DPL_addrTranslate(uint64_t addr, uint32_t size)
 }
 
 /**
- * Design: PROC_SDL-1143,PROC_SDL-1144
+ * Design: PROC_SDL-6205
  */
 int32_t SDL_DPL_globalDisableInterrupts(uintptr_t *key)
 {
@@ -202,7 +206,7 @@ int32_t SDL_DPL_globalDisableInterrupts(uintptr_t *key)
 }
 
 /**
- * Design: PROC_SDL-1141,PROC_SDL-1142
+ * Design: PROC_SDL-6204
  */
 int32_t SDL_DPL_globalRestoreInterrupts(uintptr_t key)
 {
diff --git a/source/sdl/ecc/V1/sdl_ip_ecc.h b/source/sdl/ecc/V1/sdl_ip_ecc.h
index e41fa03ec3..c940390f3e 100644
--- a/source/sdl/ecc/V1/sdl_ip_ecc.h
+++ b/source/sdl/ecc/V1/sdl_ip_ecc.h
@@ -87,32 +87,24 @@ extern "C" {
 @defgroup SDL_ECC_AGGR_ENUM ECC_AGGR Enumerated Data Types
 @ingroup SDL_ECC_AGGR_API
 */
-
 /**
- *  @addtogroup SDL_ECC_AGGR_ENUM
-    @{
- *
- */
-
+@defgroup SDL_ECC_AGGR_MACROS ECC_AGGR Macros
+@ingroup SDL_ECC_AGGR_API
+*/
 /**
- * @brief This enumerator defines the types of possible ECC errors
- *
+ *  @addtogroup SDL_ECC_AGGR_MACROS
+    @{
  *
  */
-
-/**
- * Design: PROC_SDL-1272
- */
-typedef uint32_t SDL_Ecc_AggrIntrSrc;
-    /** No interrupt */
+/** No interrupt */
 #define SDL_ECC_AGGR_INTR_SRC_NONE                      ((uint32_t) 0U)
-    /** Single-bit Error Correcting (SEC) */
+/** Single-bit Error Correcting (SEC) */
 #define SDL_ECC_AGGR_INTR_SRC_SINGLE_BIT                ((uint32_t) 1U)
-    /** Double-bit Error Detection (DED) */
+/** Double-bit Error Detection (DED) */
 #define SDL_ECC_AGGR_INTR_SRC_DOUBLE_BIT                ((uint32_t) 2U)
-    /** Two or more successive SEC errors */
+/** Two or more successive SEC errors */
 #define SDL_ECC_ADDR_ERROR_TYPE_SUCCESSIVE_SINGLE_BITS  ((uint32_t) 3U)
-    /** Denotes an invalid interrupt source */
+/** Denotes an invalid interrupt source */
 #define SDL_ECC_AGGR_INTR_SRC_INVALID                   ((uint32_t) 4U)
 
 /**
@@ -120,26 +112,27 @@ typedef uint32_t SDL_Ecc_AggrIntrSrc;
  *
  *
  */
+/** Error controller instance 1 */
 #define SDL_ECC_AGGR_SELECT_ERR_CTRL1                   (0U)
-    /** Error controller instance 1 */
+/** Error Controller instance 2 */    
 #define SDL_ECC_AGGR_SELECT_ERR_CTRL2                   (1U)
-    /** Error Controller instance 2 */
+/** Maximum number of RAM Error Controller registers */    
 #define SDL_ECC_AGGR_MAX_NUM_RAM_ERR_CTRL               (2U)
-    /** Maximum number of RAM Error Controller registers */
-
+    
 /**
  * @brief This defines the types of possible ECC error status instances
  *
  *
  */
+/** Error Status instance 1 */
 #define SDL_ECC_AGGR_SELECT_ERR_STAT1                   (0U)
-    /** Error Status instance 1 */
+/** Error Status instance 2 */
 #define SDL_ECC_AGGR_SELECT_ERR_STAT2                   (1U)
-    /** Error Status instance 2 */
+/** Error Status instance 3 */
 #define SDL_ECC_AGGR_SELECT_ERR_STAT3                   (2U)
-    /** Error Status instance 3 */
+/** Maximum number of RAM Error Status registers */    
 #define SDL_ECC_AGGR_MAX_NUM_RAM_ERR_STAT               (3U)
-    /** Maximum number of RAM Error Status registers */
+    
 
 /**
  * @brief This defines the number of enable registers
@@ -147,36 +140,46 @@ typedef uint32_t SDL_Ecc_AggrIntrSrc;
  *
  */
 #define SDL_ECC_AGGR_NUM_ENABLE_REGISTERS               (8U)
+/** Valid Timeout Error parameter */
+#define SDL_ECC_AGGR_VALID_TIMEOUT_ERR                  (1U)
+/** Valid Timeout Error parameter */
+#define SDL_ECC_AGGR_VALID_PARITY_ERR                   (2U)
 
+/** Zero inject pattern */
+#define SDL_ECC_AGGR_INJECT_PATTERN_ZERO                ((uint32_t) 0U)
+/** Inject pattern 0xF */
+#define SDL_ECC_AGGR_INJECT_PATTERN_F                   ((uint32_t) 1U)
+/** Inject pattern 0xA */
+#define SDL_ECC_AGGR_INJECT_PATTERN_A                   ((uint32_t) 2U)
+/** Inject pattern 0x5 */
+#define SDL_ECC_AGGR_INJECT_PATTERN_5                   ((uint32_t) 3U)
+/* Max Inject pattern */
+#define SDL_ECC_EGGR_INJECT_PATTERN_MAX                 (SDL_ECC_AGGR_INJECT_PATTERN_A)
+
+/** Normal errors */
+#define SDL_ECC_AGGR_ERROR_SUBTYPE_NORMAL               ((uint32_t) 0U)
+/** Inject errors */
+#define SDL_ECC_AGGR_ERROR_SUBTYPE_INJECT               ((uint32_t) 1U)
+
+/** @} */
 
 /**
- * @brief This defines the valid ecc aggr error configuration
- *
+ *  @addtogroup SDL_ECC_AGGR_ENUM
+    @{
  *
  */
-typedef uint8_t     SDL_ecc_aggrValid;
-#define SDL_ECC_AGGR_VALID_TIMEOUT_ERR                  (1U)
-    /** Valid Timeout Error parameter */
-#define SDL_ECC_AGGR_VALID_PARITY_ERR                   (2U)
-    /** Valid Timeout Error parameter */
 
 /**
- * @brief This enumerator defines the types of ECC patterns
+ * @brief This enumerator defines the types of possible ECC errors
  *
- * Design: PROC_SDL-1273
  *
  */
-typedef uint32_t SDL_Ecc_injectPattern;
-    /** Zero inject pattern */
-#define SDL_ECC_AGGR_INJECT_PATTERN_ZERO                 ((uint32_t) 0U)
-    /** Inject pattern 0xF */
-#define SDL_ECC_AGGR_INJECT_PATTERN_F                    ((uint32_t) 1U)
-    /** Inject pattern 0xA */
-#define SDL_ECC_AGGR_INJECT_PATTERN_A                    ((uint32_t) 2U)
-    /** Inject pattern 0x5 */
-#define SDL_ECC_AGGR_INJECT_PATTERN_5                    ((uint32_t) 3U)
-   /* Max Inject pattern */
-#define SDL_ECC_EGGR_INJECT_PATTERN_MAX                  (SDL_ECC_AGGR_INJECT_PATTERN_A)
+
+/**
+ * Design: PROC_SDL-1272
+ */
+typedef uint32_t SDL_Ecc_AggrIntrSrc;
+
 
 /**
  * @brief This enumerator defines the types of possible EDC errors
@@ -185,11 +188,22 @@ typedef uint32_t SDL_Ecc_injectPattern;
  *
  */
 typedef uint32_t SDL_Ecc_AggrEDCErrorSubType;
-    /** Normal errors */
-#define SDL_ECC_AGGR_ERROR_SUBTYPE_NORMAL                  ((uint32_t) 0U)
-    /** Inject errors */
-#define SDL_ECC_AGGR_ERROR_SUBTYPE_INJECT                  ((uint32_t) 1U)
 
+
+/**
+ * @brief This defines the valid ecc aggr error configuration
+ *
+ *
+ */
+typedef uint8_t  SDL_ecc_aggrValid;
+
+/**
+ * @brief This enumerator defines the types of ECC patterns
+ *
+ * Design: PROC_SDL-1273
+ *
+ */
+typedef uint32_t SDL_Ecc_injectPattern;
 /** @} */
 
 /**
diff --git a/source/sdl/ecc/soc/am273x/sdl_ecc.c b/source/sdl/ecc/soc/am273x/sdl_ecc.c
index 343874977c..45ec030639 100644
--- a/source/sdl/ecc/soc/am273x/sdl_ecc.c
+++ b/source/sdl/ecc/soc/am273x/sdl_ecc.c
@@ -48,19 +48,59 @@
 #include <sdl/ecc/sdl_ecc_priv.h>
 #include <sdl/dpl/sdl_dpl.h>
 
+/* ========================================================================== */
+/*                           Macros                                            */
+/* ========================================================================== */
 /* Local defines */
-#define SDL_ECC_INVALID_ERROR_SOURCE      (0xffffffffu)
-#define SDL_ECC_BITS_PER_WORD             (32U)
-#define ECC_AGGR_LINE_SIZE                (4U)
-#define SDL_ECC_INVALID_SELF_TEST_RAM_ID  (0xffffffffu)
-#define SDL_ECC_INVALID_CHECKER_TYPE      (0xffffffffu)
-#define SDL_ESM_MAX_MSS_PARAM_MAP_WORDS   (10U)
-#define SDL_ESM_MAX_DSS_PARAM_MAP_WORDS   (2U)
-
-#define SDL_INTR_GROUP_NUM                (1U)
-#define SDL_INTR_PRIORITY_LVL             (1U)
-#define SDL_ENABLE_ERR_PIN                (1U)
-
+#define SDL_ECC_INVALID_ERROR_SOURCE            (0xffffffffu)
+#define SDL_ECC_BITS_PER_WORD                   (32U)
+#define ECC_AGGR_LINE_SIZE                      (4U)
+#define SDL_ECC_INVALID_SELF_TEST_RAM_ID        (0xffffffffu)
+#define SDL_ECC_INVALID_CHECKER_TYPE            (0xffffffffu)
+#define SDL_ESM_MAX_MSS_PARAM_MAP_WORDS         (10U)
+#define SDL_ESM_MAX_DSS_PARAM_MAP_WORDS         (2U)
+
+#define SDL_INTR_GROUP_NUM                      (1U)
+#define SDL_INTR_PRIORITY_LVL                   (1U)
+#define SDL_ENABLE_ERR_PIN                      (1U)
+
+#define SDL_DSS_DSP_L2RAM_PARITY_MEMINIT_START  (0x0602008Cu)
+#define SDL_DSS_DSP_L2RAM_PARITY_MEMINIT_DONE   (0x06020094u)
+#define SDL_ECC_DSS_L2RAM_PARITY_MEM_INIT       (0xffu)
+
+#define SDL_DSS_DSP_L2RAM_PARITY_CTRL           (0x0602006Cu)
+#define SDL_ECC_DSS_L2RAM_PARITY_ENABLE         (0xffu)
+#define SDL_ECC_DSS_L2RAM_PARITY_ERROR_CLEAR    (0xff00u)
+
+#define SDL_DSP_ICFG_EDCINTMASK                 (0x01831100u) /*Error Detect and Correct Interrupt Mask Register*/
+#define SDL_DSP_ICFG_EDCINTFLG                  (0x01831104u) /*Error Detect and Correct Interrupt Flag Register*/
+
+/*DSS DSP L2 command Registers*/
+#define SDL_L1PEDCMD_EN                         (0x00000000U)
+#define SDL_L1PEDCMD_SUSP                       (0x00000003U)
+
+/*DSS DSP ICFG EDC Registers*/
+#define SDL_DSP_ICFG_L1PEDSTAT                  (0x01846404U) /*L1 Error Detection Status Register*/
+#define SDL_DSP_ICFG_L1PEDCMD                   (0x01846408U) /*L1 Error Detection Command Register*/
+
+/*DSS DSP L2 command Registers*/
+#define SDL_L2EDCMD_EN                          (0x00000000U)
+#define SDL_L2EDCMD_SUSP                        (0x00000003U)
+
+/*DSS DSP ICFG EDC Registers*/
+#define SDL_DSP_ICFG_L2EDSTAT                   (0x01846004U) /*L2 Error Detection Status Register*/
+#define SDL_DSP_ICFG_L2EDCMD                    (0x01846008U) /*L2 Error Detection Command Register*/
+
+#define SDL_DSP_ICFG_IDMA1_SOURCE               (0x01820108U) /*IDMA Channel 1 Source Address*/
+#define SDL_DSP_ICFG_IDMA1_DEST                 (0x0182010cU) /*IDMA Channel 1 Destination Address*/
+#define SDL_DSP_ICFG_IDMA1_COUNT                (0x01820110U) /*IDMA Channel 1 Count*/
+
+#define SDL_DSP_ICFG__IDMA1_COUNT__PRI__POS     (29U)
+#define SDL_DSP_ICFG__IDMA1_COUNT__INT__POS     (28U)
+#define SDL_DSP_ICFG_COUNT_VAL                  (((7U << SDL_DSP_ICFG__IDMA1_COUNT__PRI__POS) | (1U << SDL_DSP_ICFG__IDMA1_COUNT__INT__POS) | 0x100U))
+
+#define SDL_DSP_ICFG_STAT_EN                    (1U)
+#define SDL_DSP_ICFG_STAT_SUSP                  (8U)
 /* ========================================================================== */
 /*                           enums                                            */
 /* ========================================================================== */
@@ -137,6 +177,9 @@ static int32_t SDL_ECC_enableParityerr(SDL_ECC_MemType eccMemType,
 									 uint32_t setmask,
 									 uint32_t paramregs,
 									 uint32_t paramval);
+
+static int32_t SDL_ECC_dss_l2_parity_memInit(void);
+
 /* Event BitMap for ECC ESM callback for MSS */
 SDL_ESM_NotifyParams paramsMSS[SDL_ESM_MAX_MSS_PARAM_MAP_WORDS] =
 {
@@ -1704,3 +1747,254 @@ static int32_t SDL_ECC_enableParityerr(SDL_ECC_MemType eccMemType,
 	return ((int32_t)result);
 
 }
+
+/***********************************************************************
+ *
+ * \brief   DSS L2 parity memory init
+ *
+ * \param1  void
+ * @return  SDL_PASS or SDL_EFAIL
+ **********************************************************************/
+static int32_t SDL_ECC_dss_l2_parity_memInit(void)
+{
+	int32_t retVal = SDL_PASS;
+	uint32_t maxTimeOutMilliSeconds = 1000000000u;
+    uint32_t timeOutCnt = 0u;
+    /* Initialization of DSS L2 memory*/
+    SDL_REG32_WR(SDL_DSS_DSP_L2RAM_PARITY_MEMINIT_START, SDL_ECC_DSS_L2RAM_PARITY_MEM_INIT);
+
+    /*Poll till memory initialization*/
+    while(SDL_REG32_RD(SDL_DSS_DSP_L2RAM_PARITY_MEMINIT_DONE)!=SDL_ECC_DSS_L2RAM_PARITY_MEM_INIT)
+    {
+        if (timeOutCnt > maxTimeOutMilliSeconds)
+        {
+            retVal = SDL_EFAIL;
+            break;
+        }
+        timeOutCnt++;
+    }
+
+	/* Clear Done memory after MEM init*/
+	SDL_REG32_WR(SDL_DSS_DSP_L2RAM_PARITY_MEMINIT_DONE, SDL_ECC_DSS_L2RAM_PARITY_MEM_INIT);
+	
+	return retVal;
+	
+}/*End of SDL_ECC_dss_l2_parity_memInit()*/
+
+/***********************************************************************
+ *
+ * \brief   DSS L2 parity init
+ *
+ * \param1  void
+ * @return  void
+ **********************************************************************/
+void SDL_ECC_dss_l2_parity_init(void)
+{
+	int32_t retVal = SDL_PASS;
+    /*DSS L2 parity memory init*/
+    retVal = SDL_ECC_dss_l2_parity_memInit();
+
+	if(retVal == SDL_PASS)
+	{
+		/*
+		 * Write 0xFF to DSS_CTRL. DSS_DSP_L2RAM_PARITY_CTRL.DSS_DSP_L2RAM_PARITY_CTRL_ENABLE
+		 * register field to enable parity. Each bit corresponds to an L2 Bank
+		 */
+		SDL_REG32_WR(SDL_DSS_DSP_L2RAM_PARITY_CTRL, SDL_ECC_DSS_L2RAM_PARITY_ENABLE);
+	}
+
+}/*End of SDL_ECC_dss_l2_parity_init()*/
+
+/***********************************************************************
+ *
+ * \brief   DSS L2 parity error inject
+ *
+ * \param1  injectError : single bit inject for parity error
+ * \param2  injectErrAdd: Inject memory address
+ * \param3  value	    : Initial value before injecting
+ * @return  void
+ **********************************************************************/
+void SDL_ECC_dss_l2_parity_errorInject(uint32_t injectError, uint32_t injectErrAdd, uint32_t value)
+{
+    /*Write to a memory location "injectErrAdd" when the parity is enabled*/
+    SDL_REG32_WR(injectErrAdd, value);
+
+    /*
+     *Disable the parity by clearing DSS_CTRL.DSS_DSP_L2RAM_PARITY_CTRL.DSS_DSP_L2RAM_PARITY_CTRL_ENABLE
+     *Disable register field
+     */
+    SDL_REG32_WR(SDL_DSS_DSP_L2RAM_PARITY_CTRL, SDL_ECC_DSS_L2RAM_PARITY_ERROR_CLEAR);
+
+    /*Toggle a single bit in DSS L2 memory*/
+    SDL_REG32_WR(injectErrAdd, injectError);
+
+    /*Read injected error address memory*/
+    SDL_REG32_RD(injectErrAdd);
+
+    /*
+     * Enable the parity
+     */
+    SDL_REG32_WR(SDL_DSS_DSP_L2RAM_PARITY_CTRL, SDL_ECC_DSS_L2RAM_PARITY_ENABLE);
+
+    /*Read injected error address memory*/
+    SDL_REG32_RD(injectErrAdd);
+
+}/*End of SDL_ECC_dss_l2_parity_errorInject()*/
+
+/***********************************************************************
+ *
+ * \brief   The single-bit error correction and double-bit error
+ *          detection errors from the memories of L1 and L2 using EDC
+ *          Mask and FLG registers
+ *
+ * \param1  exception_mask_flag : Register value used to enable
+ *                                propagation of particular exceptions
+ * @return  void
+ **********************************************************************/
+void SDL_ECC_DSP_Aggregated_EDC_Errors(uint32_t exception_mask_flag)
+{
+    /*Write to DSP_ICFG__EDCINTMASK REGISTER TO ENABLE PROPOGATION OF
+     *particular EXCEPTION
+     */
+    SDL_REG32_WR(SDL_DSP_ICFG_EDCINTMASK, exception_mask_flag);
+
+    /*Write to DSP_ICFG__EDCINTFLG REGISTER TO PROPOGATE AN particular
+     * EXCEPTION
+     */
+    SDL_REG32_WR(SDL_DSP_ICFG_EDCINTFLG, exception_mask_flag);
+
+}/*End of SDL_ECC_DSP_Aggregated_EDC_Errors()*/
+
+/***********************************************************************
+ *
+ * \brief   EDC Command Enable for L1P memory
+ *
+ * \param1  void
+ * @return  SDL_PASS or SDL_EFAIL
+ **********************************************************************/
+int32_t SDL_ECC_dss_l1p_edc_CMD_EN(void)
+{
+    int32_t retVal = SDL_PASS;
+    uint32_t maxTimeOutMilliSeconds = 1000000000u;
+    uint32_t timeOutCnt = 0u;
+    /*Enable the Error Detect logic by writing a 0x1 to DSP_ICFG.L1PEDCMD.EN bit*/
+    SDL_REG32_WR(SDL_DSP_ICFG_L1PEDCMD, (0x1u << SDL_L1PEDCMD_EN));
+
+    /*Poll till the bit DSP_ICFG.L1PEDSTAT.EN is set to 0x1*/
+    while((SDL_REG32_RD(SDL_DSP_ICFG_L1PEDSTAT) & SDL_DSP_ICFG_STAT_EN) !=SDL_DSP_ICFG_STAT_EN)
+    {
+        if (timeOutCnt > maxTimeOutMilliSeconds)
+        {
+            retVal = SDL_EFAIL;
+            break;
+        }
+        timeOutCnt++;
+    }
+    return retVal;
+}/* End of SDL_ECC_dss_l1p_edc_CMD_EN() */
+
+/***********************************************************************
+ *
+ * \brief   EDC Command Suspend for L1P memory
+ *
+ * \param1  void
+ * @return  SDL_PASS or SDL_EFAIL
+ **********************************************************************/
+int32_t SDL_ECC_dss_l1p_CMD_SUSP(void)
+{
+    int32_t retVal = SDL_PASS;
+    uint32_t maxTimeOutMilliSeconds = 1000000000u;
+    uint32_t timeOutCnt = 0u;
+    /*Suspend the Error Detect logic by writing a 0x1 to DSP_ICFG.L1PEDCMD.SUSP bit*/
+    SDL_REG32_WR(SDL_DSP_ICFG_L1PEDCMD, (0x1u << SDL_L1PEDCMD_SUSP));
+
+    /*Poll till the bit DSP_ICFG.L1PEDSTAT.SUSP is set to 0x1*/
+    while((SDL_REG32_RD(SDL_DSP_ICFG_L1PEDSTAT) & SDL_DSP_ICFG_STAT_SUSP) !=SDL_DSP_ICFG_STAT_SUSP)
+    {
+        if (timeOutCnt > maxTimeOutMilliSeconds)
+        {
+            retVal = SDL_EFAIL;
+            break;
+        }
+        timeOutCnt++;
+    }
+    return retVal;
+}/*End of SDL_ECC_dss_l1p_CMD_SUSP()*/
+
+/***********************************************************************
+ *
+ * \brief   EDC Command Enable for L2 memory
+ *
+ * \param1  void
+ * @return  SDL_PASS or SDL_EFAIL
+ **********************************************************************/
+int32_t SDL_ECC_dss_l2_edc_CMD_EN(void)
+{
+    int32_t retVal = SDL_PASS;
+    uint32_t maxTimeOutMilliSeconds = 1000000000u;
+    uint32_t timeOutCnt = 0u;
+    /*Enable the Error Detect logic by writing a 0x1 to DSP_ICFG.L2EDCMD.EN bit*/
+    SDL_REG32_WR(SDL_DSP_ICFG_L2EDCMD, (0x1u << SDL_L2EDCMD_EN));
+
+    /*Poll till the bit DSP_ICFG.L2EDSTAT.EN is set to 0x1*/
+    while((SDL_REG32_RD(SDL_DSP_ICFG_L2EDSTAT) & SDL_DSP_ICFG_STAT_EN)!=SDL_DSP_ICFG_STAT_EN)
+    {
+        if (timeOutCnt > maxTimeOutMilliSeconds)
+        {
+            retVal = SDL_EFAIL;
+            break;
+        }
+        timeOutCnt++;
+    }
+    return retVal;
+}/* End of SDL_ECC_dss_l2_edc_CMD_EN() */
+
+/***********************************************************************
+ *
+ * \brief   EDC Command Suspend for L2 memory
+ *
+ * \param1  void
+ * @return  SDL_PASS or SDL_EFAIL
+ **********************************************************************/
+int32_t SDL_ECC_dss_l2_CMD_SUSP(void)
+{
+    int32_t retVal = SDL_PASS;
+    uint32_t maxTimeOutMilliSeconds = 1000000000u;
+    uint32_t timeOutCnt = 0u;
+    /*Suspend the Error Detect logic by writing a 0x1 to DSP_ICFG.L2EDCMD.SUSP bit*/
+    SDL_REG32_WR(SDL_DSP_ICFG_L2EDCMD, (0x1u << SDL_L2EDCMD_SUSP));
+
+    /*Poll till the bit DSP_ICFG.L2EDSTAT.SUSP is set to 0x1*/
+    while((SDL_REG32_RD(SDL_DSP_ICFG_L2EDSTAT) & (SDL_DSP_ICFG_STAT_SUSP))!=SDL_DSP_ICFG_STAT_SUSP)
+    {
+        if (timeOutCnt > maxTimeOutMilliSeconds)
+        {
+            retVal = SDL_EFAIL;
+            break;
+        }
+        timeOutCnt++;
+    }
+    return retVal;
+}/*End of SDL_ECC_dss_l2_CMD_SUSP()*/
+
+/***********************************************************************
+ *
+ * \brief   IDMA 1 Transfer function
+ *
+ * \param1  srcAddr : Source address of the IDMA 1 transfer
+ * \param2  destAddr: Destination address of the IDMA 1 transfer
+ *
+ * @return  void
+ **********************************************************************/
+void SDL_ECC_IDMA1_transfer(uint32_t srcAddr, uint32_t destAddr)
+{
+
+    /* Configure the IDMA1 Source address */
+    SDL_REG32_WR(SDL_DSP_ICFG_IDMA1_SOURCE, srcAddr);
+
+    /* Configure the IDMA1 Destination address */
+    SDL_REG32_WR(SDL_DSP_ICFG_IDMA1_DEST, destAddr);
+
+    /* Configure the IDMA1 Count value */
+    SDL_REG32_WR(SDL_DSP_ICFG_IDMA1_COUNT, SDL_DSP_ICFG_COUNT_VAL);
+}
diff --git a/source/sdl/ecc/soc/am273x/sdl_ecc_soc.h b/source/sdl/ecc/soc/am273x/sdl_ecc_soc.h
index b7ef4988a1..4b5c60357d 100644
--- a/source/sdl/ecc/soc/am273x/sdl_ecc_soc.h
+++ b/source/sdl/ecc/soc/am273x/sdl_ecc_soc.h
@@ -77,7 +77,6 @@
 #define SDL_R5FSS0_CORE0_TPCCA_PARITY_STATUS		(0x060200C8U)
 #define SDL_R5FSS0_CORE0_TPCCB_PARITY_STATUS		(0x060200CCU)
 #define SDL_R5FSS0_CORE0_TPCCC_PARITY_STATUS		(0x060200D0U)
-
 /** ----------------------------------------------------------------------------------
  * This structure holds the memory config for each memory subtype SDL_R5FSS0_CORE0_ECC_AGGR
  * -----------------------------------------------------------------------------------
diff --git a/source/sdl/ecc/soc/am64x_am243x/sdl_ecc_soc.h b/source/sdl/ecc/soc/am64x_am243x/sdl_ecc_soc.h
index 525f446b92..af924ed6f9 100644
--- a/source/sdl/ecc/soc/am64x_am243x/sdl_ecc_soc.h
+++ b/source/sdl/ecc/soc/am64x_am243x/sdl_ecc_soc.h
@@ -3978,16 +3978,16 @@ static const SDL_RAMIdEntry_t SDL_ECC_AGGR1_RamIdTable[SDL_ECC_AGGR1_NUM_RAMS] =
       SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ECC_TYPE,
       SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS,
       SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries },
-    { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_RAM_ID,
-      SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
-      SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
-      SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
-      SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries },
     { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
       SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
       SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
       SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
       SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries },
+    { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_RAM_ID,
+      SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
+      SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
+      SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
+      SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries },
     { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_RAM_ID,
       SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_INJECT_TYPE,
       SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ECC_TYPE,
diff --git a/source/sdl/ecc_bus_safety/v0/soc/am263x/sdl_ecc_bus_safety.c b/source/sdl/ecc_bus_safety/v0/soc/am263x/sdl_ecc_bus_safety.c
index 04f63a1e7d..9e40beaf51 100644
--- a/source/sdl/ecc_bus_safety/v0/soc/am263x/sdl_ecc_bus_safety.c
+++ b/source/sdl/ecc_bus_safety/v0/soc/am263x/sdl_ecc_bus_safety.c
@@ -209,7 +209,7 @@ int32_t SDL_ECC_BUS_SAFETY_MSS_dedErrorClear(uint32_t busSftyNode)
 *   API to get DED error status
 *********************************************************************************************************/
 /**
- *  Design: PROC_SDL-3716
+ *  Design: PROC_SDL-6287
  */
 int32_t SDL_ECC_BUS_SAFETY_MSS_getDedErrorStatus(uint32_t busSftyNode , uint32_t *status)
 {
@@ -270,7 +270,7 @@ int32_t SDL_ECC_BUS_SAFETY_MSS_redErrorClear(uint32_t busSftyNode)
 *   API to clear RED error
 *********************************************************************************************************/
 /**
- *  Design: PROC_SDL-3720
+ *  Design: PROC_SDL-6288
  */
 int32_t SDL_ECC_BUS_SAFETY_MSS_getRedErrorStatus(uint32_t busSftyNode , uint32_t *status)
 {
diff --git a/source/sdl/ecc_bus_safety/v0/soc/am273x/sdl_ecc_bus_safety.c b/source/sdl/ecc_bus_safety/v0/soc/am273x/sdl_ecc_bus_safety.c
index 744bab0c8f..932de7a2fe 100644
--- a/source/sdl/ecc_bus_safety/v0/soc/am273x/sdl_ecc_bus_safety.c
+++ b/source/sdl/ecc_bus_safety/v0/soc/am273x/sdl_ecc_bus_safety.c
@@ -245,7 +245,7 @@ int32_t SDL_ECC_BUS_SAFETY_DSS_dedErrorClear(uint32_t busSftyNode)
 *   API to get DED error status on DSS Node
 *********************************************************************************************************/
 /**
- *  Design: PROC_SDL-3716
+ *  Design: PROC_SDL-6287
  */
 int32_t SDL_ECC_BUS_SAFETY_DSS_getDedErrorStatus(uint32_t busSftyNode , uint32_t *status)
 {
@@ -306,7 +306,7 @@ int32_t SDL_ECC_BUS_SAFETY_DSS_redErrorClear(uint32_t busSftyNode)
 *   API to get RED error status on DSS Node
 *********************************************************************************************************/
 /**
- *  Design: PROC_SDL-3720
+ *  Design: PROC_SDL-6288
  */
 int32_t SDL_ECC_BUS_SAFETY_DSS_getRedErrorStatus(uint32_t busSftyNode , uint32_t *status)
 {
@@ -1254,7 +1254,7 @@ int32_t SDL_ECC_BUS_SAFETY_MSS_dedErrorClear(uint32_t busSftyNode)
 *   API to get DED error status on MSS Node
 *********************************************************************************************************/
 /**
- *  Design: PROC_SDL-3716
+ *  Design: PROC_SDL-6287
  */
 int32_t SDL_ECC_BUS_SAFETY_MSS_getDedErrorStatus(uint32_t busSftyNode , uint32_t *status)
 {
@@ -1315,7 +1315,7 @@ int32_t SDL_ECC_BUS_SAFETY_MSS_redErrorClear(uint32_t busSftyNode)
 *   API to clear RED error on MSS Node
 *********************************************************************************************************/
 /**
- *  Design: PROC_SDL-3720
+ *  Design: PROC_SDL-6288
  */
 int32_t SDL_ECC_BUS_SAFETY_MSS_getRedErrorStatus(uint32_t busSftyNode , uint32_t *status)
 {
diff --git a/source/sdl/ecc_bus_safety/v0/soc/awr294x/sdl_ecc_bus_safety.c b/source/sdl/ecc_bus_safety/v0/soc/awr294x/sdl_ecc_bus_safety.c
index 23582ac788..f53c27b449 100644
--- a/source/sdl/ecc_bus_safety/v0/soc/awr294x/sdl_ecc_bus_safety.c
+++ b/source/sdl/ecc_bus_safety/v0/soc/awr294x/sdl_ecc_bus_safety.c
@@ -244,7 +244,7 @@ int32_t SDL_ECC_BUS_SAFETY_DSS_dedErrorClear(uint32_t busSftyNode)
 *   API to get DED error status on DSS Node
 *********************************************************************************************************/
 /**
- *  Design: PROC_SDL-3716
+ *  Design: PROC_SDL-6287
  */
 int32_t SDL_ECC_BUS_SAFETY_DSS_getDedErrorStatus(uint32_t busSftyNode , uint32_t *status)
 {
@@ -305,7 +305,7 @@ int32_t SDL_ECC_BUS_SAFETY_DSS_redErrorClear(uint32_t busSftyNode)
 *   API to get RED error status on DSS Node
 *********************************************************************************************************/
 /**
- *  Design: PROC_SDL-3720
+ *  Design: PROC_SDL-6288
  */
 int32_t SDL_ECC_BUS_SAFETY_DSS_getRedErrorStatus(uint32_t busSftyNode , uint32_t *status)
 {
@@ -1259,7 +1259,7 @@ int32_t SDL_ECC_BUS_SAFETY_MSS_dedErrorClear(uint32_t busSftyNode)
 *   API to get DED error status on MSS Node
 *********************************************************************************************************/
 /**
- *  Design: PROC_SDL-3716
+ *  Design: PROC_SDL-6287
  */
 int32_t SDL_ECC_BUS_SAFETY_MSS_getDedErrorStatus(uint32_t busSftyNode , uint32_t *status)
 {
@@ -1317,10 +1317,10 @@ int32_t SDL_ECC_BUS_SAFETY_MSS_redErrorClear(uint32_t busSftyNode)
 }
 
 /********************************************************************************************************
-*   API to clear RED error on MSS Node
+*   API to get RED error on MSS Node
 *********************************************************************************************************/
 /**
- *  Design: PROC_SDL-3720
+ *  Design: PROC_SDL-6288
  */
 int32_t SDL_ECC_BUS_SAFETY_MSS_getRedErrorStatus(uint32_t busSftyNode , uint32_t *status)
 {
diff --git a/source/sdl/esm/soc/am64x/sdl_esm_core.c b/source/sdl/esm/soc/am64x/sdl_esm_core.c
index 9b536b88e2..0e8b347b92 100644
--- a/source/sdl/esm/soc/am64x/sdl_esm_core.c
+++ b/source/sdl/esm/soc/am64x/sdl_esm_core.c
@@ -85,10 +85,8 @@ bool SDL_ESM_getBaseAddr(const SDL_ESM_Inst esmInstType, uint32_t *esmBaseAddr)
             default:
                 break;
         }
+	    *esmBaseAddr = (uint32_t)SDL_DPL_addrTranslate(*esmBaseAddr, size);
     }
-
-    *esmBaseAddr = (uint32_t)SDL_DPL_addrTranslate(*esmBaseAddr, size);
-
     return (instValid);
 }
 
diff --git a/source/sdl/esm/v1/sdl_esm.c b/source/sdl/esm/v1/sdl_esm.c
index 9418f1d72e..3fa9373f8b 100644
--- a/source/sdl/esm/v1/sdl_esm.c
+++ b/source/sdl/esm/v1/sdl_esm.c
@@ -147,6 +147,10 @@ static int32_t SDL_ESM_configErrorGating(SDL_ESM_Handle gHandle, uint8_t groupNu
     return retVal;
 }
 
+/*
+ * Design: PROC_SDL-1047
+ */
+
 static void SDL_ESM_highpriority_interrupt(void *args)
 {
     uint32_t            esmioffhr, vec;
@@ -166,6 +170,10 @@ static void SDL_ESM_highpriority_interrupt(void *args)
 
 }
 
+/*
+ * Design: PROC_SDL-1047
+ */
+
 static void SDL_ESM_lowpriority_interrupt(void *args)
 {
     uint32_t            esmioffhr, vec;
@@ -233,13 +241,6 @@ static void SDL_ESM_processInterrupt (void *arg, uint32_t vec, int32_t* groupNum
         *groupNum = GROUP_ONE;
         *vecNum = vec;
     }
-    else if (vec < 128u)
-    {
-        while((bool)1u)
-		{
-			/* Reserved */
-		};
-    }
     else if (vec < 160u)
     {
         /* group 1 64-95 errors */
@@ -248,13 +249,6 @@ static void SDL_ESM_processInterrupt (void *arg, uint32_t vec, int32_t* groupNum
         *groupNum = GROUP_ONE;
         *vecNum = vec;
     }
-    else if (vec < 192u)
-    {
-        while((bool)1u)
-		{
-			/* Reserved */
-		};
-    }
     else if (vec < 224u)
     {
         /* group 1 96-127 errors */
@@ -265,10 +259,7 @@ static void SDL_ESM_processInterrupt (void *arg, uint32_t vec, int32_t* groupNum
     }
     else
     {
-        while((bool)1u)
-		{
-			/* Reserved */
-		};
+        /*Required for MISRA C*/
     }
 
     if (*groupNum != -1)
@@ -322,27 +313,30 @@ static void SDL_ESM_processInterrupt (void *arg, uint32_t vec, int32_t* groupNum
 						/*Nothing*/
 				   }
 				}
-			}	
+			}
         }
     }
 }
 
-static void SDL_ESM_memcpy(void *dest, void *src, size_t n) 
+static void SDL_ESM_memcpy(void *dest, void *src, size_t n)
 {
-    uint8_t *csrc = (uint8_t *)src; 
-    uint8_t *cdest = (uint8_t *)dest; 
+    uint8_t *csrc = (uint8_t *)src;
+    uint8_t *cdest = (uint8_t *)dest;
     uint32_t i=0U;
-  
+
     /* Copy contents of src[] to dest[] */
     for(i=0U; i<n; i++)
     {
-        cdest[i] = csrc[i]; 
+        cdest[i] = csrc[i];
     }
 }
 /* ========================================================================== */
 /*                          Function Definitions                              */
 /* ========================================================================== */
 
+/*
+ * Design: PROC_SDL-1049, PROC_SDL-1048
+ */
 
 static SDL_Result SDL_esmgHandlerInit(SDL_ESM_Inst esmInstType, const SDL_ESM_Params  *hwAttrs, SDL_ESM_Object *object)
 {
@@ -425,7 +419,7 @@ SDL_Result SDL_ESM_init (const SDL_ESM_Inst esmInstType,
         retVal = SDL_EBADARGS;
     }
     else if (notifierIndex == SDL_ESM_MAX_NOTIFIERS)
-    {                        
+    {
         retVal = SDL_EBADARGS;
     }
     else
@@ -712,10 +706,10 @@ int32_t SDL_ESM_registerCCMCallback(SDL_ESM_Inst esmInstType,uint32_t ccmEvent,
     static uint8_t callbackcount1 = 0U;
     SDL_Result result = SDL_PASS;
 	SDL_ESM_Object          *object;
-	
+
 	if(callbackcount1 <= 255U)
-	{		
-		object = &gEsmObjects[CONFIG_ESM0];		
+	{
+		object = &gEsmObjects[CONFIG_ESM0];
 		object->ccmenableBitmap[callbackcount1] = ccmEvent;
 		object->ccmCallBackFunction[callbackcount1] = callBack;
 		object->ccmCallBackFunctionArg[callbackcount1] = callbackArg;
diff --git a/source/sdl/include/am273x/soc_config.h b/source/sdl/include/am273x/soc_config.h
index 073928dd1a..2d59f6ca71 100644
--- a/source/sdl/include/am273x/soc_config.h
+++ b/source/sdl/include/am273x/soc_config.h
@@ -49,7 +49,6 @@ extern "C"
 
 /* IP versions */
 #define IP_VERSION_ESM_V1_0
-#define IP_VERSION_DCC_V1
 #define IP_VERSION_DSS_L3_V0
 #define IP_VERSION_HWA_V0
 #define IP_VERSION_MBOX_V0
diff --git a/source/sdl/include/am64x_am243x/sdlr_soc_ecc_aggr.h b/source/sdl/include/am64x_am243x/sdlr_soc_ecc_aggr.h
index 8f2d01719a..a676003c88 100644
--- a/source/sdl/include/am64x_am243x/sdlr_soc_ecc_aggr.h
+++ b/source/sdl/include/am64x_am243x/sdlr_soc_ecc_aggr.h
@@ -2797,6 +2797,11712 @@ extern "C"
 
 
 
+/* Properties of ECC Aggregator instance : MCU_ECC_AGGR0 */
+#define SDL_MCU_ECC_AGGR0_NUM_RAMS                                                                 (31U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_RAM_ID (0U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_ECC_TYPE (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_INJECT_TYPE (0U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_ACCESSIBLE (0U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS (256U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_RAM_ID (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_ECC_TYPE (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_INJECT_TYPE (0U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_ACCESSIBLE (0U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS (45U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_RAM_ID          (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_ECC_TYPE        (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_INJECT_TYPE     (0U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_ACCESSIBLE      (0U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS (45U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_RAM_ID      (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_ECC_TYPE    (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_INJECT_TYPE (0U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_ACCESSIBLE  (0U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS (256U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_RAM_ID      (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_ECC_TYPE    (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_INJECT_TYPE (0U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_ACCESSIBLE  (0U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS (49U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_RAM_ID (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ECC_TYPE (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_INJECT_TYPE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ACCESSIBLE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS (13U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_DST_BUSECC_RAM_ID (6U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_DST_BUSECC_ECC_TYPE (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_DST_BUSECC_ACCESSIBLE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS (7U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_RAM_ID (7U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_ACCESSIBLE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS (17U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_RAM_ID (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_ECC_TYPE (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_INJECT_TYPE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_ACCESSIBLE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS (13U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MAIN2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_RAM_ID                       (9U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MAIN2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_ECC_TYPE                     (1U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MAIN2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_INJECT_TYPE                  (0U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MAIN2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_ACCESSIBLE                   (0U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MAIN2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS             (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_RAM_ID                       (10U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_ECC_TYPE                     (1U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_INJECT_TYPE                  (0U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_ACCESSIBLE                   (0U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS             (69U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_RD_RAMECC_RAM_ID                      (11U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_RD_RAMECC_ECC_TYPE                    (0U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_RD_RAMECC_INJECT_TYPE                 (0U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_RD_RAMECC_ACCESSIBLE                  (0U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_RD_RAMECC_ROW_WIDTH                   (76U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_RD_RAMECC_RAM_SIZE                    (38U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_WR_RAMECC_RAM_ID                      (12U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_WR_RAMECC_ECC_TYPE                    (0U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_WR_RAMECC_INJECT_TYPE                 (0U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_WR_RAMECC_ACCESSIBLE                  (0U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_WR_RAMECC_ROW_WIDTH                   (76U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_WR_RAMECC_RAM_SIZE                    (38U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_RAM_ID (13U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_ECC_TYPE (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_INJECT_TYPE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_ACCESSIBLE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS (13U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_RAM_ID (14U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_ECC_TYPE (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_INJECT_TYPE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_ACCESSIBLE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_MAX_NUM_CHECKERS (256U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_RAM_ID (15U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_ECC_TYPE (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_INJECT_TYPE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_ACCESSIBLE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_MAX_NUM_CHECKERS (154U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_RAM_ID (16U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ECC_TYPE (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_INJECT_TYPE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ACCESSIBLE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS (5U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_RAM_ID (17U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ECC_TYPE (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_INJECT_TYPE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ACCESSIBLE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS (8U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_RAM_ID (18U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ECC_TYPE (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_INJECT_TYPE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ACCESSIBLE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS (42U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_RAM_ID   (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ECC_TYPE (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_INJECT_TYPE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ACCESSIBLE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS (19U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_RAM_ID (20U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ECC_TYPE (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ACCESSIBLE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS (42U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_RAM_ID     (21U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ECC_TYPE   (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_INJECT_TYPE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ACCESSIBLE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS (19U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_RAM_ID (22U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_ACCESSIBLE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS (256U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_RAM_ID (23U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_ACCESSIBLE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS (256U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_RAM_ID (24U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_ECC_TYPE (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_INJECT_TYPE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_ACCESSIBLE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS (256U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_RAM_ID (25U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_ECC_TYPE (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_INJECT_TYPE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_ACCESSIBLE (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS (152U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_DST_BUSECC_RAM_ID                                     (26U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_DST_BUSECC_ECC_TYPE                                   (1U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_DST_BUSECC_INJECT_TYPE                                (0U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_DST_BUSECC_ACCESSIBLE                                 (0U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_DST_BUSECC_MAX_NUM_CHECKERS                           (4U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_RAM_ID                                     (27U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_ECC_TYPE                                   (1U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_INJECT_TYPE                                (0U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_ACCESSIBLE                                 (0U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_MAX_NUM_CHECKERS                           (15U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_DST_BUSECC_RAM_ID                                     (28U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_DST_BUSECC_ECC_TYPE                                   (1U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_DST_BUSECC_INJECT_TYPE                                (0U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_DST_BUSECC_ACCESSIBLE                                 (0U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_DST_BUSECC_MAX_NUM_CHECKERS                           (5U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_RAM_ID                                     (29U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_ECC_TYPE                                   (1U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_INJECT_TYPE                                (0U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_ACCESSIBLE                                 (0U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_MAX_NUM_CHECKERS                           (17U)
+
+
+#define SDL_MCU_ECC_AGGR0_SAM64_MCU_ECC_AGGR_EDC_CTRL_RAM_ID                                       (30U)
+#define SDL_MCU_ECC_AGGR0_SAM64_MCU_ECC_AGGR_EDC_CTRL_ECC_TYPE                                     (1U)
+#define SDL_MCU_ECC_AGGR0_SAM64_MCU_ECC_AGGR_EDC_CTRL_INJECT_TYPE                                  (0U)
+#define SDL_MCU_ECC_AGGR0_SAM64_MCU_ECC_AGGR_EDC_CTRL_ACCESSIBLE                                   (0U)
+#define SDL_MCU_ECC_AGGR0_SAM64_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS                             (6U)
+
+
+
+/* EDC checkers information for ECC Aggregator instance : MCU_ECC_AGGR0 */
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_ID (0U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_ID (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_ID (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_ID (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_ID (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_ID (5U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_ID (6U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_ID (7U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_ID (8U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_ID (9U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_ID (10U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_ID (11U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_ID (12U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_ID (13U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_ID (14U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_ID (15U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_ID (16U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_ID (17U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_ID (18U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_ID (19U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_ID (20U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_ID (21U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_ID (22U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_ID (23U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_ID (24U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_ID (25U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_ID (26U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_ID (27U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_ID (28U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_ID (29U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_ID (30U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_ID (31U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_ID (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_ID (33U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_ID (34U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_ID (35U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_ID (36U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_ID (37U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_ID (38U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_ID (39U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_ID (40U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_ID (41U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_ID (42U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_ID (43U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_ID (44U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_ID (45U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_ID (46U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_ID (47U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_ID (48U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_ID (49U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_ID (50U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_ID (51U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_ID (52U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_ID (53U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_ID (54U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_ID (55U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_ID (56U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_ID (57U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_ID (58U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_ID (59U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_ID (60U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_ID (61U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_ID (62U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_ID (63U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_ID (64U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_ID (65U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_ID (66U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_ID (67U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_ID (68U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_ID (69U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_ID (70U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_ID (71U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_ID (72U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_ID (73U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_ID (74U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_ID (75U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_ID (76U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_ID (77U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_ID (78U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_ID (79U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_ID (80U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_ID (81U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_ID (82U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_ID (83U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_ID (84U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_ID (85U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_ID (86U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_ID (87U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_ID (88U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_ID (89U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_ID (90U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_ID (91U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_ID (92U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_ID (93U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_ID (94U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_ID (95U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_ID (96U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_ID (97U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_ID (98U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_ID (99U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_ID (100U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_ID (101U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_ID (102U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_ID (103U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_ID (104U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_ID (105U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_ID (106U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_ID (107U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_ID (108U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_ID (109U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_ID (110U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_ID (111U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_ID (112U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_ID (113U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_ID (114U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_ID (115U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_ID (116U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_ID (117U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_ID (118U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_ID (119U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_ID (120U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_ID (121U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_ID (122U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_ID (123U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_ID (124U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_ID (125U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_ID (126U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_ID (127U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_ID (128U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_ID (129U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_ID (130U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_ID (131U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_ID (132U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_ID (133U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_ID (134U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_ID (135U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_ID (136U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_ID (137U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_ID (138U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_ID (139U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_ID (140U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_ID (141U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_ID (142U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_ID (143U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_ID (144U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_ID (145U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_ID (146U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_ID (147U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_ID (148U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_ID (149U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_ID (150U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_ID (151U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_ID (152U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_ID (153U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_ID (154U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_ID (155U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_ID (156U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_ID (157U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_ID (158U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_ID (159U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_ID (160U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_ID (161U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_ID (162U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_ID (163U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_ID (164U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_ID (165U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_ID (166U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_ID (167U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_ID (168U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_ID (169U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_ID (170U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_ID (171U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_ID (172U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_ID (173U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_ID (174U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_ID (175U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_ID (176U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_ID (177U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_ID (178U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_ID (179U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_ID (180U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_ID (181U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_ID (182U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_ID (183U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_ID (184U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_ID (185U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_ID (186U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_ID (187U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_ID (188U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_ID (189U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_ID (190U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_ID (191U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_ID (192U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_ID (193U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_ID (194U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_ID (195U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_ID (196U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_ID (197U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_ID (198U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_ID (199U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_ID (200U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_ID (201U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_ID (202U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_ID (203U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_ID (204U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_ID (205U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_ID (206U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_ID (207U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_ID (208U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_ID (209U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_ID (210U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_ID (211U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_ID (212U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_ID (213U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_ID (214U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_ID (215U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_ID (216U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_ID (217U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_ID (218U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_ID (219U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_ID (220U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_ID (221U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_ID (222U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_ID (223U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_ID (224U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_ID (225U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_ID (226U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_ID (227U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_ID (228U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_ID (229U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_ID (230U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_ID (231U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_ID (232U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_ID (233U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_ID (234U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_ID (235U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_ID (236U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_ID (237U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_ID (238U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_ID (239U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_ID (240U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_ID (241U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_ID (242U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_ID (243U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_ID (244U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_ID (245U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_ID (246U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_ID (247U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_ID (248U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_ID (249U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_ID (250U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_ID (251U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_ID (252U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_ID (253U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_ID (254U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_ID (255U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_ID (0U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_ID (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_ID (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_ID (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_ID (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_ID (5U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_ID (6U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_ID (7U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_ID (8U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_ID (9U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_ID (10U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_ID (11U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_ID (12U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_ID (13U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_ID (14U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_ID (15U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_ID (16U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_ID (17U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_ID (18U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_ID (19U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_ID (20U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_ID (21U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_ID (22U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_ID (23U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_ID (24U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_ID (25U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_ID (26U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_ID (27U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_ID (28U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_ID (29U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_ID (30U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_ID (31U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_ID (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_ID (33U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_ID (34U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_ID (35U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_ID (36U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_ID (37U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_ID (38U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_ID (39U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_ID (40U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_ID (41U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_ID (42U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_ID (43U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_ID (44U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64XX_MCU_PADCFG_CTRL_MMR_MCU_0_AM64XX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_0_ID      (0U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_0_WIDTH   (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_1_ID      (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_1_WIDTH   (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_2_ID      (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_2_WIDTH   (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_3_ID      (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_3_WIDTH   (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_4_ID      (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_4_WIDTH   (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_5_ID      (5U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_5_WIDTH   (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_6_ID      (6U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_6_WIDTH   (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_7_ID      (7U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_7_WIDTH   (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_8_ID      (8U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_8_WIDTH   (12U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_9_ID      (9U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_9_WIDTH   (24U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_10_ID     (10U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_10_WIDTH  (6U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_11_ID     (11U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_11_WIDTH  (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_12_ID     (12U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_12_WIDTH  (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_13_ID     (13U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_13_WIDTH  (12U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_14_ID     (14U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_14_WIDTH  (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_15_ID     (15U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_15_WIDTH  (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_16_ID     (16U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_16_WIDTH  (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_17_ID     (17U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_17_WIDTH  (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_18_ID     (18U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_18_WIDTH  (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_19_ID     (19U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_19_WIDTH  (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_20_ID     (20U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_20_WIDTH  (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_21_ID     (21U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_21_WIDTH  (8U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_22_ID     (22U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_22_WIDTH  (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_23_ID     (23U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_23_WIDTH  (5U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_24_ID     (24U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_24_WIDTH  (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_25_ID     (25U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_25_WIDTH  (7U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_26_ID     (26U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_26_WIDTH  (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_27_ID     (27U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_27_WIDTH  (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_28_ID     (28U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_28_WIDTH  (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_29_ID     (29U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_29_WIDTH  (7U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_30_ID     (30U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_30_WIDTH  (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_31_ID     (31U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_31_WIDTH  (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_32_ID     (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_32_WIDTH  (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_33_ID     (33U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_33_WIDTH  (7U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_34_ID     (34U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_34_WIDTH  (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_35_ID     (35U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_35_WIDTH  (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_36_ID     (36U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_36_WIDTH  (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_37_ID     (37U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_37_WIDTH  (7U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_38_ID     (38U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_38_WIDTH  (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_39_ID     (39U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_39_WIDTH  (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_40_ID     (40U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_40_WIDTH  (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_41_ID     (41U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_41_WIDTH  (7U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_42_ID     (42U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_42_WIDTH  (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_43_ID     (43U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_43_WIDTH  (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_44_ID     (44U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_44_WIDTH  (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_PLL_MMR_MCU_0_AM64_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_ID  (0U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_ID  (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_ID  (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH (6U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_ID  (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH (6U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_ID  (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH (6U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_ID  (5U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH (6U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_ID  (6U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH (6U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_ID  (7U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH (6U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_ID  (8U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_ID  (9U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_ID (10U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_ID (11U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_ID (12U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_ID (13U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_ID (14U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_ID (15U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_ID (16U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_ID (17U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_ID (18U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_ID (19U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_ID (20U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_ID (21U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_ID (22U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_ID (23U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_ID (24U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_ID (25U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_ID (26U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_ID (27U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_ID (28U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_ID (29U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_ID (30U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_ID (31U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH (6U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_ID (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_ID (33U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_ID (34U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_ID (35U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_ID (36U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_ID (37U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_ID (38U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH (7U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_ID (39U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_ID (40U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_ID (41U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_ID (42U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_ID (43U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_ID (44U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_ID (45U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_ID (46U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_ID (47U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_ID (48U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_ID (49U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_ID (50U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_ID (51U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_ID (52U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_ID (53U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_ID (54U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_ID (55U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_ID (56U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_ID (57U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_ID (58U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_ID (59U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_ID (60U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_ID (61U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_ID (62U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_ID (63U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_ID (64U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_ID (65U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_ID (66U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_ID (67U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_ID (68U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_ID (69U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH (14U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_ID (70U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_ID (71U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH (21U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_ID (72U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_ID (73U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_ID (74U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH (30U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_ID (75U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_ID (76U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_ID (77U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_ID (78U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_ID (79U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_ID (80U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_ID (81U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_ID (82U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_ID (83U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_ID (84U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_ID (85U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_ID (86U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_ID (87U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_ID (88U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_ID (89U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_ID (90U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_ID (91U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_ID (92U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH (31U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_ID (93U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_ID (94U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_ID (95U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_ID (96U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_ID (97U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_ID (98U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_ID (99U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_ID (100U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_ID (101U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_ID (102U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_ID (103U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_ID (104U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_ID (105U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_ID (106U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_ID (107U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_ID (108U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_ID (109U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_ID (110U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_ID (111U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_ID (112U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_ID (113U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_ID (114U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_ID (115U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_ID (116U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_ID (117U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_ID (118U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_ID (119U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_ID (120U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_ID (121U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_ID (122U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_ID (123U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_ID (124U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_ID (125U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_ID (126U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_ID (127U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_ID (128U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_ID (129U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_ID (130U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_ID (131U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_ID (132U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_ID (133U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_ID (134U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_ID (135U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_ID (136U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH (6U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_ID (137U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_ID (138U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_ID (139U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_ID (140U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_ID (141U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_ID (142U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_ID (143U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_ID (144U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_ID (145U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_ID (146U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_ID (147U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_ID (148U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_ID (149U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_ID (150U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_ID (151U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_ID (152U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_ID (153U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_ID (154U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_ID (155U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_ID (156U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_ID (157U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_ID (158U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_ID (159U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_ID (160U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_ID (161U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_ID (162U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_ID (163U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_ID (164U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_ID (165U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_ID (166U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_ID (167U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_ID (168U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_ID (169U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH (7U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_ID (170U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_ID (171U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_ID (172U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH (7U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_ID (173U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_ID (174U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_ID (175U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH (7U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_ID (176U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_ID (177U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_ID (178U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH (7U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_ID (179U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_ID (180U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_ID (181U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH (7U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_ID (182U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_ID (183U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_ID (184U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH (7U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_ID (185U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_ID (186U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_ID (187U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH (7U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_ID (188U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_ID (189U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_ID (190U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH (7U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_ID (191U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_ID (192U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_ID (193U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH (7U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_ID (194U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_ID (195U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_ID (196U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH (7U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_ID (197U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_ID (198U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_ID (199U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH (7U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_ID (200U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_ID (201U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_ID (202U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH (7U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_ID (203U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_ID (204U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_ID (205U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH (7U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_ID (206U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_ID (207U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_ID (208U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH (7U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_ID (209U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_ID (210U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_ID (211U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH (7U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_ID (212U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_ID (213U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_ID (214U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH (7U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_ID (215U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_ID (216U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_ID (217U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH (7U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_ID (218U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_ID (219U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_ID (220U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH (7U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_ID (221U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_ID (222U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_ID (223U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_ID (224U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_ID (225U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_ID (226U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_ID (227U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_ID (228U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_ID (229U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_ID (230U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_ID (231U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_ID (232U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_ID (233U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_ID (234U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_ID (235U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_ID (236U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_ID (237U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_ID (238U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_ID (239U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_ID (240U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_ID (241U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_ID (242U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_ID (243U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_ID (244U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_ID (245U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_ID (246U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_ID (247U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH (6U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_ID (248U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH (6U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_ID (249U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_ID (250U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_ID (251U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_ID (252U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_ID (253U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_ID (254U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_ID (255U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_ID  (0U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_ID  (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_ID  (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_ID  (3U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_ID  (4U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_ID  (5U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_ID  (6U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_ID  (7U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_ID  (8U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_ID  (9U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_ID (10U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_ID (11U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_ID (12U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_ID (13U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_ID (14U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_ID (15U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_ID (16U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_ID (17U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_ID (18U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_ID (19U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_ID (20U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_ID (21U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_ID (22U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_ID (23U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_ID (24U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_ID (25U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_ID (26U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_ID (27U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_ID (28U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_ID (29U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_ID (30U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_ID (31U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_ID (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_ID (33U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_ID (34U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_ID (35U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_ID (36U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_ID (37U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_ID (38U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_ID (39U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_ID (40U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_ID (41U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_ID (42U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_ID (43U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_ID (44U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_45_ID (45U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_46_ID (46U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_47_ID (47U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH (24U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_48_ID (48U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_IAM64_MCU_CTRL_MMR_MCU_0_AM64_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_ID (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_ID (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_ID (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_3_ID (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_4_ID (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_5_ID (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_6_ID (6U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_7_ID (7U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_8_ID (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_9_ID (9U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_10_ID (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_11_ID (11U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_12_ID (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_ID (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_ID (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_ID (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_ID (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_DST_BUSECC_GROUP_4_ID (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_DST_BUSECC_GROUP_4_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_DST_BUSECC_GROUP_5_ID (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_DST_BUSECC_GROUP_5_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_DST_BUSECC_GROUP_6_ID (6U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_DST_BUSECC_GROUP_6_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_0_ID (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_1_ID (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_2_ID (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_3_ID (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_4_ID (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_5_ID (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_6_ID (6U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_7_ID (7U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_8_ID (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_9_ID (9U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_10_ID (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_11_ID (11U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_12_ID (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_13_ID (13U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_14_ID (14U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_15_ID (15U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_16_ID (16U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM64_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_0_ID (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_0_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_1_ID (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_1_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_2_ID (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_2_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_3_ID (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_3_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_4_ID (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_4_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_5_ID (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_5_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_6_ID (6U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_6_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_7_ID (7U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_7_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_8_ID (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_8_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_9_ID (9U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_9_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_10_ID (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_10_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_11_ID (11U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_11_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_12_ID (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_12_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_IBLAZAR_MCU_0_VBUSP_S_P2P_BRIDGE_IBLAZAR_MCU_0_VBUSP_S_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MAIN2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_0_ID                   (0U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MAIN2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_0_WIDTH                (48U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MAIN2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_0_CHECKER_TYPE         (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_0_ID                   (0U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_0_WIDTH                (1U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_0_CHECKER_TYPE         (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_1_ID                   (1U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_1_WIDTH                (1U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_1_CHECKER_TYPE         (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_2_ID                   (2U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_2_WIDTH                (4U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_2_CHECKER_TYPE         (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_3_ID                   (3U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_3_WIDTH                (10U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_3_CHECKER_TYPE         (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_4_ID                   (4U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_4_WIDTH                (32U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_4_CHECKER_TYPE         (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_5_ID                   (5U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_5_WIDTH                (1U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_5_CHECKER_TYPE         (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_6_ID                   (6U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_6_WIDTH                (2U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_6_CHECKER_TYPE         (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_7_ID                   (7U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_7_WIDTH                (2U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_7_CHECKER_TYPE         (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_8_ID                   (8U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_8_WIDTH                (1U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_8_CHECKER_TYPE         (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_9_ID                   (9U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_9_WIDTH                (30U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_9_CHECKER_TYPE         (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_10_ID                  (10U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_10_WIDTH               (2U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_10_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_11_ID                  (11U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_11_WIDTH               (2U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_11_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_12_ID                  (12U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_12_WIDTH               (10U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_12_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_13_ID                  (13U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_13_WIDTH               (12U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_13_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_14_ID                  (14U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_14_WIDTH               (4U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_14_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_15_ID                  (15U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_15_WIDTH               (3U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_15_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_16_ID                  (16U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_16_WIDTH               (1U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_16_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_17_ID                  (17U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_17_WIDTH               (1U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_17_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_18_ID                  (18U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_18_WIDTH               (1U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_18_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_19_ID                  (19U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_19_WIDTH               (1U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_19_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_20_ID                  (20U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_20_WIDTH               (2U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_20_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_21_ID                  (21U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_21_WIDTH               (10U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_21_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_22_ID                  (22U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_22_WIDTH               (10U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_22_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_23_ID                  (23U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_23_WIDTH               (12U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_23_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_24_ID                  (24U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_24_WIDTH               (4U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_24_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_25_ID                  (25U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_25_WIDTH               (3U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_25_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_26_ID                  (26U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_26_WIDTH               (1U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_26_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_27_ID                  (27U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_27_WIDTH               (10U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_27_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_28_ID                  (28U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_28_WIDTH               (3U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_28_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_29_ID                  (29U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_29_WIDTH               (3U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_29_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_30_ID                  (30U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_30_WIDTH               (1U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_30_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_31_ID                  (31U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_31_WIDTH               (1U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_31_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_32_ID                  (32U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_32_WIDTH               (1U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_32_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_33_ID                  (33U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_33_WIDTH               (1U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_33_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_34_ID                  (34U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_34_WIDTH               (3U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_34_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_35_ID                  (35U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_35_WIDTH               (1U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_35_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_36_ID                  (36U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_36_WIDTH               (1U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_36_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_37_ID                  (37U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_37_WIDTH               (1U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_37_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_38_ID                  (38U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_38_WIDTH               (30U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_38_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_39_ID                  (39U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_39_WIDTH               (6U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_39_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_40_ID                  (40U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_40_WIDTH               (6U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_40_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_41_ID                  (41U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_41_WIDTH               (6U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_41_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_42_ID                  (42U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_42_WIDTH               (2U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_42_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_43_ID                  (43U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_43_WIDTH               (10U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_43_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_44_ID                  (44U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_44_WIDTH               (3U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_44_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_45_ID                  (45U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_45_WIDTH               (2U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_45_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_46_ID                  (46U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_46_WIDTH               (4U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_46_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_47_ID                  (47U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_47_WIDTH               (5U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_47_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_48_ID                  (48U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_48_WIDTH               (4U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_48_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_49_ID                  (49U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_49_WIDTH               (2U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_49_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_50_ID                  (50U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_50_WIDTH               (2U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_50_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_51_ID                  (51U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_51_WIDTH               (2U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_51_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_52_ID                  (52U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_52_WIDTH               (2U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_52_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_53_ID                  (53U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_53_WIDTH               (22U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_53_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_54_ID                  (54U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_54_WIDTH               (22U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_54_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_55_ID                  (55U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_55_WIDTH               (10U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_55_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_56_ID                  (56U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_56_WIDTH               (3U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_56_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_57_ID                  (57U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_57_WIDTH               (2U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_57_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_58_ID                  (58U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_58_WIDTH               (4U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_58_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_59_ID                  (59U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_59_WIDTH               (5U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_59_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_60_ID                  (60U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_60_WIDTH               (4U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_60_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_61_ID                  (61U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_61_WIDTH               (2U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_61_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_62_ID                  (62U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_62_WIDTH               (2U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_62_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_63_ID                  (63U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_63_WIDTH               (2U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_63_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_64_ID                  (64U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_64_WIDTH               (2U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_64_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_65_ID                  (65U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_65_WIDTH               (55U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_65_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_66_ID                  (66U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_66_WIDTH               (55U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_66_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_67_ID                  (67U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_67_WIDTH               (8U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_67_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_68_ID                  (68U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_68_WIDTH               (8U)
+#define SDL_MCU_ECC_AGGR0_ISAM64_MCU2MAIN_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_68_CHECKER_TYPE        (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_ID (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_ID (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_ID (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_ID (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_ID (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_ID (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_ID (6U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_ID (7U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_ID (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_ID (9U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_ID (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_ID (11U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_ID (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ISLAVE_SAFETY_GASKET_MCU_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_0_ID (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_0_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_0_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_1_ID (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_1_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_1_CHECKER_TYPE (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_2_ID (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_2_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_2_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_3_ID (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_3_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_3_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_4_ID (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_4_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_4_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_5_ID (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_5_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_5_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_6_ID (6U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_6_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_6_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_7_ID (7U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_7_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_7_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_8_ID (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_8_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_8_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_9_ID (9U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_9_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_9_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_10_ID (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_10_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_10_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_11_ID (11U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_11_WIDTH (36U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_11_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_12_ID (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_12_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_12_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_13_ID (13U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_13_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_13_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_14_ID (14U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_14_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_14_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_15_ID (15U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_15_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_15_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_16_ID (16U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_16_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_16_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_17_ID (17U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_17_WIDTH (25U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_17_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_18_ID (18U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_18_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_18_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_19_ID (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_19_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_19_CHECKER_TYPE (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_20_ID (20U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_20_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_20_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_21_ID (21U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_21_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_21_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_22_ID (22U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_22_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_22_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_23_ID (23U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_23_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_23_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_24_ID (24U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_24_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_24_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_25_ID (25U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_25_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_25_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_26_ID (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_26_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_26_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_27_ID (27U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_27_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_27_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_28_ID (28U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_28_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_28_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_29_ID (29U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_29_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_29_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_30_ID (30U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_30_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_30_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_31_ID (31U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_31_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_31_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_32_ID (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_32_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_32_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_33_ID (33U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_33_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_33_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_34_ID (34U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_34_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_34_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_35_ID (35U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_35_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_35_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_36_ID (36U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_36_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_36_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_37_ID (37U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_37_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_37_CHECKER_TYPE (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_38_ID (38U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_38_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_38_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_39_ID (39U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_39_WIDTH (11U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_39_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_40_ID (40U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_40_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_40_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_41_ID (41U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_41_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_41_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_42_ID (42U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_42_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_42_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_43_ID (43U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_43_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_43_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_44_ID (44U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_44_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_44_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_45_ID (45U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_45_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_45_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_46_ID (46U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_46_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_46_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_47_ID (47U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_47_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_47_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_48_ID (48U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_48_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_48_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_49_ID (49U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_49_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_49_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_50_ID (50U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_50_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_50_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_51_ID (51U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_51_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_51_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_52_ID (52U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_52_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_52_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_53_ID (53U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_53_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_53_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_54_ID (54U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_54_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_54_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_55_ID (55U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_55_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_55_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_56_ID (56U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_56_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_56_CHECKER_TYPE (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_57_ID (57U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_57_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_57_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_58_ID (58U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_58_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_58_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_59_ID (59U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_59_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_59_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_60_ID (60U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_60_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_60_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_61_ID (61U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_61_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_61_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_62_ID (62U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_62_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_62_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_63_ID (63U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_63_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_63_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_64_ID (64U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_64_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_64_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_65_ID (65U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_65_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_65_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_66_ID (66U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_66_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_66_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_67_ID (67U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_67_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_67_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_68_ID (68U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_68_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_68_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_69_ID (69U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_69_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_69_CHECKER_TYPE (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_70_ID (70U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_70_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_70_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_71_ID (71U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_71_WIDTH (9U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_71_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_72_ID (72U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_72_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_72_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_73_ID (73U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_73_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_73_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_74_ID (74U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_74_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_74_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_75_ID (75U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_75_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_75_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_76_ID (76U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_76_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_76_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_77_ID (77U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_77_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_77_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_78_ID (78U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_78_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_78_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_79_ID (79U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_79_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_79_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_80_ID (80U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_80_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_80_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_81_ID (81U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_81_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_81_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_82_ID (82U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_82_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_82_CHECKER_TYPE (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_83_ID (83U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_83_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_83_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_84_ID (84U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_84_WIDTH (9U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_84_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_85_ID (85U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_85_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_85_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_86_ID (86U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_86_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_86_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_87_ID (87U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_87_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_87_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_88_ID (88U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_88_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_88_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_89_ID (89U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_89_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_89_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_90_ID (90U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_90_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_90_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_91_ID (91U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_91_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_91_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_92_ID (92U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_92_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_92_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_93_ID (93U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_93_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_93_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_94_ID (94U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_94_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_94_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_95_ID (95U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_95_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_95_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_96_ID (96U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_96_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_96_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_97_ID (97U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_97_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_97_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_98_ID (98U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_98_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_98_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_99_ID (99U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_99_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_99_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_100_ID (100U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_100_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_100_CHECKER_TYPE (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_101_ID (101U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_101_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_101_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_102_ID (102U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_102_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_102_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_103_ID (103U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_103_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_103_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_104_ID (104U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_104_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_104_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_105_ID (105U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_105_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_105_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_106_ID (106U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_106_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_106_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_107_ID (107U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_107_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_107_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_108_ID (108U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_108_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_108_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_109_ID (109U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_109_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_109_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_110_ID (110U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_110_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_110_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_111_ID (111U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_111_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_111_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_112_ID (112U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_112_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_112_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_113_ID (113U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_113_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_113_CHECKER_TYPE (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_114_ID (114U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_114_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_114_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_115_ID (115U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_115_WIDTH (17U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_115_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_116_ID (116U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_116_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_116_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_117_ID (117U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_117_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_117_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_118_ID (118U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_118_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_118_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_119_ID (119U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_119_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_119_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_120_ID (120U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_120_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_120_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_121_ID (121U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_121_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_121_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_122_ID (122U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_122_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_122_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_123_ID (123U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_123_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_123_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_124_ID (124U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_124_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_124_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_125_ID (125U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_125_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_125_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_126_ID (126U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_126_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_126_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_127_ID (127U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_127_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_127_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_128_ID (128U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_128_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_128_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_129_ID (129U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_129_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_129_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_130_ID (130U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_130_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_130_CHECKER_TYPE (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_131_ID (131U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_131_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_131_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_132_ID (132U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_132_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_132_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_133_ID (133U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_133_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_133_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_134_ID (134U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_134_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_134_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_135_ID (135U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_135_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_135_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_136_ID (136U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_136_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_136_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_137_ID (137U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_137_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_137_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_138_ID (138U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_138_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_138_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_139_ID (139U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_139_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_139_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_140_ID (140U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_140_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_140_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_141_ID (141U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_141_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_141_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_142_ID (142U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_142_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_142_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_143_ID (143U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_143_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_143_CHECKER_TYPE (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_144_ID (144U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_144_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_144_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_145_ID (145U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_145_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_145_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_146_ID (146U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_146_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_146_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_147_ID (147U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_147_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_147_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_148_ID (148U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_148_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_148_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_149_ID (149U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_149_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_149_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_150_ID (150U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_150_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_150_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_151_ID (151U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_151_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_151_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_152_ID (152U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_152_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_152_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_153_ID (153U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_153_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_153_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_154_ID (154U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_154_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_154_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_155_ID (155U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_155_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_155_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_156_ID (156U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_156_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_156_CHECKER_TYPE (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_157_ID (157U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_157_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_157_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_158_ID (158U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_158_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_158_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_159_ID (159U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_159_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_159_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_160_ID (160U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_160_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_160_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_161_ID (161U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_161_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_161_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_162_ID (162U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_162_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_162_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_163_ID (163U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_163_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_163_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_164_ID (164U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_164_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_164_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_165_ID (165U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_165_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_165_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_166_ID (166U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_166_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_166_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_167_ID (167U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_167_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_167_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_168_ID (168U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_168_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_168_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_169_ID (169U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_169_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_169_CHECKER_TYPE (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_170_ID (170U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_170_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_170_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_171_ID (171U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_171_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_171_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_172_ID (172U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_172_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_172_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_173_ID (173U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_173_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_173_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_174_ID (174U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_174_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_174_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_175_ID (175U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_175_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_175_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_176_ID (176U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_176_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_176_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_177_ID (177U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_177_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_177_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_178_ID (178U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_178_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_178_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_179_ID (179U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_179_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_179_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_180_ID (180U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_180_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_180_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_181_ID (181U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_181_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_181_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_182_ID (182U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_182_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_182_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_183_ID (183U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_183_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_183_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_184_ID (184U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_184_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_184_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_185_ID (185U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_185_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_185_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_186_ID (186U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_186_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_186_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_187_ID (187U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_187_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_187_CHECKER_TYPE (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_188_ID (188U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_188_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_188_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_189_ID (189U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_189_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_189_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_190_ID (190U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_190_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_190_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_191_ID (191U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_191_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_191_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_192_ID (192U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_192_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_192_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_193_ID (193U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_193_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_193_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_194_ID (194U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_194_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_194_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_195_ID (195U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_195_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_195_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_196_ID (196U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_196_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_196_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_197_ID (197U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_197_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_197_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_198_ID (198U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_198_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_198_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_199_ID (199U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_199_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_199_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_200_ID (200U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_200_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_200_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_201_ID (201U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_201_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_201_CHECKER_TYPE (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_202_ID (202U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_202_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_202_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_203_ID (203U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_203_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_203_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_204_ID (204U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_204_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_204_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_205_ID (205U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_205_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_205_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_206_ID (206U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_206_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_206_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_207_ID (207U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_207_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_207_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_208_ID (208U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_208_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_208_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_209_ID (209U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_209_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_209_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_210_ID (210U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_210_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_210_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_211_ID (211U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_211_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_211_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_212_ID (212U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_212_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_212_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_213_ID (213U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_213_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_213_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_214_ID (214U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_214_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_214_CHECKER_TYPE (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_215_ID (215U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_215_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_215_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_216_ID (216U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_216_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_216_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_217_ID (217U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_217_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_217_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_218_ID (218U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_218_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_218_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_219_ID (219U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_219_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_219_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_220_ID (220U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_220_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_220_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_221_ID (221U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_221_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_221_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_222_ID (222U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_222_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_222_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_223_ID (223U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_223_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_223_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_224_ID (224U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_224_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_224_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_225_ID (225U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_225_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_225_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_226_ID (226U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_226_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_226_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_227_ID (227U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_227_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_227_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_228_ID (228U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_228_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_228_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_229_ID (229U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_229_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_229_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_230_ID (230U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_230_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_230_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_231_ID (231U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_231_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_231_CHECKER_TYPE (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_232_ID (232U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_232_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_232_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_233_ID (233U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_233_WIDTH (9U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_233_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_234_ID (234U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_234_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_234_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_235_ID (235U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_235_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_235_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_236_ID (236U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_236_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_236_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_237_ID (237U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_237_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_237_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_238_ID (238U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_238_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_238_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_239_ID (239U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_239_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_239_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_240_ID (240U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_240_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_240_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_241_ID (241U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_241_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_241_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_242_ID (242U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_242_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_242_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_243_ID (243U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_243_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_243_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_244_ID (244U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_244_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_244_CHECKER_TYPE (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_245_ID (245U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_245_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_245_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_246_ID (246U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_246_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_246_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_247_ID (247U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_247_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_247_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_248_ID (248U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_248_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_248_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_249_ID (249U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_249_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_249_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_250_ID (250U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_250_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_250_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_251_ID (251U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_251_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_251_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_252_ID (252U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_252_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_252_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_253_ID (253U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_253_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_253_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_254_ID (254U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_254_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_254_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_255_ID (255U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_255_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_0_GROUP_255_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_0_ID (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_0_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_0_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_1_ID (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_1_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_1_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_2_ID (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_2_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_2_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_3_ID (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_3_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_3_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_4_ID (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_4_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_4_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_5_ID (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_5_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_5_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_6_ID (6U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_6_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_6_CHECKER_TYPE (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_7_ID (7U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_7_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_7_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_8_ID (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_8_WIDTH (9U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_8_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_9_ID (9U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_9_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_9_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_10_ID (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_10_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_10_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_11_ID (11U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_11_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_11_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_12_ID (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_12_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_12_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_13_ID (13U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_13_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_13_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_14_ID (14U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_14_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_14_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_15_ID (15U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_15_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_15_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_16_ID (16U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_16_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_16_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_17_ID (17U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_17_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_17_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_18_ID (18U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_18_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_18_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_19_ID (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_19_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_19_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_20_ID (20U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_20_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_20_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_21_ID (21U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_21_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_21_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_22_ID (22U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_22_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_22_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_23_ID (23U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_23_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_23_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_24_ID (24U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_24_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_24_CHECKER_TYPE (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_25_ID (25U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_25_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_25_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_26_ID (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_26_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_26_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_27_ID (27U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_27_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_27_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_28_ID (28U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_28_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_28_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_29_ID (29U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_29_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_29_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_30_ID (30U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_30_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_30_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_31_ID (31U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_31_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_31_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_32_ID (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_32_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_32_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_33_ID (33U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_33_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_33_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_34_ID (34U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_34_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_34_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_35_ID (35U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_35_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_35_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_36_ID (36U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_36_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_36_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_37_ID (37U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_37_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_37_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_38_ID (38U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_38_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_38_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_39_ID (39U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_39_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_39_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_40_ID (40U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_40_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_40_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_41_ID (41U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_41_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_41_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_42_ID (42U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_42_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_42_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_43_ID (43U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_43_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_43_CHECKER_TYPE (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_44_ID (44U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_44_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_44_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_45_ID (45U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_45_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_45_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_46_ID (46U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_46_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_46_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_47_ID (47U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_47_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_47_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_48_ID (48U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_48_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_48_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_49_ID (49U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_49_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_49_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_50_ID (50U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_50_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_50_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_51_ID (51U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_51_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_51_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_52_ID (52U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_52_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_52_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_53_ID (53U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_53_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_53_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_54_ID (54U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_54_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_54_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_55_ID (55U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_55_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_55_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_56_ID (56U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_56_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_56_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_57_ID (57U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_57_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_57_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_58_ID (58U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_58_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_58_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_59_ID (59U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_59_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_59_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_60_ID (60U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_60_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_60_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_61_ID (61U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_61_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_61_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_62_ID (62U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_62_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_62_CHECKER_TYPE (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_63_ID (63U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_63_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_63_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_64_ID (64U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_64_WIDTH (36U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_64_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_65_ID (65U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_65_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_65_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_66_ID (66U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_66_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_66_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_67_ID (67U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_67_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_67_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_68_ID (68U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_68_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_68_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_69_ID (69U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_69_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_69_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_70_ID (70U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_70_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_70_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_71_ID (71U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_71_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_71_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_72_ID (72U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_72_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_72_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_73_ID (73U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_73_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_73_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_74_ID (74U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_74_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_74_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_75_ID (75U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_75_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_75_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_76_ID (76U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_76_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_76_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_77_ID (77U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_77_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_77_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_78_ID (78U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_78_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_78_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_79_ID (79U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_79_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_79_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_80_ID (80U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_80_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_80_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_81_ID (81U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_81_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_81_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_82_ID (82U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_82_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_82_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_83_ID (83U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_83_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_83_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_84_ID (84U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_84_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_84_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_85_ID (85U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_85_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_85_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_86_ID (86U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_86_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_86_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_87_ID (87U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_87_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_87_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_88_ID (88U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_88_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_88_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_89_ID (89U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_89_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_89_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_90_ID (90U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_90_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_90_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_91_ID (91U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_91_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_91_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_92_ID (92U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_92_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_92_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_93_ID (93U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_93_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_93_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_94_ID (94U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_94_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_94_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_95_ID (95U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_95_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_95_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_96_ID (96U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_96_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_96_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_97_ID (97U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_97_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_97_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_98_ID (98U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_98_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_98_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_99_ID (99U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_99_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_99_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_100_ID (100U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_100_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_100_CHECKER_TYPE (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_101_ID (101U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_101_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_101_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_102_ID (102U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_102_WIDTH (15U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_102_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_103_ID (103U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_103_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_103_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_104_ID (104U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_104_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_104_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_105_ID (105U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_105_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_105_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_106_ID (106U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_106_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_106_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_107_ID (107U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_107_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_107_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_108_ID (108U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_108_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_108_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_109_ID (109U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_109_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_109_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_110_ID (110U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_110_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_110_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_111_ID (111U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_111_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_111_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_112_ID (112U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_112_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_112_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_113_ID (113U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_113_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_113_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_114_ID (114U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_114_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_114_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_115_ID (115U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_115_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_115_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_116_ID (116U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_116_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_116_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_117_ID (117U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_117_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_117_CHECKER_TYPE (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_118_ID (118U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_118_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_118_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_119_ID (119U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_119_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_119_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_120_ID (120U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_120_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_120_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_121_ID (121U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_121_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_121_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_122_ID (122U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_122_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_122_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_123_ID (123U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_123_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_123_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_124_ID (124U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_124_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_124_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_125_ID (125U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_125_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_125_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_126_ID (126U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_126_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_126_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_127_ID (127U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_127_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_127_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_128_ID (128U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_128_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_128_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_129_ID (129U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_129_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_129_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_130_ID (130U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_130_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_130_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_131_ID (131U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_131_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_131_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_132_ID (132U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_132_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_132_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_133_ID (133U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_133_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_133_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_134_ID (134U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_134_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_134_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_135_ID (135U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_135_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_135_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_136_ID (136U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_136_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_136_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_137_ID (137U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_137_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_137_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_138_ID (138U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_138_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_138_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_139_ID (139U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_139_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_139_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_140_ID (140U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_140_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_140_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_141_ID (141U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_141_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_141_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_142_ID (142U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_142_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_142_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_143_ID (143U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_143_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_143_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_144_ID (144U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_144_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_144_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_145_ID (145U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_145_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_145_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_146_ID (146U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_146_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_146_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_147_ID (147U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_147_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_147_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_148_ID (148U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_148_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_148_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_149_ID (149U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_149_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_149_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_150_ID (150U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_150_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_150_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_151_ID (151U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_151_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_151_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_152_ID (152U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_152_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_152_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_153_ID (153U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_153_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_1_GROUP_153_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_ID (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_ID (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_ID (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_ID (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_ID (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_ID (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_ID (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_ID (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_ID (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_ID (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_ID (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_ID (6U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_ID (7U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_AM64_MCU_CBASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_ID (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_ID (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH (13U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_ID (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_ID (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_ID (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_ID (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_ID (6U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_ID (7U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_ID (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_ID (9U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_ID (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_ID (11U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_ID (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_ID (13U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_ID (14U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_ID (15U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_ID (16U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_ID (17U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_ID (18U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_ID (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_ID (20U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_ID (21U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_ID (22U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_ID (23U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_ID (24U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH (7U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_ID (25U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_ID (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_ID (27U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_ID (28U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_ID (29U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_ID (30U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_ID (31U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_ID (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_ID (33U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_ID (34U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_ID (35U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_ID (36U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_ID (37U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_ID (38U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_ID (39U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_ID (40U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_ID (41U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_AM64_MCU_CBASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_ID (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_ID (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_ID (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_ID (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_ID (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_5_ID (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_6_ID (6U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_7_ID (7U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_8_ID (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_9_ID (9U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_10_ID (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_11_ID (11U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_12_ID (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_13_ID (13U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_13_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_14_ID (14U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_14_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_15_ID (15U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_15_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_16_ID (16U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_16_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_17_ID (17U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_17_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_18_ID (18U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_18_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_ID (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_ID (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_ID (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_ID (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_ID (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_ID (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_ID (6U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_ID (7U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_ID (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_ID (9U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_ID (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_ID (11U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_ID (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_ID (13U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_ID (14U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_ID (15U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_ID (16U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_ID (17U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_ID (18U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_ID (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_ID (20U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_ID (21U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_ID (22U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_ID (23U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_ID (24U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH (7U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_ID (25U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_ID (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_ID (27U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_ID (28U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_ID (29U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_ID (30U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_ID (31U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_ID (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_ID (33U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_ID (34U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_ID (35U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_ID (36U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_ID (37U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_ID (38U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_ID (39U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_ID (40U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_ID (41U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SCR_AM64_MCU_CBASS_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_0_ID (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_1_ID (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_2_ID (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_3_ID (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_4_ID (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_5_ID (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_6_ID (6U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_7_ID (7U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_8_ID (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_9_ID (9U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_10_ID (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_11_ID (11U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_12_ID (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_13_ID (13U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_13_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_14_ID (14U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_14_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_15_ID (15U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_15_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_16_ID (16U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_16_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_17_ID (17U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_17_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_18_ID (18U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_18_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_0_ID (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_1_ID (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH (36U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_2_ID (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_3_ID (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_4_ID (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_5_ID (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_6_ID (6U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_7_ID (7U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_8_ID (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_9_ID (9U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_10_ID (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_11_ID (11U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_12_ID (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH (36U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_13_ID (13U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_14_ID (14U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_15_ID (15U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_16_ID (16U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_17_ID (17U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_18_ID (18U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_19_ID (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_20_ID (20U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_21_ID (21U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_22_ID (22U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_23_ID (23U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_24_ID (24U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_25_ID (25U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_26_ID (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_27_ID (27U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_28_ID (28U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_29_ID (29U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_30_ID (30U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_31_ID (31U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_32_ID (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_33_ID (33U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_34_ID (34U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_35_ID (35U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_36_ID (36U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_37_ID (37U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_38_ID (38U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_39_ID (39U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_40_ID (40U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_41_ID (41U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_42_ID (42U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_43_ID (43U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_44_ID (44U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_45_ID (45U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_46_ID (46U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_47_ID (47U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_48_ID (48U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_49_ID (49U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_50_ID (50U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_51_ID (51U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_52_ID (52U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_53_ID (53U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_54_ID (54U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_55_ID (55U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_56_ID (56U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_57_ID (57U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_58_ID (58U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_59_ID (59U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_60_ID (60U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_61_ID (61U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_62_ID (62U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_63_ID (63U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_64_ID (64U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_65_ID (65U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_66_ID (66U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_67_ID (67U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_68_ID (68U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_69_ID (69U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_70_ID (70U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_71_ID (71U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_72_ID (72U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_73_ID (73U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_74_ID (74U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_75_ID (75U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_76_ID (76U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_77_ID (77U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_78_ID (78U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_79_ID (79U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_80_ID (80U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_81_ID (81U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_82_ID (82U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_83_ID (83U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_84_ID (84U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_85_ID (85U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_86_ID (86U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_87_ID (87U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_88_ID (88U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_89_ID (89U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_90_ID (90U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_91_ID (91U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_92_ID (92U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_93_ID (93U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_94_ID (94U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_95_ID (95U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_96_ID (96U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_97_ID (97U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_98_ID (98U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_99_ID (99U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_100_ID (100U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_101_ID (101U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_102_ID (102U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_103_ID (103U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_104_ID (104U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_105_ID (105U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_106_ID (106U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_107_ID (107U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_108_ID (108U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_109_ID (109U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_110_ID (110U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_111_ID (111U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_112_ID (112U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_113_ID (113U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_114_ID (114U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_115_ID (115U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_116_ID (116U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_117_ID (117U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_118_ID (118U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_119_ID (119U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_120_ID (120U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_121_ID (121U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_122_ID (122U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_123_ID (123U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_124_ID (124U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_125_ID (125U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_126_ID (126U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_127_ID (127U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_128_ID (128U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_129_ID (129U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_130_ID (130U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_131_ID (131U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_132_ID (132U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_133_ID (133U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_134_ID (134U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_135_ID (135U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_136_ID (136U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_137_ID (137U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_138_ID (138U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_139_ID (139U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_140_ID (140U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_141_ID (141U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_142_ID (142U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_143_ID (143U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_144_ID (144U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_145_ID (145U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_146_ID (146U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_147_ID (147U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_148_ID (148U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_149_ID (149U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_150_ID (150U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_151_ID (151U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_152_ID (152U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_153_ID (153U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_154_ID (154U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_155_ID (155U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_156_ID (156U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_157_ID (157U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_158_ID (158U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_159_ID (159U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_160_ID (160U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_161_ID (161U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_162_ID (162U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_163_ID (163U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_164_ID (164U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_165_ID (165U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_166_ID (166U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_167_ID (167U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_168_ID (168U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_169_ID (169U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_170_ID (170U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_171_ID (171U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_172_ID (172U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_173_ID (173U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_174_ID (174U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_175_ID (175U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_176_ID (176U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_177_ID (177U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_178_ID (178U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_179_ID (179U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_180_ID (180U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_181_ID (181U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_182_ID (182U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_183_ID (183U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_184_ID (184U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_185_ID (185U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_186_ID (186U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_187_ID (187U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_188_ID (188U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_189_ID (189U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_190_ID (190U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_191_ID (191U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_192_ID (192U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_193_ID (193U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_194_ID (194U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_195_ID (195U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_196_ID (196U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH (36U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_197_ID (197U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_198_ID (198U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_199_ID (199U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_200_ID (200U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_201_ID (201U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_202_ID (202U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_203_ID (203U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_204_ID (204U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_205_ID (205U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH (25U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_206_ID (206U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH (30U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_207_ID (207U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_208_ID (208U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH (27U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_209_ID (209U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_210_ID (210U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_211_ID (211U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_212_ID (212U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_213_ID (213U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_214_ID (214U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_215_ID (215U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_216_ID (216U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_217_ID (217U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_218_ID (218U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH (36U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_219_ID (219U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_220_ID (220U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_221_ID (221U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_222_ID (222U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_223_ID (223U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_224_ID (224U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_225_ID (225U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_226_ID (226U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_227_ID (227U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH (25U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_228_ID (228U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH (30U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_229_ID (229U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_230_ID (230U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH (27U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_231_ID (231U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_232_ID (232U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_233_ID (233U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_234_ID (234U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_235_ID (235U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_236_ID (236U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_237_ID (237U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_238_ID (238U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_239_ID (239U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_240_ID (240U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_241_ID (241U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_242_ID (242U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_243_ID (243U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_244_ID (244U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_245_ID (245U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_246_ID (246U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_247_ID (247U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_248_ID (248U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_249_ID (249U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_250_ID (250U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_251_ID (251U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_252_ID (252U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_253_ID (253U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_254_ID (254U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_255_ID (255U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_0_ID (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_1_ID (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_2_ID (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_3_ID (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_4_ID (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_5_ID (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_6_ID (6U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_7_ID (7U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_8_ID (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_9_ID (9U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH (11U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_10_ID (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_11_ID (11U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_12_ID (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_13_ID (13U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_14_ID (14U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_15_ID (15U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_16_ID (16U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_17_ID (17U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_18_ID (18U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH (11U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_19_ID (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_20_ID (20U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_21_ID (21U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_22_ID (22U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_23_ID (23U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_24_ID (24U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_25_ID (25U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_26_ID (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_27_ID (27U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_28_ID (28U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_29_ID (29U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_30_ID (30U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_31_ID (31U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_32_ID (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_33_ID (33U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_34_ID (34U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_35_ID (35U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_36_ID (36U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_37_ID (37U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_38_ID (38U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_39_ID (39U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_40_ID (40U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_41_ID (41U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_42_ID (42U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_43_ID (43U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_44_ID (44U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_45_ID (45U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_46_ID (46U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_47_ID (47U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_48_ID (48U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_49_ID (49U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_50_ID (50U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_51_ID (51U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_52_ID (52U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_53_ID (53U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_54_ID (54U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_55_ID (55U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_56_ID (56U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_57_ID (57U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_58_ID (58U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_59_ID (59U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_60_ID (60U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_61_ID (61U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH (9U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_62_ID (62U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_63_ID (63U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_64_ID (64U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_65_ID (65U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_66_ID (66U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_67_ID (67U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_68_ID (68U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_69_ID (69U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_70_ID (70U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH (9U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_71_ID (71U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_72_ID (72U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_73_ID (73U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_74_ID (74U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_75_ID (75U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_76_ID (76U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_77_ID (77U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_78_ID (78U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_79_ID (79U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_80_ID (80U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_81_ID (81U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_82_ID (82U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_83_ID (83U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_84_ID (84U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_85_ID (85U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_86_ID (86U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_87_ID (87U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH (9U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_88_ID (88U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_89_ID (89U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_90_ID (90U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_91_ID (91U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_92_ID (92U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_93_ID (93U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_94_ID (94U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_95_ID (95U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_96_ID (96U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH (9U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_97_ID (97U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_98_ID (98U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_99_ID (99U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_100_ID (100U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_101_ID (101U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_102_ID (102U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_103_ID (103U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_104_ID (104U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_105_ID (105U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_106_ID (106U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_107_ID (107U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_108_ID (108U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_109_ID (109U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_110_ID (110U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_111_ID (111U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_112_ID (112U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_113_ID (113U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_114_ID (114U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_115_ID (115U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_116_ID (116U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_117_ID (117U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_118_ID (118U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_119_ID (119U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_120_ID (120U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_121_ID (121U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_122_ID (122U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_123_ID (123U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_124_ID (124U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_125_ID (125U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_126_ID (126U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_127_ID (127U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_128_ID (128U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_129_ID (129U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_130_ID (130U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_131_ID (131U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_132_ID (132U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_133_ID (133U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_134_ID (134U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_135_ID (135U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_136_ID (136U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_137_ID (137U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_138_ID (138U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_139_ID (139U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH (17U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_140_ID (140U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_141_ID (141U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_142_ID (142U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_143_ID (143U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_144_ID (144U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_145_ID (145U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_146_ID (146U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_147_ID (147U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_148_ID (148U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH (17U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_149_ID (149U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_150_ID (150U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_151_ID (151U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_152_ID (152U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_153_ID (153U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_154_ID (154U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_154_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_155_ID (155U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_155_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_156_ID (156U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_156_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_157_ID (157U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_157_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_158_ID (158U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_158_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_159_ID (159U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_159_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_160_ID (160U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_160_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_161_ID (161U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_161_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_162_ID (162U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_162_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_163_ID (163U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_163_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_164_ID (164U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_164_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_165_ID (165U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_165_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_166_ID (166U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_166_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_167_ID (167U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_167_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_168_ID (168U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_168_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_169_ID (169U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_169_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_170_ID (170U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_170_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_171_ID (171U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_171_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_172_ID (172U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_172_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_173_ID (173U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_173_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_174_ID (174U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_174_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_175_ID (175U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_175_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_176_ID (176U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_176_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_177_ID (177U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_177_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_178_ID (178U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_178_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_179_ID (179U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_179_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_180_ID (180U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_180_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_181_ID (181U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_181_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_182_ID (182U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_182_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_183_ID (183U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_183_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_184_ID (184U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_184_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_185_ID (185U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_185_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_186_ID (186U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_186_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_187_ID (187U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_187_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_188_ID (188U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_188_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_189_ID (189U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_189_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_190_ID (190U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_190_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_191_ID (191U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_191_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_192_ID (192U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_192_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_193_ID (193U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_193_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_194_ID (194U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_194_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_195_ID (195U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_195_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_196_ID (196U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_196_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_197_ID (197U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_197_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_198_ID (198U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_198_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_199_ID (199U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_199_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_200_ID (200U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_200_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_201_ID (201U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_201_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_201_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_202_ID (202U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_202_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_202_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_203_ID (203U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_203_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_203_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_204_ID (204U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_204_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_204_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_205_ID (205U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_205_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_205_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_206_ID (206U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_206_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_206_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_207_ID (207U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_207_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_207_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_208_ID (208U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_208_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_208_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_209_ID (209U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_209_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_209_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_210_ID (210U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_210_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_210_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_211_ID (211U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_211_WIDTH (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_211_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_212_ID (212U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_212_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_212_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_213_ID (213U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_213_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_213_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_214_ID (214U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_214_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_214_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_215_ID (215U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_215_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_215_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_216_ID (216U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_216_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_216_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_217_ID (217U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_217_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_217_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_218_ID (218U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_218_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_218_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_219_ID (219U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_219_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_219_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_220_ID (220U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_220_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_220_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_221_ID (221U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_221_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_221_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_222_ID (222U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_222_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_222_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_223_ID (223U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_223_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_223_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_224_ID (224U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_224_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_224_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_225_ID (225U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_225_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_225_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_226_ID (226U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_226_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_226_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_227_ID (227U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_227_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_227_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_228_ID (228U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_228_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_228_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_229_ID (229U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_229_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_229_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_230_ID (230U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_230_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_230_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_231_ID (231U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_231_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_231_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_232_ID (232U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_232_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_232_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_233_ID (233U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_233_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_233_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_234_ID (234U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_234_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_234_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_235_ID (235U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_235_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_235_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_236_ID (236U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_236_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_236_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_237_ID (237U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_237_WIDTH (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_237_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_238_ID (238U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_238_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_238_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_239_ID (239U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_239_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_239_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_240_ID (240U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_240_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_240_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_241_ID (241U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_241_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_241_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_242_ID (242U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_242_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_242_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_243_ID (243U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_243_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_243_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_244_ID (244U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_244_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_244_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_245_ID (245U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_245_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_245_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_246_ID (246U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_246_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_246_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_247_ID (247U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_247_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_247_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_248_ID (248U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_248_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_248_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_249_ID (249U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_249_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_249_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_250_ID (250U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_250_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_250_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_251_ID (251U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_251_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_251_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_252_ID (252U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_252_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_252_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_253_ID (253U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_253_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_253_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_254_ID (254U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_254_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_254_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_255_ID (255U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_255_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_255_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_0_ID (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_0_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_0_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_1_ID (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_1_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_1_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_2_ID (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_2_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_2_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_3_ID (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_3_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_3_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_4_ID (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_4_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_4_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_5_ID (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_5_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_5_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_6_ID (6U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_6_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_6_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_7_ID (7U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_7_WIDTH (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_7_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_8_ID (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_8_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_8_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_9_ID (9U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_9_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_9_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_10_ID (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_10_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_10_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_11_ID (11U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_11_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_11_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_12_ID (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_12_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_12_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_13_ID (13U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_13_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_13_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_14_ID (14U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_14_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_14_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_15_ID (15U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_15_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_15_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_16_ID (16U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_16_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_16_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_17_ID (17U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_17_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_17_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_18_ID (18U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_18_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_18_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_19_ID (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_19_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_19_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_20_ID (20U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_20_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_20_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_21_ID (21U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_21_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_21_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_22_ID (22U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_22_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_22_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_23_ID (23U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_23_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_23_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_24_ID (24U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_24_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_24_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_25_ID (25U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_25_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_25_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_26_ID (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_26_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_26_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_27_ID (27U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_27_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_27_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_28_ID (28U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_28_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_28_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_29_ID (29U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_29_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_29_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_30_ID (30U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_30_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_30_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_31_ID (31U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_31_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_31_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_32_ID (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_32_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_32_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_33_ID (33U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_33_WIDTH (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_33_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_34_ID (34U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_34_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_34_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_35_ID (35U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_35_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_35_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_36_ID (36U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_36_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_36_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_37_ID (37U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_37_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_37_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_38_ID (38U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_38_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_38_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_39_ID (39U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_39_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_39_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_40_ID (40U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_40_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_40_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_41_ID (41U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_41_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_41_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_42_ID (42U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_42_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_42_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_43_ID (43U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_43_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_43_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_44_ID (44U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_44_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_44_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_45_ID (45U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_45_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_45_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_46_ID (46U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_46_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_46_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_47_ID (47U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_47_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_47_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_48_ID (48U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_48_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_48_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_49_ID (49U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_49_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_49_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_50_ID (50U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_50_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_50_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_51_ID (51U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_51_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_51_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_52_ID (52U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_52_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_52_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_53_ID (53U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_53_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_53_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_54_ID (54U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_54_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_54_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_55_ID (55U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_55_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_55_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_56_ID (56U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_56_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_56_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_57_ID (57U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_57_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_57_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_58_ID (58U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_58_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_58_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_59_ID (59U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_59_WIDTH (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_59_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_60_ID (60U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_60_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_60_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_61_ID (61U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_61_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_61_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_62_ID (62U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_62_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_62_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_63_ID (63U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_63_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_63_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_64_ID (64U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_64_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_64_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_65_ID (65U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_65_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_65_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_66_ID (66U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_66_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_66_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_67_ID (67U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_67_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_67_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_68_ID (68U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_68_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_68_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_69_ID (69U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_69_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_69_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_70_ID (70U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_70_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_70_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_71_ID (71U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_71_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_71_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_72_ID (72U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_72_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_72_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_73_ID (73U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_73_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_73_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_74_ID (74U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_74_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_74_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_75_ID (75U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_75_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_75_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_76_ID (76U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_76_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_76_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_77_ID (77U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_77_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_77_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_78_ID (78U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_78_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_78_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_79_ID (79U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_79_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_79_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_80_ID (80U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_80_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_80_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_81_ID (81U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_81_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_81_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_82_ID (82U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_82_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_82_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_83_ID (83U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_83_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_83_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_84_ID (84U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_84_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_84_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_85_ID (85U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_85_WIDTH (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_85_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_86_ID (86U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_86_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_86_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_87_ID (87U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_87_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_87_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_88_ID (88U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_88_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_88_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_89_ID (89U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_89_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_89_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_90_ID (90U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_90_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_90_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_91_ID (91U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_91_WIDTH (9U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_91_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_92_ID (92U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_92_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_92_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_93_ID (93U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_93_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_93_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_94_ID (94U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_94_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_94_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_95_ID (95U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_95_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_95_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_96_ID (96U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_96_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_96_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_97_ID (97U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_97_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_97_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_98_ID (98U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_98_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_98_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_99_ID (99U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_99_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_99_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_100_ID (100U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_100_WIDTH (9U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_100_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_101_ID (101U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_101_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_101_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_102_ID (102U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_102_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_102_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_103_ID (103U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_103_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_103_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_104_ID (104U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_104_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_104_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_105_ID (105U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_105_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_105_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_106_ID (106U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_106_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_106_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_107_ID (107U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_107_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_107_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_108_ID (108U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_108_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_108_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_109_ID (109U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_109_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_109_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_110_ID (110U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_110_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_110_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_111_ID (111U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_111_WIDTH (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_111_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_112_ID (112U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_112_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_112_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_113_ID (113U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_113_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_113_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_114_ID (114U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_114_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_114_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_115_ID (115U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_115_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_115_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_116_ID (116U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_116_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_116_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_117_ID (117U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_117_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_117_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_118_ID (118U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_118_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_118_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_119_ID (119U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_119_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_119_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_120_ID (120U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_120_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_120_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_121_ID (121U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_121_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_121_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_122_ID (122U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_122_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_122_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_123_ID (123U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_123_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_123_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_124_ID (124U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_124_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_124_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_125_ID (125U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_125_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_125_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_126_ID (126U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_126_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_126_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_127_ID (127U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_127_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_127_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_128_ID (128U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_128_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_128_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_129_ID (129U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_129_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_129_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_130_ID (130U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_130_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_130_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_131_ID (131U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_131_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_131_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_132_ID (132U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_132_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_132_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_133_ID (133U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_133_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_133_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_134_ID (134U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_134_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_134_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_135_ID (135U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_135_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_135_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_136_ID (136U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_136_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_136_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_137_ID (137U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_137_WIDTH (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_137_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_138_ID (138U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_138_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_138_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_139_ID (139U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_139_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_139_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_140_ID (140U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_140_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_140_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_141_ID (141U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_141_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_141_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_142_ID (142U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_142_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_142_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_143_ID (143U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_143_WIDTH (9U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_143_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_144_ID (144U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_144_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_144_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_145_ID (145U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_145_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_145_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_146_ID (146U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_146_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_146_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_147_ID (147U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_147_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_147_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_148_ID (148U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_148_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_148_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_149_ID (149U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_149_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_149_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_150_ID (150U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_150_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_150_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_151_ID (151U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_151_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_151_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_152_ID (152U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_152_WIDTH (9U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_152_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_153_ID (153U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_153_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_153_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_154_ID (154U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_154_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_154_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_155_ID (155U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_155_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_155_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_156_ID (156U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_156_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_156_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_157_ID (157U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_157_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_157_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_158_ID (158U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_158_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_158_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_159_ID (159U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_159_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_159_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_160_ID (160U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_160_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_160_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_161_ID (161U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_161_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_161_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_162_ID (162U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_162_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_162_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_163_ID (163U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_163_WIDTH (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_163_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_164_ID (164U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_164_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_164_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_165_ID (165U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_165_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_165_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_166_ID (166U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_166_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_166_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_167_ID (167U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_167_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_167_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_168_ID (168U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_168_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_168_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_169_ID (169U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_169_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_169_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_170_ID (170U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_170_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_170_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_171_ID (171U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_171_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_171_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_172_ID (172U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_172_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_172_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_173_ID (173U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_173_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_173_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_174_ID (174U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_174_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_174_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_175_ID (175U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_175_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_175_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_176_ID (176U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_176_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_176_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_177_ID (177U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_177_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_177_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_178_ID (178U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_178_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_178_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_179_ID (179U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_179_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_179_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_180_ID (180U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_180_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_180_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_181_ID (181U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_181_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_181_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_182_ID (182U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_182_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_182_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_183_ID (183U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_183_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_183_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_184_ID (184U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_184_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_184_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_185_ID (185U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_185_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_185_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_186_ID (186U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_186_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_186_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_187_ID (187U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_187_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_187_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_188_ID (188U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_188_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_188_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_189_ID (189U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_189_WIDTH (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_189_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_190_ID (190U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_190_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_190_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_191_ID (191U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_191_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_191_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_192_ID (192U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_192_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_192_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_193_ID (193U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_193_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_193_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_194_ID (194U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_194_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_194_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_195_ID (195U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_195_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_195_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_196_ID (196U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_196_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_196_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_197_ID (197U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_197_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_197_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_198_ID (198U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_198_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_198_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_199_ID (199U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_199_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_199_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_200_ID (200U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_200_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_200_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_201_ID (201U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_201_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_201_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_202_ID (202U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_202_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_202_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_203_ID (203U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_203_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_203_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_204_ID (204U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_204_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_204_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_205_ID (205U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_205_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_205_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_206_ID (206U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_206_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_206_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_207_ID (207U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_207_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_207_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_208_ID (208U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_208_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_208_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_209_ID (209U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_209_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_209_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_210_ID (210U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_210_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_210_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_211_ID (211U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_211_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_211_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_212_ID (212U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_212_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_212_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_213_ID (213U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_213_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_213_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_214_ID (214U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_214_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_214_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_215_ID (215U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_215_WIDTH (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_215_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_216_ID (216U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_216_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_216_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_217_ID (217U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_217_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_217_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_218_ID (218U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_218_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_218_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_219_ID (219U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_219_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_219_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_220_ID (220U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_220_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_220_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_221_ID (221U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_221_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_221_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_222_ID (222U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_222_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_222_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_223_ID (223U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_223_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_223_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_224_ID (224U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_224_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_224_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_225_ID (225U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_225_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_225_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_226_ID (226U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_226_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_226_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_227_ID (227U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_227_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_227_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_228_ID (228U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_228_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_228_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_229_ID (229U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_229_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_229_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_230_ID (230U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_230_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_230_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_231_ID (231U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_231_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_231_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_232_ID (232U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_232_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_232_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_233_ID (233U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_233_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_233_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_234_ID (234U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_234_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_234_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_235_ID (235U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_235_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_235_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_236_ID (236U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_236_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_236_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_237_ID (237U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_237_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_237_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_238_ID (238U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_238_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_238_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_239_ID (239U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_239_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_239_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_240_ID (240U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_240_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_240_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_241_ID (241U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_241_WIDTH (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_241_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_242_ID (242U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_242_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_242_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_243_ID (243U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_243_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_243_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_244_ID (244U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_244_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_244_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_245_ID (245U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_245_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_245_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_246_ID (246U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_246_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_246_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_247_ID (247U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_247_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_247_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_248_ID (248U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_248_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_248_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_249_ID (249U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_249_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_249_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_250_ID (250U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_250_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_250_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_251_ID (251U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_251_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_251_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_252_ID (252U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_252_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_252_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_253_ID (253U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_253_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_253_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_254_ID (254U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_254_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_254_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_255_ID (255U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_255_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_2_GROUP_255_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_0_ID (0U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_0_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_0_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_1_ID (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_1_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_1_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_2_ID (2U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_2_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_2_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_3_ID (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_3_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_3_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_4_ID (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_4_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_4_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_5_ID (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_5_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_5_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_6_ID (6U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_6_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_6_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_7_ID (7U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_7_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_7_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_8_ID (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_8_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_8_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_9_ID (9U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_9_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_9_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_10_ID (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_10_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_10_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_11_ID (11U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_11_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_11_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_12_ID (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_12_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_12_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_13_ID (13U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_13_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_13_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_14_ID (14U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_14_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_14_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_15_ID (15U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_15_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_15_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_16_ID (16U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_16_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_16_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_17_ID (17U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_17_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_17_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_18_ID (18U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_18_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_18_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_19_ID (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_19_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_19_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_20_ID (20U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_20_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_20_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_21_ID (21U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_21_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_21_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_22_ID (22U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_22_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_22_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_23_ID (23U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_23_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_23_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_24_ID (24U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_24_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_24_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_25_ID (25U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_25_WIDTH (36U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_25_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_26_ID (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_26_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_26_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_27_ID (27U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_27_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_27_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_28_ID (28U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_28_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_28_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_29_ID (29U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_29_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_29_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_30_ID (30U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_30_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_30_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_31_ID (31U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_31_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_31_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_32_ID (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_32_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_32_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_33_ID (33U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_33_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_33_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_34_ID (34U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_34_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_34_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_35_ID (35U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_35_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_35_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_36_ID (36U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_36_WIDTH (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_36_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_37_ID (37U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_37_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_37_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_38_ID (38U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_38_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_38_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_39_ID (39U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_39_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_39_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_40_ID (40U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_40_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_40_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_41_ID (41U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_41_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_41_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_42_ID (42U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_42_WIDTH (15U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_42_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_43_ID (43U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_43_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_43_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_44_ID (44U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_44_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_44_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_45_ID (45U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_45_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_45_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_46_ID (46U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_46_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_46_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_47_ID (47U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_47_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_47_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_48_ID (48U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_48_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_48_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_49_ID (49U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_49_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_49_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_50_ID (50U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_50_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_50_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_51_ID (51U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_51_WIDTH (15U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_51_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_52_ID (52U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_52_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_52_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_53_ID (53U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_53_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_53_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_54_ID (54U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_54_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_54_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_55_ID (55U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_55_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_55_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_56_ID (56U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_56_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_56_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_57_ID (57U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_57_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_57_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_58_ID (58U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_58_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_58_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_59_ID (59U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_59_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_59_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_60_ID (60U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_60_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_60_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_61_ID (61U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_61_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_61_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_62_ID (62U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_62_WIDTH (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_62_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_63_ID (63U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_63_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_63_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_64_ID (64U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_64_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_64_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_65_ID (65U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_65_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_65_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_66_ID (66U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_66_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_66_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_67_ID (67U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_67_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_67_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_68_ID (68U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_68_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_68_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_69_ID (69U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_69_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_69_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_70_ID (70U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_70_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_70_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_71_ID (71U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_71_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_71_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_72_ID (72U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_72_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_72_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_73_ID (73U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_73_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_73_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_74_ID (74U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_74_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_74_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_75_ID (75U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_75_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_75_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_76_ID (76U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_76_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_76_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_77_ID (77U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_77_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_77_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_78_ID (78U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_78_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_78_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_79_ID (79U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_79_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_79_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_80_ID (80U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_80_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_80_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_81_ID (81U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_81_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_81_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_82_ID (82U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_82_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_82_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_83_ID (83U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_83_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_83_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_84_ID (84U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_84_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_84_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_85_ID (85U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_85_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_85_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_86_ID (86U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_86_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_86_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_87_ID (87U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_87_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_87_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_88_ID (88U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_88_WIDTH (19U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_88_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_89_ID (89U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_89_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_89_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_90_ID (90U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_90_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_90_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_91_ID (91U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_91_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_91_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_92_ID (92U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_92_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_92_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_93_ID (93U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_93_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_93_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_94_ID (94U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_94_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_94_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_95_ID (95U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_95_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_95_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_96_ID (96U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_96_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_96_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_97_ID (97U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_97_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_97_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_98_ID (98U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_98_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_98_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_99_ID (99U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_99_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_99_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_100_ID (100U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_100_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_100_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_101_ID (101U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_101_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_101_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_102_ID (102U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_102_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_102_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_103_ID (103U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_103_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_103_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_104_ID (104U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_104_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_104_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_105_ID (105U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_105_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_105_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_106_ID (106U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_106_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_106_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_107_ID (107U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_107_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_107_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_108_ID (108U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_108_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_108_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_109_ID (109U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_109_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_109_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_110_ID (110U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_110_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_110_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_111_ID (111U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_111_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_111_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_112_ID (112U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_112_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_112_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_113_ID (113U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_113_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_113_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_114_ID (114U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_114_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_114_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_115_ID (115U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_115_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_115_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_116_ID (116U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_116_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_116_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_117_ID (117U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_117_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_117_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_118_ID (118U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_118_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_118_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_119_ID (119U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_119_WIDTH (12U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_119_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_120_ID (120U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_120_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_120_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_121_ID (121U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_121_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_121_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_122_ID (122U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_122_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_122_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_123_ID (123U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_123_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_123_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_124_ID (124U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_124_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_124_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_125_ID (125U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_125_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_125_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_126_ID (126U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_126_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_126_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_127_ID (127U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_127_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_127_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_128_ID (128U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_128_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_128_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_129_ID (129U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_129_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_129_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_130_ID (130U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_130_WIDTH (4U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_130_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_131_ID (131U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_131_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_131_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_132_ID (132U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_132_WIDTH (5U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_132_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_133_ID (133U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_133_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_133_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_134_ID (134U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_134_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_134_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_135_ID (135U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_135_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_135_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_136_ID (136U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_136_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_136_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_137_ID (137U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_137_WIDTH (8U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_137_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_138_ID (138U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_138_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_138_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_139_ID (139U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_139_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_139_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_140_ID (140U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_140_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_140_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_141_ID (141U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_141_WIDTH (26U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_141_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_142_ID (142U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_142_WIDTH (3U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_142_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_143_ID (143U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_143_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_143_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_144_ID (144U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_144_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_144_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_145_ID (145U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_145_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_145_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_146_ID (146U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_146_WIDTH (32U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_146_CHECKER_TYPE (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_147_ID (147U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_147_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_147_CHECKER_TYPE (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_148_ID (148U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_148_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_148_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_149_ID (149U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_149_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_149_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_150_ID (150U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_150_WIDTH (10U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_150_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_151_ID (151U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_151_WIDTH (1U)
+#define SDL_MCU_ECC_AGGR0_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_AM64_MCU_CBASS_CBASS_SCRP_MCU_CLK4_SCR_EDC_CTRL_BUSECC_3_GROUP_151_CHECKER_TYPE (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_DST_BUSECC_GROUP_0_ID                                 (0U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_DST_BUSECC_GROUP_0_WIDTH                              (1U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_DST_BUSECC_GROUP_0_CHECKER_TYPE                       (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_DST_BUSECC_GROUP_1_ID                                 (1U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_DST_BUSECC_GROUP_1_WIDTH                              (1U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_DST_BUSECC_GROUP_1_CHECKER_TYPE                       (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_DST_BUSECC_GROUP_2_ID                                 (2U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_DST_BUSECC_GROUP_2_WIDTH                              (36U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_DST_BUSECC_GROUP_2_CHECKER_TYPE                       (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_DST_BUSECC_GROUP_3_ID                                 (3U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_DST_BUSECC_GROUP_3_WIDTH                              (3U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_DST_BUSECC_GROUP_3_CHECKER_TYPE                       (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_0_ID                                 (0U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_0_WIDTH                              (1U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_0_CHECKER_TYPE                       (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_1_ID                                 (1U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_1_WIDTH                              (1U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_1_CHECKER_TYPE                       (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_2_ID                                 (2U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_2_WIDTH                              (36U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_2_CHECKER_TYPE                       (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_3_ID                                 (3U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_3_WIDTH                              (3U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_3_CHECKER_TYPE                       (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_4_ID                                 (4U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_4_WIDTH                              (3U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_4_CHECKER_TYPE                       (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_5_ID                                 (5U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_5_WIDTH                              (1U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_5_CHECKER_TYPE                       (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_6_ID                                 (6U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_6_WIDTH                              (1U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_6_CHECKER_TYPE                       (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_7_ID                                 (7U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_7_WIDTH                              (2U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_7_CHECKER_TYPE                       (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_8_ID                                 (8U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_8_WIDTH                              (3U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_8_CHECKER_TYPE                       (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_9_ID                                 (9U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_9_WIDTH                              (1U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_9_CHECKER_TYPE                       (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_10_ID                                (10U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_10_WIDTH                             (10U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_10_CHECKER_TYPE                      (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_11_ID                                (11U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_11_WIDTH                             (5U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_11_CHECKER_TYPE                      (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_12_ID                                (12U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_12_WIDTH                             (3U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_12_CHECKER_TYPE                      (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_13_ID                                (13U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_13_WIDTH                             (4U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_13_CHECKER_TYPE                      (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_14_ID                                (14U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_14_WIDTH                             (2U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_M_P2P_SRC_BUSECC_GROUP_14_CHECKER_TYPE                      (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_DST_BUSECC_GROUP_0_ID                                 (0U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_DST_BUSECC_GROUP_0_WIDTH                              (1U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_DST_BUSECC_GROUP_0_CHECKER_TYPE                       (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_DST_BUSECC_GROUP_1_ID                                 (1U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_DST_BUSECC_GROUP_1_WIDTH                              (1U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_DST_BUSECC_GROUP_1_CHECKER_TYPE                       (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_DST_BUSECC_GROUP_2_ID                                 (2U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_DST_BUSECC_GROUP_2_WIDTH                              (1U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_DST_BUSECC_GROUP_2_CHECKER_TYPE                       (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_DST_BUSECC_GROUP_3_ID                                 (3U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_DST_BUSECC_GROUP_3_WIDTH                              (32U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_DST_BUSECC_GROUP_3_CHECKER_TYPE                       (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_DST_BUSECC_GROUP_4_ID                                 (4U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_DST_BUSECC_GROUP_4_WIDTH                              (3U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_DST_BUSECC_GROUP_4_CHECKER_TYPE                       (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_0_ID                                 (0U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_0_WIDTH                              (1U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_0_CHECKER_TYPE                       (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_1_ID                                 (1U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_1_WIDTH                              (32U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_1_CHECKER_TYPE                       (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_2_ID                                 (2U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_2_WIDTH                              (1U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_2_CHECKER_TYPE                       (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_3_ID                                 (3U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_3_WIDTH                              (1U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_3_CHECKER_TYPE                       (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_4_ID                                 (4U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_4_WIDTH                              (32U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_4_CHECKER_TYPE                       (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_5_ID                                 (5U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_5_WIDTH                              (3U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_5_CHECKER_TYPE                       (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_6_ID                                 (6U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_6_WIDTH                              (3U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_6_CHECKER_TYPE                       (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_7_ID                                 (7U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_7_WIDTH                              (1U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_7_CHECKER_TYPE                       (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_8_ID                                 (8U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_8_WIDTH                              (1U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_8_CHECKER_TYPE                       (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_9_ID                                 (9U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_9_WIDTH                              (2U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_9_CHECKER_TYPE                       (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_10_ID                                (10U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_10_WIDTH                             (3U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_10_CHECKER_TYPE                      (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_11_ID                                (11U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_11_WIDTH                             (1U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_11_CHECKER_TYPE                      (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_12_ID                                (12U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_12_WIDTH                             (10U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_12_CHECKER_TYPE                      (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_13_ID                                (13U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_13_WIDTH                             (5U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_13_CHECKER_TYPE                      (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_14_ID                                (14U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_14_WIDTH                             (3U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_14_CHECKER_TYPE                      (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_15_ID                                (15U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_15_WIDTH                             (4U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_15_CHECKER_TYPE                      (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_16_ID                                (16U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_16_WIDTH                             (2U)
+#define SDL_MCU_ECC_AGGR0_BLAZAR_VBUSP_S_P2P_SRC_BUSECC_GROUP_16_CHECKER_TYPE                      (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_SAM64_MCU_ECC_AGGR_EDC_CTRL_GROUP_0_ID                                   (0U)
+#define SDL_MCU_ECC_AGGR0_SAM64_MCU_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH                                (1U)
+#define SDL_MCU_ECC_AGGR0_SAM64_MCU_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE                         (3U)
+
+
+#define SDL_MCU_ECC_AGGR0_SAM64_MCU_ECC_AGGR_EDC_CTRL_GROUP_1_ID                                   (1U)
+#define SDL_MCU_ECC_AGGR0_SAM64_MCU_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH                                (32U)
+#define SDL_MCU_ECC_AGGR0_SAM64_MCU_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE                         (1U)
+
+
+#define SDL_MCU_ECC_AGGR0_SAM64_MCU_ECC_AGGR_EDC_CTRL_GROUP_2_ID                                   (2U)
+#define SDL_MCU_ECC_AGGR0_SAM64_MCU_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH                                (1U)
+#define SDL_MCU_ECC_AGGR0_SAM64_MCU_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE                         (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_SAM64_MCU_ECC_AGGR_EDC_CTRL_GROUP_3_ID                                   (3U)
+#define SDL_MCU_ECC_AGGR0_SAM64_MCU_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH                                (10U)
+#define SDL_MCU_ECC_AGGR0_SAM64_MCU_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE                         (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_SAM64_MCU_ECC_AGGR_EDC_CTRL_GROUP_4_ID                                   (4U)
+#define SDL_MCU_ECC_AGGR0_SAM64_MCU_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH                                (4U)
+#define SDL_MCU_ECC_AGGR0_SAM64_MCU_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE                         (2U)
+
+
+#define SDL_MCU_ECC_AGGR0_SAM64_MCU_ECC_AGGR_EDC_CTRL_GROUP_5_ID                                   (5U)
+#define SDL_MCU_ECC_AGGR0_SAM64_MCU_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH                                (3U)
+#define SDL_MCU_ECC_AGGR0_SAM64_MCU_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE                         (2U)
+
+
+
 /* Properties of ECC Aggregator instance : ECC_AGGR1 */
 #define SDL_ECC_AGGR1_NUM_RAMS                                                                     (6U)
 
@@ -2823,14 +14529,14 @@ extern "C"
 #define SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS (11U)
 
 
-#define SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_RAM_ID (3U)
+#define SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_RAM_ID (4U)
 #define SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ECC_TYPE (1U)
 #define SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE (0U)
 #define SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ACCESSIBLE (0U)
 #define SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS (4U)
 
 
-#define SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_RAM_ID (4U)
+#define SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_RAM_ID (3U)
 #define SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE (1U)
 #define SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE (0U)
 #define SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ACCESSIBLE (0U)
@@ -5874,7 +17580,7 @@ extern "C"
 
 
 /* Summary of ECC aggregators */
-#define SDL_ECC_AGGR_NUM_ECC_AGGREGATORS                                                           (40U)
+#define SDL_ECC_AGGR_NUM_ECC_AGGREGATORS                                                           (41U)
 
 #ifdef __cplusplus
 }
diff --git a/source/sdl/include/am64x_am243x/soc_config.h b/source/sdl/include/am64x_am243x/soc_config.h
index 70e02d72d5..6b4adb8e57 100644
--- a/source/sdl/include/am64x_am243x/soc_config.h
+++ b/source/sdl/include/am64x_am243x/soc_config.h
@@ -49,6 +49,7 @@ extern "C"
 #define IP_VERSION_POK_V1
 #define IP_VERSION_ECC_V0
 #define IP_VERSION_PBIST_V0_1
+#define IP_VERSION_ROMCHECKSUM_V0
 #ifdef __cplusplus
 }
 #endif
diff --git a/source/sdl/include/awr294x/sdlr_mss_ecc_agg_mss.h b/source/sdl/include/awr294x/sdlr_mss_ecc_agg_mss.h
new file mode 100644
index 0000000000..c91b19c597
--- /dev/null
+++ b/source/sdl/include/awr294x/sdlr_mss_ecc_agg_mss.h
@@ -0,0 +1,728 @@
+/********************************************************************
+ * Copyright (C) 2023 Texas Instruments Incorporated.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  Name        : sdlr_mss_ecc_agg_mss.h
+*/
+#ifndef SDLR_MSS_ECC_AGG_MSS_H_
+#define SDLR_MSS_ECC_AGG_MSS_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**************************************************************************
+* Hardware Region  :
+**************************************************************************/
+
+
+/**************************************************************************
+* Register Overlay Structure
+**************************************************************************/
+
+typedef struct {
+    volatile uint32_t AGGR_REVISION;
+    volatile uint8_t  Resv_8[4];
+    volatile uint32_t ECC_VECTOR;
+    volatile uint32_t MISC_STATUS;
+    volatile uint32_t ECC_WRAP_REVISION;
+    volatile uint32_t CONTROL;
+    volatile uint32_t ERROR_CTRL1;
+    volatile uint32_t ERROR_CTRL2;
+    volatile uint32_t ERROR_STATUS1;
+    volatile uint32_t ERROR_STATUS2;
+    volatile uint32_t ERROR_STATUS3;
+    volatile uint8_t  Resv_60[16];
+    volatile uint32_t SEC_EOI_REG;
+    volatile uint32_t SEC_STATUS_REG0;
+    volatile uint8_t  Resv_128[60];
+    volatile uint32_t SEC_ENABLE_SET_REG0;
+    volatile uint8_t  Resv_192[60];
+    volatile uint32_t SEC_ENABLE_CLR_REG0;
+    volatile uint8_t  Resv_316[120];
+    volatile uint32_t DED_EOI_REG;
+    volatile uint32_t DED_STATUS_REG0;
+    volatile uint8_t  Resv_384[60];
+    volatile uint32_t DED_ENABLE_SET_REG0;
+    volatile uint8_t  Resv_448[60];
+    volatile uint32_t DED_ENABLE_CLR_REG0;
+    volatile uint8_t  Resv_512[60];
+    volatile uint32_t AGGR_ENABLE_SET;
+    volatile uint32_t AGGR_ENABLE_CLR;
+    volatile uint32_t AGGR_STATUS_SET;
+    volatile uint32_t AGGR_STATUS_CLR;
+} SDL_mss_ecc_agg_mssRegs;
+
+
+/**************************************************************************
+* Register Macros
+**************************************************************************/
+
+#define SDL_MSS_ECC_AGG_MSS_AGGR_REVISION                                      (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ECC_VECTOR                                         (0x00000008U)
+#define SDL_MSS_ECC_AGG_MSS_MISC_STATUS                                        (0x0000000CU)
+#define SDL_MSS_ECC_AGG_MSS_ECC_WRAP_REVISION                                  (0x00000010U)
+#define SDL_MSS_ECC_AGG_MSS_CONTROL                                            (0x00000014U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_CTRL1                                        (0x00000018U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_CTRL2                                        (0x0000001CU)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1                                      (0x00000020U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS2                                      (0x00000024U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS3                                      (0x00000028U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_EOI_REG                                        (0x0000003CU)
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0                                    (0x00000040U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0                                (0x00000080U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0                                (0x000000C0U)
+#define SDL_MSS_ECC_AGG_MSS_DED_EOI_REG                                        (0x0000013CU)
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0                                    (0x00000140U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0                                (0x00000180U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0                                (0x000001C0U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_ENABLE_SET                                    (0x00000200U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_ENABLE_CLR                                    (0x00000204U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_STATUS_SET                                    (0x00000208U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_STATUS_CLR                                    (0x0000020CU)
+
+/**************************************************************************
+* Field Definition Macros
+**************************************************************************/
+
+
+/* AGGR_REVISION */
+
+#define SDL_MSS_ECC_AGG_MSS_AGGR_REVISION_SCHEME_MASK                          (0xC0000000U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_REVISION_SCHEME_SHIFT                         (0x0000001EU)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_REVISION_SCHEME_RESETVAL                      (0x00000001U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_REVISION_SCHEME_MAX                           (0x00000003U)
+
+#define SDL_MSS_ECC_AGG_MSS_AGGR_REVISION_BU_MASK                              (0x30000000U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_REVISION_BU_SHIFT                             (0x0000001CU)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_REVISION_BU_RESETVAL                          (0x00000002U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_REVISION_BU_MAX                               (0x00000003U)
+
+#define SDL_MSS_ECC_AGG_MSS_AGGR_REVISION_MODULE_ID_MASK                       (0x0FFF0000U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_REVISION_MODULE_ID_SHIFT                      (0x00000010U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_REVISION_MODULE_ID_RESETVAL                   (0x000006A0U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_REVISION_MODULE_ID_MAX                        (0x00000FFFU)
+
+#define SDL_MSS_ECC_AGG_MSS_AGGR_REVISION_REVRTL_MASK                          (0x0000F800U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_REVISION_REVRTL_SHIFT                         (0x0000000BU)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_REVISION_REVRTL_RESETVAL                      (0x00000018U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_REVISION_REVRTL_MAX                           (0x0000001FU)
+
+#define SDL_MSS_ECC_AGG_MSS_AGGR_REVISION_REVMAJ_MASK                          (0x00000700U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_REVISION_REVMAJ_SHIFT                         (0x00000008U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_REVISION_REVMAJ_RESETVAL                      (0x00000002U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_REVISION_REVMAJ_MAX                           (0x00000007U)
+
+#define SDL_MSS_ECC_AGG_MSS_AGGR_REVISION_CUSTOM_MASK                          (0x000000C0U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_REVISION_CUSTOM_SHIFT                         (0x00000006U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_REVISION_CUSTOM_RESETVAL                      (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_REVISION_CUSTOM_MAX                           (0x00000003U)
+
+#define SDL_MSS_ECC_AGG_MSS_AGGR_REVISION_REVMIN_MASK                          (0x0000003FU)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_REVISION_REVMIN_SHIFT                         (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_REVISION_REVMIN_RESETVAL                      (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_REVISION_REVMIN_MAX                           (0x0000003FU)
+
+#define SDL_MSS_ECC_AGG_MSS_AGGR_REVISION_RESETVAL                             (0x66A0C200U)
+
+/* ECC_VECTOR */
+
+#define SDL_MSS_ECC_AGG_MSS_ECC_VECTOR_ECC_VECTOR_MASK                         (0x000007FFU)
+#define SDL_MSS_ECC_AGG_MSS_ECC_VECTOR_ECC_VECTOR_SHIFT                        (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ECC_VECTOR_ECC_VECTOR_RESETVAL                     (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ECC_VECTOR_ECC_VECTOR_MAX                          (0x000007FFU)
+
+#define SDL_MSS_ECC_AGG_MSS_ECC_VECTOR_RD_SVBUS_MASK                           (0x00008000U)
+#define SDL_MSS_ECC_AGG_MSS_ECC_VECTOR_RD_SVBUS_SHIFT                          (0x0000000FU)
+#define SDL_MSS_ECC_AGG_MSS_ECC_VECTOR_RD_SVBUS_RESETVAL                       (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ECC_VECTOR_RD_SVBUS_MAX                            (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_ECC_VECTOR_RD_SVBUS_ADDRESS_MASK                   (0x00FF0000U)
+#define SDL_MSS_ECC_AGG_MSS_ECC_VECTOR_RD_SVBUS_ADDRESS_SHIFT                  (0x00000010U)
+#define SDL_MSS_ECC_AGG_MSS_ECC_VECTOR_RD_SVBUS_ADDRESS_RESETVAL               (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ECC_VECTOR_RD_SVBUS_ADDRESS_MAX                    (0x000000FFU)
+
+#define SDL_MSS_ECC_AGG_MSS_ECC_VECTOR_RD_SVBUS_DONE_MASK                      (0x01000000U)
+#define SDL_MSS_ECC_AGG_MSS_ECC_VECTOR_RD_SVBUS_DONE_SHIFT                     (0x00000018U)
+#define SDL_MSS_ECC_AGG_MSS_ECC_VECTOR_RD_SVBUS_DONE_RESETVAL                  (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ECC_VECTOR_RD_SVBUS_DONE_MAX                       (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_ECC_VECTOR_RESETVAL                                (0x00000000U)
+
+/* MISC_STATUS */
+
+#define SDL_MSS_ECC_AGG_MSS_MISC_STATUS_NUM_RAMS_MASK                          (0x000007FFU)
+#define SDL_MSS_ECC_AGG_MSS_MISC_STATUS_NUM_RAMS_SHIFT                         (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_MISC_STATUS_NUM_RAMS_RESETVAL                      (0x00000008U)
+#define SDL_MSS_ECC_AGG_MSS_MISC_STATUS_NUM_RAMS_MAX                           (0x000007FFU)
+
+#define SDL_MSS_ECC_AGG_MSS_MISC_STATUS_RESETVAL                               (0x00000008U)
+
+/* ECC_WRAP_REVISION */
+
+#define SDL_MSS_ECC_AGG_MSS_ECC_WRAP_REVISION_SCHEME_MASK                      (0xC0000000U)
+#define SDL_MSS_ECC_AGG_MSS_ECC_WRAP_REVISION_SCHEME_SHIFT                     (0x0000001EU)
+#define SDL_MSS_ECC_AGG_MSS_ECC_WRAP_REVISION_SCHEME_RESETVAL                  (0x00000001U)
+#define SDL_MSS_ECC_AGG_MSS_ECC_WRAP_REVISION_SCHEME_MAX                       (0x00000003U)
+
+#define SDL_MSS_ECC_AGG_MSS_ECC_WRAP_REVISION_BU_MASK                          (0x30000000U)
+#define SDL_MSS_ECC_AGG_MSS_ECC_WRAP_REVISION_BU_SHIFT                         (0x0000001CU)
+#define SDL_MSS_ECC_AGG_MSS_ECC_WRAP_REVISION_BU_RESETVAL                      (0x00000002U)
+#define SDL_MSS_ECC_AGG_MSS_ECC_WRAP_REVISION_BU_MAX                           (0x00000003U)
+
+#define SDL_MSS_ECC_AGG_MSS_ECC_WRAP_REVISION_MODULE_ID_MASK                   (0x0FFF0000U)
+#define SDL_MSS_ECC_AGG_MSS_ECC_WRAP_REVISION_MODULE_ID_SHIFT                  (0x00000010U)
+#define SDL_MSS_ECC_AGG_MSS_ECC_WRAP_REVISION_MODULE_ID_RESETVAL               (0x000006A4U)
+#define SDL_MSS_ECC_AGG_MSS_ECC_WRAP_REVISION_MODULE_ID_MAX                    (0x00000FFFU)
+
+#define SDL_MSS_ECC_AGG_MSS_ECC_WRAP_REVISION_REVRTL_MASK                      (0x0000F800U)
+#define SDL_MSS_ECC_AGG_MSS_ECC_WRAP_REVISION_REVRTL_SHIFT                     (0x0000000BU)
+#define SDL_MSS_ECC_AGG_MSS_ECC_WRAP_REVISION_REVRTL_RESETVAL                  (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ECC_WRAP_REVISION_REVRTL_MAX                       (0x0000001FU)
+
+#define SDL_MSS_ECC_AGG_MSS_ECC_WRAP_REVISION_REVMAJ_MASK                      (0x00000700U)
+#define SDL_MSS_ECC_AGG_MSS_ECC_WRAP_REVISION_REVMAJ_SHIFT                     (0x00000008U)
+#define SDL_MSS_ECC_AGG_MSS_ECC_WRAP_REVISION_REVMAJ_RESETVAL                  (0x00000002U)
+#define SDL_MSS_ECC_AGG_MSS_ECC_WRAP_REVISION_REVMAJ_MAX                       (0x00000007U)
+
+#define SDL_MSS_ECC_AGG_MSS_ECC_WRAP_REVISION_CUSTOM_MASK                      (0x000000C0U)
+#define SDL_MSS_ECC_AGG_MSS_ECC_WRAP_REVISION_CUSTOM_SHIFT                     (0x00000006U)
+#define SDL_MSS_ECC_AGG_MSS_ECC_WRAP_REVISION_CUSTOM_RESETVAL                  (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ECC_WRAP_REVISION_CUSTOM_MAX                       (0x00000003U)
+
+#define SDL_MSS_ECC_AGG_MSS_ECC_WRAP_REVISION_REVMIN_MASK                      (0x0000003FU)
+#define SDL_MSS_ECC_AGG_MSS_ECC_WRAP_REVISION_REVMIN_SHIFT                     (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ECC_WRAP_REVISION_REVMIN_RESETVAL                  (0x00000002U)
+#define SDL_MSS_ECC_AGG_MSS_ECC_WRAP_REVISION_REVMIN_MAX                       (0x0000003FU)
+
+#define SDL_MSS_ECC_AGG_MSS_ECC_WRAP_REVISION_RESETVAL                         (0x66A40202U)
+
+/* CONTROL */
+
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_ECC_ENABLE_MASK                            (0x00000001U)
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_ECC_ENABLE_SHIFT                           (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_ECC_ENABLE_RESETVAL                        (0x00000001U)
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_ECC_ENABLE_MAX                             (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_ECC_CHECK_MASK                             (0x00000002U)
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_ECC_CHECK_SHIFT                            (0x00000001U)
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_ECC_CHECK_RESETVAL                         (0x00000001U)
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_ECC_CHECK_MAX                              (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_ENABLE_RMW_MASK                            (0x00000004U)
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_ENABLE_RMW_SHIFT                           (0x00000002U)
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_ENABLE_RMW_RESETVAL                        (0x00000001U)
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_ENABLE_RMW_MAX                             (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_FORCE_SEC_MASK                             (0x00000008U)
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_FORCE_SEC_SHIFT                            (0x00000003U)
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_FORCE_SEC_RESETVAL                         (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_FORCE_SEC_MAX                              (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_FORCE_DED_MASK                             (0x00000010U)
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_FORCE_DED_SHIFT                            (0x00000004U)
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_FORCE_DED_RESETVAL                         (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_FORCE_DED_MAX                              (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_FORCE_N_ROW_MASK                           (0x00000020U)
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_FORCE_N_ROW_SHIFT                          (0x00000005U)
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_FORCE_N_ROW_RESETVAL                       (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_FORCE_N_ROW_MAX                            (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_ERROR_ONCE_MASK                            (0x00000040U)
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_ERROR_ONCE_SHIFT                           (0x00000006U)
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_ERROR_ONCE_RESETVAL                        (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_ERROR_ONCE_MAX                             (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_CHECK_PARITY_MASK                          (0x00000080U)
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_CHECK_PARITY_SHIFT                         (0x00000007U)
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_CHECK_PARITY_RESETVAL                      (0x00000001U)
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_CHECK_PARITY_MAX                           (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_CHECK_SVBUS_TIMEOUT_MASK                   (0x00000100U)
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_CHECK_SVBUS_TIMEOUT_SHIFT                  (0x00000008U)
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_CHECK_SVBUS_TIMEOUT_RESETVAL               (0x00000001U)
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_CHECK_SVBUS_TIMEOUT_MAX                    (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_CONTROL_RESETVAL                                   (0x00000187U)
+
+/* ERROR_CTRL1 */
+
+#define SDL_MSS_ECC_AGG_MSS_ERROR_CTRL1_ECC_ROW_MASK                           (0xFFFFFFFFU)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_CTRL1_ECC_ROW_SHIFT                          (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_CTRL1_ECC_ROW_RESETVAL                       (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_CTRL1_ECC_ROW_MAX                            (0xFFFFFFFFU)
+
+#define SDL_MSS_ECC_AGG_MSS_ERROR_CTRL1_RESETVAL                               (0x00000000U)
+
+/* ERROR_CTRL2 */
+
+#define SDL_MSS_ECC_AGG_MSS_ERROR_CTRL2_ECC_BIT1_MASK                          (0x0000FFFFU)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_CTRL2_ECC_BIT1_SHIFT                         (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_CTRL2_ECC_BIT1_RESETVAL                      (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_CTRL2_ECC_BIT1_MAX                           (0x0000FFFFU)
+
+#define SDL_MSS_ECC_AGG_MSS_ERROR_CTRL2_ECC_BIT2_MASK                          (0xFFFF0000U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_CTRL2_ECC_BIT2_SHIFT                         (0x00000010U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_CTRL2_ECC_BIT2_RESETVAL                      (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_CTRL2_ECC_BIT2_MAX                           (0x0000FFFFU)
+
+#define SDL_MSS_ECC_AGG_MSS_ERROR_CTRL2_RESETVAL                               (0x00000000U)
+
+/* ERROR_STATUS1 */
+
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_ECC_SEC_MASK                         (0x00000003U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_ECC_SEC_SHIFT                        (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_ECC_SEC_RESETVAL                     (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_ECC_SEC_MAX                          (0x00000003U)
+
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_ECC_DED_MASK                         (0x0000000CU)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_ECC_DED_SHIFT                        (0x00000002U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_ECC_DED_RESETVAL                     (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_ECC_DED_MAX                          (0x00000003U)
+
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_ECC_OTHER_MASK                       (0x00000010U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_ECC_OTHER_SHIFT                      (0x00000004U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_ECC_OTHER_RESETVAL                   (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_ECC_OTHER_MAX                        (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_PARITY_ERR_MASK                      (0x00000060U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_PARITY_ERR_SHIFT                     (0x00000005U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_PARITY_ERR_RESETVAL                  (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_PARITY_ERR_MAX                       (0x00000003U)
+
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_CTR_REG_ERR_MASK                     (0x00000080U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_CTR_REG_ERR_SHIFT                    (0x00000007U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_CTR_REG_ERR_RESETVAL                 (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_CTR_REG_ERR_MAX                      (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_CLR_ECC_SEC_MASK                     (0x00000300U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_CLR_ECC_SEC_SHIFT                    (0x00000008U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_CLR_ECC_SEC_RESETVAL                 (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_CLR_ECC_SEC_MAX                      (0x00000003U)
+
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_CLR_ECC_DED_MASK                     (0x00000C00U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_CLR_ECC_DED_SHIFT                    (0x0000000AU)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_CLR_ECC_DED_RESETVAL                 (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_CLR_ECC_DED_MAX                      (0x00000003U)
+
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_CLR_ECC_OTHER_MASK                   (0x00001000U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_CLR_ECC_OTHER_SHIFT                  (0x0000000CU)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_CLR_ECC_OTHER_RESETVAL               (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_CLR_ECC_OTHER_MAX                    (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_CLR_PARITY_ERR_MASK                  (0x00006000U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_CLR_PARITY_ERR_SHIFT                 (0x0000000DU)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_CLR_PARITY_ERR_RESETVAL              (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_CLR_PARITY_ERR_MAX                   (0x00000003U)
+
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_CLR_CTRL_REG_ERR_MASK                (0x00008000U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_CLR_CTRL_REG_ERR_SHIFT               (0x0000000FU)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_CLR_CTRL_REG_ERR_RESETVAL            (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_CLR_CTRL_REG_ERR_MAX                 (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_ECC_BIT1_MASK                        (0xFFFF0000U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_ECC_BIT1_SHIFT                       (0x00000010U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_ECC_BIT1_RESETVAL                    (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_ECC_BIT1_MAX                         (0x0000FFFFU)
+
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS1_RESETVAL                             (0x00000000U)
+
+/* ERROR_STATUS2 */
+
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS2_ECC_ROW_MASK                         (0xFFFFFFFFU)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS2_ECC_ROW_SHIFT                        (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS2_ECC_ROW_RESETVAL                     (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS2_ECC_ROW_MAX                          (0xFFFFFFFFU)
+
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS2_RESETVAL                             (0x00000000U)
+
+/* ERROR_STATUS3 */
+
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS3_WB_PEND_MASK                         (0x00000001U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS3_WB_PEND_SHIFT                        (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS3_WB_PEND_RESETVAL                     (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS3_WB_PEND_MAX                          (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS3_SVBUS_TIMEOUT_ERR_MASK               (0x00000002U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS3_SVBUS_TIMEOUT_ERR_SHIFT              (0x00000001U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS3_SVBUS_TIMEOUT_ERR_RESETVAL           (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS3_SVBUS_TIMEOUT_ERR_MAX                (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS3_CLR_SVBUS_TIMEOUT_ERR_MASK           (0x00000200U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS3_CLR_SVBUS_TIMEOUT_ERR_SHIFT          (0x00000009U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS3_CLR_SVBUS_TIMEOUT_ERR_RESETVAL       (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS3_CLR_SVBUS_TIMEOUT_ERR_MAX            (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_ERROR_STATUS3_RESETVAL                             (0x00000000U)
+
+/* SEC_EOI_REG */
+
+#define SDL_MSS_ECC_AGG_MSS_SEC_EOI_REG_EOI_WR_MASK                            (0x00000001U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_EOI_REG_EOI_WR_SHIFT                           (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_EOI_REG_EOI_WR_RESETVAL                        (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_EOI_REG_EOI_WR_MAX                             (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_SEC_EOI_REG_RESETVAL                               (0x00000000U)
+
+/* SEC_STATUS_REG0 */
+
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_MSS_L2SLV0_PEND_MASK               (0x00000001U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_MSS_L2SLV0_PEND_SHIFT              (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_MSS_L2SLV0_PEND_RESETVAL           (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_MSS_L2SLV0_PEND_MAX                (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_MSS_L2SLV1_PEND_MASK               (0x00000002U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_MSS_L2SLV1_PEND_SHIFT              (0x00000001U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_MSS_L2SLV1_PEND_RESETVAL           (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_MSS_L2SLV1_PEND_MAX                (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_MSS_MBOX_PEND_MASK                 (0x00000004U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_MSS_MBOX_PEND_SHIFT                (0x00000002U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_MSS_MBOX_PEND_RESETVAL             (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_MSS_MBOX_PEND_MAX                  (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_MSS_RETRAM_PEND_MASK               (0x00000008U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_MSS_RETRAM_PEND_SHIFT              (0x00000003U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_MSS_RETRAM_PEND_RESETVAL           (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_MSS_RETRAM_PEND_MAX                (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_GPADC_PEND_MASK                    (0x00000010U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_GPADC_PEND_SHIFT                   (0x00000004U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_GPADC_PEND_RESETVAL                (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_GPADC_PEND_MAX                     (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_TPTC_A0_PEND_MASK                  (0x00000020U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_TPTC_A0_PEND_SHIFT                 (0x00000005U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_TPTC_A0_PEND_RESETVAL              (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_TPTC_A0_PEND_MAX                   (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_TPTC_A1_PEND_MASK                  (0x00000040U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_TPTC_A1_PEND_SHIFT                 (0x00000006U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_TPTC_A1_PEND_RESETVAL              (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_TPTC_A1_PEND_MAX                   (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_TPTC_B0_PEND_MASK                  (0x00000080U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_TPTC_B0_PEND_SHIFT                 (0x00000007U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_TPTC_B0_PEND_RESETVAL              (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_TPTC_B0_PEND_MAX                   (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_SEC_STATUS_REG0_RESETVAL                           (0x00000000U)
+
+/* SEC_ENABLE_SET_REG0 */
+
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_MSS_L2SLV0_ENABLE_SET_MASK     (0x00000001U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_MSS_L2SLV0_ENABLE_SET_SHIFT    (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_MSS_L2SLV0_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_MSS_L2SLV0_ENABLE_SET_MAX      (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_MSS_L2SLV1_ENABLE_SET_MASK     (0x00000002U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_MSS_L2SLV1_ENABLE_SET_SHIFT    (0x00000001U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_MSS_L2SLV1_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_MSS_L2SLV1_ENABLE_SET_MAX      (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_MSS_MBOX_ENABLE_SET_MASK       (0x00000004U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_MSS_MBOX_ENABLE_SET_SHIFT      (0x00000002U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_MSS_MBOX_ENABLE_SET_RESETVAL   (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_MSS_MBOX_ENABLE_SET_MAX        (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_MSS_RETRAM_ENABLE_SET_MASK     (0x00000008U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_MSS_RETRAM_ENABLE_SET_SHIFT    (0x00000003U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_MSS_RETRAM_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_MSS_RETRAM_ENABLE_SET_MAX      (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_GPADC_ENABLE_SET_MASK          (0x00000010U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_GPADC_ENABLE_SET_SHIFT         (0x00000004U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_GPADC_ENABLE_SET_RESETVAL      (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_GPADC_ENABLE_SET_MAX           (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_TPTC_A0_ENABLE_SET_MASK        (0x00000020U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_TPTC_A0_ENABLE_SET_SHIFT       (0x00000005U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_TPTC_A0_ENABLE_SET_RESETVAL    (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_TPTC_A0_ENABLE_SET_MAX         (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_TPTC_A1_ENABLE_SET_MASK        (0x00000040U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_TPTC_A1_ENABLE_SET_SHIFT       (0x00000006U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_TPTC_A1_ENABLE_SET_RESETVAL    (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_TPTC_A1_ENABLE_SET_MAX         (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_TPTC_B0_ENABLE_SET_MASK        (0x00000080U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_TPTC_B0_ENABLE_SET_SHIFT       (0x00000007U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_TPTC_B0_ENABLE_SET_RESETVAL    (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_TPTC_B0_ENABLE_SET_MAX         (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_SET_REG0_RESETVAL                       (0x00000000U)
+
+/* SEC_ENABLE_CLR_REG0 */
+
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_MSS_L2SLV0_ENABLE_CLR_MASK     (0x00000001U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_MSS_L2SLV0_ENABLE_CLR_SHIFT    (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_MSS_L2SLV0_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_MSS_L2SLV0_ENABLE_CLR_MAX      (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_MSS_L2SLV1_ENABLE_CLR_MASK     (0x00000002U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_MSS_L2SLV1_ENABLE_CLR_SHIFT    (0x00000001U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_MSS_L2SLV1_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_MSS_L2SLV1_ENABLE_CLR_MAX      (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_MSS_MBOX_ENABLE_CLR_MASK       (0x00000004U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_MSS_MBOX_ENABLE_CLR_SHIFT      (0x00000002U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_MSS_MBOX_ENABLE_CLR_RESETVAL   (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_MSS_MBOX_ENABLE_CLR_MAX        (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_MSS_RETRAM_ENABLE_CLR_MASK     (0x00000008U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_MSS_RETRAM_ENABLE_CLR_SHIFT    (0x00000003U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_MSS_RETRAM_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_MSS_RETRAM_ENABLE_CLR_MAX      (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_GPADC_ENABLE_CLR_MASK          (0x00000010U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_GPADC_ENABLE_CLR_SHIFT         (0x00000004U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_GPADC_ENABLE_CLR_RESETVAL      (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_GPADC_ENABLE_CLR_MAX           (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_TPTC_A0_ENABLE_CLR_MASK        (0x00000020U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_TPTC_A0_ENABLE_CLR_SHIFT       (0x00000005U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_TPTC_A0_ENABLE_CLR_RESETVAL    (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_TPTC_A0_ENABLE_CLR_MAX         (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_TPTC_A1_ENABLE_CLR_MASK        (0x00000040U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_TPTC_A1_ENABLE_CLR_SHIFT       (0x00000006U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_TPTC_A1_ENABLE_CLR_RESETVAL    (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_TPTC_A1_ENABLE_CLR_MAX         (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_TPTC_B0_ENABLE_CLR_MASK        (0x00000080U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_TPTC_B0_ENABLE_CLR_SHIFT       (0x00000007U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_TPTC_B0_ENABLE_CLR_RESETVAL    (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_TPTC_B0_ENABLE_CLR_MAX         (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_SEC_ENABLE_CLR_REG0_RESETVAL                       (0x00000000U)
+
+/* DED_EOI_REG */
+
+#define SDL_MSS_ECC_AGG_MSS_DED_EOI_REG_EOI_WR_MASK                            (0x00000001U)
+#define SDL_MSS_ECC_AGG_MSS_DED_EOI_REG_EOI_WR_SHIFT                           (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_DED_EOI_REG_EOI_WR_RESETVAL                        (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_DED_EOI_REG_EOI_WR_MAX                             (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_DED_EOI_REG_RESETVAL                               (0x00000000U)
+
+/* DED_STATUS_REG0 */
+
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_MSS_L2SLV0_PEND_MASK               (0x00000001U)
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_MSS_L2SLV0_PEND_SHIFT              (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_MSS_L2SLV0_PEND_RESETVAL           (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_MSS_L2SLV0_PEND_MAX                (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_MSS_L2SLV1_PEND_MASK               (0x00000002U)
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_MSS_L2SLV1_PEND_SHIFT              (0x00000001U)
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_MSS_L2SLV1_PEND_RESETVAL           (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_MSS_L2SLV1_PEND_MAX                (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_MSS_MBOX_PEND_MASK                 (0x00000004U)
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_MSS_MBOX_PEND_SHIFT                (0x00000002U)
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_MSS_MBOX_PEND_RESETVAL             (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_MSS_MBOX_PEND_MAX                  (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_MSS_RETRAM_PEND_MASK               (0x00000008U)
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_MSS_RETRAM_PEND_SHIFT              (0x00000003U)
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_MSS_RETRAM_PEND_RESETVAL           (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_MSS_RETRAM_PEND_MAX                (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_GPADC_PEND_MASK                    (0x00000010U)
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_GPADC_PEND_SHIFT                   (0x00000004U)
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_GPADC_PEND_RESETVAL                (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_GPADC_PEND_MAX                     (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_TPTC_A0_PEND_MASK                  (0x00000020U)
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_TPTC_A0_PEND_SHIFT                 (0x00000005U)
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_TPTC_A0_PEND_RESETVAL              (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_TPTC_A0_PEND_MAX                   (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_TPTC_A1_PEND_MASK                  (0x00000040U)
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_TPTC_A1_PEND_SHIFT                 (0x00000006U)
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_TPTC_A1_PEND_RESETVAL              (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_TPTC_A1_PEND_MAX                   (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_TPTC_B0_PEND_MASK                  (0x00000080U)
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_TPTC_B0_PEND_SHIFT                 (0x00000007U)
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_TPTC_B0_PEND_RESETVAL              (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_TPTC_B0_PEND_MAX                   (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_DED_STATUS_REG0_RESETVAL                           (0x00000000U)
+
+/* DED_ENABLE_SET_REG0 */
+
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_MSS_L2SLV0_ENABLE_SET_MASK     (0x00000001U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_MSS_L2SLV0_ENABLE_SET_SHIFT    (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_MSS_L2SLV0_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_MSS_L2SLV0_ENABLE_SET_MAX      (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_MSS_L2SLV1_ENABLE_SET_MASK     (0x00000002U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_MSS_L2SLV1_ENABLE_SET_SHIFT    (0x00000001U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_MSS_L2SLV1_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_MSS_L2SLV1_ENABLE_SET_MAX      (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_MSS_MBOX_ENABLE_SET_MASK       (0x00000004U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_MSS_MBOX_ENABLE_SET_SHIFT      (0x00000002U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_MSS_MBOX_ENABLE_SET_RESETVAL   (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_MSS_MBOX_ENABLE_SET_MAX        (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_MSS_RETRAM_ENABLE_SET_MASK     (0x00000008U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_MSS_RETRAM_ENABLE_SET_SHIFT    (0x00000003U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_MSS_RETRAM_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_MSS_RETRAM_ENABLE_SET_MAX      (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_GPADC_ENABLE_SET_MASK          (0x00000010U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_GPADC_ENABLE_SET_SHIFT         (0x00000004U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_GPADC_ENABLE_SET_RESETVAL      (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_GPADC_ENABLE_SET_MAX           (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_TPTC_A0_ENABLE_SET_MASK        (0x00000020U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_TPTC_A0_ENABLE_SET_SHIFT       (0x00000005U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_TPTC_A0_ENABLE_SET_RESETVAL    (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_TPTC_A0_ENABLE_SET_MAX         (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_TPTC_A1_ENABLE_SET_MASK        (0x00000040U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_TPTC_A1_ENABLE_SET_SHIFT       (0x00000006U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_TPTC_A1_ENABLE_SET_RESETVAL    (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_TPTC_A1_ENABLE_SET_MAX         (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_TPTC_B0_ENABLE_SET_MASK        (0x00000080U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_TPTC_B0_ENABLE_SET_SHIFT       (0x00000007U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_TPTC_B0_ENABLE_SET_RESETVAL    (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_TPTC_B0_ENABLE_SET_MAX         (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_SET_REG0_RESETVAL                       (0x00000000U)
+
+/* DED_ENABLE_CLR_REG0 */
+
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_MSS_L2SLV0_ENABLE_CLR_MASK     (0x00000001U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_MSS_L2SLV0_ENABLE_CLR_SHIFT    (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_MSS_L2SLV0_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_MSS_L2SLV0_ENABLE_CLR_MAX      (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_MSS_L2SLV1_ENABLE_CLR_MASK     (0x00000002U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_MSS_L2SLV1_ENABLE_CLR_SHIFT    (0x00000001U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_MSS_L2SLV1_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_MSS_L2SLV1_ENABLE_CLR_MAX      (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_MSS_MBOX_ENABLE_CLR_MASK       (0x00000004U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_MSS_MBOX_ENABLE_CLR_SHIFT      (0x00000002U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_MSS_MBOX_ENABLE_CLR_RESETVAL   (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_MSS_MBOX_ENABLE_CLR_MAX        (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_MSS_RETRAM_ENABLE_CLR_MASK     (0x00000008U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_MSS_RETRAM_ENABLE_CLR_SHIFT    (0x00000003U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_MSS_RETRAM_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_MSS_RETRAM_ENABLE_CLR_MAX      (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_GPADC_ENABLE_CLR_MASK          (0x00000010U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_GPADC_ENABLE_CLR_SHIFT         (0x00000004U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_GPADC_ENABLE_CLR_RESETVAL      (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_GPADC_ENABLE_CLR_MAX           (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_TPTC_A0_ENABLE_CLR_MASK        (0x00000020U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_TPTC_A0_ENABLE_CLR_SHIFT       (0x00000005U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_TPTC_A0_ENABLE_CLR_RESETVAL    (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_TPTC_A0_ENABLE_CLR_MAX         (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_TPTC_A1_ENABLE_CLR_MASK        (0x00000040U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_TPTC_A1_ENABLE_CLR_SHIFT       (0x00000006U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_TPTC_A1_ENABLE_CLR_RESETVAL    (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_TPTC_A1_ENABLE_CLR_MAX         (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_TPTC_B0_ENABLE_CLR_MASK        (0x00000080U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_TPTC_B0_ENABLE_CLR_SHIFT       (0x00000007U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_TPTC_B0_ENABLE_CLR_RESETVAL    (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_TPTC_B0_ENABLE_CLR_MAX         (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_DED_ENABLE_CLR_REG0_RESETVAL                       (0x00000000U)
+
+/* AGGR_ENABLE_SET */
+
+#define SDL_MSS_ECC_AGG_MSS_AGGR_ENABLE_SET_PARITY_MASK                        (0x00000001U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_ENABLE_SET_PARITY_SHIFT                       (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_ENABLE_SET_PARITY_RESETVAL                    (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_ENABLE_SET_PARITY_MAX                         (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_AGGR_ENABLE_SET_TIMEOUT_MASK                       (0x00000002U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_ENABLE_SET_TIMEOUT_SHIFT                      (0x00000001U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_ENABLE_SET_TIMEOUT_RESETVAL                   (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_ENABLE_SET_TIMEOUT_MAX                        (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_AGGR_ENABLE_SET_RESETVAL                           (0x00000000U)
+
+/* AGGR_ENABLE_CLR */
+
+#define SDL_MSS_ECC_AGG_MSS_AGGR_ENABLE_CLR_PARITY_MASK                        (0x00000001U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_ENABLE_CLR_PARITY_SHIFT                       (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_ENABLE_CLR_PARITY_RESETVAL                    (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_ENABLE_CLR_PARITY_MAX                         (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_AGGR_ENABLE_CLR_TIMEOUT_MASK                       (0x00000002U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_ENABLE_CLR_TIMEOUT_SHIFT                      (0x00000001U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_ENABLE_CLR_TIMEOUT_RESETVAL                   (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_ENABLE_CLR_TIMEOUT_MAX                        (0x00000001U)
+
+#define SDL_MSS_ECC_AGG_MSS_AGGR_ENABLE_CLR_RESETVAL                           (0x00000000U)
+
+/* AGGR_STATUS_SET */
+
+#define SDL_MSS_ECC_AGG_MSS_AGGR_STATUS_SET_PARITY_MASK                        (0x00000003U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_STATUS_SET_PARITY_SHIFT                       (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_STATUS_SET_PARITY_RESETVAL                    (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_STATUS_SET_PARITY_MAX                         (0x00000003U)
+
+#define SDL_MSS_ECC_AGG_MSS_AGGR_STATUS_SET_TIMEOUT_MASK                       (0x0000000CU)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_STATUS_SET_TIMEOUT_SHIFT                      (0x00000002U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_STATUS_SET_TIMEOUT_RESETVAL                   (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_STATUS_SET_TIMEOUT_MAX                        (0x00000003U)
+
+#define SDL_MSS_ECC_AGG_MSS_AGGR_STATUS_SET_RESETVAL                           (0x00000000U)
+
+/* AGGR_STATUS_CLR */
+
+#define SDL_MSS_ECC_AGG_MSS_AGGR_STATUS_CLR_PARITY_MASK                        (0x00000003U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_STATUS_CLR_PARITY_SHIFT                       (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_STATUS_CLR_PARITY_RESETVAL                    (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_STATUS_CLR_PARITY_MAX                         (0x00000003U)
+
+#define SDL_MSS_ECC_AGG_MSS_AGGR_STATUS_CLR_TIMEOUT_MASK                       (0x0000000CU)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_STATUS_CLR_TIMEOUT_SHIFT                      (0x00000002U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_STATUS_CLR_TIMEOUT_RESETVAL                   (0x00000000U)
+#define SDL_MSS_ECC_AGG_MSS_AGGR_STATUS_CLR_TIMEOUT_MAX                        (0x00000003U)
+
+#define SDL_MSS_ECC_AGG_MSS_AGGR_STATUS_CLR_RESETVAL                           (0x00000000U)
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/source/sdl/include/awr294x/sdlr_mss_ecc_agga.h b/source/sdl/include/awr294x/sdlr_mss_ecc_agga.h
new file mode 100644
index 0000000000..2d2d247c97
--- /dev/null
+++ b/source/sdl/include/awr294x/sdlr_mss_ecc_agga.h
@@ -0,0 +1,1328 @@
+/********************************************************************
+ * Copyright (C) 2023 Texas Instruments Incorporated.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  Name        : sdlr_mss_ecc_agga.h
+*/
+#ifndef SDLR_MSS_ECC_AGGA_H_
+#define SDLR_MSS_ECC_AGGA_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**************************************************************************
+* Hardware Region  :
+**************************************************************************/
+
+
+/**************************************************************************
+* Register Overlay Structure
+**************************************************************************/
+
+typedef struct {
+    volatile uint32_t AGGR_REVISION;
+    volatile uint8_t  Resv_8[4];
+    volatile uint32_t ECC_VECTOR;
+    volatile uint32_t MISC_STATUS;
+    volatile uint32_t ECC_WRAP_REVISION;
+    volatile uint32_t CONTROL;
+    volatile uint32_t ERROR_CTRL1;
+    volatile uint32_t ERROR_CTRL2;
+    volatile uint32_t ERROR_STATUS1;
+    volatile uint32_t ERROR_STATUS2;
+    volatile uint32_t ERROR_STATUS3;
+    volatile uint8_t  Resv_60[16];
+    volatile uint32_t SEC_EOI_REG;
+    volatile uint32_t SEC_STATUS_REG0;
+    volatile uint8_t  Resv_128[60];
+    volatile uint32_t SEC_ENABLE_SET_REG0;
+    volatile uint8_t  Resv_192[60];
+    volatile uint32_t SEC_ENABLE_CLR_REG0;
+    volatile uint8_t  Resv_316[120];
+    volatile uint32_t DED_EOI_REG;
+    volatile uint32_t DED_STATUS_REG0;
+    volatile uint8_t  Resv_384[60];
+    volatile uint32_t DED_ENABLE_SET_REG0;
+    volatile uint8_t  Resv_448[60];
+    volatile uint32_t DED_ENABLE_CLR_REG0;
+    volatile uint8_t  Resv_512[60];
+    volatile uint32_t AGGR_ENABLE_SET;
+    volatile uint32_t AGGR_ENABLE_CLR;
+    volatile uint32_t AGGR_STATUS_SET;
+    volatile uint32_t AGGR_STATUS_CLR;
+} SDL_mss_ecc_aggaRegs;
+
+
+/**************************************************************************
+* Register Macros
+**************************************************************************/
+
+#define SDL_MSS_ECC_AGGA_AGGR_REVISION                                         (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ECC_VECTOR                                            (0x00000008U)
+#define SDL_MSS_ECC_AGGA_MISC_STATUS                                           (0x0000000CU)
+#define SDL_MSS_ECC_AGGA_ECC_WRAP_REVISION                                     (0x00000010U)
+#define SDL_MSS_ECC_AGGA_CONTROL                                               (0x00000014U)
+#define SDL_MSS_ECC_AGGA_ERROR_CTRL1                                           (0x00000018U)
+#define SDL_MSS_ECC_AGGA_ERROR_CTRL2                                           (0x0000001CU)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1                                         (0x00000020U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS2                                         (0x00000024U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS3                                         (0x00000028U)
+#define SDL_MSS_ECC_AGGA_SEC_EOI_REG                                           (0x0000003CU)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0                                       (0x00000040U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0                                   (0x00000080U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0                                   (0x000000C0U)
+#define SDL_MSS_ECC_AGGA_DED_EOI_REG                                           (0x0000013CU)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0                                       (0x00000140U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0                                   (0x00000180U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0                                   (0x000001C0U)
+#define SDL_MSS_ECC_AGGA_AGGR_ENABLE_SET                                       (0x00000200U)
+#define SDL_MSS_ECC_AGGA_AGGR_ENABLE_CLR                                       (0x00000204U)
+#define SDL_MSS_ECC_AGGA_AGGR_STATUS_SET                                       (0x00000208U)
+#define SDL_MSS_ECC_AGGA_AGGR_STATUS_CLR                                       (0x0000020CU)
+
+/**************************************************************************
+* Field Definition Macros
+**************************************************************************/
+
+
+/* AGGR_REVISION */
+
+#define SDL_MSS_ECC_AGGA_AGGR_REVISION_SCHEME_MASK                             (0xC0000000U)
+#define SDL_MSS_ECC_AGGA_AGGR_REVISION_SCHEME_SHIFT                            (0x0000001EU)
+#define SDL_MSS_ECC_AGGA_AGGR_REVISION_SCHEME_RESETVAL                         (0x00000001U)
+#define SDL_MSS_ECC_AGGA_AGGR_REVISION_SCHEME_MAX                              (0x00000003U)
+
+#define SDL_MSS_ECC_AGGA_AGGR_REVISION_BU_MASK                                 (0x30000000U)
+#define SDL_MSS_ECC_AGGA_AGGR_REVISION_BU_SHIFT                                (0x0000001CU)
+#define SDL_MSS_ECC_AGGA_AGGR_REVISION_BU_RESETVAL                             (0x00000002U)
+#define SDL_MSS_ECC_AGGA_AGGR_REVISION_BU_MAX                                  (0x00000003U)
+
+#define SDL_MSS_ECC_AGGA_AGGR_REVISION_MODULE_ID_MASK                          (0x0FFF0000U)
+#define SDL_MSS_ECC_AGGA_AGGR_REVISION_MODULE_ID_SHIFT                         (0x00000010U)
+#define SDL_MSS_ECC_AGGA_AGGR_REVISION_MODULE_ID_RESETVAL                      (0x000006A0U)
+#define SDL_MSS_ECC_AGGA_AGGR_REVISION_MODULE_ID_MAX                           (0x00000FFFU)
+
+#define SDL_MSS_ECC_AGGA_AGGR_REVISION_REVRTL_MASK                             (0x0000F800U)
+#define SDL_MSS_ECC_AGGA_AGGR_REVISION_REVRTL_SHIFT                            (0x0000000BU)
+#define SDL_MSS_ECC_AGGA_AGGR_REVISION_REVRTL_RESETVAL                         (0x00000018U)
+#define SDL_MSS_ECC_AGGA_AGGR_REVISION_REVRTL_MAX                              (0x0000001FU)
+
+#define SDL_MSS_ECC_AGGA_AGGR_REVISION_REVMAJ_MASK                             (0x00000700U)
+#define SDL_MSS_ECC_AGGA_AGGR_REVISION_REVMAJ_SHIFT                            (0x00000008U)
+#define SDL_MSS_ECC_AGGA_AGGR_REVISION_REVMAJ_RESETVAL                         (0x00000002U)
+#define SDL_MSS_ECC_AGGA_AGGR_REVISION_REVMAJ_MAX                              (0x00000007U)
+
+#define SDL_MSS_ECC_AGGA_AGGR_REVISION_CUSTOM_MASK                             (0x000000C0U)
+#define SDL_MSS_ECC_AGGA_AGGR_REVISION_CUSTOM_SHIFT                            (0x00000006U)
+#define SDL_MSS_ECC_AGGA_AGGR_REVISION_CUSTOM_RESETVAL                         (0x00000000U)
+#define SDL_MSS_ECC_AGGA_AGGR_REVISION_CUSTOM_MAX                              (0x00000003U)
+
+#define SDL_MSS_ECC_AGGA_AGGR_REVISION_REVMIN_MASK                             (0x0000003FU)
+#define SDL_MSS_ECC_AGGA_AGGR_REVISION_REVMIN_SHIFT                            (0x00000000U)
+#define SDL_MSS_ECC_AGGA_AGGR_REVISION_REVMIN_RESETVAL                         (0x00000000U)
+#define SDL_MSS_ECC_AGGA_AGGR_REVISION_REVMIN_MAX                              (0x0000003FU)
+
+#define SDL_MSS_ECC_AGGA_AGGR_REVISION_RESETVAL                                (0x66A0C200U)
+
+/* ECC_VECTOR */
+
+#define SDL_MSS_ECC_AGGA_ECC_VECTOR_ECC_VECTOR_MASK                            (0x000007FFU)
+#define SDL_MSS_ECC_AGGA_ECC_VECTOR_ECC_VECTOR_SHIFT                           (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ECC_VECTOR_ECC_VECTOR_RESETVAL                        (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ECC_VECTOR_ECC_VECTOR_MAX                             (0x000007FFU)
+
+#define SDL_MSS_ECC_AGGA_ECC_VECTOR_RD_SVBUS_MASK                              (0x00008000U)
+#define SDL_MSS_ECC_AGGA_ECC_VECTOR_RD_SVBUS_SHIFT                             (0x0000000FU)
+#define SDL_MSS_ECC_AGGA_ECC_VECTOR_RD_SVBUS_RESETVAL                          (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ECC_VECTOR_RD_SVBUS_MAX                               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_ECC_VECTOR_RD_SVBUS_ADDRESS_MASK                      (0x00FF0000U)
+#define SDL_MSS_ECC_AGGA_ECC_VECTOR_RD_SVBUS_ADDRESS_SHIFT                     (0x00000010U)
+#define SDL_MSS_ECC_AGGA_ECC_VECTOR_RD_SVBUS_ADDRESS_RESETVAL                  (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ECC_VECTOR_RD_SVBUS_ADDRESS_MAX                       (0x000000FFU)
+
+#define SDL_MSS_ECC_AGGA_ECC_VECTOR_RD_SVBUS_DONE_MASK                         (0x01000000U)
+#define SDL_MSS_ECC_AGGA_ECC_VECTOR_RD_SVBUS_DONE_SHIFT                        (0x00000018U)
+#define SDL_MSS_ECC_AGGA_ECC_VECTOR_RD_SVBUS_DONE_RESETVAL                     (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ECC_VECTOR_RD_SVBUS_DONE_MAX                          (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_ECC_VECTOR_RESETVAL                                   (0x00000000U)
+
+/* MISC_STATUS */
+
+#define SDL_MSS_ECC_AGGA_MISC_STATUS_NUM_RAMS_MASK                             (0x000007FFU)
+#define SDL_MSS_ECC_AGGA_MISC_STATUS_NUM_RAMS_SHIFT                            (0x00000000U)
+#define SDL_MSS_ECC_AGGA_MISC_STATUS_NUM_RAMS_RESETVAL                         (0x0000001CU)
+#define SDL_MSS_ECC_AGGA_MISC_STATUS_NUM_RAMS_MAX                              (0x000007FFU)
+
+#define SDL_MSS_ECC_AGGA_MISC_STATUS_RESETVAL                                  (0x0000001CU)
+
+/* ECC_WRAP_REVISION */
+
+#define SDL_MSS_ECC_AGGA_ECC_WRAP_REVISION_SCHEME_MASK                         (0xC0000000U)
+#define SDL_MSS_ECC_AGGA_ECC_WRAP_REVISION_SCHEME_SHIFT                        (0x0000001EU)
+#define SDL_MSS_ECC_AGGA_ECC_WRAP_REVISION_SCHEME_RESETVAL                     (0x00000001U)
+#define SDL_MSS_ECC_AGGA_ECC_WRAP_REVISION_SCHEME_MAX                          (0x00000003U)
+
+#define SDL_MSS_ECC_AGGA_ECC_WRAP_REVISION_BU_MASK                             (0x30000000U)
+#define SDL_MSS_ECC_AGGA_ECC_WRAP_REVISION_BU_SHIFT                            (0x0000001CU)
+#define SDL_MSS_ECC_AGGA_ECC_WRAP_REVISION_BU_RESETVAL                         (0x00000002U)
+#define SDL_MSS_ECC_AGGA_ECC_WRAP_REVISION_BU_MAX                              (0x00000003U)
+
+#define SDL_MSS_ECC_AGGA_ECC_WRAP_REVISION_MODULE_ID_MASK                      (0x0FFF0000U)
+#define SDL_MSS_ECC_AGGA_ECC_WRAP_REVISION_MODULE_ID_SHIFT                     (0x00000010U)
+#define SDL_MSS_ECC_AGGA_ECC_WRAP_REVISION_MODULE_ID_RESETVAL                  (0x000006A4U)
+#define SDL_MSS_ECC_AGGA_ECC_WRAP_REVISION_MODULE_ID_MAX                       (0x00000FFFU)
+
+#define SDL_MSS_ECC_AGGA_ECC_WRAP_REVISION_REVRTL_MASK                         (0x0000F800U)
+#define SDL_MSS_ECC_AGGA_ECC_WRAP_REVISION_REVRTL_SHIFT                        (0x0000000BU)
+#define SDL_MSS_ECC_AGGA_ECC_WRAP_REVISION_REVRTL_RESETVAL                     (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ECC_WRAP_REVISION_REVRTL_MAX                          (0x0000001FU)
+
+#define SDL_MSS_ECC_AGGA_ECC_WRAP_REVISION_REVMAJ_MASK                         (0x00000700U)
+#define SDL_MSS_ECC_AGGA_ECC_WRAP_REVISION_REVMAJ_SHIFT                        (0x00000008U)
+#define SDL_MSS_ECC_AGGA_ECC_WRAP_REVISION_REVMAJ_RESETVAL                     (0x00000002U)
+#define SDL_MSS_ECC_AGGA_ECC_WRAP_REVISION_REVMAJ_MAX                          (0x00000007U)
+
+#define SDL_MSS_ECC_AGGA_ECC_WRAP_REVISION_CUSTOM_MASK                         (0x000000C0U)
+#define SDL_MSS_ECC_AGGA_ECC_WRAP_REVISION_CUSTOM_SHIFT                        (0x00000006U)
+#define SDL_MSS_ECC_AGGA_ECC_WRAP_REVISION_CUSTOM_RESETVAL                     (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ECC_WRAP_REVISION_CUSTOM_MAX                          (0x00000003U)
+
+#define SDL_MSS_ECC_AGGA_ECC_WRAP_REVISION_REVMIN_MASK                         (0x0000003FU)
+#define SDL_MSS_ECC_AGGA_ECC_WRAP_REVISION_REVMIN_SHIFT                        (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ECC_WRAP_REVISION_REVMIN_RESETVAL                     (0x00000002U)
+#define SDL_MSS_ECC_AGGA_ECC_WRAP_REVISION_REVMIN_MAX                          (0x0000003FU)
+
+#define SDL_MSS_ECC_AGGA_ECC_WRAP_REVISION_RESETVAL                            (0x66A40202U)
+
+/* CONTROL */
+
+#define SDL_MSS_ECC_AGGA_CONTROL_ECC_ENABLE_MASK                               (0x00000001U)
+#define SDL_MSS_ECC_AGGA_CONTROL_ECC_ENABLE_SHIFT                              (0x00000000U)
+#define SDL_MSS_ECC_AGGA_CONTROL_ECC_ENABLE_RESETVAL                           (0x00000001U)
+#define SDL_MSS_ECC_AGGA_CONTROL_ECC_ENABLE_MAX                                (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_CONTROL_ECC_CHECK_MASK                                (0x00000002U)
+#define SDL_MSS_ECC_AGGA_CONTROL_ECC_CHECK_SHIFT                               (0x00000001U)
+#define SDL_MSS_ECC_AGGA_CONTROL_ECC_CHECK_RESETVAL                            (0x00000001U)
+#define SDL_MSS_ECC_AGGA_CONTROL_ECC_CHECK_MAX                                 (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_CONTROL_ENABLE_RMW_MASK                               (0x00000004U)
+#define SDL_MSS_ECC_AGGA_CONTROL_ENABLE_RMW_SHIFT                              (0x00000002U)
+#define SDL_MSS_ECC_AGGA_CONTROL_ENABLE_RMW_RESETVAL                           (0x00000001U)
+#define SDL_MSS_ECC_AGGA_CONTROL_ENABLE_RMW_MAX                                (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_CONTROL_FORCE_SEC_MASK                                (0x00000008U)
+#define SDL_MSS_ECC_AGGA_CONTROL_FORCE_SEC_SHIFT                               (0x00000003U)
+#define SDL_MSS_ECC_AGGA_CONTROL_FORCE_SEC_RESETVAL                            (0x00000000U)
+#define SDL_MSS_ECC_AGGA_CONTROL_FORCE_SEC_MAX                                 (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_CONTROL_FORCE_DED_MASK                                (0x00000010U)
+#define SDL_MSS_ECC_AGGA_CONTROL_FORCE_DED_SHIFT                               (0x00000004U)
+#define SDL_MSS_ECC_AGGA_CONTROL_FORCE_DED_RESETVAL                            (0x00000000U)
+#define SDL_MSS_ECC_AGGA_CONTROL_FORCE_DED_MAX                                 (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_CONTROL_FORCE_N_ROW_MASK                              (0x00000020U)
+#define SDL_MSS_ECC_AGGA_CONTROL_FORCE_N_ROW_SHIFT                             (0x00000005U)
+#define SDL_MSS_ECC_AGGA_CONTROL_FORCE_N_ROW_RESETVAL                          (0x00000000U)
+#define SDL_MSS_ECC_AGGA_CONTROL_FORCE_N_ROW_MAX                               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_CONTROL_ERROR_ONCE_MASK                               (0x00000040U)
+#define SDL_MSS_ECC_AGGA_CONTROL_ERROR_ONCE_SHIFT                              (0x00000006U)
+#define SDL_MSS_ECC_AGGA_CONTROL_ERROR_ONCE_RESETVAL                           (0x00000000U)
+#define SDL_MSS_ECC_AGGA_CONTROL_ERROR_ONCE_MAX                                (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_CONTROL_CHECK_PARITY_MASK                             (0x00000080U)
+#define SDL_MSS_ECC_AGGA_CONTROL_CHECK_PARITY_SHIFT                            (0x00000007U)
+#define SDL_MSS_ECC_AGGA_CONTROL_CHECK_PARITY_RESETVAL                         (0x00000001U)
+#define SDL_MSS_ECC_AGGA_CONTROL_CHECK_PARITY_MAX                              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_CONTROL_CHECK_SVBUS_TIMEOUT_MASK                      (0x00000100U)
+#define SDL_MSS_ECC_AGGA_CONTROL_CHECK_SVBUS_TIMEOUT_SHIFT                     (0x00000008U)
+#define SDL_MSS_ECC_AGGA_CONTROL_CHECK_SVBUS_TIMEOUT_RESETVAL                  (0x00000001U)
+#define SDL_MSS_ECC_AGGA_CONTROL_CHECK_SVBUS_TIMEOUT_MAX                       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_CONTROL_RESETVAL                                      (0x00000187U)
+
+/* ERROR_CTRL1 */
+
+#define SDL_MSS_ECC_AGGA_ERROR_CTRL1_ECC_ROW_MASK                              (0xFFFFFFFFU)
+#define SDL_MSS_ECC_AGGA_ERROR_CTRL1_ECC_ROW_SHIFT                             (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ERROR_CTRL1_ECC_ROW_RESETVAL                          (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ERROR_CTRL1_ECC_ROW_MAX                               (0xFFFFFFFFU)
+
+#define SDL_MSS_ECC_AGGA_ERROR_CTRL1_RESETVAL                                  (0x00000000U)
+
+/* ERROR_CTRL2 */
+
+#define SDL_MSS_ECC_AGGA_ERROR_CTRL2_ECC_BIT1_MASK                             (0x0000FFFFU)
+#define SDL_MSS_ECC_AGGA_ERROR_CTRL2_ECC_BIT1_SHIFT                            (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ERROR_CTRL2_ECC_BIT1_RESETVAL                         (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ERROR_CTRL2_ECC_BIT1_MAX                              (0x0000FFFFU)
+
+#define SDL_MSS_ECC_AGGA_ERROR_CTRL2_ECC_BIT2_MASK                             (0xFFFF0000U)
+#define SDL_MSS_ECC_AGGA_ERROR_CTRL2_ECC_BIT2_SHIFT                            (0x00000010U)
+#define SDL_MSS_ECC_AGGA_ERROR_CTRL2_ECC_BIT2_RESETVAL                         (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ERROR_CTRL2_ECC_BIT2_MAX                              (0x0000FFFFU)
+
+#define SDL_MSS_ECC_AGGA_ERROR_CTRL2_RESETVAL                                  (0x00000000U)
+
+/* ERROR_STATUS1 */
+
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_ECC_SEC_MASK                            (0x00000003U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_ECC_SEC_SHIFT                           (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_ECC_SEC_RESETVAL                        (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_ECC_SEC_MAX                             (0x00000003U)
+
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_ECC_DED_MASK                            (0x0000000CU)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_ECC_DED_SHIFT                           (0x00000002U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_ECC_DED_RESETVAL                        (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_ECC_DED_MAX                             (0x00000003U)
+
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_ECC_OTHER_MASK                          (0x00000010U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_ECC_OTHER_SHIFT                         (0x00000004U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_ECC_OTHER_RESETVAL                      (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_ECC_OTHER_MAX                           (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_PARITY_ERR_MASK                         (0x00000060U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_PARITY_ERR_SHIFT                        (0x00000005U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_PARITY_ERR_RESETVAL                     (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_PARITY_ERR_MAX                          (0x00000003U)
+
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_CTR_REG_ERR_MASK                        (0x00000080U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_CTR_REG_ERR_SHIFT                       (0x00000007U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_CTR_REG_ERR_RESETVAL                    (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_CTR_REG_ERR_MAX                         (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_CLR_ECC_SEC_MASK                        (0x00000300U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_CLR_ECC_SEC_SHIFT                       (0x00000008U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_CLR_ECC_SEC_RESETVAL                    (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_CLR_ECC_SEC_MAX                         (0x00000003U)
+
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_CLR_ECC_DED_MASK                        (0x00000C00U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_CLR_ECC_DED_SHIFT                       (0x0000000AU)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_CLR_ECC_DED_RESETVAL                    (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_CLR_ECC_DED_MAX                         (0x00000003U)
+
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_CLR_ECC_OTHER_MASK                      (0x00001000U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_CLR_ECC_OTHER_SHIFT                     (0x0000000CU)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_CLR_ECC_OTHER_RESETVAL                  (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_CLR_ECC_OTHER_MAX                       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_CLR_PARITY_ERR_MASK                     (0x00006000U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_CLR_PARITY_ERR_SHIFT                    (0x0000000DU)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_CLR_PARITY_ERR_RESETVAL                 (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_CLR_PARITY_ERR_MAX                      (0x00000003U)
+
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_CLR_CTRL_REG_ERR_MASK                   (0x00008000U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_CLR_CTRL_REG_ERR_SHIFT                  (0x0000000FU)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_CLR_CTRL_REG_ERR_RESETVAL               (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_CLR_CTRL_REG_ERR_MAX                    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_ECC_BIT1_MASK                           (0xFFFF0000U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_ECC_BIT1_SHIFT                          (0x00000010U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_ECC_BIT1_RESETVAL                       (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_ECC_BIT1_MAX                            (0x0000FFFFU)
+
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS1_RESETVAL                                (0x00000000U)
+
+/* ERROR_STATUS2 */
+
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS2_ECC_ROW_MASK                            (0xFFFFFFFFU)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS2_ECC_ROW_SHIFT                           (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS2_ECC_ROW_RESETVAL                        (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS2_ECC_ROW_MAX                             (0xFFFFFFFFU)
+
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS2_RESETVAL                                (0x00000000U)
+
+/* ERROR_STATUS3 */
+
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS3_WB_PEND_MASK                            (0x00000001U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS3_WB_PEND_SHIFT                           (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS3_WB_PEND_RESETVAL                        (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS3_WB_PEND_MAX                             (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS3_SVBUS_TIMEOUT_ERR_MASK                  (0x00000002U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS3_SVBUS_TIMEOUT_ERR_SHIFT                 (0x00000001U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS3_SVBUS_TIMEOUT_ERR_RESETVAL              (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS3_SVBUS_TIMEOUT_ERR_MAX                   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS3_CLR_SVBUS_TIMEOUT_ERR_MASK              (0x00000200U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS3_CLR_SVBUS_TIMEOUT_ERR_SHIFT             (0x00000009U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS3_CLR_SVBUS_TIMEOUT_ERR_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS3_CLR_SVBUS_TIMEOUT_ERR_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_ERROR_STATUS3_RESETVAL                                (0x00000000U)
+
+/* SEC_EOI_REG */
+
+#define SDL_MSS_ECC_AGGA_SEC_EOI_REG_EOI_WR_MASK                               (0x00000001U)
+#define SDL_MSS_ECC_AGGA_SEC_EOI_REG_EOI_WR_SHIFT                              (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_EOI_REG_EOI_WR_RESETVAL                           (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_EOI_REG_EOI_WR_MAX                                (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_EOI_REG_RESETVAL                                  (0x00000000U)
+
+/* SEC_STATUS_REG0 */
+
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_ITAG_RAM0_PEND_MASK              (0x00000001U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_ITAG_RAM0_PEND_SHIFT             (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_ITAG_RAM0_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_ITAG_RAM0_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_ITAG_RAM1_PEND_MASK              (0x00000002U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_ITAG_RAM1_PEND_SHIFT             (0x00000001U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_ITAG_RAM1_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_ITAG_RAM1_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_ITAG_RAM2_PEND_MASK              (0x00000004U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_ITAG_RAM2_PEND_SHIFT             (0x00000002U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_ITAG_RAM2_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_ITAG_RAM2_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_ITAG_RAM3_PEND_MASK              (0x00000008U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_ITAG_RAM3_PEND_SHIFT             (0x00000003U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_ITAG_RAM3_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_ITAG_RAM3_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_IDATA_BANK0_PEND_MASK            (0x00000010U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_IDATA_BANK0_PEND_SHIFT           (0x00000004U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_IDATA_BANK0_PEND_RESETVAL        (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_IDATA_BANK0_PEND_MAX             (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_IDATA_BANK1_PEND_MASK            (0x00000020U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_IDATA_BANK1_PEND_SHIFT           (0x00000005U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_IDATA_BANK1_PEND_RESETVAL        (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_IDATA_BANK1_PEND_MAX             (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_IDATA_BANK2_PEND_MASK            (0x00000040U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_IDATA_BANK2_PEND_SHIFT           (0x00000006U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_IDATA_BANK2_PEND_RESETVAL        (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_IDATA_BANK2_PEND_MAX             (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_IDATA_BANK3_PEND_MASK            (0x00000080U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_IDATA_BANK3_PEND_SHIFT           (0x00000007U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_IDATA_BANK3_PEND_RESETVAL        (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_IDATA_BANK3_PEND_MAX             (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DTAG_RAM0_PEND_MASK              (0x00000100U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DTAG_RAM0_PEND_SHIFT             (0x00000008U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DTAG_RAM0_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DTAG_RAM0_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DTAG_RAM1_PEND_MASK              (0x00000200U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DTAG_RAM1_PEND_SHIFT             (0x00000009U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DTAG_RAM1_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DTAG_RAM1_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DTAG_RAM2_PEND_MASK              (0x00000400U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DTAG_RAM2_PEND_SHIFT             (0x0000000AU)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DTAG_RAM2_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DTAG_RAM2_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DTAG_RAM3_PEND_MASK              (0x00000800U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DTAG_RAM3_PEND_SHIFT             (0x0000000BU)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DTAG_RAM3_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DTAG_RAM3_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDIRTY_RAM_PEND_MASK             (0x00001000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDIRTY_RAM_PEND_SHIFT            (0x0000000CU)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDIRTY_RAM_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDIRTY_RAM_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM0_PEND_MASK             (0x00002000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM0_PEND_SHIFT            (0x0000000DU)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM0_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM0_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM1_PEND_MASK             (0x00004000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM1_PEND_SHIFT            (0x0000000EU)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM1_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM1_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM2_PEND_MASK             (0x00008000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM2_PEND_SHIFT            (0x0000000FU)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM2_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM2_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM3_PEND_MASK             (0x00010000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM3_PEND_SHIFT            (0x00000010U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM3_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM3_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM4_PEND_MASK             (0x00020000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM4_PEND_SHIFT            (0x00000011U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM4_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM4_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM5_PEND_MASK             (0x00040000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM5_PEND_SHIFT            (0x00000012U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM5_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM5_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM6_PEND_MASK             (0x00080000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM6_PEND_SHIFT            (0x00000013U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM6_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM6_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM7_PEND_MASK             (0x00100000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM7_PEND_SHIFT            (0x00000014U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM7_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_DDATA_RAM7_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_ATCM0_BANK0_PEND_MASK                 (0x00200000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_ATCM0_BANK0_PEND_SHIFT                (0x00000015U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_ATCM0_BANK0_PEND_RESETVAL             (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_ATCM0_BANK0_PEND_MAX                  (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_ATCM0_BANK1_PEND_MASK                 (0x00400000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_ATCM0_BANK1_PEND_SHIFT                (0x00000016U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_ATCM0_BANK1_PEND_RESETVAL             (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_ATCM0_BANK1_PEND_MAX                  (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_B0TCM0_BANK0_PEND_MASK                (0x00800000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_B0TCM0_BANK0_PEND_SHIFT               (0x00000017U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_B0TCM0_BANK0_PEND_RESETVAL            (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_B0TCM0_BANK0_PEND_MAX                 (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_B0TCM0_BANK1_PEND_MASK                (0x01000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_B0TCM0_BANK1_PEND_SHIFT               (0x00000018U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_B0TCM0_BANK1_PEND_RESETVAL            (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_B0TCM0_BANK1_PEND_MAX                 (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_B1TCM0_BANK0_PEND_MASK                (0x02000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_B1TCM0_BANK0_PEND_SHIFT               (0x00000019U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_B1TCM0_BANK0_PEND_RESETVAL            (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_B1TCM0_BANK0_PEND_MAX                 (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_B1TCM0_BANK1_PEND_MASK                (0x04000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_B1TCM0_BANK1_PEND_SHIFT               (0x0000001AU)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_B1TCM0_BANK1_PEND_RESETVAL            (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_B1TCM0_BANK1_PEND_MAX                 (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_KS_VIM_RAMECC_PEND_MASK          (0x08000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_KS_VIM_RAMECC_PEND_SHIFT         (0x0000001BU)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_KS_VIM_RAMECC_PEND_RESETVAL      (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_CPU0_KS_VIM_RAMECC_PEND_MAX           (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_STATUS_REG0_RESETVAL                              (0x00000000U)
+
+/* SEC_ENABLE_SET_REG0 */
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_ITAG_RAM0_ENABLE_SET_MASK    (0x00000001U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_ITAG_RAM0_ENABLE_SET_SHIFT   (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_ITAG_RAM0_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_ITAG_RAM0_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_ITAG_RAM1_ENABLE_SET_MASK    (0x00000002U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_ITAG_RAM1_ENABLE_SET_SHIFT   (0x00000001U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_ITAG_RAM1_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_ITAG_RAM1_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_ITAG_RAM2_ENABLE_SET_MASK    (0x00000004U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_ITAG_RAM2_ENABLE_SET_SHIFT   (0x00000002U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_ITAG_RAM2_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_ITAG_RAM2_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_ITAG_RAM3_ENABLE_SET_MASK    (0x00000008U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_ITAG_RAM3_ENABLE_SET_SHIFT   (0x00000003U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_ITAG_RAM3_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_ITAG_RAM3_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_IDATA_BANK0_ENABLE_SET_MASK  (0x00000010U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_IDATA_BANK0_ENABLE_SET_SHIFT (0x00000004U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_IDATA_BANK0_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_IDATA_BANK0_ENABLE_SET_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_IDATA_BANK1_ENABLE_SET_MASK  (0x00000020U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_IDATA_BANK1_ENABLE_SET_SHIFT (0x00000005U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_IDATA_BANK1_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_IDATA_BANK1_ENABLE_SET_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_IDATA_BANK2_ENABLE_SET_MASK  (0x00000040U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_IDATA_BANK2_ENABLE_SET_SHIFT (0x00000006U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_IDATA_BANK2_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_IDATA_BANK2_ENABLE_SET_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_IDATA_BANK3_ENABLE_SET_MASK  (0x00000080U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_IDATA_BANK3_ENABLE_SET_SHIFT (0x00000007U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_IDATA_BANK3_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_IDATA_BANK3_ENABLE_SET_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DTAG_RAM0_ENABLE_SET_MASK    (0x00000100U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DTAG_RAM0_ENABLE_SET_SHIFT   (0x00000008U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DTAG_RAM0_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DTAG_RAM0_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DTAG_RAM1_ENABLE_SET_MASK    (0x00000200U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DTAG_RAM1_ENABLE_SET_SHIFT   (0x00000009U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DTAG_RAM1_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DTAG_RAM1_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DTAG_RAM2_ENABLE_SET_MASK    (0x00000400U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DTAG_RAM2_ENABLE_SET_SHIFT   (0x0000000AU)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DTAG_RAM2_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DTAG_RAM2_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DTAG_RAM3_ENABLE_SET_MASK    (0x00000800U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DTAG_RAM3_ENABLE_SET_SHIFT   (0x0000000BU)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DTAG_RAM3_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DTAG_RAM3_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDIRTY_RAM_ENABLE_SET_MASK   (0x00001000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDIRTY_RAM_ENABLE_SET_SHIFT  (0x0000000CU)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDIRTY_RAM_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDIRTY_RAM_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM0_ENABLE_SET_MASK   (0x00002000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM0_ENABLE_SET_SHIFT  (0x0000000DU)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM0_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM0_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM1_ENABLE_SET_MASK   (0x00004000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM1_ENABLE_SET_SHIFT  (0x0000000EU)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM1_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM1_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM2_ENABLE_SET_MASK   (0x00008000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM2_ENABLE_SET_SHIFT  (0x0000000FU)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM2_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM2_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM3_ENABLE_SET_MASK   (0x00010000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM3_ENABLE_SET_SHIFT  (0x00000010U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM3_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM3_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM4_ENABLE_SET_MASK   (0x00020000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM4_ENABLE_SET_SHIFT  (0x00000011U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM4_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM4_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM5_ENABLE_SET_MASK   (0x00040000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM5_ENABLE_SET_SHIFT  (0x00000012U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM5_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM5_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM6_ENABLE_SET_MASK   (0x00080000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM6_ENABLE_SET_SHIFT  (0x00000013U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM6_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM6_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM7_ENABLE_SET_MASK   (0x00100000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM7_ENABLE_SET_SHIFT  (0x00000014U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM7_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_DDATA_RAM7_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_ATCM0_BANK0_ENABLE_SET_MASK       (0x00200000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_ATCM0_BANK0_ENABLE_SET_SHIFT      (0x00000015U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_ATCM0_BANK0_ENABLE_SET_RESETVAL   (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_ATCM0_BANK0_ENABLE_SET_MAX        (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_ATCM0_BANK1_ENABLE_SET_MASK       (0x00400000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_ATCM0_BANK1_ENABLE_SET_SHIFT      (0x00000016U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_ATCM0_BANK1_ENABLE_SET_RESETVAL   (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_ATCM0_BANK1_ENABLE_SET_MAX        (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_B0TCM0_BANK0_ENABLE_SET_MASK      (0x00800000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_B0TCM0_BANK0_ENABLE_SET_SHIFT     (0x00000017U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_B0TCM0_BANK0_ENABLE_SET_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_B0TCM0_BANK0_ENABLE_SET_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_B0TCM0_BANK1_ENABLE_SET_MASK      (0x01000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_B0TCM0_BANK1_ENABLE_SET_SHIFT     (0x00000018U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_B0TCM0_BANK1_ENABLE_SET_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_B0TCM0_BANK1_ENABLE_SET_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_B1TCM0_BANK0_ENABLE_SET_MASK      (0x02000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_B1TCM0_BANK0_ENABLE_SET_SHIFT     (0x00000019U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_B1TCM0_BANK0_ENABLE_SET_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_B1TCM0_BANK0_ENABLE_SET_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_B1TCM0_BANK1_ENABLE_SET_MASK      (0x04000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_B1TCM0_BANK1_ENABLE_SET_SHIFT     (0x0000001AU)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_B1TCM0_BANK1_ENABLE_SET_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_B1TCM0_BANK1_ENABLE_SET_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_KS_VIM_RAMECC_ENABLE_SET_MASK (0x08000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_KS_VIM_RAMECC_ENABLE_SET_SHIFT (0x0000001BU)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_KS_VIM_RAMECC_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_CPU0_KS_VIM_RAMECC_ENABLE_SET_MAX (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_SET_REG0_RESETVAL                          (0x00000000U)
+
+/* SEC_ENABLE_CLR_REG0 */
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_ITAG_RAM0_ENABLE_CLR_MASK    (0x00000001U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_ITAG_RAM0_ENABLE_CLR_SHIFT   (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_ITAG_RAM0_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_ITAG_RAM0_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_ITAG_RAM1_ENABLE_CLR_MASK    (0x00000002U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_ITAG_RAM1_ENABLE_CLR_SHIFT   (0x00000001U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_ITAG_RAM1_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_ITAG_RAM1_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_ITAG_RAM2_ENABLE_CLR_MASK    (0x00000004U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_ITAG_RAM2_ENABLE_CLR_SHIFT   (0x00000002U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_ITAG_RAM2_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_ITAG_RAM2_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_ITAG_RAM3_ENABLE_CLR_MASK    (0x00000008U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_ITAG_RAM3_ENABLE_CLR_SHIFT   (0x00000003U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_ITAG_RAM3_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_ITAG_RAM3_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_IDATA_BANK0_ENABLE_CLR_MASK  (0x00000010U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_IDATA_BANK0_ENABLE_CLR_SHIFT (0x00000004U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_IDATA_BANK0_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_IDATA_BANK0_ENABLE_CLR_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_IDATA_BANK1_ENABLE_CLR_MASK  (0x00000020U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_IDATA_BANK1_ENABLE_CLR_SHIFT (0x00000005U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_IDATA_BANK1_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_IDATA_BANK1_ENABLE_CLR_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_IDATA_BANK2_ENABLE_CLR_MASK  (0x00000040U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_IDATA_BANK2_ENABLE_CLR_SHIFT (0x00000006U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_IDATA_BANK2_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_IDATA_BANK2_ENABLE_CLR_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_IDATA_BANK3_ENABLE_CLR_MASK  (0x00000080U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_IDATA_BANK3_ENABLE_CLR_SHIFT (0x00000007U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_IDATA_BANK3_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_IDATA_BANK3_ENABLE_CLR_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DTAG_RAM0_ENABLE_CLR_MASK    (0x00000100U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DTAG_RAM0_ENABLE_CLR_SHIFT   (0x00000008U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DTAG_RAM0_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DTAG_RAM0_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DTAG_RAM1_ENABLE_CLR_MASK    (0x00000200U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DTAG_RAM1_ENABLE_CLR_SHIFT   (0x00000009U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DTAG_RAM1_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DTAG_RAM1_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DTAG_RAM2_ENABLE_CLR_MASK    (0x00000400U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DTAG_RAM2_ENABLE_CLR_SHIFT   (0x0000000AU)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DTAG_RAM2_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DTAG_RAM2_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DTAG_RAM3_ENABLE_CLR_MASK    (0x00000800U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DTAG_RAM3_ENABLE_CLR_SHIFT   (0x0000000BU)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DTAG_RAM3_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DTAG_RAM3_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDIRTY_RAM_ENABLE_CLR_MASK   (0x00001000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDIRTY_RAM_ENABLE_CLR_SHIFT  (0x0000000CU)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDIRTY_RAM_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDIRTY_RAM_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM0_ENABLE_CLR_MASK   (0x00002000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM0_ENABLE_CLR_SHIFT  (0x0000000DU)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM0_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM0_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM1_ENABLE_CLR_MASK   (0x00004000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM1_ENABLE_CLR_SHIFT  (0x0000000EU)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM1_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM1_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM2_ENABLE_CLR_MASK   (0x00008000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM2_ENABLE_CLR_SHIFT  (0x0000000FU)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM2_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM2_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM3_ENABLE_CLR_MASK   (0x00010000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM3_ENABLE_CLR_SHIFT  (0x00000010U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM3_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM3_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM4_ENABLE_CLR_MASK   (0x00020000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM4_ENABLE_CLR_SHIFT  (0x00000011U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM4_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM4_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM5_ENABLE_CLR_MASK   (0x00040000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM5_ENABLE_CLR_SHIFT  (0x00000012U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM5_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM5_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM6_ENABLE_CLR_MASK   (0x00080000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM6_ENABLE_CLR_SHIFT  (0x00000013U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM6_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM6_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM7_ENABLE_CLR_MASK   (0x00100000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM7_ENABLE_CLR_SHIFT  (0x00000014U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM7_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_DDATA_RAM7_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_ATCM0_BANK0_ENABLE_CLR_MASK       (0x00200000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_ATCM0_BANK0_ENABLE_CLR_SHIFT      (0x00000015U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_ATCM0_BANK0_ENABLE_CLR_RESETVAL   (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_ATCM0_BANK0_ENABLE_CLR_MAX        (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_ATCM0_BANK1_ENABLE_CLR_MASK       (0x00400000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_ATCM0_BANK1_ENABLE_CLR_SHIFT      (0x00000016U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_ATCM0_BANK1_ENABLE_CLR_RESETVAL   (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_ATCM0_BANK1_ENABLE_CLR_MAX        (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_B0TCM0_BANK0_ENABLE_CLR_MASK      (0x00800000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_B0TCM0_BANK0_ENABLE_CLR_SHIFT     (0x00000017U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_B0TCM0_BANK0_ENABLE_CLR_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_B0TCM0_BANK0_ENABLE_CLR_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_B0TCM0_BANK1_ENABLE_CLR_MASK      (0x01000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_B0TCM0_BANK1_ENABLE_CLR_SHIFT     (0x00000018U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_B0TCM0_BANK1_ENABLE_CLR_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_B0TCM0_BANK1_ENABLE_CLR_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_B1TCM0_BANK0_ENABLE_CLR_MASK      (0x02000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_B1TCM0_BANK0_ENABLE_CLR_SHIFT     (0x00000019U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_B1TCM0_BANK0_ENABLE_CLR_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_B1TCM0_BANK0_ENABLE_CLR_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_B1TCM0_BANK1_ENABLE_CLR_MASK      (0x04000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_B1TCM0_BANK1_ENABLE_CLR_SHIFT     (0x0000001AU)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_B1TCM0_BANK1_ENABLE_CLR_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_B1TCM0_BANK1_ENABLE_CLR_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_KS_VIM_RAMECC_ENABLE_CLR_MASK (0x08000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_KS_VIM_RAMECC_ENABLE_CLR_SHIFT (0x0000001BU)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_KS_VIM_RAMECC_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_CPU0_KS_VIM_RAMECC_ENABLE_CLR_MAX (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_SEC_ENABLE_CLR_REG0_RESETVAL                          (0x00000000U)
+
+/* DED_EOI_REG */
+
+#define SDL_MSS_ECC_AGGA_DED_EOI_REG_EOI_WR_MASK                               (0x00000001U)
+#define SDL_MSS_ECC_AGGA_DED_EOI_REG_EOI_WR_SHIFT                              (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_EOI_REG_EOI_WR_RESETVAL                           (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_EOI_REG_EOI_WR_MAX                                (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_EOI_REG_RESETVAL                                  (0x00000000U)
+
+/* DED_STATUS_REG0 */
+
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_ITAG_RAM0_PEND_MASK              (0x00000001U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_ITAG_RAM0_PEND_SHIFT             (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_ITAG_RAM0_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_ITAG_RAM0_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_ITAG_RAM1_PEND_MASK              (0x00000002U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_ITAG_RAM1_PEND_SHIFT             (0x00000001U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_ITAG_RAM1_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_ITAG_RAM1_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_ITAG_RAM2_PEND_MASK              (0x00000004U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_ITAG_RAM2_PEND_SHIFT             (0x00000002U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_ITAG_RAM2_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_ITAG_RAM2_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_ITAG_RAM3_PEND_MASK              (0x00000008U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_ITAG_RAM3_PEND_SHIFT             (0x00000003U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_ITAG_RAM3_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_ITAG_RAM3_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_IDATA_BANK0_PEND_MASK            (0x00000010U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_IDATA_BANK0_PEND_SHIFT           (0x00000004U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_IDATA_BANK0_PEND_RESETVAL        (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_IDATA_BANK0_PEND_MAX             (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_IDATA_BANK1_PEND_MASK            (0x00000020U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_IDATA_BANK1_PEND_SHIFT           (0x00000005U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_IDATA_BANK1_PEND_RESETVAL        (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_IDATA_BANK1_PEND_MAX             (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_IDATA_BANK2_PEND_MASK            (0x00000040U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_IDATA_BANK2_PEND_SHIFT           (0x00000006U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_IDATA_BANK2_PEND_RESETVAL        (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_IDATA_BANK2_PEND_MAX             (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_IDATA_BANK3_PEND_MASK            (0x00000080U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_IDATA_BANK3_PEND_SHIFT           (0x00000007U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_IDATA_BANK3_PEND_RESETVAL        (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_IDATA_BANK3_PEND_MAX             (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DTAG_RAM0_PEND_MASK              (0x00000100U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DTAG_RAM0_PEND_SHIFT             (0x00000008U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DTAG_RAM0_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DTAG_RAM0_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DTAG_RAM1_PEND_MASK              (0x00000200U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DTAG_RAM1_PEND_SHIFT             (0x00000009U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DTAG_RAM1_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DTAG_RAM1_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DTAG_RAM2_PEND_MASK              (0x00000400U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DTAG_RAM2_PEND_SHIFT             (0x0000000AU)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DTAG_RAM2_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DTAG_RAM2_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DTAG_RAM3_PEND_MASK              (0x00000800U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DTAG_RAM3_PEND_SHIFT             (0x0000000BU)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DTAG_RAM3_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DTAG_RAM3_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDIRTY_RAM_PEND_MASK             (0x00001000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDIRTY_RAM_PEND_SHIFT            (0x0000000CU)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDIRTY_RAM_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDIRTY_RAM_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM0_PEND_MASK             (0x00002000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM0_PEND_SHIFT            (0x0000000DU)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM0_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM0_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM1_PEND_MASK             (0x00004000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM1_PEND_SHIFT            (0x0000000EU)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM1_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM1_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM2_PEND_MASK             (0x00008000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM2_PEND_SHIFT            (0x0000000FU)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM2_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM2_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM3_PEND_MASK             (0x00010000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM3_PEND_SHIFT            (0x00000010U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM3_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM3_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM4_PEND_MASK             (0x00020000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM4_PEND_SHIFT            (0x00000011U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM4_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM4_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM5_PEND_MASK             (0x00040000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM5_PEND_SHIFT            (0x00000012U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM5_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM5_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM6_PEND_MASK             (0x00080000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM6_PEND_SHIFT            (0x00000013U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM6_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM6_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM7_PEND_MASK             (0x00100000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM7_PEND_SHIFT            (0x00000014U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM7_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_DDATA_RAM7_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_ATCM0_BANK0_PEND_MASK                 (0x00200000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_ATCM0_BANK0_PEND_SHIFT                (0x00000015U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_ATCM0_BANK0_PEND_RESETVAL             (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_ATCM0_BANK0_PEND_MAX                  (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_ATCM0_BANK1_PEND_MASK                 (0x00400000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_ATCM0_BANK1_PEND_SHIFT                (0x00000016U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_ATCM0_BANK1_PEND_RESETVAL             (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_ATCM0_BANK1_PEND_MAX                  (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_B0TCM0_BANK0_PEND_MASK                (0x00800000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_B0TCM0_BANK0_PEND_SHIFT               (0x00000017U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_B0TCM0_BANK0_PEND_RESETVAL            (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_B0TCM0_BANK0_PEND_MAX                 (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_B0TCM0_BANK1_PEND_MASK                (0x01000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_B0TCM0_BANK1_PEND_SHIFT               (0x00000018U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_B0TCM0_BANK1_PEND_RESETVAL            (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_B0TCM0_BANK1_PEND_MAX                 (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_B1TCM0_BANK0_PEND_MASK                (0x02000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_B1TCM0_BANK0_PEND_SHIFT               (0x00000019U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_B1TCM0_BANK0_PEND_RESETVAL            (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_B1TCM0_BANK0_PEND_MAX                 (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_B1TCM0_BANK1_PEND_MASK                (0x04000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_B1TCM0_BANK1_PEND_SHIFT               (0x0000001AU)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_B1TCM0_BANK1_PEND_RESETVAL            (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_B1TCM0_BANK1_PEND_MAX                 (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_KS_VIM_RAMECC_PEND_MASK          (0x08000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_KS_VIM_RAMECC_PEND_SHIFT         (0x0000001BU)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_KS_VIM_RAMECC_PEND_RESETVAL      (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_CPU0_KS_VIM_RAMECC_PEND_MAX           (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_STATUS_REG0_RESETVAL                              (0x00000000U)
+
+/* DED_ENABLE_SET_REG0 */
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_ITAG_RAM0_ENABLE_SET_MASK    (0x00000001U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_ITAG_RAM0_ENABLE_SET_SHIFT   (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_ITAG_RAM0_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_ITAG_RAM0_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_ITAG_RAM1_ENABLE_SET_MASK    (0x00000002U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_ITAG_RAM1_ENABLE_SET_SHIFT   (0x00000001U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_ITAG_RAM1_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_ITAG_RAM1_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_ITAG_RAM2_ENABLE_SET_MASK    (0x00000004U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_ITAG_RAM2_ENABLE_SET_SHIFT   (0x00000002U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_ITAG_RAM2_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_ITAG_RAM2_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_ITAG_RAM3_ENABLE_SET_MASK    (0x00000008U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_ITAG_RAM3_ENABLE_SET_SHIFT   (0x00000003U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_ITAG_RAM3_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_ITAG_RAM3_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_IDATA_BANK0_ENABLE_SET_MASK  (0x00000010U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_IDATA_BANK0_ENABLE_SET_SHIFT (0x00000004U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_IDATA_BANK0_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_IDATA_BANK0_ENABLE_SET_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_IDATA_BANK1_ENABLE_SET_MASK  (0x00000020U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_IDATA_BANK1_ENABLE_SET_SHIFT (0x00000005U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_IDATA_BANK1_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_IDATA_BANK1_ENABLE_SET_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_IDATA_BANK2_ENABLE_SET_MASK  (0x00000040U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_IDATA_BANK2_ENABLE_SET_SHIFT (0x00000006U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_IDATA_BANK2_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_IDATA_BANK2_ENABLE_SET_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_IDATA_BANK3_ENABLE_SET_MASK  (0x00000080U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_IDATA_BANK3_ENABLE_SET_SHIFT (0x00000007U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_IDATA_BANK3_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_IDATA_BANK3_ENABLE_SET_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DTAG_RAM0_ENABLE_SET_MASK    (0x00000100U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DTAG_RAM0_ENABLE_SET_SHIFT   (0x00000008U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DTAG_RAM0_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DTAG_RAM0_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DTAG_RAM1_ENABLE_SET_MASK    (0x00000200U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DTAG_RAM1_ENABLE_SET_SHIFT   (0x00000009U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DTAG_RAM1_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DTAG_RAM1_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DTAG_RAM2_ENABLE_SET_MASK    (0x00000400U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DTAG_RAM2_ENABLE_SET_SHIFT   (0x0000000AU)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DTAG_RAM2_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DTAG_RAM2_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DTAG_RAM3_ENABLE_SET_MASK    (0x00000800U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DTAG_RAM3_ENABLE_SET_SHIFT   (0x0000000BU)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DTAG_RAM3_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DTAG_RAM3_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDIRTY_RAM_ENABLE_SET_MASK   (0x00001000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDIRTY_RAM_ENABLE_SET_SHIFT  (0x0000000CU)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDIRTY_RAM_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDIRTY_RAM_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM0_ENABLE_SET_MASK   (0x00002000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM0_ENABLE_SET_SHIFT  (0x0000000DU)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM0_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM0_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM1_ENABLE_SET_MASK   (0x00004000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM1_ENABLE_SET_SHIFT  (0x0000000EU)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM1_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM1_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM2_ENABLE_SET_MASK   (0x00008000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM2_ENABLE_SET_SHIFT  (0x0000000FU)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM2_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM2_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM3_ENABLE_SET_MASK   (0x00010000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM3_ENABLE_SET_SHIFT  (0x00000010U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM3_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM3_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM4_ENABLE_SET_MASK   (0x00020000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM4_ENABLE_SET_SHIFT  (0x00000011U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM4_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM4_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM5_ENABLE_SET_MASK   (0x00040000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM5_ENABLE_SET_SHIFT  (0x00000012U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM5_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM5_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM6_ENABLE_SET_MASK   (0x00080000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM6_ENABLE_SET_SHIFT  (0x00000013U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM6_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM6_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM7_ENABLE_SET_MASK   (0x00100000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM7_ENABLE_SET_SHIFT  (0x00000014U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM7_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_DDATA_RAM7_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_ATCM0_BANK0_ENABLE_SET_MASK       (0x00200000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_ATCM0_BANK0_ENABLE_SET_SHIFT      (0x00000015U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_ATCM0_BANK0_ENABLE_SET_RESETVAL   (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_ATCM0_BANK0_ENABLE_SET_MAX        (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_ATCM0_BANK1_ENABLE_SET_MASK       (0x00400000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_ATCM0_BANK1_ENABLE_SET_SHIFT      (0x00000016U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_ATCM0_BANK1_ENABLE_SET_RESETVAL   (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_ATCM0_BANK1_ENABLE_SET_MAX        (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_B0TCM0_BANK0_ENABLE_SET_MASK      (0x00800000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_B0TCM0_BANK0_ENABLE_SET_SHIFT     (0x00000017U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_B0TCM0_BANK0_ENABLE_SET_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_B0TCM0_BANK0_ENABLE_SET_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_B0TCM0_BANK1_ENABLE_SET_MASK      (0x01000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_B0TCM0_BANK1_ENABLE_SET_SHIFT     (0x00000018U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_B0TCM0_BANK1_ENABLE_SET_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_B0TCM0_BANK1_ENABLE_SET_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_B1TCM0_BANK0_ENABLE_SET_MASK      (0x02000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_B1TCM0_BANK0_ENABLE_SET_SHIFT     (0x00000019U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_B1TCM0_BANK0_ENABLE_SET_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_B1TCM0_BANK0_ENABLE_SET_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_B1TCM0_BANK1_ENABLE_SET_MASK      (0x04000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_B1TCM0_BANK1_ENABLE_SET_SHIFT     (0x0000001AU)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_B1TCM0_BANK1_ENABLE_SET_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_B1TCM0_BANK1_ENABLE_SET_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_KS_VIM_RAMECC_ENABLE_SET_MASK (0x08000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_KS_VIM_RAMECC_ENABLE_SET_SHIFT (0x0000001BU)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_KS_VIM_RAMECC_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_CPU0_KS_VIM_RAMECC_ENABLE_SET_MAX (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_SET_REG0_RESETVAL                          (0x00000000U)
+
+/* DED_ENABLE_CLR_REG0 */
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_ITAG_RAM0_ENABLE_CLR_MASK    (0x00000001U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_ITAG_RAM0_ENABLE_CLR_SHIFT   (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_ITAG_RAM0_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_ITAG_RAM0_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_ITAG_RAM1_ENABLE_CLR_MASK    (0x00000002U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_ITAG_RAM1_ENABLE_CLR_SHIFT   (0x00000001U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_ITAG_RAM1_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_ITAG_RAM1_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_ITAG_RAM2_ENABLE_CLR_MASK    (0x00000004U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_ITAG_RAM2_ENABLE_CLR_SHIFT   (0x00000002U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_ITAG_RAM2_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_ITAG_RAM2_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_ITAG_RAM3_ENABLE_CLR_MASK    (0x00000008U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_ITAG_RAM3_ENABLE_CLR_SHIFT   (0x00000003U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_ITAG_RAM3_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_ITAG_RAM3_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_IDATA_BANK0_ENABLE_CLR_MASK  (0x00000010U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_IDATA_BANK0_ENABLE_CLR_SHIFT (0x00000004U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_IDATA_BANK0_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_IDATA_BANK0_ENABLE_CLR_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_IDATA_BANK1_ENABLE_CLR_MASK  (0x00000020U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_IDATA_BANK1_ENABLE_CLR_SHIFT (0x00000005U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_IDATA_BANK1_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_IDATA_BANK1_ENABLE_CLR_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_IDATA_BANK2_ENABLE_CLR_MASK  (0x00000040U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_IDATA_BANK2_ENABLE_CLR_SHIFT (0x00000006U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_IDATA_BANK2_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_IDATA_BANK2_ENABLE_CLR_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_IDATA_BANK3_ENABLE_CLR_MASK  (0x00000080U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_IDATA_BANK3_ENABLE_CLR_SHIFT (0x00000007U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_IDATA_BANK3_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_IDATA_BANK3_ENABLE_CLR_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DTAG_RAM0_ENABLE_CLR_MASK    (0x00000100U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DTAG_RAM0_ENABLE_CLR_SHIFT   (0x00000008U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DTAG_RAM0_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DTAG_RAM0_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DTAG_RAM1_ENABLE_CLR_MASK    (0x00000200U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DTAG_RAM1_ENABLE_CLR_SHIFT   (0x00000009U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DTAG_RAM1_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DTAG_RAM1_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DTAG_RAM2_ENABLE_CLR_MASK    (0x00000400U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DTAG_RAM2_ENABLE_CLR_SHIFT   (0x0000000AU)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DTAG_RAM2_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DTAG_RAM2_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DTAG_RAM3_ENABLE_CLR_MASK    (0x00000800U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DTAG_RAM3_ENABLE_CLR_SHIFT   (0x0000000BU)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DTAG_RAM3_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DTAG_RAM3_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDIRTY_RAM_ENABLE_CLR_MASK   (0x00001000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDIRTY_RAM_ENABLE_CLR_SHIFT  (0x0000000CU)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDIRTY_RAM_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDIRTY_RAM_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM0_ENABLE_CLR_MASK   (0x00002000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM0_ENABLE_CLR_SHIFT  (0x0000000DU)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM0_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM0_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM1_ENABLE_CLR_MASK   (0x00004000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM1_ENABLE_CLR_SHIFT  (0x0000000EU)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM1_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM1_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM2_ENABLE_CLR_MASK   (0x00008000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM2_ENABLE_CLR_SHIFT  (0x0000000FU)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM2_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM2_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM3_ENABLE_CLR_MASK   (0x00010000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM3_ENABLE_CLR_SHIFT  (0x00000010U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM3_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM3_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM4_ENABLE_CLR_MASK   (0x00020000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM4_ENABLE_CLR_SHIFT  (0x00000011U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM4_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM4_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM5_ENABLE_CLR_MASK   (0x00040000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM5_ENABLE_CLR_SHIFT  (0x00000012U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM5_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM5_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM6_ENABLE_CLR_MASK   (0x00080000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM6_ENABLE_CLR_SHIFT  (0x00000013U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM6_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM6_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM7_ENABLE_CLR_MASK   (0x00100000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM7_ENABLE_CLR_SHIFT  (0x00000014U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM7_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_DDATA_RAM7_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_ATCM0_BANK0_ENABLE_CLR_MASK       (0x00200000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_ATCM0_BANK0_ENABLE_CLR_SHIFT      (0x00000015U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_ATCM0_BANK0_ENABLE_CLR_RESETVAL   (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_ATCM0_BANK0_ENABLE_CLR_MAX        (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_ATCM0_BANK1_ENABLE_CLR_MASK       (0x00400000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_ATCM0_BANK1_ENABLE_CLR_SHIFT      (0x00000016U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_ATCM0_BANK1_ENABLE_CLR_RESETVAL   (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_ATCM0_BANK1_ENABLE_CLR_MAX        (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_B0TCM0_BANK0_ENABLE_CLR_MASK      (0x00800000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_B0TCM0_BANK0_ENABLE_CLR_SHIFT     (0x00000017U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_B0TCM0_BANK0_ENABLE_CLR_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_B0TCM0_BANK0_ENABLE_CLR_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_B0TCM0_BANK1_ENABLE_CLR_MASK      (0x01000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_B0TCM0_BANK1_ENABLE_CLR_SHIFT     (0x00000018U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_B0TCM0_BANK1_ENABLE_CLR_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_B0TCM0_BANK1_ENABLE_CLR_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_B1TCM0_BANK0_ENABLE_CLR_MASK      (0x02000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_B1TCM0_BANK0_ENABLE_CLR_SHIFT     (0x00000019U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_B1TCM0_BANK0_ENABLE_CLR_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_B1TCM0_BANK0_ENABLE_CLR_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_B1TCM0_BANK1_ENABLE_CLR_MASK      (0x04000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_B1TCM0_BANK1_ENABLE_CLR_SHIFT     (0x0000001AU)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_B1TCM0_BANK1_ENABLE_CLR_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_B1TCM0_BANK1_ENABLE_CLR_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_KS_VIM_RAMECC_ENABLE_CLR_MASK (0x08000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_KS_VIM_RAMECC_ENABLE_CLR_SHIFT (0x0000001BU)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_KS_VIM_RAMECC_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_CPU0_KS_VIM_RAMECC_ENABLE_CLR_MAX (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_DED_ENABLE_CLR_REG0_RESETVAL                          (0x00000000U)
+
+/* AGGR_ENABLE_SET */
+
+#define SDL_MSS_ECC_AGGA_AGGR_ENABLE_SET_PARITY_MASK                           (0x00000001U)
+#define SDL_MSS_ECC_AGGA_AGGR_ENABLE_SET_PARITY_SHIFT                          (0x00000000U)
+#define SDL_MSS_ECC_AGGA_AGGR_ENABLE_SET_PARITY_RESETVAL                       (0x00000000U)
+#define SDL_MSS_ECC_AGGA_AGGR_ENABLE_SET_PARITY_MAX                            (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_AGGR_ENABLE_SET_TIMEOUT_MASK                          (0x00000002U)
+#define SDL_MSS_ECC_AGGA_AGGR_ENABLE_SET_TIMEOUT_SHIFT                         (0x00000001U)
+#define SDL_MSS_ECC_AGGA_AGGR_ENABLE_SET_TIMEOUT_RESETVAL                      (0x00000000U)
+#define SDL_MSS_ECC_AGGA_AGGR_ENABLE_SET_TIMEOUT_MAX                           (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_AGGR_ENABLE_SET_RESETVAL                              (0x00000000U)
+
+/* AGGR_ENABLE_CLR */
+
+#define SDL_MSS_ECC_AGGA_AGGR_ENABLE_CLR_PARITY_MASK                           (0x00000001U)
+#define SDL_MSS_ECC_AGGA_AGGR_ENABLE_CLR_PARITY_SHIFT                          (0x00000000U)
+#define SDL_MSS_ECC_AGGA_AGGR_ENABLE_CLR_PARITY_RESETVAL                       (0x00000000U)
+#define SDL_MSS_ECC_AGGA_AGGR_ENABLE_CLR_PARITY_MAX                            (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_AGGR_ENABLE_CLR_TIMEOUT_MASK                          (0x00000002U)
+#define SDL_MSS_ECC_AGGA_AGGR_ENABLE_CLR_TIMEOUT_SHIFT                         (0x00000001U)
+#define SDL_MSS_ECC_AGGA_AGGR_ENABLE_CLR_TIMEOUT_RESETVAL                      (0x00000000U)
+#define SDL_MSS_ECC_AGGA_AGGR_ENABLE_CLR_TIMEOUT_MAX                           (0x00000001U)
+
+#define SDL_MSS_ECC_AGGA_AGGR_ENABLE_CLR_RESETVAL                              (0x00000000U)
+
+/* AGGR_STATUS_SET */
+
+#define SDL_MSS_ECC_AGGA_AGGR_STATUS_SET_PARITY_MASK                           (0x00000003U)
+#define SDL_MSS_ECC_AGGA_AGGR_STATUS_SET_PARITY_SHIFT                          (0x00000000U)
+#define SDL_MSS_ECC_AGGA_AGGR_STATUS_SET_PARITY_RESETVAL                       (0x00000000U)
+#define SDL_MSS_ECC_AGGA_AGGR_STATUS_SET_PARITY_MAX                            (0x00000003U)
+
+#define SDL_MSS_ECC_AGGA_AGGR_STATUS_SET_TIMEOUT_MASK                          (0x0000000CU)
+#define SDL_MSS_ECC_AGGA_AGGR_STATUS_SET_TIMEOUT_SHIFT                         (0x00000002U)
+#define SDL_MSS_ECC_AGGA_AGGR_STATUS_SET_TIMEOUT_RESETVAL                      (0x00000000U)
+#define SDL_MSS_ECC_AGGA_AGGR_STATUS_SET_TIMEOUT_MAX                           (0x00000003U)
+
+#define SDL_MSS_ECC_AGGA_AGGR_STATUS_SET_RESETVAL                              (0x00000000U)
+
+/* AGGR_STATUS_CLR */
+
+#define SDL_MSS_ECC_AGGA_AGGR_STATUS_CLR_PARITY_MASK                           (0x00000003U)
+#define SDL_MSS_ECC_AGGA_AGGR_STATUS_CLR_PARITY_SHIFT                          (0x00000000U)
+#define SDL_MSS_ECC_AGGA_AGGR_STATUS_CLR_PARITY_RESETVAL                       (0x00000000U)
+#define SDL_MSS_ECC_AGGA_AGGR_STATUS_CLR_PARITY_MAX                            (0x00000003U)
+
+#define SDL_MSS_ECC_AGGA_AGGR_STATUS_CLR_TIMEOUT_MASK                          (0x0000000CU)
+#define SDL_MSS_ECC_AGGA_AGGR_STATUS_CLR_TIMEOUT_SHIFT                         (0x00000002U)
+#define SDL_MSS_ECC_AGGA_AGGR_STATUS_CLR_TIMEOUT_RESETVAL                      (0x00000000U)
+#define SDL_MSS_ECC_AGGA_AGGR_STATUS_CLR_TIMEOUT_MAX                           (0x00000003U)
+
+#define SDL_MSS_ECC_AGGA_AGGR_STATUS_CLR_RESETVAL                              (0x00000000U)
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/source/sdl/include/awr294x/sdlr_mss_ecc_aggb.h b/source/sdl/include/awr294x/sdlr_mss_ecc_aggb.h
new file mode 100644
index 0000000000..950e11940b
--- /dev/null
+++ b/source/sdl/include/awr294x/sdlr_mss_ecc_aggb.h
@@ -0,0 +1,1328 @@
+/********************************************************************
+ * Copyright (C) 2021 Texas Instruments Incorporated.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  Name        : sdlr_mss_ecc_aggb.h
+*/
+#ifndef SDLR_MSS_ECC_AGGB_H_
+#define SDLR_MSS_ECC_AGGB_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**************************************************************************
+* Hardware Region  :
+**************************************************************************/
+
+
+/**************************************************************************
+* Register Overlay Structure
+**************************************************************************/
+
+typedef struct {
+    volatile uint32_t AGGR_REVISION;
+    volatile uint8_t  Resv_8[4];
+    volatile uint32_t ECC_VECTOR;
+    volatile uint32_t MISC_STATUS;
+    volatile uint32_t ECC_WRAP_REVISION;
+    volatile uint32_t CONTROL;
+    volatile uint32_t ERROR_CTRL1;
+    volatile uint32_t ERROR_CTRL2;
+    volatile uint32_t ERROR_STATUS1;
+    volatile uint32_t ERROR_STATUS2;
+    volatile uint32_t ERROR_STATUS3;
+    volatile uint8_t  Resv_60[16];
+    volatile uint32_t SEC_EOI_REG;
+    volatile uint32_t SEC_STATUS_REG0;
+    volatile uint8_t  Resv_128[60];
+    volatile uint32_t SEC_ENABLE_SET_REG0;
+    volatile uint8_t  Resv_192[60];
+    volatile uint32_t SEC_ENABLE_CLR_REG0;
+    volatile uint8_t  Resv_316[120];
+    volatile uint32_t DED_EOI_REG;
+    volatile uint32_t DED_STATUS_REG0;
+    volatile uint8_t  Resv_384[60];
+    volatile uint32_t DED_ENABLE_SET_REG0;
+    volatile uint8_t  Resv_448[60];
+    volatile uint32_t DED_ENABLE_CLR_REG0;
+    volatile uint8_t  Resv_512[60];
+    volatile uint32_t AGGR_ENABLE_SET;
+    volatile uint32_t AGGR_ENABLE_CLR;
+    volatile uint32_t AGGR_STATUS_SET;
+    volatile uint32_t AGGR_STATUS_CLR;
+} SDL_mss_ecc_aggbRegs;
+
+
+/**************************************************************************
+* Register Macros
+**************************************************************************/
+
+#define SDL_MSS_ECC_AGGB_AGGR_REVISION                                         (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ECC_VECTOR                                            (0x00000008U)
+#define SDL_MSS_ECC_AGGB_MISC_STATUS                                           (0x0000000CU)
+#define SDL_MSS_ECC_AGGB_ECC_WRAP_REVISION                                     (0x00000010U)
+#define SDL_MSS_ECC_AGGB_CONTROL                                               (0x00000014U)
+#define SDL_MSS_ECC_AGGB_ERROR_CTRL1                                           (0x00000018U)
+#define SDL_MSS_ECC_AGGB_ERROR_CTRL2                                           (0x0000001CU)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1                                         (0x00000020U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS2                                         (0x00000024U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS3                                         (0x00000028U)
+#define SDL_MSS_ECC_AGGB_SEC_EOI_REG                                           (0x0000003CU)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0                                       (0x00000040U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0                                   (0x00000080U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0                                   (0x000000C0U)
+#define SDL_MSS_ECC_AGGB_DED_EOI_REG                                           (0x0000013CU)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0                                       (0x00000140U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0                                   (0x00000180U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0                                   (0x000001C0U)
+#define SDL_MSS_ECC_AGGB_AGGR_ENABLE_SET                                       (0x00000200U)
+#define SDL_MSS_ECC_AGGB_AGGR_ENABLE_CLR                                       (0x00000204U)
+#define SDL_MSS_ECC_AGGB_AGGR_STATUS_SET                                       (0x00000208U)
+#define SDL_MSS_ECC_AGGB_AGGR_STATUS_CLR                                       (0x0000020CU)
+
+/**************************************************************************
+* Field Definition Macros
+**************************************************************************/
+
+
+/* AGGR_REVISION */
+
+#define SDL_MSS_ECC_AGGB_AGGR_REVISION_SCHEME_MASK                             (0xC0000000U)
+#define SDL_MSS_ECC_AGGB_AGGR_REVISION_SCHEME_SHIFT                            (0x0000001EU)
+#define SDL_MSS_ECC_AGGB_AGGR_REVISION_SCHEME_RESETVAL                         (0x00000001U)
+#define SDL_MSS_ECC_AGGB_AGGR_REVISION_SCHEME_MAX                              (0x00000003U)
+
+#define SDL_MSS_ECC_AGGB_AGGR_REVISION_BU_MASK                                 (0x30000000U)
+#define SDL_MSS_ECC_AGGB_AGGR_REVISION_BU_SHIFT                                (0x0000001CU)
+#define SDL_MSS_ECC_AGGB_AGGR_REVISION_BU_RESETVAL                             (0x00000002U)
+#define SDL_MSS_ECC_AGGB_AGGR_REVISION_BU_MAX                                  (0x00000003U)
+
+#define SDL_MSS_ECC_AGGB_AGGR_REVISION_MODULE_ID_MASK                          (0x0FFF0000U)
+#define SDL_MSS_ECC_AGGB_AGGR_REVISION_MODULE_ID_SHIFT                         (0x00000010U)
+#define SDL_MSS_ECC_AGGB_AGGR_REVISION_MODULE_ID_RESETVAL                      (0x000006A0U)
+#define SDL_MSS_ECC_AGGB_AGGR_REVISION_MODULE_ID_MAX                           (0x00000FFFU)
+
+#define SDL_MSS_ECC_AGGB_AGGR_REVISION_REVRTL_MASK                             (0x0000F800U)
+#define SDL_MSS_ECC_AGGB_AGGR_REVISION_REVRTL_SHIFT                            (0x0000000BU)
+#define SDL_MSS_ECC_AGGB_AGGR_REVISION_REVRTL_RESETVAL                         (0x00000018U)
+#define SDL_MSS_ECC_AGGB_AGGR_REVISION_REVRTL_MAX                              (0x0000001FU)
+
+#define SDL_MSS_ECC_AGGB_AGGR_REVISION_REVMAJ_MASK                             (0x00000700U)
+#define SDL_MSS_ECC_AGGB_AGGR_REVISION_REVMAJ_SHIFT                            (0x00000008U)
+#define SDL_MSS_ECC_AGGB_AGGR_REVISION_REVMAJ_RESETVAL                         (0x00000002U)
+#define SDL_MSS_ECC_AGGB_AGGR_REVISION_REVMAJ_MAX                              (0x00000007U)
+
+#define SDL_MSS_ECC_AGGB_AGGR_REVISION_CUSTOM_MASK                             (0x000000C0U)
+#define SDL_MSS_ECC_AGGB_AGGR_REVISION_CUSTOM_SHIFT                            (0x00000006U)
+#define SDL_MSS_ECC_AGGB_AGGR_REVISION_CUSTOM_RESETVAL                         (0x00000000U)
+#define SDL_MSS_ECC_AGGB_AGGR_REVISION_CUSTOM_MAX                              (0x00000003U)
+
+#define SDL_MSS_ECC_AGGB_AGGR_REVISION_REVMIN_MASK                             (0x0000003FU)
+#define SDL_MSS_ECC_AGGB_AGGR_REVISION_REVMIN_SHIFT                            (0x00000000U)
+#define SDL_MSS_ECC_AGGB_AGGR_REVISION_REVMIN_RESETVAL                         (0x00000000U)
+#define SDL_MSS_ECC_AGGB_AGGR_REVISION_REVMIN_MAX                              (0x0000003FU)
+
+#define SDL_MSS_ECC_AGGB_AGGR_REVISION_RESETVAL                                (0x66A0C200U)
+
+/* ECC_VECTOR */
+
+#define SDL_MSS_ECC_AGGB_ECC_VECTOR_ECC_VECTOR_MASK                            (0x000007FFU)
+#define SDL_MSS_ECC_AGGB_ECC_VECTOR_ECC_VECTOR_SHIFT                           (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ECC_VECTOR_ECC_VECTOR_RESETVAL                        (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ECC_VECTOR_ECC_VECTOR_MAX                             (0x000007FFU)
+
+#define SDL_MSS_ECC_AGGB_ECC_VECTOR_RD_SVBUS_MASK                              (0x00008000U)
+#define SDL_MSS_ECC_AGGB_ECC_VECTOR_RD_SVBUS_SHIFT                             (0x0000000FU)
+#define SDL_MSS_ECC_AGGB_ECC_VECTOR_RD_SVBUS_RESETVAL                          (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ECC_VECTOR_RD_SVBUS_MAX                               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_ECC_VECTOR_RD_SVBUS_ADDRESS_MASK                      (0x00FF0000U)
+#define SDL_MSS_ECC_AGGB_ECC_VECTOR_RD_SVBUS_ADDRESS_SHIFT                     (0x00000010U)
+#define SDL_MSS_ECC_AGGB_ECC_VECTOR_RD_SVBUS_ADDRESS_RESETVAL                  (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ECC_VECTOR_RD_SVBUS_ADDRESS_MAX                       (0x000000FFU)
+
+#define SDL_MSS_ECC_AGGB_ECC_VECTOR_RD_SVBUS_DONE_MASK                         (0x01000000U)
+#define SDL_MSS_ECC_AGGB_ECC_VECTOR_RD_SVBUS_DONE_SHIFT                        (0x00000018U)
+#define SDL_MSS_ECC_AGGB_ECC_VECTOR_RD_SVBUS_DONE_RESETVAL                     (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ECC_VECTOR_RD_SVBUS_DONE_MAX                          (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_ECC_VECTOR_RESETVAL                                   (0x00000000U)
+
+/* MISC_STATUS */
+
+#define SDL_MSS_ECC_AGGB_MISC_STATUS_NUM_RAMS_MASK                             (0x000007FFU)
+#define SDL_MSS_ECC_AGGB_MISC_STATUS_NUM_RAMS_SHIFT                            (0x00000000U)
+#define SDL_MSS_ECC_AGGB_MISC_STATUS_NUM_RAMS_RESETVAL                         (0x0000001CU)
+#define SDL_MSS_ECC_AGGB_MISC_STATUS_NUM_RAMS_MAX                              (0x000007FFU)
+
+#define SDL_MSS_ECC_AGGB_MISC_STATUS_RESETVAL                                  (0x0000001CU)
+
+/* ECC_WRAP_REVISION */
+
+#define SDL_MSS_ECC_AGGB_ECC_WRAP_REVISION_SCHEME_MASK                         (0xC0000000U)
+#define SDL_MSS_ECC_AGGB_ECC_WRAP_REVISION_SCHEME_SHIFT                        (0x0000001EU)
+#define SDL_MSS_ECC_AGGB_ECC_WRAP_REVISION_SCHEME_RESETVAL                     (0x00000001U)
+#define SDL_MSS_ECC_AGGB_ECC_WRAP_REVISION_SCHEME_MAX                          (0x00000003U)
+
+#define SDL_MSS_ECC_AGGB_ECC_WRAP_REVISION_BU_MASK                             (0x30000000U)
+#define SDL_MSS_ECC_AGGB_ECC_WRAP_REVISION_BU_SHIFT                            (0x0000001CU)
+#define SDL_MSS_ECC_AGGB_ECC_WRAP_REVISION_BU_RESETVAL                         (0x00000002U)
+#define SDL_MSS_ECC_AGGB_ECC_WRAP_REVISION_BU_MAX                              (0x00000003U)
+
+#define SDL_MSS_ECC_AGGB_ECC_WRAP_REVISION_MODULE_ID_MASK                      (0x0FFF0000U)
+#define SDL_MSS_ECC_AGGB_ECC_WRAP_REVISION_MODULE_ID_SHIFT                     (0x00000010U)
+#define SDL_MSS_ECC_AGGB_ECC_WRAP_REVISION_MODULE_ID_RESETVAL                  (0x000006A4U)
+#define SDL_MSS_ECC_AGGB_ECC_WRAP_REVISION_MODULE_ID_MAX                       (0x00000FFFU)
+
+#define SDL_MSS_ECC_AGGB_ECC_WRAP_REVISION_REVRTL_MASK                         (0x0000F800U)
+#define SDL_MSS_ECC_AGGB_ECC_WRAP_REVISION_REVRTL_SHIFT                        (0x0000000BU)
+#define SDL_MSS_ECC_AGGB_ECC_WRAP_REVISION_REVRTL_RESETVAL                     (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ECC_WRAP_REVISION_REVRTL_MAX                          (0x0000001FU)
+
+#define SDL_MSS_ECC_AGGB_ECC_WRAP_REVISION_REVMAJ_MASK                         (0x00000700U)
+#define SDL_MSS_ECC_AGGB_ECC_WRAP_REVISION_REVMAJ_SHIFT                        (0x00000008U)
+#define SDL_MSS_ECC_AGGB_ECC_WRAP_REVISION_REVMAJ_RESETVAL                     (0x00000002U)
+#define SDL_MSS_ECC_AGGB_ECC_WRAP_REVISION_REVMAJ_MAX                          (0x00000007U)
+
+#define SDL_MSS_ECC_AGGB_ECC_WRAP_REVISION_CUSTOM_MASK                         (0x000000C0U)
+#define SDL_MSS_ECC_AGGB_ECC_WRAP_REVISION_CUSTOM_SHIFT                        (0x00000006U)
+#define SDL_MSS_ECC_AGGB_ECC_WRAP_REVISION_CUSTOM_RESETVAL                     (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ECC_WRAP_REVISION_CUSTOM_MAX                          (0x00000003U)
+
+#define SDL_MSS_ECC_AGGB_ECC_WRAP_REVISION_REVMIN_MASK                         (0x0000003FU)
+#define SDL_MSS_ECC_AGGB_ECC_WRAP_REVISION_REVMIN_SHIFT                        (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ECC_WRAP_REVISION_REVMIN_RESETVAL                     (0x00000002U)
+#define SDL_MSS_ECC_AGGB_ECC_WRAP_REVISION_REVMIN_MAX                          (0x0000003FU)
+
+#define SDL_MSS_ECC_AGGB_ECC_WRAP_REVISION_RESETVAL                            (0x66A40202U)
+
+/* CONTROL */
+
+#define SDL_MSS_ECC_AGGB_CONTROL_ECC_ENABLE_MASK                               (0x00000001U)
+#define SDL_MSS_ECC_AGGB_CONTROL_ECC_ENABLE_SHIFT                              (0x00000000U)
+#define SDL_MSS_ECC_AGGB_CONTROL_ECC_ENABLE_RESETVAL                           (0x00000001U)
+#define SDL_MSS_ECC_AGGB_CONTROL_ECC_ENABLE_MAX                                (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_CONTROL_ECC_CHECK_MASK                                (0x00000002U)
+#define SDL_MSS_ECC_AGGB_CONTROL_ECC_CHECK_SHIFT                               (0x00000001U)
+#define SDL_MSS_ECC_AGGB_CONTROL_ECC_CHECK_RESETVAL                            (0x00000001U)
+#define SDL_MSS_ECC_AGGB_CONTROL_ECC_CHECK_MAX                                 (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_CONTROL_ENABLE_RMW_MASK                               (0x00000004U)
+#define SDL_MSS_ECC_AGGB_CONTROL_ENABLE_RMW_SHIFT                              (0x00000002U)
+#define SDL_MSS_ECC_AGGB_CONTROL_ENABLE_RMW_RESETVAL                           (0x00000001U)
+#define SDL_MSS_ECC_AGGB_CONTROL_ENABLE_RMW_MAX                                (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_CONTROL_FORCE_SEC_MASK                                (0x00000008U)
+#define SDL_MSS_ECC_AGGB_CONTROL_FORCE_SEC_SHIFT                               (0x00000003U)
+#define SDL_MSS_ECC_AGGB_CONTROL_FORCE_SEC_RESETVAL                            (0x00000000U)
+#define SDL_MSS_ECC_AGGB_CONTROL_FORCE_SEC_MAX                                 (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_CONTROL_FORCE_DED_MASK                                (0x00000010U)
+#define SDL_MSS_ECC_AGGB_CONTROL_FORCE_DED_SHIFT                               (0x00000004U)
+#define SDL_MSS_ECC_AGGB_CONTROL_FORCE_DED_RESETVAL                            (0x00000000U)
+#define SDL_MSS_ECC_AGGB_CONTROL_FORCE_DED_MAX                                 (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_CONTROL_FORCE_N_ROW_MASK                              (0x00000020U)
+#define SDL_MSS_ECC_AGGB_CONTROL_FORCE_N_ROW_SHIFT                             (0x00000005U)
+#define SDL_MSS_ECC_AGGB_CONTROL_FORCE_N_ROW_RESETVAL                          (0x00000000U)
+#define SDL_MSS_ECC_AGGB_CONTROL_FORCE_N_ROW_MAX                               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_CONTROL_ERROR_ONCE_MASK                               (0x00000040U)
+#define SDL_MSS_ECC_AGGB_CONTROL_ERROR_ONCE_SHIFT                              (0x00000006U)
+#define SDL_MSS_ECC_AGGB_CONTROL_ERROR_ONCE_RESETVAL                           (0x00000000U)
+#define SDL_MSS_ECC_AGGB_CONTROL_ERROR_ONCE_MAX                                (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_CONTROL_CHECK_PARITY_MASK                             (0x00000080U)
+#define SDL_MSS_ECC_AGGB_CONTROL_CHECK_PARITY_SHIFT                            (0x00000007U)
+#define SDL_MSS_ECC_AGGB_CONTROL_CHECK_PARITY_RESETVAL                         (0x00000001U)
+#define SDL_MSS_ECC_AGGB_CONTROL_CHECK_PARITY_MAX                              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_CONTROL_CHECK_SVBUS_TIMEOUT_MASK                      (0x00000100U)
+#define SDL_MSS_ECC_AGGB_CONTROL_CHECK_SVBUS_TIMEOUT_SHIFT                     (0x00000008U)
+#define SDL_MSS_ECC_AGGB_CONTROL_CHECK_SVBUS_TIMEOUT_RESETVAL                  (0x00000001U)
+#define SDL_MSS_ECC_AGGB_CONTROL_CHECK_SVBUS_TIMEOUT_MAX                       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_CONTROL_RESETVAL                                      (0x00000187U)
+
+/* ERROR_CTRL1 */
+
+#define SDL_MSS_ECC_AGGB_ERROR_CTRL1_ECC_ROW_MASK                              (0xFFFFFFFFU)
+#define SDL_MSS_ECC_AGGB_ERROR_CTRL1_ECC_ROW_SHIFT                             (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ERROR_CTRL1_ECC_ROW_RESETVAL                          (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ERROR_CTRL1_ECC_ROW_MAX                               (0xFFFFFFFFU)
+
+#define SDL_MSS_ECC_AGGB_ERROR_CTRL1_RESETVAL                                  (0x00000000U)
+
+/* ERROR_CTRL2 */
+
+#define SDL_MSS_ECC_AGGB_ERROR_CTRL2_ECC_BIT1_MASK                             (0x0000FFFFU)
+#define SDL_MSS_ECC_AGGB_ERROR_CTRL2_ECC_BIT1_SHIFT                            (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ERROR_CTRL2_ECC_BIT1_RESETVAL                         (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ERROR_CTRL2_ECC_BIT1_MAX                              (0x0000FFFFU)
+
+#define SDL_MSS_ECC_AGGB_ERROR_CTRL2_ECC_BIT2_MASK                             (0xFFFF0000U)
+#define SDL_MSS_ECC_AGGB_ERROR_CTRL2_ECC_BIT2_SHIFT                            (0x00000010U)
+#define SDL_MSS_ECC_AGGB_ERROR_CTRL2_ECC_BIT2_RESETVAL                         (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ERROR_CTRL2_ECC_BIT2_MAX                              (0x0000FFFFU)
+
+#define SDL_MSS_ECC_AGGB_ERROR_CTRL2_RESETVAL                                  (0x00000000U)
+
+/* ERROR_STATUS1 */
+
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_ECC_SEC_MASK                            (0x00000003U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_ECC_SEC_SHIFT                           (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_ECC_SEC_RESETVAL                        (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_ECC_SEC_MAX                             (0x00000003U)
+
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_ECC_DED_MASK                            (0x0000000CU)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_ECC_DED_SHIFT                           (0x00000002U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_ECC_DED_RESETVAL                        (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_ECC_DED_MAX                             (0x00000003U)
+
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_ECC_OTHER_MASK                          (0x00000010U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_ECC_OTHER_SHIFT                         (0x00000004U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_ECC_OTHER_RESETVAL                      (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_ECC_OTHER_MAX                           (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_PARITY_ERR_MASK                         (0x00000060U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_PARITY_ERR_SHIFT                        (0x00000005U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_PARITY_ERR_RESETVAL                     (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_PARITY_ERR_MAX                          (0x00000003U)
+
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_CTR_REG_ERR_MASK                        (0x00000080U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_CTR_REG_ERR_SHIFT                       (0x00000007U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_CTR_REG_ERR_RESETVAL                    (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_CTR_REG_ERR_MAX                         (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_CLR_ECC_SEC_MASK                        (0x00000300U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_CLR_ECC_SEC_SHIFT                       (0x00000008U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_CLR_ECC_SEC_RESETVAL                    (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_CLR_ECC_SEC_MAX                         (0x00000003U)
+
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_CLR_ECC_DED_MASK                        (0x00000C00U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_CLR_ECC_DED_SHIFT                       (0x0000000AU)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_CLR_ECC_DED_RESETVAL                    (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_CLR_ECC_DED_MAX                         (0x00000003U)
+
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_CLR_ECC_OTHER_MASK                      (0x00001000U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_CLR_ECC_OTHER_SHIFT                     (0x0000000CU)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_CLR_ECC_OTHER_RESETVAL                  (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_CLR_ECC_OTHER_MAX                       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_CLR_PARITY_ERR_MASK                     (0x00006000U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_CLR_PARITY_ERR_SHIFT                    (0x0000000DU)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_CLR_PARITY_ERR_RESETVAL                 (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_CLR_PARITY_ERR_MAX                      (0x00000003U)
+
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_CLR_CTRL_REG_ERR_MASK                   (0x00008000U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_CLR_CTRL_REG_ERR_SHIFT                  (0x0000000FU)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_CLR_CTRL_REG_ERR_RESETVAL               (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_CLR_CTRL_REG_ERR_MAX                    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_ECC_BIT1_MASK                           (0xFFFF0000U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_ECC_BIT1_SHIFT                          (0x00000010U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_ECC_BIT1_RESETVAL                       (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_ECC_BIT1_MAX                            (0x0000FFFFU)
+
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS1_RESETVAL                                (0x00000000U)
+
+/* ERROR_STATUS2 */
+
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS2_ECC_ROW_MASK                            (0xFFFFFFFFU)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS2_ECC_ROW_SHIFT                           (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS2_ECC_ROW_RESETVAL                        (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS2_ECC_ROW_MAX                             (0xFFFFFFFFU)
+
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS2_RESETVAL                                (0x00000000U)
+
+/* ERROR_STATUS3 */
+
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS3_WB_PEND_MASK                            (0x00000001U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS3_WB_PEND_SHIFT                           (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS3_WB_PEND_RESETVAL                        (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS3_WB_PEND_MAX                             (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS3_SVBUS_TIMEOUT_ERR_MASK                  (0x00000002U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS3_SVBUS_TIMEOUT_ERR_SHIFT                 (0x00000001U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS3_SVBUS_TIMEOUT_ERR_RESETVAL              (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS3_SVBUS_TIMEOUT_ERR_MAX                   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS3_CLR_SVBUS_TIMEOUT_ERR_MASK              (0x00000200U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS3_CLR_SVBUS_TIMEOUT_ERR_SHIFT             (0x00000009U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS3_CLR_SVBUS_TIMEOUT_ERR_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS3_CLR_SVBUS_TIMEOUT_ERR_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_ERROR_STATUS3_RESETVAL                                (0x00000000U)
+
+/* SEC_EOI_REG */
+
+#define SDL_MSS_ECC_AGGB_SEC_EOI_REG_EOI_WR_MASK                               (0x00000001U)
+#define SDL_MSS_ECC_AGGB_SEC_EOI_REG_EOI_WR_SHIFT                              (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_EOI_REG_EOI_WR_RESETVAL                           (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_EOI_REG_EOI_WR_MAX                                (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_EOI_REG_RESETVAL                                  (0x00000000U)
+
+/* SEC_STATUS_REG0 */
+
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_ITAG_RAM0_PEND_MASK              (0x00000001U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_ITAG_RAM0_PEND_SHIFT             (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_ITAG_RAM0_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_ITAG_RAM0_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_ITAG_RAM1_PEND_MASK              (0x00000002U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_ITAG_RAM1_PEND_SHIFT             (0x00000001U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_ITAG_RAM1_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_ITAG_RAM1_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_ITAG_RAM2_PEND_MASK              (0x00000004U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_ITAG_RAM2_PEND_SHIFT             (0x00000002U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_ITAG_RAM2_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_ITAG_RAM2_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_ITAG_RAM3_PEND_MASK              (0x00000008U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_ITAG_RAM3_PEND_SHIFT             (0x00000003U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_ITAG_RAM3_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_ITAG_RAM3_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_IDATA_BANK0_PEND_MASK            (0x00000010U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_IDATA_BANK0_PEND_SHIFT           (0x00000004U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_IDATA_BANK0_PEND_RESETVAL        (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_IDATA_BANK0_PEND_MAX             (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_IDATA_BANK1_PEND_MASK            (0x00000020U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_IDATA_BANK1_PEND_SHIFT           (0x00000005U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_IDATA_BANK1_PEND_RESETVAL        (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_IDATA_BANK1_PEND_MAX             (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_IDATA_BANK2_PEND_MASK            (0x00000040U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_IDATA_BANK2_PEND_SHIFT           (0x00000006U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_IDATA_BANK2_PEND_RESETVAL        (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_IDATA_BANK2_PEND_MAX             (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_IDATA_BANK3_PEND_MASK            (0x00000080U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_IDATA_BANK3_PEND_SHIFT           (0x00000007U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_IDATA_BANK3_PEND_RESETVAL        (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_IDATA_BANK3_PEND_MAX             (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DTAG_RAM0_PEND_MASK              (0x00000100U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DTAG_RAM0_PEND_SHIFT             (0x00000008U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DTAG_RAM0_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DTAG_RAM0_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DTAG_RAM1_PEND_MASK              (0x00000200U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DTAG_RAM1_PEND_SHIFT             (0x00000009U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DTAG_RAM1_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DTAG_RAM1_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DTAG_RAM2_PEND_MASK              (0x00000400U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DTAG_RAM2_PEND_SHIFT             (0x0000000AU)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DTAG_RAM2_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DTAG_RAM2_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DTAG_RAM3_PEND_MASK              (0x00000800U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DTAG_RAM3_PEND_SHIFT             (0x0000000BU)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DTAG_RAM3_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DTAG_RAM3_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDIRTY_RAM_PEND_MASK             (0x00001000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDIRTY_RAM_PEND_SHIFT            (0x0000000CU)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDIRTY_RAM_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDIRTY_RAM_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM0_PEND_MASK             (0x00002000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM0_PEND_SHIFT            (0x0000000DU)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM0_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM0_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM1_PEND_MASK             (0x00004000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM1_PEND_SHIFT            (0x0000000EU)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM1_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM1_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM2_PEND_MASK             (0x00008000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM2_PEND_SHIFT            (0x0000000FU)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM2_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM2_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM3_PEND_MASK             (0x00010000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM3_PEND_SHIFT            (0x00000010U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM3_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM3_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM4_PEND_MASK             (0x00020000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM4_PEND_SHIFT            (0x00000011U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM4_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM4_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM5_PEND_MASK             (0x00040000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM5_PEND_SHIFT            (0x00000012U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM5_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM5_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM6_PEND_MASK             (0x00080000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM6_PEND_SHIFT            (0x00000013U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM6_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM6_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM7_PEND_MASK             (0x00100000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM7_PEND_SHIFT            (0x00000014U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM7_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_DDATA_RAM7_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_ATCM1_BANK0_PEND_MASK                 (0x00200000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_ATCM1_BANK0_PEND_SHIFT                (0x00000015U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_ATCM1_BANK0_PEND_RESETVAL             (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_ATCM1_BANK0_PEND_MAX                  (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_ATCM1_BANK1_PEND_MASK                 (0x00400000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_ATCM1_BANK1_PEND_SHIFT                (0x00000016U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_ATCM1_BANK1_PEND_RESETVAL             (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_ATCM1_BANK1_PEND_MAX                  (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_B0TCM1_BANK0_PEND_MASK                (0x00800000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_B0TCM1_BANK0_PEND_SHIFT               (0x00000017U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_B0TCM1_BANK0_PEND_RESETVAL            (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_B0TCM1_BANK0_PEND_MAX                 (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_B0TCM1_BANK1_PEND_MASK                (0x01000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_B0TCM1_BANK1_PEND_SHIFT               (0x00000018U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_B0TCM1_BANK1_PEND_RESETVAL            (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_B0TCM1_BANK1_PEND_MAX                 (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_B1TCM1_BANK0_PEND_MASK                (0x02000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_B1TCM1_BANK0_PEND_SHIFT               (0x00000019U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_B1TCM1_BANK0_PEND_RESETVAL            (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_B1TCM1_BANK0_PEND_MAX                 (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_B1TCM1_BANK1_PEND_MASK                (0x04000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_B1TCM1_BANK1_PEND_SHIFT               (0x0000001AU)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_B1TCM1_BANK1_PEND_RESETVAL            (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_B1TCM1_BANK1_PEND_MAX                 (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_KS_VIM_RAMECC_PEND_MASK          (0x08000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_KS_VIM_RAMECC_PEND_SHIFT         (0x0000001BU)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_KS_VIM_RAMECC_PEND_RESETVAL      (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_CPU1_KS_VIM_RAMECC_PEND_MAX           (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_STATUS_REG0_RESETVAL                              (0x00000000U)
+
+/* SEC_ENABLE_SET_REG0 */
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_ITAG_RAM0_ENABLE_SET_MASK    (0x00000001U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_ITAG_RAM0_ENABLE_SET_SHIFT   (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_ITAG_RAM0_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_ITAG_RAM0_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_ITAG_RAM1_ENABLE_SET_MASK    (0x00000002U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_ITAG_RAM1_ENABLE_SET_SHIFT   (0x00000001U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_ITAG_RAM1_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_ITAG_RAM1_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_ITAG_RAM2_ENABLE_SET_MASK    (0x00000004U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_ITAG_RAM2_ENABLE_SET_SHIFT   (0x00000002U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_ITAG_RAM2_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_ITAG_RAM2_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_ITAG_RAM3_ENABLE_SET_MASK    (0x00000008U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_ITAG_RAM3_ENABLE_SET_SHIFT   (0x00000003U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_ITAG_RAM3_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_ITAG_RAM3_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_IDATA_BANK0_ENABLE_SET_MASK  (0x00000010U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_IDATA_BANK0_ENABLE_SET_SHIFT (0x00000004U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_IDATA_BANK0_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_IDATA_BANK0_ENABLE_SET_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_IDATA_BANK1_ENABLE_SET_MASK  (0x00000020U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_IDATA_BANK1_ENABLE_SET_SHIFT (0x00000005U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_IDATA_BANK1_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_IDATA_BANK1_ENABLE_SET_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_IDATA_BANK2_ENABLE_SET_MASK  (0x00000040U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_IDATA_BANK2_ENABLE_SET_SHIFT (0x00000006U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_IDATA_BANK2_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_IDATA_BANK2_ENABLE_SET_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_IDATA_BANK3_ENABLE_SET_MASK  (0x00000080U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_IDATA_BANK3_ENABLE_SET_SHIFT (0x00000007U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_IDATA_BANK3_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_IDATA_BANK3_ENABLE_SET_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DTAG_RAM0_ENABLE_SET_MASK    (0x00000100U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DTAG_RAM0_ENABLE_SET_SHIFT   (0x00000008U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DTAG_RAM0_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DTAG_RAM0_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DTAG_RAM1_ENABLE_SET_MASK    (0x00000200U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DTAG_RAM1_ENABLE_SET_SHIFT   (0x00000009U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DTAG_RAM1_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DTAG_RAM1_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DTAG_RAM2_ENABLE_SET_MASK    (0x00000400U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DTAG_RAM2_ENABLE_SET_SHIFT   (0x0000000AU)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DTAG_RAM2_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DTAG_RAM2_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DTAG_RAM3_ENABLE_SET_MASK    (0x00000800U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DTAG_RAM3_ENABLE_SET_SHIFT   (0x0000000BU)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DTAG_RAM3_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DTAG_RAM3_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDIRTY_RAM_ENABLE_SET_MASK   (0x00001000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDIRTY_RAM_ENABLE_SET_SHIFT  (0x0000000CU)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDIRTY_RAM_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDIRTY_RAM_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM0_ENABLE_SET_MASK   (0x00002000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM0_ENABLE_SET_SHIFT  (0x0000000DU)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM0_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM0_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM1_ENABLE_SET_MASK   (0x00004000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM1_ENABLE_SET_SHIFT  (0x0000000EU)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM1_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM1_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM2_ENABLE_SET_MASK   (0x00008000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM2_ENABLE_SET_SHIFT  (0x0000000FU)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM2_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM2_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM3_ENABLE_SET_MASK   (0x00010000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM3_ENABLE_SET_SHIFT  (0x00000010U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM3_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM3_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM4_ENABLE_SET_MASK   (0x00020000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM4_ENABLE_SET_SHIFT  (0x00000011U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM4_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM4_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM5_ENABLE_SET_MASK   (0x00040000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM5_ENABLE_SET_SHIFT  (0x00000012U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM5_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM5_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM6_ENABLE_SET_MASK   (0x00080000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM6_ENABLE_SET_SHIFT  (0x00000013U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM6_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM6_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM7_ENABLE_SET_MASK   (0x00100000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM7_ENABLE_SET_SHIFT  (0x00000014U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM7_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_DDATA_RAM7_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_ATCM1_BANK0_ENABLE_SET_MASK       (0x00200000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_ATCM1_BANK0_ENABLE_SET_SHIFT      (0x00000015U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_ATCM1_BANK0_ENABLE_SET_RESETVAL   (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_ATCM1_BANK0_ENABLE_SET_MAX        (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_ATCM1_BANK1_ENABLE_SET_MASK       (0x00400000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_ATCM1_BANK1_ENABLE_SET_SHIFT      (0x00000016U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_ATCM1_BANK1_ENABLE_SET_RESETVAL   (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_ATCM1_BANK1_ENABLE_SET_MAX        (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_B0TCM1_BANK0_ENABLE_SET_MASK      (0x00800000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_B0TCM1_BANK0_ENABLE_SET_SHIFT     (0x00000017U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_B0TCM1_BANK0_ENABLE_SET_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_B0TCM1_BANK0_ENABLE_SET_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_B0TCM1_BANK1_ENABLE_SET_MASK      (0x01000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_B0TCM1_BANK1_ENABLE_SET_SHIFT     (0x00000018U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_B0TCM1_BANK1_ENABLE_SET_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_B0TCM1_BANK1_ENABLE_SET_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_B1TCM1_BANK0_ENABLE_SET_MASK      (0x02000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_B1TCM1_BANK0_ENABLE_SET_SHIFT     (0x00000019U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_B1TCM1_BANK0_ENABLE_SET_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_B1TCM1_BANK0_ENABLE_SET_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_B1TCM1_BANK1_ENABLE_SET_MASK      (0x04000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_B1TCM1_BANK1_ENABLE_SET_SHIFT     (0x0000001AU)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_B1TCM1_BANK1_ENABLE_SET_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_B1TCM1_BANK1_ENABLE_SET_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_KS_VIM_RAMECC_ENABLE_SET_MASK (0x08000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_KS_VIM_RAMECC_ENABLE_SET_SHIFT (0x0000001BU)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_KS_VIM_RAMECC_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_CPU1_KS_VIM_RAMECC_ENABLE_SET_MAX (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_SET_REG0_RESETVAL                          (0x00000000U)
+
+/* SEC_ENABLE_CLR_REG0 */
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_ITAG_RAM0_ENABLE_CLR_MASK    (0x00000001U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_ITAG_RAM0_ENABLE_CLR_SHIFT   (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_ITAG_RAM0_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_ITAG_RAM0_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_ITAG_RAM1_ENABLE_CLR_MASK    (0x00000002U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_ITAG_RAM1_ENABLE_CLR_SHIFT   (0x00000001U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_ITAG_RAM1_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_ITAG_RAM1_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_ITAG_RAM2_ENABLE_CLR_MASK    (0x00000004U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_ITAG_RAM2_ENABLE_CLR_SHIFT   (0x00000002U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_ITAG_RAM2_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_ITAG_RAM2_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_ITAG_RAM3_ENABLE_CLR_MASK    (0x00000008U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_ITAG_RAM3_ENABLE_CLR_SHIFT   (0x00000003U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_ITAG_RAM3_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_ITAG_RAM3_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_IDATA_BANK0_ENABLE_CLR_MASK  (0x00000010U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_IDATA_BANK0_ENABLE_CLR_SHIFT (0x00000004U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_IDATA_BANK0_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_IDATA_BANK0_ENABLE_CLR_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_IDATA_BANK1_ENABLE_CLR_MASK  (0x00000020U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_IDATA_BANK1_ENABLE_CLR_SHIFT (0x00000005U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_IDATA_BANK1_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_IDATA_BANK1_ENABLE_CLR_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_IDATA_BANK2_ENABLE_CLR_MASK  (0x00000040U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_IDATA_BANK2_ENABLE_CLR_SHIFT (0x00000006U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_IDATA_BANK2_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_IDATA_BANK2_ENABLE_CLR_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_IDATA_BANK3_ENABLE_CLR_MASK  (0x00000080U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_IDATA_BANK3_ENABLE_CLR_SHIFT (0x00000007U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_IDATA_BANK3_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_IDATA_BANK3_ENABLE_CLR_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DTAG_RAM0_ENABLE_CLR_MASK    (0x00000100U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DTAG_RAM0_ENABLE_CLR_SHIFT   (0x00000008U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DTAG_RAM0_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DTAG_RAM0_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DTAG_RAM1_ENABLE_CLR_MASK    (0x00000200U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DTAG_RAM1_ENABLE_CLR_SHIFT   (0x00000009U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DTAG_RAM1_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DTAG_RAM1_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DTAG_RAM2_ENABLE_CLR_MASK    (0x00000400U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DTAG_RAM2_ENABLE_CLR_SHIFT   (0x0000000AU)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DTAG_RAM2_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DTAG_RAM2_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DTAG_RAM3_ENABLE_CLR_MASK    (0x00000800U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DTAG_RAM3_ENABLE_CLR_SHIFT   (0x0000000BU)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DTAG_RAM3_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DTAG_RAM3_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDIRTY_RAM_ENABLE_CLR_MASK   (0x00001000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDIRTY_RAM_ENABLE_CLR_SHIFT  (0x0000000CU)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDIRTY_RAM_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDIRTY_RAM_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM0_ENABLE_CLR_MASK   (0x00002000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM0_ENABLE_CLR_SHIFT  (0x0000000DU)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM0_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM0_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM1_ENABLE_CLR_MASK   (0x00004000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM1_ENABLE_CLR_SHIFT  (0x0000000EU)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM1_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM1_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM2_ENABLE_CLR_MASK   (0x00008000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM2_ENABLE_CLR_SHIFT  (0x0000000FU)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM2_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM2_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM3_ENABLE_CLR_MASK   (0x00010000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM3_ENABLE_CLR_SHIFT  (0x00000010U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM3_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM3_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM4_ENABLE_CLR_MASK   (0x00020000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM4_ENABLE_CLR_SHIFT  (0x00000011U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM4_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM4_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM5_ENABLE_CLR_MASK   (0x00040000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM5_ENABLE_CLR_SHIFT  (0x00000012U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM5_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM5_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM6_ENABLE_CLR_MASK   (0x00080000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM6_ENABLE_CLR_SHIFT  (0x00000013U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM6_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM6_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM7_ENABLE_CLR_MASK   (0x00100000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM7_ENABLE_CLR_SHIFT  (0x00000014U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM7_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_DDATA_RAM7_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_ATCM1_BANK0_ENABLE_CLR_MASK       (0x00200000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_ATCM1_BANK0_ENABLE_CLR_SHIFT      (0x00000015U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_ATCM1_BANK0_ENABLE_CLR_RESETVAL   (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_ATCM1_BANK0_ENABLE_CLR_MAX        (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_ATCM1_BANK1_ENABLE_CLR_MASK       (0x00400000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_ATCM1_BANK1_ENABLE_CLR_SHIFT      (0x00000016U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_ATCM1_BANK1_ENABLE_CLR_RESETVAL   (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_ATCM1_BANK1_ENABLE_CLR_MAX        (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_B0TCM1_BANK0_ENABLE_CLR_MASK      (0x00800000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_B0TCM1_BANK0_ENABLE_CLR_SHIFT     (0x00000017U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_B0TCM1_BANK0_ENABLE_CLR_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_B0TCM1_BANK0_ENABLE_CLR_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_B0TCM1_BANK1_ENABLE_CLR_MASK      (0x01000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_B0TCM1_BANK1_ENABLE_CLR_SHIFT     (0x00000018U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_B0TCM1_BANK1_ENABLE_CLR_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_B0TCM1_BANK1_ENABLE_CLR_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_B1TCM1_BANK0_ENABLE_CLR_MASK      (0x02000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_B1TCM1_BANK0_ENABLE_CLR_SHIFT     (0x00000019U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_B1TCM1_BANK0_ENABLE_CLR_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_B1TCM1_BANK0_ENABLE_CLR_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_B1TCM1_BANK1_ENABLE_CLR_MASK      (0x04000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_B1TCM1_BANK1_ENABLE_CLR_SHIFT     (0x0000001AU)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_B1TCM1_BANK1_ENABLE_CLR_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_B1TCM1_BANK1_ENABLE_CLR_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_KS_VIM_RAMECC_ENABLE_CLR_MASK (0x08000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_KS_VIM_RAMECC_ENABLE_CLR_SHIFT (0x0000001BU)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_KS_VIM_RAMECC_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_CPU1_KS_VIM_RAMECC_ENABLE_CLR_MAX (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_SEC_ENABLE_CLR_REG0_RESETVAL                          (0x00000000U)
+
+/* DED_EOI_REG */
+
+#define SDL_MSS_ECC_AGGB_DED_EOI_REG_EOI_WR_MASK                               (0x00000001U)
+#define SDL_MSS_ECC_AGGB_DED_EOI_REG_EOI_WR_SHIFT                              (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_EOI_REG_EOI_WR_RESETVAL                           (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_EOI_REG_EOI_WR_MAX                                (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_EOI_REG_RESETVAL                                  (0x00000000U)
+
+/* DED_STATUS_REG0 */
+
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_ITAG_RAM0_PEND_MASK              (0x00000001U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_ITAG_RAM0_PEND_SHIFT             (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_ITAG_RAM0_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_ITAG_RAM0_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_ITAG_RAM1_PEND_MASK              (0x00000002U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_ITAG_RAM1_PEND_SHIFT             (0x00000001U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_ITAG_RAM1_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_ITAG_RAM1_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_ITAG_RAM2_PEND_MASK              (0x00000004U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_ITAG_RAM2_PEND_SHIFT             (0x00000002U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_ITAG_RAM2_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_ITAG_RAM2_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_ITAG_RAM3_PEND_MASK              (0x00000008U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_ITAG_RAM3_PEND_SHIFT             (0x00000003U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_ITAG_RAM3_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_ITAG_RAM3_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_IDATA_BANK0_PEND_MASK            (0x00000010U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_IDATA_BANK0_PEND_SHIFT           (0x00000004U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_IDATA_BANK0_PEND_RESETVAL        (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_IDATA_BANK0_PEND_MAX             (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_IDATA_BANK1_PEND_MASK            (0x00000020U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_IDATA_BANK1_PEND_SHIFT           (0x00000005U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_IDATA_BANK1_PEND_RESETVAL        (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_IDATA_BANK1_PEND_MAX             (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_IDATA_BANK2_PEND_MASK            (0x00000040U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_IDATA_BANK2_PEND_SHIFT           (0x00000006U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_IDATA_BANK2_PEND_RESETVAL        (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_IDATA_BANK2_PEND_MAX             (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_IDATA_BANK3_PEND_MASK            (0x00000080U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_IDATA_BANK3_PEND_SHIFT           (0x00000007U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_IDATA_BANK3_PEND_RESETVAL        (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_IDATA_BANK3_PEND_MAX             (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DTAG_RAM0_PEND_MASK              (0x00000100U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DTAG_RAM0_PEND_SHIFT             (0x00000008U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DTAG_RAM0_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DTAG_RAM0_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DTAG_RAM1_PEND_MASK              (0x00000200U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DTAG_RAM1_PEND_SHIFT             (0x00000009U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DTAG_RAM1_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DTAG_RAM1_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DTAG_RAM2_PEND_MASK              (0x00000400U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DTAG_RAM2_PEND_SHIFT             (0x0000000AU)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DTAG_RAM2_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DTAG_RAM2_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DTAG_RAM3_PEND_MASK              (0x00000800U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DTAG_RAM3_PEND_SHIFT             (0x0000000BU)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DTAG_RAM3_PEND_RESETVAL          (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DTAG_RAM3_PEND_MAX               (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDIRTY_RAM_PEND_MASK             (0x00001000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDIRTY_RAM_PEND_SHIFT            (0x0000000CU)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDIRTY_RAM_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDIRTY_RAM_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM0_PEND_MASK             (0x00002000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM0_PEND_SHIFT            (0x0000000DU)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM0_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM0_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM1_PEND_MASK             (0x00004000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM1_PEND_SHIFT            (0x0000000EU)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM1_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM1_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM2_PEND_MASK             (0x00008000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM2_PEND_SHIFT            (0x0000000FU)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM2_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM2_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM3_PEND_MASK             (0x00010000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM3_PEND_SHIFT            (0x00000010U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM3_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM3_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM4_PEND_MASK             (0x00020000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM4_PEND_SHIFT            (0x00000011U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM4_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM4_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM5_PEND_MASK             (0x00040000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM5_PEND_SHIFT            (0x00000012U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM5_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM5_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM6_PEND_MASK             (0x00080000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM6_PEND_SHIFT            (0x00000013U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM6_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM6_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM7_PEND_MASK             (0x00100000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM7_PEND_SHIFT            (0x00000014U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM7_PEND_RESETVAL         (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_DDATA_RAM7_PEND_MAX              (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_ATCM1_BANK0_PEND_MASK                 (0x00200000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_ATCM1_BANK0_PEND_SHIFT                (0x00000015U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_ATCM1_BANK0_PEND_RESETVAL             (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_ATCM1_BANK0_PEND_MAX                  (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_ATCM1_BANK1_PEND_MASK                 (0x00400000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_ATCM1_BANK1_PEND_SHIFT                (0x00000016U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_ATCM1_BANK1_PEND_RESETVAL             (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_ATCM1_BANK1_PEND_MAX                  (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_B0TCM1_BANK0_PEND_MASK                (0x00800000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_B0TCM1_BANK0_PEND_SHIFT               (0x00000017U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_B0TCM1_BANK0_PEND_RESETVAL            (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_B0TCM1_BANK0_PEND_MAX                 (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_B0TCM1_BANK1_PEND_MASK                (0x01000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_B0TCM1_BANK1_PEND_SHIFT               (0x00000018U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_B0TCM1_BANK1_PEND_RESETVAL            (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_B0TCM1_BANK1_PEND_MAX                 (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_B1TCM1_BANK0_PEND_MASK                (0x02000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_B1TCM1_BANK0_PEND_SHIFT               (0x00000019U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_B1TCM1_BANK0_PEND_RESETVAL            (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_B1TCM1_BANK0_PEND_MAX                 (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_B1TCM1_BANK1_PEND_MASK                (0x04000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_B1TCM1_BANK1_PEND_SHIFT               (0x0000001AU)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_B1TCM1_BANK1_PEND_RESETVAL            (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_B1TCM1_BANK1_PEND_MAX                 (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_KS_VIM_RAMECC_PEND_MASK          (0x08000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_KS_VIM_RAMECC_PEND_SHIFT         (0x0000001BU)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_KS_VIM_RAMECC_PEND_RESETVAL      (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_CPU1_KS_VIM_RAMECC_PEND_MAX           (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_STATUS_REG0_RESETVAL                              (0x00000000U)
+
+/* DED_ENABLE_SET_REG0 */
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_ITAG_RAM0_ENABLE_SET_MASK    (0x00000001U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_ITAG_RAM0_ENABLE_SET_SHIFT   (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_ITAG_RAM0_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_ITAG_RAM0_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_ITAG_RAM1_ENABLE_SET_MASK    (0x00000002U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_ITAG_RAM1_ENABLE_SET_SHIFT   (0x00000001U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_ITAG_RAM1_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_ITAG_RAM1_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_ITAG_RAM2_ENABLE_SET_MASK    (0x00000004U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_ITAG_RAM2_ENABLE_SET_SHIFT   (0x00000002U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_ITAG_RAM2_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_ITAG_RAM2_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_ITAG_RAM3_ENABLE_SET_MASK    (0x00000008U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_ITAG_RAM3_ENABLE_SET_SHIFT   (0x00000003U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_ITAG_RAM3_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_ITAG_RAM3_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_IDATA_BANK0_ENABLE_SET_MASK  (0x00000010U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_IDATA_BANK0_ENABLE_SET_SHIFT (0x00000004U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_IDATA_BANK0_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_IDATA_BANK0_ENABLE_SET_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_IDATA_BANK1_ENABLE_SET_MASK  (0x00000020U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_IDATA_BANK1_ENABLE_SET_SHIFT (0x00000005U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_IDATA_BANK1_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_IDATA_BANK1_ENABLE_SET_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_IDATA_BANK2_ENABLE_SET_MASK  (0x00000040U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_IDATA_BANK2_ENABLE_SET_SHIFT (0x00000006U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_IDATA_BANK2_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_IDATA_BANK2_ENABLE_SET_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_IDATA_BANK3_ENABLE_SET_MASK  (0x00000080U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_IDATA_BANK3_ENABLE_SET_SHIFT (0x00000007U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_IDATA_BANK3_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_IDATA_BANK3_ENABLE_SET_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DTAG_RAM0_ENABLE_SET_MASK    (0x00000100U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DTAG_RAM0_ENABLE_SET_SHIFT   (0x00000008U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DTAG_RAM0_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DTAG_RAM0_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DTAG_RAM1_ENABLE_SET_MASK    (0x00000200U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DTAG_RAM1_ENABLE_SET_SHIFT   (0x00000009U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DTAG_RAM1_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DTAG_RAM1_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DTAG_RAM2_ENABLE_SET_MASK    (0x00000400U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DTAG_RAM2_ENABLE_SET_SHIFT   (0x0000000AU)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DTAG_RAM2_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DTAG_RAM2_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DTAG_RAM3_ENABLE_SET_MASK    (0x00000800U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DTAG_RAM3_ENABLE_SET_SHIFT   (0x0000000BU)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DTAG_RAM3_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DTAG_RAM3_ENABLE_SET_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDIRTY_RAM_ENABLE_SET_MASK   (0x00001000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDIRTY_RAM_ENABLE_SET_SHIFT  (0x0000000CU)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDIRTY_RAM_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDIRTY_RAM_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM0_ENABLE_SET_MASK   (0x00002000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM0_ENABLE_SET_SHIFT  (0x0000000DU)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM0_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM0_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM1_ENABLE_SET_MASK   (0x00004000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM1_ENABLE_SET_SHIFT  (0x0000000EU)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM1_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM1_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM2_ENABLE_SET_MASK   (0x00008000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM2_ENABLE_SET_SHIFT  (0x0000000FU)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM2_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM2_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM3_ENABLE_SET_MASK   (0x00010000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM3_ENABLE_SET_SHIFT  (0x00000010U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM3_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM3_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM4_ENABLE_SET_MASK   (0x00020000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM4_ENABLE_SET_SHIFT  (0x00000011U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM4_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM4_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM5_ENABLE_SET_MASK   (0x00040000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM5_ENABLE_SET_SHIFT  (0x00000012U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM5_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM5_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM6_ENABLE_SET_MASK   (0x00080000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM6_ENABLE_SET_SHIFT  (0x00000013U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM6_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM6_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM7_ENABLE_SET_MASK   (0x00100000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM7_ENABLE_SET_SHIFT  (0x00000014U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM7_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_DDATA_RAM7_ENABLE_SET_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_ATCM1_BANK0_ENABLE_SET_MASK       (0x00200000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_ATCM1_BANK0_ENABLE_SET_SHIFT      (0x00000015U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_ATCM1_BANK0_ENABLE_SET_RESETVAL   (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_ATCM1_BANK0_ENABLE_SET_MAX        (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_ATCM1_BANK1_ENABLE_SET_MASK       (0x00400000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_ATCM1_BANK1_ENABLE_SET_SHIFT      (0x00000016U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_ATCM1_BANK1_ENABLE_SET_RESETVAL   (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_ATCM1_BANK1_ENABLE_SET_MAX        (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_B0TCM1_BANK0_ENABLE_SET_MASK      (0x00800000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_B0TCM1_BANK0_ENABLE_SET_SHIFT     (0x00000017U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_B0TCM1_BANK0_ENABLE_SET_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_B0TCM1_BANK0_ENABLE_SET_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_B0TCM1_BANK1_ENABLE_SET_MASK      (0x01000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_B0TCM1_BANK1_ENABLE_SET_SHIFT     (0x00000018U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_B0TCM1_BANK1_ENABLE_SET_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_B0TCM1_BANK1_ENABLE_SET_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_B1TCM1_BANK0_ENABLE_SET_MASK      (0x02000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_B1TCM1_BANK0_ENABLE_SET_SHIFT     (0x00000019U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_B1TCM1_BANK0_ENABLE_SET_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_B1TCM1_BANK0_ENABLE_SET_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_B1TCM1_BANK1_ENABLE_SET_MASK      (0x04000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_B1TCM1_BANK1_ENABLE_SET_SHIFT     (0x0000001AU)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_B1TCM1_BANK1_ENABLE_SET_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_B1TCM1_BANK1_ENABLE_SET_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_KS_VIM_RAMECC_ENABLE_SET_MASK (0x08000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_KS_VIM_RAMECC_ENABLE_SET_SHIFT (0x0000001BU)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_KS_VIM_RAMECC_ENABLE_SET_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_CPU1_KS_VIM_RAMECC_ENABLE_SET_MAX (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_SET_REG0_RESETVAL                          (0x00000000U)
+
+/* DED_ENABLE_CLR_REG0 */
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_ITAG_RAM0_ENABLE_CLR_MASK    (0x00000001U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_ITAG_RAM0_ENABLE_CLR_SHIFT   (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_ITAG_RAM0_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_ITAG_RAM0_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_ITAG_RAM1_ENABLE_CLR_MASK    (0x00000002U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_ITAG_RAM1_ENABLE_CLR_SHIFT   (0x00000001U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_ITAG_RAM1_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_ITAG_RAM1_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_ITAG_RAM2_ENABLE_CLR_MASK    (0x00000004U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_ITAG_RAM2_ENABLE_CLR_SHIFT   (0x00000002U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_ITAG_RAM2_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_ITAG_RAM2_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_ITAG_RAM3_ENABLE_CLR_MASK    (0x00000008U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_ITAG_RAM3_ENABLE_CLR_SHIFT   (0x00000003U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_ITAG_RAM3_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_ITAG_RAM3_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_IDATA_BANK0_ENABLE_CLR_MASK  (0x00000010U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_IDATA_BANK0_ENABLE_CLR_SHIFT (0x00000004U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_IDATA_BANK0_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_IDATA_BANK0_ENABLE_CLR_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_IDATA_BANK1_ENABLE_CLR_MASK  (0x00000020U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_IDATA_BANK1_ENABLE_CLR_SHIFT (0x00000005U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_IDATA_BANK1_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_IDATA_BANK1_ENABLE_CLR_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_IDATA_BANK2_ENABLE_CLR_MASK  (0x00000040U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_IDATA_BANK2_ENABLE_CLR_SHIFT (0x00000006U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_IDATA_BANK2_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_IDATA_BANK2_ENABLE_CLR_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_IDATA_BANK3_ENABLE_CLR_MASK  (0x00000080U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_IDATA_BANK3_ENABLE_CLR_SHIFT (0x00000007U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_IDATA_BANK3_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_IDATA_BANK3_ENABLE_CLR_MAX   (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DTAG_RAM0_ENABLE_CLR_MASK    (0x00000100U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DTAG_RAM0_ENABLE_CLR_SHIFT   (0x00000008U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DTAG_RAM0_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DTAG_RAM0_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DTAG_RAM1_ENABLE_CLR_MASK    (0x00000200U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DTAG_RAM1_ENABLE_CLR_SHIFT   (0x00000009U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DTAG_RAM1_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DTAG_RAM1_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DTAG_RAM2_ENABLE_CLR_MASK    (0x00000400U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DTAG_RAM2_ENABLE_CLR_SHIFT   (0x0000000AU)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DTAG_RAM2_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DTAG_RAM2_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DTAG_RAM3_ENABLE_CLR_MASK    (0x00000800U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DTAG_RAM3_ENABLE_CLR_SHIFT   (0x0000000BU)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DTAG_RAM3_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DTAG_RAM3_ENABLE_CLR_MAX     (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDIRTY_RAM_ENABLE_CLR_MASK   (0x00001000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDIRTY_RAM_ENABLE_CLR_SHIFT  (0x0000000CU)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDIRTY_RAM_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDIRTY_RAM_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM0_ENABLE_CLR_MASK   (0x00002000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM0_ENABLE_CLR_SHIFT  (0x0000000DU)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM0_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM0_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM1_ENABLE_CLR_MASK   (0x00004000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM1_ENABLE_CLR_SHIFT  (0x0000000EU)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM1_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM1_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM2_ENABLE_CLR_MASK   (0x00008000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM2_ENABLE_CLR_SHIFT  (0x0000000FU)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM2_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM2_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM3_ENABLE_CLR_MASK   (0x00010000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM3_ENABLE_CLR_SHIFT  (0x00000010U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM3_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM3_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM4_ENABLE_CLR_MASK   (0x00020000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM4_ENABLE_CLR_SHIFT  (0x00000011U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM4_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM4_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM5_ENABLE_CLR_MASK   (0x00040000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM5_ENABLE_CLR_SHIFT  (0x00000012U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM5_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM5_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM6_ENABLE_CLR_MASK   (0x00080000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM6_ENABLE_CLR_SHIFT  (0x00000013U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM6_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM6_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM7_ENABLE_CLR_MASK   (0x00100000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM7_ENABLE_CLR_SHIFT  (0x00000014U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM7_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_DDATA_RAM7_ENABLE_CLR_MAX    (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_ATCM1_BANK0_ENABLE_CLR_MASK       (0x00200000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_ATCM1_BANK0_ENABLE_CLR_SHIFT      (0x00000015U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_ATCM1_BANK0_ENABLE_CLR_RESETVAL   (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_ATCM1_BANK0_ENABLE_CLR_MAX        (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_ATCM1_BANK1_ENABLE_CLR_MASK       (0x00400000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_ATCM1_BANK1_ENABLE_CLR_SHIFT      (0x00000016U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_ATCM1_BANK1_ENABLE_CLR_RESETVAL   (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_ATCM1_BANK1_ENABLE_CLR_MAX        (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_B0TCM1_BANK0_ENABLE_CLR_MASK      (0x00800000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_B0TCM1_BANK0_ENABLE_CLR_SHIFT     (0x00000017U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_B0TCM1_BANK0_ENABLE_CLR_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_B0TCM1_BANK0_ENABLE_CLR_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_B0TCM1_BANK1_ENABLE_CLR_MASK      (0x01000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_B0TCM1_BANK1_ENABLE_CLR_SHIFT     (0x00000018U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_B0TCM1_BANK1_ENABLE_CLR_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_B0TCM1_BANK1_ENABLE_CLR_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_B1TCM1_BANK0_ENABLE_CLR_MASK      (0x02000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_B1TCM1_BANK0_ENABLE_CLR_SHIFT     (0x00000019U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_B1TCM1_BANK0_ENABLE_CLR_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_B1TCM1_BANK0_ENABLE_CLR_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_B1TCM1_BANK1_ENABLE_CLR_MASK      (0x04000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_B1TCM1_BANK1_ENABLE_CLR_SHIFT     (0x0000001AU)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_B1TCM1_BANK1_ENABLE_CLR_RESETVAL  (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_B1TCM1_BANK1_ENABLE_CLR_MAX       (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_KS_VIM_RAMECC_ENABLE_CLR_MASK (0x08000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_KS_VIM_RAMECC_ENABLE_CLR_SHIFT (0x0000001BU)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_KS_VIM_RAMECC_ENABLE_CLR_RESETVAL (0x00000000U)
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_CPU1_KS_VIM_RAMECC_ENABLE_CLR_MAX (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_DED_ENABLE_CLR_REG0_RESETVAL                          (0x00000000U)
+
+/* AGGR_ENABLE_SET */
+
+#define SDL_MSS_ECC_AGGB_AGGR_ENABLE_SET_PARITY_MASK                           (0x00000001U)
+#define SDL_MSS_ECC_AGGB_AGGR_ENABLE_SET_PARITY_SHIFT                          (0x00000000U)
+#define SDL_MSS_ECC_AGGB_AGGR_ENABLE_SET_PARITY_RESETVAL                       (0x00000000U)
+#define SDL_MSS_ECC_AGGB_AGGR_ENABLE_SET_PARITY_MAX                            (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_AGGR_ENABLE_SET_TIMEOUT_MASK                          (0x00000002U)
+#define SDL_MSS_ECC_AGGB_AGGR_ENABLE_SET_TIMEOUT_SHIFT                         (0x00000001U)
+#define SDL_MSS_ECC_AGGB_AGGR_ENABLE_SET_TIMEOUT_RESETVAL                      (0x00000000U)
+#define SDL_MSS_ECC_AGGB_AGGR_ENABLE_SET_TIMEOUT_MAX                           (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_AGGR_ENABLE_SET_RESETVAL                              (0x00000000U)
+
+/* AGGR_ENABLE_CLR */
+
+#define SDL_MSS_ECC_AGGB_AGGR_ENABLE_CLR_PARITY_MASK                           (0x00000001U)
+#define SDL_MSS_ECC_AGGB_AGGR_ENABLE_CLR_PARITY_SHIFT                          (0x00000000U)
+#define SDL_MSS_ECC_AGGB_AGGR_ENABLE_CLR_PARITY_RESETVAL                       (0x00000000U)
+#define SDL_MSS_ECC_AGGB_AGGR_ENABLE_CLR_PARITY_MAX                            (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_AGGR_ENABLE_CLR_TIMEOUT_MASK                          (0x00000002U)
+#define SDL_MSS_ECC_AGGB_AGGR_ENABLE_CLR_TIMEOUT_SHIFT                         (0x00000001U)
+#define SDL_MSS_ECC_AGGB_AGGR_ENABLE_CLR_TIMEOUT_RESETVAL                      (0x00000000U)
+#define SDL_MSS_ECC_AGGB_AGGR_ENABLE_CLR_TIMEOUT_MAX                           (0x00000001U)
+
+#define SDL_MSS_ECC_AGGB_AGGR_ENABLE_CLR_RESETVAL                              (0x00000000U)
+
+/* AGGR_STATUS_SET */
+
+#define SDL_MSS_ECC_AGGB_AGGR_STATUS_SET_PARITY_MASK                           (0x00000003U)
+#define SDL_MSS_ECC_AGGB_AGGR_STATUS_SET_PARITY_SHIFT                          (0x00000000U)
+#define SDL_MSS_ECC_AGGB_AGGR_STATUS_SET_PARITY_RESETVAL                       (0x00000000U)
+#define SDL_MSS_ECC_AGGB_AGGR_STATUS_SET_PARITY_MAX                            (0x00000003U)
+
+#define SDL_MSS_ECC_AGGB_AGGR_STATUS_SET_TIMEOUT_MASK                          (0x0000000CU)
+#define SDL_MSS_ECC_AGGB_AGGR_STATUS_SET_TIMEOUT_SHIFT                         (0x00000002U)
+#define SDL_MSS_ECC_AGGB_AGGR_STATUS_SET_TIMEOUT_RESETVAL                      (0x00000000U)
+#define SDL_MSS_ECC_AGGB_AGGR_STATUS_SET_TIMEOUT_MAX                           (0x00000003U)
+
+#define SDL_MSS_ECC_AGGB_AGGR_STATUS_SET_RESETVAL                              (0x00000000U)
+
+/* AGGR_STATUS_CLR */
+
+#define SDL_MSS_ECC_AGGB_AGGR_STATUS_CLR_PARITY_MASK                           (0x00000003U)
+#define SDL_MSS_ECC_AGGB_AGGR_STATUS_CLR_PARITY_SHIFT                          (0x00000000U)
+#define SDL_MSS_ECC_AGGB_AGGR_STATUS_CLR_PARITY_RESETVAL                       (0x00000000U)
+#define SDL_MSS_ECC_AGGB_AGGR_STATUS_CLR_PARITY_MAX                            (0x00000003U)
+
+#define SDL_MSS_ECC_AGGB_AGGR_STATUS_CLR_TIMEOUT_MASK                          (0x0000000CU)
+#define SDL_MSS_ECC_AGGB_AGGR_STATUS_CLR_TIMEOUT_SHIFT                         (0x00000002U)
+#define SDL_MSS_ECC_AGGB_AGGR_STATUS_CLR_TIMEOUT_RESETVAL                      (0x00000000U)
+#define SDL_MSS_ECC_AGGB_AGGR_STATUS_CLR_TIMEOUT_MAX                           (0x00000003U)
+
+#define SDL_MSS_ECC_AGGB_AGGR_STATUS_CLR_RESETVAL                              (0x00000000U)
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/source/sdl/makefile.am243x.r5f.ti-arm-clang b/source/sdl/makefile.am243x.r5f.ti-arm-clang
index 12d333a398..f7b9705eaa 100644
--- a/source/sdl/makefile.am243x.r5f.ti-arm-clang
+++ b/source/sdl/makefile.am243x.r5f.ti-arm-clang
@@ -53,6 +53,9 @@ FILES_common := \
     sdl_interrupt_register.c \
     sdl_exception.c \
     sdl_ecc_r5.c \
+    sdl_r5f_utils.c \
+    sdl_ip_rom_checksum.c \
+    sdl_rom_checksum.c \
 
 ASMFILES_common := \
     sdl_ecc_utils.S \
@@ -97,6 +100,7 @@ FILES_PATH_common = \
     pbist/v0/soc/am243x \
     r5 \
     r5/v0 \
+    rom_checksum \
 
 INCLUDES_common := \
     -I${CG_TOOL_ROOT}/include/c \
diff --git a/source/sdl/makefile.am263x.r5f.ti-arm-clang b/source/sdl/makefile.am263x.r5f.ti-arm-clang
index 7886a744be..407b623a17 100644
--- a/source/sdl/makefile.am263x.r5f.ti-arm-clang
+++ b/source/sdl/makefile.am263x.r5f.ti-arm-clang
@@ -42,6 +42,7 @@ FILES_common := \
     sdl_ccm.c \
     sdl_mcu_armss_ccmr5.c \
     sdl_stc_soc.c \
+    sdl_r5f_utils.c \
 
 ASMFILES_common := \
     sdl_ecc_utils.S \
diff --git a/source/sdl/makefile.am273x.c66.ti-c6000 b/source/sdl/makefile.am273x.c66.ti-c6000
index 53590018fc..800a4c1ba7 100644
--- a/source/sdl/makefile.am273x.c66.ti-c6000
+++ b/source/sdl/makefile.am273x.c66.ti-c6000
@@ -17,7 +17,6 @@ LIBNAME:=sdl.am273x.c66.ti-c6000.$(PROFILE).lib
 
 FILES_common := \
     sdl_dpl.c \
-    sdl_dcc.c \
     sdl_ip_esm.c \
     sdl_esm.c \
     sdl_esm_core.c \
@@ -35,7 +34,6 @@ FILES_common := \
 
 FILES_PATH_common = \
     dpl \
-    dcc/v1 \
     esm \
     esm/v1 \
     esm/v1/v1_0 \
diff --git a/source/sdl/makefile.am273x.r5f.ti-arm-clang b/source/sdl/makefile.am273x.r5f.ti-arm-clang
index 3e74f40caf..a1fa7688b9 100644
--- a/source/sdl/makefile.am273x.r5f.ti-arm-clang
+++ b/source/sdl/makefile.am273x.r5f.ti-arm-clang
@@ -17,7 +17,6 @@ LIBNAME:=sdl.am273x.r5f.ti-arm-clang.$(PROFILE).lib
 
 FILES_common := \
     sdl_dpl.c \
-    sdl_dcc.c \
     sdl_ip_esm.c \
     sdl_esm.c \
     sdl_esm_core.c \
@@ -50,7 +49,6 @@ ASMFILES_common := \
 
 FILES_PATH_common = \
     dpl \
-    dcc/v1 \
     esm \
     esm/v1 \
     esm/v1/v1_0 \
diff --git a/source/sdl/makefile.am273x.r5fss1.ti-arm-clang b/source/sdl/makefile.am273x.r5fss1.ti-arm-clang
index 7d1816a44e..59ab879b74 100644
--- a/source/sdl/makefile.am273x.r5fss1.ti-arm-clang
+++ b/source/sdl/makefile.am273x.r5fss1.ti-arm-clang
@@ -27,7 +27,6 @@ ASMFILES_common := \
 
 FILES_PATH_common = \
     dpl \
-    dcc/v1 \
     esm \
     esm/v1 \
     esm/v1/v1_0 \
diff --git a/source/sdl/makefile.awr294x.c66.ti-c6000 b/source/sdl/makefile.awr294x.c66.ti-c6000
index 32ff08bfd6..77b96994f4 100644
--- a/source/sdl/makefile.awr294x.c66.ti-c6000
+++ b/source/sdl/makefile.awr294x.c66.ti-c6000
@@ -1,165 +1,165 @@
-#
-# Auto generated makefile
-#
-
-export MCU_PLUS_SDK_PATH?=$(abspath ../..)
-include $(MCU_PLUS_SDK_PATH)/imports.mak
-
-CG_TOOL_ROOT=$(CGT_TI_C6000_PATH)
-
-CC=$(CGT_TI_C6000_PATH)/bin/cl6x
-AR=$(CGT_TI_C6000_PATH)/bin/ar6x
-
-PROFILE?=release
-ConfigName:=$(PROFILE)
-
-LIBNAME:=sdl.awr294x.c66.ti-c6000.$(PROFILE).lib
-
-FILES_common := \
-    sdl_dpl.c \
-    sdl_dcc.c \
-    sdl_ip_esm.c \
-    sdl_esm.c \
-    sdl_esm_core.c \
-    sdl_hwa.c \
-    sdl_ip_hwa.c \
-    sdl_mcrc.c \
-    sdl_ip_mcrc.c \
-    sdl_mcrc_soc.c \
-    sdl_rti.c \
-    sdl_ip_rti.c \
-    sdl_soc_rti.c \
-    sdl_ecc_bus_safety.c \
-    sdl_ecc.c \
-    sdl_ip_ecc.c \
-
-FILES_PATH_common = \
-    dpl \
-    dcc/v1 \
-    esm \
-    esm/v1 \
-    esm/v1/v1_0 \
-    esm/soc \
-    esm/soc/awr294x \
-    hwa \
-    hwa/v0 \
-    rti \
-    rti/v0 \
-    rti/v0/soc/awr294x \
-    mcrc \
-    mcrc/v0 \
-    mcrc/v0/soc/awr294x \
-    ecc \
-    ecc/soc/awr294x \
-    ecc/V1 \
-    r5 \
-    r5/v0 \
-    r5/v0/awr294x \
-    pbist \
-    pbist/v0 \
-    pbist/v0/soc \
-    pbist/v0/soc/awr294x \
-    ecc_bus_safety \
-    ecc_bus_safety/v0 \
-    stc/v0/soc/awr294x \
-    ecc_bus_safety/v0/soc \
-    ecc_bus_safety/v0/soc/awr294x \
-    reset/soc/awr294x \
-    soc/awr294x \
-
-INCLUDES_common := \
-    -I${CG_TOOL_ROOT}/include \
-    -I${MCU_PLUS_SDK_PATH}/source \
-
-DEFINES_common := \
-    -DSOC_AWR294X \
-    -DSUBSYS_DSS \
-
-CFLAGS_common := \
-    -mv6600 \
-    --c99 \
-    -q \
-    -mo \
-    -pden \
-    --emit_warnings_as_errors \
-    --mem_model:const=data \
-    --mem_model:data=far_aggregates \
-    --remove_hooks_when_inlining \
-    -on2 \
-    --disable_push_pop \
-    --fp_mode=relaxed \
-    --assume_control_regs_read \
-
-CFLAGS_debug := \
-    -D_DEBUG_=1 \
-
-CFLAGS_release := \
-    --program_level_compile \
-    -o3 \
-    -mf2 \
-
-ARFLAGS_common := \
-    rq \
-
-FILES := $(FILES_common) $(FILES_$(PROFILE))
-ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE))
-ASMEXTNFILES := $(ASMEXTNFILES_common) $(ASMEXTNFILES_$(PROFILE))
-FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE))
-CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE))
-ASMFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE))
-ifeq ($(CPLUSPLUS_BUILD), yes)
-CFLAGS += $(CFLAGS_cpp_common)
-endif
-DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE))
-INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE))
-ARFLAGS := $(ARFLAGS_common) $(ARFLAGS_$(PROFILE))
-
-LIBDIR := lib
-OBJDIR := obj/awr294x/ti-c6000/$(PROFILE)/c66/sdl/
-OBJS := $(FILES:%.c=%.obj)
-OBJS += $(ASMFILES:%.S=%.obj)
-OBJS += $(ASMEXTNFILES:%.asm=%.obj)
-DEPS := $(FILES:%.c=%.d)
-
-vpath %.obj $(OBJDIR)
-vpath %.c $(FILES_PATH)
-vpath %.S $(FILES_PATH)
-vpath %.asm $(FILES_PATH)
-
-$(OBJDIR)/%.obj %.obj: %.c
-	@echo  Compiling: $(LIBNAME): $<
-	$(CC) $(CFLAGS) $(INCLUDES) $(DEFINES) -ppd=$(OBJDIR)/$(basename $@).d -ppa -fr=$(OBJDIR)/ -fc=$<
-
-$(OBJDIR)/%.obj %.obj: %.S
-	@echo  Compiling: $(LIBNAME): $<
-	$(CC) $(CFLAGS) $(INCLUDES) $(DEFINES) -ppd=$(OBJDIR)/$(basename $@).d -ppa -fr=$(OBJDIR)/ -fa=$<
-
-$(OBJDIR)/%.obj %.obj: %.asm
-	@echo  Compiling: $(LIBNAME): $<
-	$(CC) $(CFLAGS) $(INCLUDES) $(DEFINES) -ppd=$(OBJDIR)/$(basename $@).d -ppa -fr=$(OBJDIR)/ -fa=$<
-
-all: $(LIBDIR)/$(LIBNAME)
-
-$(LIBDIR)/$(LIBNAME): $(OBJS) | $(LIBDIR)
-	@echo  .
-	@echo  Archiving: $(LIBNAME) to $@ ...
-	$(AR) $(ARFLAGS) $@ $(addprefix $(OBJDIR), $(OBJS))
-	@echo  Archiving: $(LIBNAME) Done !!!
-	@echo  .
-
-clean:
-	@echo  Cleaning: $(LIBNAME) ...
-	$(RMDIR) $(OBJDIR)
-	$(RM) $(LIBDIR)/$(LIBNAME)
-
-scrub:
-	@echo  Scrubing: $(LIBNAME) ...
-	-$(RMDIR) obj/
-	-$(RMDIR) lib/
-
-$(OBJS): | $(OBJDIR)
-
-$(LIBDIR) $(OBJDIR):
-	$(MKDIR) $@
-
--include $(addprefix $(OBJDIR)/, $(DEPS))
+#
+# Auto generated makefile
+#
+
+export MCU_PLUS_SDK_PATH?=$(abspath ../..)
+include $(MCU_PLUS_SDK_PATH)/imports.mak
+
+CG_TOOL_ROOT=$(CGT_TI_C6000_PATH)
+
+CC=$(CGT_TI_C6000_PATH)/bin/cl6x
+AR=$(CGT_TI_C6000_PATH)/bin/ar6x
+
+PROFILE?=release
+ConfigName:=$(PROFILE)
+
+LIBNAME:=sdl.awr294x.c66.ti-c6000.$(PROFILE).lib
+
+FILES_common := \
+    sdl_dpl.c \
+    sdl_dcc.c \
+    sdl_ip_esm.c \
+    sdl_esm.c \
+    sdl_esm_core.c \
+    sdl_hwa.c \
+    sdl_ip_hwa.c \
+    sdl_mcrc.c \
+    sdl_ip_mcrc.c \
+    sdl_mcrc_soc.c \
+    sdl_rti.c \
+    sdl_ip_rti.c \
+    sdl_soc_rti.c \
+    sdl_ecc_bus_safety.c \
+    sdl_ecc.c \
+    sdl_ip_ecc.c \
+
+FILES_PATH_common = \
+    dpl \
+    dcc/v1 \
+    esm \
+    esm/v1 \
+    esm/v1/v1_0 \
+    esm/soc \
+    esm/soc/awr294x \
+    hwa \
+    hwa/v0 \
+    rti \
+    rti/v0 \
+    rti/v0/soc/awr294x \
+    mcrc \
+    mcrc/v0 \
+    mcrc/v0/soc/awr294x \
+    ecc \
+    ecc/soc/awr294x \
+    ecc/V1 \
+    r5 \
+    r5/v0 \
+    r5/v0/awr294x \
+    pbist \
+    pbist/v0 \
+    pbist/v0/soc \
+    pbist/v0/soc/awr294x \
+    ecc_bus_safety \
+    ecc_bus_safety/v0 \
+    stc/v0/soc/awr294x \
+    ecc_bus_safety/v0/soc \
+    ecc_bus_safety/v0/soc/awr294x \
+    reset/soc/awr294x \
+    soc/awr294x \
+
+INCLUDES_common := \
+    -I${CG_TOOL_ROOT}/include \
+    -I${MCU_PLUS_SDK_PATH}/source \
+
+DEFINES_common := \
+    -DSOC_AWR294X \
+    -DSUBSYS_DSS \
+
+CFLAGS_common := \
+    -mv6600 \
+    --c99 \
+    -q \
+    -mo \
+    -pden \
+    --emit_warnings_as_errors \
+    --mem_model:const=data \
+    --mem_model:data=far_aggregates \
+    --remove_hooks_when_inlining \
+    -on2 \
+    --disable_push_pop \
+    --fp_mode=relaxed \
+    --assume_control_regs_read \
+
+CFLAGS_debug := \
+    -D_DEBUG_=1 \
+
+CFLAGS_release := \
+    --program_level_compile \
+    -o3 \
+    -mf2 \
+
+ARFLAGS_common := \
+    rq \
+
+FILES := $(FILES_common) $(FILES_$(PROFILE))
+ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE))
+ASMEXTNFILES := $(ASMEXTNFILES_common) $(ASMEXTNFILES_$(PROFILE))
+FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE))
+CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE))
+ASMFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE))
+ifeq ($(CPLUSPLUS_BUILD), yes)
+CFLAGS += $(CFLAGS_cpp_common)
+endif
+DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE))
+INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE))
+ARFLAGS := $(ARFLAGS_common) $(ARFLAGS_$(PROFILE))
+
+LIBDIR := lib
+OBJDIR := obj/awr294x/ti-c6000/$(PROFILE)/c66/sdl/
+OBJS := $(FILES:%.c=%.obj)
+OBJS += $(ASMFILES:%.S=%.obj)
+OBJS += $(ASMEXTNFILES:%.asm=%.obj)
+DEPS := $(FILES:%.c=%.d)
+
+vpath %.obj $(OBJDIR)
+vpath %.c $(FILES_PATH)
+vpath %.S $(FILES_PATH)
+vpath %.asm $(FILES_PATH)
+
+$(OBJDIR)/%.obj %.obj: %.c
+	@echo  Compiling: $(LIBNAME): $<
+	$(CC) $(CFLAGS) $(INCLUDES) $(DEFINES) -ppd=$(OBJDIR)/$(basename $@).d -ppa -fr=$(OBJDIR)/ -fc=$<
+
+$(OBJDIR)/%.obj %.obj: %.S
+	@echo  Compiling: $(LIBNAME): $<
+	$(CC) $(CFLAGS) $(INCLUDES) $(DEFINES) -ppd=$(OBJDIR)/$(basename $@).d -ppa -fr=$(OBJDIR)/ -fa=$<
+
+$(OBJDIR)/%.obj %.obj: %.asm
+	@echo  Compiling: $(LIBNAME): $<
+	$(CC) $(CFLAGS) $(INCLUDES) $(DEFINES) -ppd=$(OBJDIR)/$(basename $@).d -ppa -fr=$(OBJDIR)/ -fa=$<
+
+all: $(LIBDIR)/$(LIBNAME)
+
+$(LIBDIR)/$(LIBNAME): $(OBJS) | $(LIBDIR)
+	@echo  .
+	@echo  Archiving: $(LIBNAME) to $@ ...
+	$(AR) $(ARFLAGS) $@ $(addprefix $(OBJDIR), $(OBJS))
+	@echo  Archiving: $(LIBNAME) Done !!!
+	@echo  .
+
+clean:
+	@echo  Cleaning: $(LIBNAME) ...
+	$(RMDIR) $(OBJDIR)
+	$(RM) $(LIBDIR)/$(LIBNAME)
+
+scrub:
+	@echo  Scrubing: $(LIBNAME) ...
+	-$(RMDIR) obj/
+	-$(RMDIR) lib/
+
+$(OBJS): | $(OBJDIR)
+
+$(LIBDIR) $(OBJDIR):
+	$(MKDIR) $@
+
+-include $(addprefix $(OBJDIR)/, $(DEPS))
diff --git a/source/sdl/makefile.awr294x.r5f.ti-arm-clang b/source/sdl/makefile.awr294x.r5f.ti-arm-clang
index 6789bd8f70..f881aa989c 100644
--- a/source/sdl/makefile.awr294x.r5f.ti-arm-clang
+++ b/source/sdl/makefile.awr294x.r5f.ti-arm-clang
@@ -1,188 +1,188 @@
-#
-# Auto generated makefile
-#
-
-export MCU_PLUS_SDK_PATH?=$(abspath ../..)
-include $(MCU_PLUS_SDK_PATH)/imports.mak
-
-CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH)
-
-CC=$(CGT_TI_ARM_CLANG_PATH)/bin/tiarmclang
-AR=$(CGT_TI_ARM_CLANG_PATH)/bin/tiarmar
-
-PROFILE?=release
-ConfigName:=$(PROFILE)
-
-LIBNAME:=sdl.awr294x.r5f.ti-arm-clang.$(PROFILE).lib
-
-FILES_common := \
-    sdl_dpl.c \
-    sdl_dcc.c \
-    sdl_ip_esm.c \
-    sdl_esm.c \
-    sdl_esm_core.c \
-    sdl_rti.c \
-    sdl_ip_rti.c \
-    sdl_soc_rti.c \
-    sdl_mcrc.c \
-    sdl_ip_mcrc.c \
-    sdl_mcrc_soc.c \
-    sdl_ecc.c \
-    sdl_ip_ecc.c \
-    sdl_ecc_r5.c \
-    sdl_interrupt.c \
-    sdl_interrupt_handlers.c \
-    sdl_interrupt_register.c \
-    sdl_exception.c \
-    sdl_ip_pbist.c \
-    sdl_pbist_soc.c \
-    sdl_pbist.c \
-    sdl_ecc_bus_safety.c \
-    sdl_stc_soc.c \
-    sdl_ccm.c \
-    sdl_mcu_armss_ccmr5.c \
-    sdl_reset.c \
-    soc.c \
-
-ASMFILES_common := \
-    sdl_ecc_utils.S \
-    sdl_r5_utils.S \
-
-FILES_PATH_common = \
-    dpl \
-    dcc/v1 \
-    esm \
-    esm/v1 \
-    esm/v1/v1_0 \
-    esm/soc \
-    esm/soc/awr294x \
-    hwa \
-    hwa/v0 \
-    rti \
-    rti/v0 \
-    rti/v0/soc/awr294x \
-    mcrc \
-    mcrc/v0 \
-    mcrc/v0/soc/awr294x \
-    ecc \
-    ecc/soc/awr294x \
-    ecc/V1 \
-    r5 \
-    r5/v0 \
-    r5/v0/awr294x \
-    pbist \
-    pbist/v0 \
-    pbist/v0/soc \
-    pbist/v0/soc/awr294x \
-    ecc_bus_safety \
-    ecc_bus_safety/v0 \
-    stc/v0/soc/awr294x \
-    ecc_bus_safety/v0/soc \
-    ecc_bus_safety/v0/soc/awr294x \
-    reset/soc/awr294x \
-    soc/awr294x \
-
-INCLUDES_common := \
-    -I${CG_TOOL_ROOT}/include/c \
-    -I${MCU_PLUS_SDK_PATH}/source \
-
-DEFINES_common := \
-    -DSOC_AWR294X \
-    -DSUBSYS_R5FSS0 \
-    -DSUBSYS_MSS \
-
-CFLAGS_common := \
-    -mcpu=cortex-r5 \
-    -mfloat-abi=hard \
-    -mfpu=vfpv3-d16 \
-    -mthumb \
-    -Wall \
-    -Werror \
-    -g \
-    -Wno-gnu-variable-sized-type-not-at-end \
-    -Wno-unused-function \
-    -Wno-extra \
-
-CFLAGS_cpp_common := \
-    -Wno-c99-designator \
-    -Wno-extern-c-compat \
-    -Wno-c++11-narrowing \
-    -Wno-reorder-init-list \
-    -Wno-deprecated-register \
-    -Wno-writable-strings \
-    -Wno-enum-compare \
-    -Wno-reserved-user-defined-literal \
-    -Wno-unused-const-variable \
-    -x c++ \
-
-CFLAGS_debug := \
-    -D_DEBUG_=1 \
-
-CFLAGS_release := \
-    -Os \
-
-ARFLAGS_common := \
-    rc \
-
-FILES := $(FILES_common) $(FILES_$(PROFILE))
-ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE))
-ASMEXTNFILES := $(ASMEXTNFILES_common) $(ASMEXTNFILES_$(PROFILE))
-FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE))
-CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE))
-ASMFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE))
-ifeq ($(CPLUSPLUS_BUILD), yes)
-CFLAGS += $(CFLAGS_cpp_common)
-endif
-DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE))
-INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE))
-ARFLAGS := $(ARFLAGS_common) $(ARFLAGS_$(PROFILE))
-
-LIBDIR := lib
-OBJDIR := obj/awr294x/ti-arm-clang/$(PROFILE)/r5f/sdl/
-OBJS := $(FILES:%.c=%.obj)
-OBJS += $(ASMFILES:%.S=%.obj)
-OBJS += $(ASMEXTNFILES:%.asm=%.obj)
-DEPS := $(FILES:%.c=%.d)
-
-vpath %.obj $(OBJDIR)
-vpath %.c $(FILES_PATH)
-vpath %.S $(FILES_PATH)
-vpath %.asm $(FILES_PATH)
-
-$(OBJDIR)/%.obj %.obj: %.c
-	@echo  Compiling: $(LIBNAME): $<
-	$(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $<
-
-$(OBJDIR)/%.obj %.obj: %.S
-	@echo  Compiling: $(LIBNAME): $<
-	$(CC) -c $(ASMFLAGS) -o $(OBJDIR)/$@ $<
-
-$(OBJDIR)/%.obj %.obj: %.asm
-	@echo  Compiling: $(LIBNAME): $<
-	$(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $<
-
-all: $(LIBDIR)/$(LIBNAME)
-
-$(LIBDIR)/$(LIBNAME): $(OBJS) | $(LIBDIR)
-	@echo  .
-	@echo  Archiving: $(LIBNAME) to $@ ...
-	$(AR) $(ARFLAGS) $@ $(addprefix $(OBJDIR), $(OBJS))
-	@echo  Archiving: $(LIBNAME) Done !!!
-	@echo  .
-
-clean:
-	@echo  Cleaning: $(LIBNAME) ...
-	$(RMDIR) $(OBJDIR)
-	$(RM) $(LIBDIR)/$(LIBNAME)
-
-scrub:
-	@echo  Scrubing: $(LIBNAME) ...
-	-$(RMDIR) obj/
-	-$(RMDIR) lib/
-
-$(OBJS): | $(OBJDIR)
-
-$(LIBDIR) $(OBJDIR):
-	$(MKDIR) $@
-
--include $(addprefix $(OBJDIR)/, $(DEPS))
+#
+# Auto generated makefile
+#
+
+export MCU_PLUS_SDK_PATH?=$(abspath ../..)
+include $(MCU_PLUS_SDK_PATH)/imports.mak
+
+CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH)
+
+CC=$(CGT_TI_ARM_CLANG_PATH)/bin/tiarmclang
+AR=$(CGT_TI_ARM_CLANG_PATH)/bin/tiarmar
+
+PROFILE?=release
+ConfigName:=$(PROFILE)
+
+LIBNAME:=sdl.awr294x.r5f.ti-arm-clang.$(PROFILE).lib
+
+FILES_common := \
+    sdl_dpl.c \
+    sdl_dcc.c \
+    sdl_ip_esm.c \
+    sdl_esm.c \
+    sdl_esm_core.c \
+    sdl_rti.c \
+    sdl_ip_rti.c \
+    sdl_soc_rti.c \
+    sdl_mcrc.c \
+    sdl_ip_mcrc.c \
+    sdl_mcrc_soc.c \
+    sdl_ecc.c \
+    sdl_ip_ecc.c \
+    sdl_ecc_r5.c \
+    sdl_interrupt.c \
+    sdl_interrupt_handlers.c \
+    sdl_interrupt_register.c \
+    sdl_exception.c \
+    sdl_ip_pbist.c \
+    sdl_pbist_soc.c \
+    sdl_pbist.c \
+    sdl_ecc_bus_safety.c \
+    sdl_stc_soc.c \
+    sdl_ccm.c \
+    sdl_mcu_armss_ccmr5.c \
+    sdl_reset.c \
+    soc.c \
+
+ASMFILES_common := \
+    sdl_ecc_utils.S \
+    sdl_r5_utils.S \
+
+FILES_PATH_common = \
+    dpl \
+    dcc/v1 \
+    esm \
+    esm/v1 \
+    esm/v1/v1_0 \
+    esm/soc \
+    esm/soc/awr294x \
+    hwa \
+    hwa/v0 \
+    rti \
+    rti/v0 \
+    rti/v0/soc/awr294x \
+    mcrc \
+    mcrc/v0 \
+    mcrc/v0/soc/awr294x \
+    ecc \
+    ecc/soc/awr294x \
+    ecc/V1 \
+    r5 \
+    r5/v0 \
+    r5/v0/awr294x \
+    pbist \
+    pbist/v0 \
+    pbist/v0/soc \
+    pbist/v0/soc/awr294x \
+    ecc_bus_safety \
+    ecc_bus_safety/v0 \
+    stc/v0/soc/awr294x \
+    ecc_bus_safety/v0/soc \
+    ecc_bus_safety/v0/soc/awr294x \
+    reset/soc/awr294x \
+    soc/awr294x \
+
+INCLUDES_common := \
+    -I${CG_TOOL_ROOT}/include/c \
+    -I${MCU_PLUS_SDK_PATH}/source \
+
+DEFINES_common := \
+    -DSOC_AWR294X \
+    -DSUBSYS_R5FSS0 \
+    -DSUBSYS_MSS \
+
+CFLAGS_common := \
+    -mcpu=cortex-r5 \
+    -mfloat-abi=hard \
+    -mfpu=vfpv3-d16 \
+    -mthumb \
+    -Wall \
+    -Werror \
+    -g \
+    -Wno-gnu-variable-sized-type-not-at-end \
+    -Wno-unused-function \
+    -Wno-extra \
+
+CFLAGS_cpp_common := \
+    -Wno-c99-designator \
+    -Wno-extern-c-compat \
+    -Wno-c++11-narrowing \
+    -Wno-reorder-init-list \
+    -Wno-deprecated-register \
+    -Wno-writable-strings \
+    -Wno-enum-compare \
+    -Wno-reserved-user-defined-literal \
+    -Wno-unused-const-variable \
+    -x c++ \
+
+CFLAGS_debug := \
+    -D_DEBUG_=1 \
+
+CFLAGS_release := \
+    -Os \
+
+ARFLAGS_common := \
+    rc \
+
+FILES := $(FILES_common) $(FILES_$(PROFILE))
+ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE))
+ASMEXTNFILES := $(ASMEXTNFILES_common) $(ASMEXTNFILES_$(PROFILE))
+FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE))
+CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE))
+ASMFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE))
+ifeq ($(CPLUSPLUS_BUILD), yes)
+CFLAGS += $(CFLAGS_cpp_common)
+endif
+DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE))
+INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE))
+ARFLAGS := $(ARFLAGS_common) $(ARFLAGS_$(PROFILE))
+
+LIBDIR := lib
+OBJDIR := obj/awr294x/ti-arm-clang/$(PROFILE)/r5f/sdl/
+OBJS := $(FILES:%.c=%.obj)
+OBJS += $(ASMFILES:%.S=%.obj)
+OBJS += $(ASMEXTNFILES:%.asm=%.obj)
+DEPS := $(FILES:%.c=%.d)
+
+vpath %.obj $(OBJDIR)
+vpath %.c $(FILES_PATH)
+vpath %.S $(FILES_PATH)
+vpath %.asm $(FILES_PATH)
+
+$(OBJDIR)/%.obj %.obj: %.c
+	@echo  Compiling: $(LIBNAME): $<
+	$(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $<
+
+$(OBJDIR)/%.obj %.obj: %.S
+	@echo  Compiling: $(LIBNAME): $<
+	$(CC) -c $(ASMFLAGS) -o $(OBJDIR)/$@ $<
+
+$(OBJDIR)/%.obj %.obj: %.asm
+	@echo  Compiling: $(LIBNAME): $<
+	$(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $<
+
+all: $(LIBDIR)/$(LIBNAME)
+
+$(LIBDIR)/$(LIBNAME): $(OBJS) | $(LIBDIR)
+	@echo  .
+	@echo  Archiving: $(LIBNAME) to $@ ...
+	$(AR) $(ARFLAGS) $@ $(addprefix $(OBJDIR), $(OBJS))
+	@echo  Archiving: $(LIBNAME) Done !!!
+	@echo  .
+
+clean:
+	@echo  Cleaning: $(LIBNAME) ...
+	$(RMDIR) $(OBJDIR)
+	$(RM) $(LIBDIR)/$(LIBNAME)
+
+scrub:
+	@echo  Scrubing: $(LIBNAME) ...
+	-$(RMDIR) obj/
+	-$(RMDIR) lib/
+
+$(OBJS): | $(OBJDIR)
+
+$(LIBDIR) $(OBJDIR):
+	$(MKDIR) $@
+
+-include $(addprefix $(OBJDIR)/, $(DEPS))
diff --git a/source/sdl/makefile.awr294x.r5fss1.ti-arm-clang b/source/sdl/makefile.awr294x.r5fss1.ti-arm-clang
index dd13d33e22..f1d1c450b8 100644
--- a/source/sdl/makefile.awr294x.r5fss1.ti-arm-clang
+++ b/source/sdl/makefile.awr294x.r5fss1.ti-arm-clang
@@ -1,164 +1,164 @@
-#
-# Auto generated makefile
-#
-
-export MCU_PLUS_SDK_PATH?=$(abspath ../..)
-include $(MCU_PLUS_SDK_PATH)/imports.mak
-
-CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH)
-
-CC=$(CGT_TI_ARM_CLANG_PATH)/bin/tiarmclang
-AR=$(CGT_TI_ARM_CLANG_PATH)/bin/tiarmar
-
-PROFILE?=release
-ConfigName:=$(PROFILE)
-
-LIBNAME:=sdl.awr294x.r5fss1.ti-arm-clang.$(PROFILE).lib
-
-FILES_common := \
-    sdl_dpl.c \
-    sdl_ip_pbist.c \
-    sdl_pbist_soc.c \
-    sdl_pbist.c \
-
-ASMFILES_common := \
-    sdl_ecc_utils.S \
-    sdl_r5_utils.S \
-
-FILES_PATH_common = \
-    dpl \
-    dcc/v1 \
-    esm \
-    esm/v1 \
-    esm/v1/v1_0 \
-    esm/soc \
-    esm/soc/awr294x \
-    hwa \
-    hwa/v0 \
-    rti \
-    rti/v0 \
-    rti/v0/soc/awr294x \
-    mcrc \
-    mcrc/v0 \
-    mcrc/v0/soc/awr294x \
-    ecc \
-    ecc/soc/awr294x \
-    ecc/V1 \
-    r5 \
-    r5/v0 \
-    r5/v0/awr294x \
-    pbist \
-    pbist/v0 \
-    pbist/v0/soc \
-    pbist/v0/soc/awr294x \
-    ecc_bus_safety \
-    ecc_bus_safety/v0 \
-    stc/v0/soc/awr294x \
-    ecc_bus_safety/v0/soc \
-    ecc_bus_safety/v0/soc/awr294x \
-    reset/soc/awr294x \
-    soc/awr294x \
-
-INCLUDES_common := \
-    -I${CG_TOOL_ROOT}/include/c \
-    -I${MCU_PLUS_SDK_PATH}/source \
-
-DEFINES_common := \
-    -DSOC_AWR294X \
-    -DSUBSYS_R5FSS1 \
-
-CFLAGS_common := \
-    -mcpu=cortex-r5 \
-    -mfloat-abi=hard \
-    -mfpu=vfpv3-d16 \
-    -mthumb \
-    -Wall \
-    -Werror \
-    -g \
-    -Wno-gnu-variable-sized-type-not-at-end \
-    -Wno-unused-function \
-    -Wno-extra \
-
-CFLAGS_cpp_common := \
-    -Wno-c99-designator \
-    -Wno-extern-c-compat \
-    -Wno-c++11-narrowing \
-    -Wno-reorder-init-list \
-    -Wno-deprecated-register \
-    -Wno-writable-strings \
-    -Wno-enum-compare \
-    -Wno-reserved-user-defined-literal \
-    -Wno-unused-const-variable \
-    -x c++ \
-
-CFLAGS_debug := \
-    -D_DEBUG_=1 \
-
-CFLAGS_release := \
-    -Os \
-
-ARFLAGS_common := \
-    rc \
-
-FILES := $(FILES_common) $(FILES_$(PROFILE))
-ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE))
-ASMEXTNFILES := $(ASMEXTNFILES_common) $(ASMEXTNFILES_$(PROFILE))
-FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE))
-CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE))
-ASMFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE))
-ifeq ($(CPLUSPLUS_BUILD), yes)
-CFLAGS += $(CFLAGS_cpp_common)
-endif
-DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE))
-INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE))
-ARFLAGS := $(ARFLAGS_common) $(ARFLAGS_$(PROFILE))
-
-LIBDIR := lib
-OBJDIR := obj/awr294x/ti-arm-clang/$(PROFILE)/r5fss1/sdl/
-OBJS := $(FILES:%.c=%.obj)
-OBJS += $(ASMFILES:%.S=%.obj)
-OBJS += $(ASMEXTNFILES:%.asm=%.obj)
-DEPS := $(FILES:%.c=%.d)
-
-vpath %.obj $(OBJDIR)
-vpath %.c $(FILES_PATH)
-vpath %.S $(FILES_PATH)
-vpath %.asm $(FILES_PATH)
-
-$(OBJDIR)/%.obj %.obj: %.c
-	@echo  Compiling: $(LIBNAME): $<
-	$(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $<
-
-$(OBJDIR)/%.obj %.obj: %.S
-	@echo  Compiling: $(LIBNAME): $<
-	$(CC) -c $(ASMFLAGS) -o $(OBJDIR)/$@ $<
-
-$(OBJDIR)/%.obj %.obj: %.asm
-	@echo  Compiling: $(LIBNAME): $<
-	$(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $<
-
-all: $(LIBDIR)/$(LIBNAME)
-
-$(LIBDIR)/$(LIBNAME): $(OBJS) | $(LIBDIR)
-	@echo  .
-	@echo  Archiving: $(LIBNAME) to $@ ...
-	$(AR) $(ARFLAGS) $@ $(addprefix $(OBJDIR), $(OBJS))
-	@echo  Archiving: $(LIBNAME) Done !!!
-	@echo  .
-
-clean:
-	@echo  Cleaning: $(LIBNAME) ...
-	$(RMDIR) $(OBJDIR)
-	$(RM) $(LIBDIR)/$(LIBNAME)
-
-scrub:
-	@echo  Scrubing: $(LIBNAME) ...
-	-$(RMDIR) obj/
-	-$(RMDIR) lib/
-
-$(OBJS): | $(OBJDIR)
-
-$(LIBDIR) $(OBJDIR):
-	$(MKDIR) $@
-
--include $(addprefix $(OBJDIR)/, $(DEPS))
+#
+# Auto generated makefile
+#
+
+export MCU_PLUS_SDK_PATH?=$(abspath ../..)
+include $(MCU_PLUS_SDK_PATH)/imports.mak
+
+CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH)
+
+CC=$(CGT_TI_ARM_CLANG_PATH)/bin/tiarmclang
+AR=$(CGT_TI_ARM_CLANG_PATH)/bin/tiarmar
+
+PROFILE?=release
+ConfigName:=$(PROFILE)
+
+LIBNAME:=sdl.awr294x.r5fss1.ti-arm-clang.$(PROFILE).lib
+
+FILES_common := \
+    sdl_dpl.c \
+    sdl_ip_pbist.c \
+    sdl_pbist_soc.c \
+    sdl_pbist.c \
+
+ASMFILES_common := \
+    sdl_ecc_utils.S \
+    sdl_r5_utils.S \
+
+FILES_PATH_common = \
+    dpl \
+    dcc/v1 \
+    esm \
+    esm/v1 \
+    esm/v1/v1_0 \
+    esm/soc \
+    esm/soc/awr294x \
+    hwa \
+    hwa/v0 \
+    rti \
+    rti/v0 \
+    rti/v0/soc/awr294x \
+    mcrc \
+    mcrc/v0 \
+    mcrc/v0/soc/awr294x \
+    ecc \
+    ecc/soc/awr294x \
+    ecc/V1 \
+    r5 \
+    r5/v0 \
+    r5/v0/awr294x \
+    pbist \
+    pbist/v0 \
+    pbist/v0/soc \
+    pbist/v0/soc/awr294x \
+    ecc_bus_safety \
+    ecc_bus_safety/v0 \
+    stc/v0/soc/awr294x \
+    ecc_bus_safety/v0/soc \
+    ecc_bus_safety/v0/soc/awr294x \
+    reset/soc/awr294x \
+    soc/awr294x \
+
+INCLUDES_common := \
+    -I${CG_TOOL_ROOT}/include/c \
+    -I${MCU_PLUS_SDK_PATH}/source \
+
+DEFINES_common := \
+    -DSOC_AWR294X \
+    -DSUBSYS_R5FSS1 \
+
+CFLAGS_common := \
+    -mcpu=cortex-r5 \
+    -mfloat-abi=hard \
+    -mfpu=vfpv3-d16 \
+    -mthumb \
+    -Wall \
+    -Werror \
+    -g \
+    -Wno-gnu-variable-sized-type-not-at-end \
+    -Wno-unused-function \
+    -Wno-extra \
+
+CFLAGS_cpp_common := \
+    -Wno-c99-designator \
+    -Wno-extern-c-compat \
+    -Wno-c++11-narrowing \
+    -Wno-reorder-init-list \
+    -Wno-deprecated-register \
+    -Wno-writable-strings \
+    -Wno-enum-compare \
+    -Wno-reserved-user-defined-literal \
+    -Wno-unused-const-variable \
+    -x c++ \
+
+CFLAGS_debug := \
+    -D_DEBUG_=1 \
+
+CFLAGS_release := \
+    -Os \
+
+ARFLAGS_common := \
+    rc \
+
+FILES := $(FILES_common) $(FILES_$(PROFILE))
+ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE))
+ASMEXTNFILES := $(ASMEXTNFILES_common) $(ASMEXTNFILES_$(PROFILE))
+FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE))
+CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE))
+ASMFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE))
+ifeq ($(CPLUSPLUS_BUILD), yes)
+CFLAGS += $(CFLAGS_cpp_common)
+endif
+DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE))
+INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE))
+ARFLAGS := $(ARFLAGS_common) $(ARFLAGS_$(PROFILE))
+
+LIBDIR := lib
+OBJDIR := obj/awr294x/ti-arm-clang/$(PROFILE)/r5fss1/sdl/
+OBJS := $(FILES:%.c=%.obj)
+OBJS += $(ASMFILES:%.S=%.obj)
+OBJS += $(ASMEXTNFILES:%.asm=%.obj)
+DEPS := $(FILES:%.c=%.d)
+
+vpath %.obj $(OBJDIR)
+vpath %.c $(FILES_PATH)
+vpath %.S $(FILES_PATH)
+vpath %.asm $(FILES_PATH)
+
+$(OBJDIR)/%.obj %.obj: %.c
+	@echo  Compiling: $(LIBNAME): $<
+	$(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $<
+
+$(OBJDIR)/%.obj %.obj: %.S
+	@echo  Compiling: $(LIBNAME): $<
+	$(CC) -c $(ASMFLAGS) -o $(OBJDIR)/$@ $<
+
+$(OBJDIR)/%.obj %.obj: %.asm
+	@echo  Compiling: $(LIBNAME): $<
+	$(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $<
+
+all: $(LIBDIR)/$(LIBNAME)
+
+$(LIBDIR)/$(LIBNAME): $(OBJS) | $(LIBDIR)
+	@echo  .
+	@echo  Archiving: $(LIBNAME) to $@ ...
+	$(AR) $(ARFLAGS) $@ $(addprefix $(OBJDIR), $(OBJS))
+	@echo  Archiving: $(LIBNAME) Done !!!
+	@echo  .
+
+clean:
+	@echo  Cleaning: $(LIBNAME) ...
+	$(RMDIR) $(OBJDIR)
+	$(RM) $(LIBDIR)/$(LIBNAME)
+
+scrub:
+	@echo  Scrubing: $(LIBNAME) ...
+	-$(RMDIR) obj/
+	-$(RMDIR) lib/
+
+$(OBJS): | $(OBJDIR)
+
+$(LIBDIR) $(OBJDIR):
+	$(MKDIR) $@
+
+-include $(addprefix $(OBJDIR)/, $(DEPS))
diff --git a/source/sdl/pbist/sdl_pbist.c b/source/sdl/pbist/sdl_pbist.c
index 0c3701e081..6bbe371462 100644
--- a/source/sdl/pbist/sdl_pbist.c
+++ b/source/sdl/pbist/sdl_pbist.c
@@ -50,6 +50,7 @@
 #if defined (SOC_AM273X) || (SOC_AWR294X)
 extern uint32_t gInst;
 #endif
+
 static int32_t SDL_PBIST_prepareTest(SDL_PBIST_inst instance, const SDL_pbistInstInfo *pInfo,
                                      SDL_pbistRegs **pRegs,
                                      pSDL_DPL_HwipHandle *PBIST_intrHandle)
@@ -254,6 +255,4 @@ int32_t SDL_PBIST_selfTest(SDL_PBIST_inst instance, SDL_PBIST_testType testType,
     (void)SDL_PBIST_cleanupTest(PBIST_intrHandle);
 
     return ret;
-}
-
-/* Nothing past this point */
+}
\ No newline at end of file
diff --git a/source/sdl/pbist/v0/soc/am263x/sdl_ip_pbist.c b/source/sdl/pbist/v0/soc/am263x/sdl_ip_pbist.c
index 7c574a0db5..76fdb011d5 100644
--- a/source/sdl/pbist/v0/soc/am263x/sdl_ip_pbist.c
+++ b/source/sdl/pbist/v0/soc/am263x/sdl_ip_pbist.c
@@ -58,8 +58,6 @@
 #define SDL_MSS_TOP_PBIST_SELF_TEST_KEY    ((uint8_t)0x05U)
 #define SDL_MSS_TOP_PBIST_MDP_LOGIC_RESET  ((uint8_t)0x0AU)
 
-SDL_mss_ctrlRegs * ptrMSSCtrlRegs = (SDL_mss_ctrlRegs *)SDL_MSS_CTRL_U_BASE;
-
 static void SDL_MSS_enableTopPbist (void)
 {
     /* Enable the TOP PBIST Self-Test Key */
diff --git a/source/sdl/pbist/v0/soc/am263x/sdl_pbist_soc.c b/source/sdl/pbist/v0/soc/am263x/sdl_pbist_soc.c
index 6a1bb26762..b2edbe7349 100644
--- a/source/sdl/pbist/v0/soc/am263x/sdl_pbist_soc.c
+++ b/source/sdl/pbist/v0/soc/am263x/sdl_pbist_soc.c
@@ -381,4 +381,4 @@ void SDL_PBIST_eventHandler( uint32_t instanceId)
     SDL_PBIST_InstInfoArray[instanceId].doneFlag = PBIST_DONE;
 
     return;
-}
+}
\ No newline at end of file
diff --git a/source/sdl/pok/v1/soc/am64x/sdl_soc_pok.c b/source/sdl/pok/v1/soc/am64x/sdl_soc_pok.c
index 07730b29bb..a8e60b0faf 100644
--- a/source/sdl/pok/v1/soc/am64x/sdl_soc_pok.c
+++ b/source/sdl/pok/v1/soc/am64x/sdl_soc_pok.c
@@ -75,8 +75,9 @@ bool SDL_POK_getBaseaddr(SDL_POK_InstanceType instance, uint32_t *pBaseAddress)
             default:
                 break;
         }
+	    *pBaseAddress = (uint32_t)SDL_DPL_addrTranslate(*pBaseAddress, size);
     }
-        *pBaseAddress = (uint32_t)SDL_DPL_addrTranslate(*pBaseAddress, size);
-      return (instValid);
+       
+    return (instValid);
 }
    
diff --git a/source/sdl/r5/v0/am263x/sdl_ccm.c b/source/sdl/r5/v0/am263x/sdl_ccm.c
index 4fecf0f024..0382b5e28f 100644
--- a/source/sdl/r5/v0/am263x/sdl_ccm.c
+++ b/source/sdl/r5/v0/am263x/sdl_ccm.c
@@ -43,6 +43,7 @@
 /*                             Global Variables                               */
 /* ========================================================================== */
 volatile bool Erroresm = false;
+volatile uint8_t CCMInstance = 0u;
 /* ========================================================================== */
 /*                             Macros                                 */
 /* ========================================================================== */
@@ -57,7 +58,7 @@ volatile bool Erroresm = false;
                                             | SDL_MCU_ARMSS_CCMR5_COMPARE_WRAPPER_CFG_MMRS_CCMSR1_STET1_MASK \
                                             | SDL_MCU_ARMSS_CCMR5_COMPARE_WRAPPER_CFG_MMRS_CCMSR1_STC1_MASK \
                                             | SDL_MCU_ARMSS_CCMR5_COMPARE_WRAPPER_CFG_MMRS_CCMSR1_CMPE1_MASK)
-											
+
 #define        SDL_ESM_CCM_0_SELF_TEST_ERR_INT   83U
    /**< R5F0 CCM Interrupt source Self test error */
 #define        SDL_ESM_CCM_0_LOCKSTEP_COMPARE   84U
@@ -68,7 +69,7 @@ volatile bool Erroresm = false;
    /**< R5F0 VIM Interrupt source Self test error */
 #define        SDL_ESM_R5F1_VIM_COMPARE_ERR_INT   75U
    /**< R5F1 VIM Interrupt lockstep error */
-   
+
 #define SDL_INTR_PRIORITY_LVL             1U
 #define SDL_ENABLE_ERR_PIN                1U
 #define SDL_ESM_MAX_EVENT_MAP_WORDS       4U
@@ -132,7 +133,7 @@ static int32_t SDL_CCM_CheckSelfTestErrorSource(SDL_CCM_MonitorType *monitorType
     int32_t retVal = SDL_PASS;
 
     /* Read status register of CPU output compare block  */
-    (void)SDL_armR5ReadCCMRegister (BASEADDRESS,
+    (void)SDL_armR5ReadCCMRegister (SDL_CCM_baseAddress[CCMInstance],
                                            SDL_MCU_ARMSS_CCMR5_CCMSR1_REGID,
                                            &statusValue,
                                            NULL);
@@ -143,7 +144,7 @@ static int32_t SDL_CCM_CheckSelfTestErrorSource(SDL_CCM_MonitorType *monitorType
         } else {
 
             /* Read status register of VIM compare block  */
-            (void)SDL_armR5ReadCCMRegister (BASEADDRESS,
+            (void)SDL_armR5ReadCCMRegister (SDL_CCM_baseAddress[CCMInstance],
                                                    SDL_MCU_ARMSS_CCMR5_CCMSR2_REGID,
                                                    &statusValue,
                                                    NULL);
@@ -153,7 +154,7 @@ static int32_t SDL_CCM_CheckSelfTestErrorSource(SDL_CCM_MonitorType *monitorType
              } else {
 
                  /* Read status register of Inactivity monitor block  */
-                 (void)SDL_armR5ReadCCMRegister (BASEADDRESS,
+                 (void)SDL_armR5ReadCCMRegister (SDL_CCM_baseAddress[CCMInstance],
                                                         SDL_MCU_ARMSS_CCMR5_CCMSR3_REGID,
                                                         &statusValue,
                                                         NULL);
@@ -290,7 +291,7 @@ static int32_t SDL_CCM_ESM_callBackFunction (SDL_ESM_Inst instance, SDL_ESM_IntT
 
     /* Read polarity convert register */
     /* Read status register 1 */
-	retVal = SDL_armR5ReadCCMRegister (SDL_CCM_baseAddress[0],
+	retVal = SDL_armR5ReadCCMRegister (SDL_CCM_baseAddress[CCMInstance],
                                         SDL_MCU_ARMSS_CCMR5_POLCNTRL_REGID,
                                         &polarityRegValue,
                                         NULL);
@@ -298,7 +299,7 @@ static int32_t SDL_CCM_ESM_callBackFunction (SDL_ESM_Inst instance, SDL_ESM_IntT
 	{
 	    if(polarityRegValue != (uint32_t)0U) {
 	        /* If polarity reverted; switch back to 0 */
-					(void)SDL_armR5ConfigureCCMRegister(SDL_CCM_baseAddress[0],
+					(void)SDL_armR5ConfigureCCMRegister(SDL_CCM_baseAddress[CCMInstance],
 	                                                   SDL_MCU_ARMSS_CCMR5_POLCNTRL_REGID,
 	                                                   0u,
 	                                                       NULL);
@@ -318,7 +319,7 @@ static int32_t SDL_CCM_ESM_callBackFunction (SDL_ESM_Inst instance, SDL_ESM_IntT
 
     if (retVal == SDL_PASS) {
         /* Read status register 1 */
-        (void)SDL_armR5ReadCCMRegister (SDL_CCM_baseAddress[0],
+        (void)SDL_armR5ReadCCMRegister (SDL_CCM_baseAddress[CCMInstance],
                                                monitorTypeStatusRegister,
                                                &status,
                                                NULL);
@@ -330,7 +331,7 @@ static int32_t SDL_CCM_ESM_callBackFunction (SDL_ESM_Inst instance, SDL_ESM_IntT
     if (retVal == SDL_PASS) {
         /* Read polarity convert register */
          /* Read status register 1 */
-         retVal = SDL_armR5ReadCCMRegister (SDL_CCM_baseAddress[0],
+         retVal = SDL_armR5ReadCCMRegister (SDL_CCM_baseAddress[CCMInstance],
                                                 monitorTypeKeyRegister,
                                                 &keyRegValue,
                                                 NULL);
@@ -339,13 +340,13 @@ static int32_t SDL_CCM_ESM_callBackFunction (SDL_ESM_Inst instance, SDL_ESM_IntT
     if (retVal == SDL_PASS) {
         if (keyRegValue == (uint32_t)SDL_MCU_ARMSS_CCMR5_MKEY_SELF_TEST_MODE) {
             /* Switch it back to active mode */
-            (void)SDL_armR5ConfigureCCMRegister(SDL_CCM_baseAddress[0],
+            (void)SDL_armR5ConfigureCCMRegister(SDL_CCM_baseAddress[CCMInstance],
                                                        monitorTypeKeyRegister,
                                                        ((uint32_t)SDL_MCU_ARMSS_CCMR5_MKEY_CMP_MODE_ACTIVE),
                                                        NULL);
         }
             /* Clear status register */
-        retVal = SDL_armR5ConfigureCCMRegister (SDL_CCM_baseAddress[0],
+        retVal = SDL_armR5ConfigureCCMRegister (SDL_CCM_baseAddress[CCMInstance],
                                                        monitorTypeStatusRegister,
                                                        status,
                                                     NULL);
@@ -590,12 +591,15 @@ int32_t SDL_CCM_selfTest (SDL_CCM_Inst instance,
     uint32_t timesCount=0;
     SDL_McuArmssCcmR5RegId monitorTypeKeyRegister;
     SDL_McuArmssCcmR5RegId monitorTypeStatusRegister;
+
+
     if((instance >= SDL_CCM_MAX_INSTANCE) || (monitorType > SDL_CCM_MONITOR_TYPE_INACTIVITY_MONITOR))
     {
         sdlResult = SDL_EBADARGS;
     }
     else
     {
+        CCMInstance = instance;
         /* Get the Key register for the monitor type */
         sdlResult = SDL_CCM_getMonitorKeyRegister(monitorType, &monitorTypeKeyRegister);
     }
@@ -862,24 +866,24 @@ int32_t SDL_VIM_cfgIntr( SDL_vimRegs *pRegs, uint32_t intrNum, uint32_t pri, SDL
 				(((vecAddr - (uint32_t)1U) & SDL_VIM_VEC_INT_VAL_MASK) == (vecAddr - (uint32_t)1U))) )
 		{
 			bitNum = intrNum & (SDL_VIM_NUM_INTRS_PER_GROUP-1U);
-	
+
 			/* Configure INTMAP */
 			regMask = (uint32_t)(1U) << bitNum;
 			regVal = SDL_REG32_RD( &pRegs->GRP[groupNum].INTMAP );
 			regVal &= ~regMask;
 			regVal |= intrMap;
 			SDL_REG32_WR( &pRegs->GRP[groupNum].INTMAP, regVal );
-	
+
 			/* Configure INTTYPE */
 			regMask = (uint32_t)(1U) << bitNum;
 			regVal = SDL_REG32_RD( &pRegs->GRP[groupNum].INTTYPE );
 			regVal &= ~regMask;
 			regVal |= intrType << bitNum;
 			SDL_REG32_WR( &pRegs->GRP[groupNum].INTTYPE, regVal );
-	
+
 			/* Configure PRI */
 			SDL_REG32_WR( &pRegs->PRI[intrNum].INT, SDL_FMK( VIM_PRI_INT_VAL, pri ) );
-	
+
 			/* Configure VEC */
 			SDL_REG32_WR( &pRegs->VEC[intrNum].INT, vecAddr );
 				retVal = SDL_PASS;
@@ -903,7 +907,7 @@ int32_t SDL_VIM_verifyCfgIntr( SDL_vimRegs *pRegs, uint32_t intrNum, uint32_t pr
     {
         maxIntrs   = pRegs->INFO;
         groupNum = intrNum / SDL_VIM_NUM_INTRS_PER_GROUP;
-    
+
 		/* Condition "(vecAddr - 1U)" is need for THUMB Mode as TI ARM CLANG marks LSB as '1' */
 		if( (intrNum < maxIntrs)                              &&
 			(pri <= SDL_VIM_PRI_INT_VAL_MAX)                  &&
@@ -913,22 +917,22 @@ int32_t SDL_VIM_verifyCfgIntr( SDL_vimRegs *pRegs, uint32_t intrNum, uint32_t pr
 				(((vecAddr - (uint32_t)1U) & SDL_VIM_VEC_INT_VAL_MASK) == (vecAddr - (uint32_t)1U))))
 		{
 			bitNum = intrNum & (SDL_VIM_NUM_INTRS_PER_GROUP-1U);
-	
+
 			/* Read INTMAP */
 			intrMapVal  = SDL_REG32_RD( &pRegs->GRP[groupNum].INTMAP );
 			/* Get the interrupt map value */
 			intrMapVal  = intrMapVal >> bitNum;
 			intrMapVal &= (uint32_t)(0x1U);
-	
+
 			/* Read INTTYPE */
 			intrTypeVal  = SDL_REG32_RD( &pRegs->GRP[groupNum].INTTYPE );
 			/* Get the interrupt type value */
 			intrTypeVal  = intrTypeVal >> bitNum;
 			intrTypeVal &= (uint32_t)(0x1U);
-	
+
 			/* Read PRI */
 			priVal = SDL_REG32_RD( &pRegs->PRI[intrNum].INT);
-	
+
 			/* Read VEC */
 			vecVal = SDL_REG32_RD( &pRegs->VEC[intrNum].INT);
 				retVal = SDL_PASS;
@@ -938,7 +942,7 @@ int32_t SDL_VIM_verifyCfgIntr( SDL_vimRegs *pRegs, uint32_t intrNum, uint32_t pr
     if (retVal != SDL_EFAIL)
     {
         /* verify if parameter matches */
-        if ((intrMapVal != intrMap) || 
+        if ((intrMapVal != intrMap) ||
 			(intrTypeVal != (uint32_t)intrType) ||
 			(priVal != pri) ||
 			(vecVal != vecAddr))
diff --git a/source/sdl/r5/v0/sdl_r5_utils.S b/source/sdl/r5/v0/sdl_r5_utils.S
index 72e37bfb68..6fea3d3a0c 100644
--- a/source/sdl/r5/v0/sdl_r5_utils.S
+++ b/source/sdl/r5/v0/sdl_r5_utils.S
@@ -45,6 +45,517 @@
 ******************************************************************************/
     .text
 
+/*==============================================================================
+*   Get the device ID code that contains information about the processor
+==============================================================================*/
+    .global SDL_UTILS_getMIDR
+SDL_UTILS_getMIDR:
+    MRC p15, #0, r0, c0, c0, #0
+    BX      lr
+
+/*==============================================================================
+*   Get the instruction and data minimum line length in bytes, to enable a range
+    of addresses to be invalidated.
+==============================================================================*/
+    .global SDL_UTILS_getCTR
+SDL_UTILS_getCTR:
+    MRC p15, #0, r0, c0, c0, #1
+    BX      lr
+
+/*==============================================================================
+*   Informs the processor of the number of ATCMs and BTCMs in the system
+==============================================================================*/
+    .global SDL_UTILS_getTCMTR
+SDL_UTILS_getTCMTR:
+    MRC p15, #0, r0, c0, c0, #2
+    BX      lr
+
+/*==============================================================================
+*   Get the value for the number of instruction and data memory regions
+    implemented in the processor.
+==============================================================================*/
+    .global SDL_UTILS_getMPUIR
+SDL_UTILS_getMPUIR:
+    MRC p15, #0, r0, c0, c0, #4
+    BX      lr
+
+/*==============================================================================
+*   Enables CPUs to be recognized and characterized within a twin-CPU system.
+==============================================================================*/
+    .global SDL_UTILS_getMPIDR
+SDL_UTILS_getMPIDR:
+    MRC p15, #0, r0, c0, c0, #5
+    BX      lr
+
+/*==============================================================================
+*   Provides information about the execution state support and programmers model
+    for the processor.(Processor Feature Register 0)
+==============================================================================*/
+    .global SDL_UTILS_getPFR0
+SDL_UTILS_getPFR0:
+    MRC p15, #0, r0, c0, c1, #0
+    BX      lr
+
+/*==============================================================================
+*   Provides information about the execution state support and programmers model
+    for the processor.(Processor Feature Register 1)
+==============================================================================*/
+    .global SDL_UTILS_getPFR1
+SDL_UTILS_getPFR1:
+    MRC p15, #0, r0, c0, c1, #1
+    BX      lr
+
+/*==============================================================================
+*   Provides information about the execution state support and programmers model
+    for the processor.(Processor Feature Register 1)
+==============================================================================*/
+    .global SDL_UTILS_getID_DFR0
+SDL_UTILS_getID_DFR0:
+    MRC p15, #0, r0, c0, c1, #2
+    BX      lr
+
+/*==============================================================================
+*   Provides additional information about the features of the processor.
+==============================================================================*/
+    .global SDL_UTILS_getID_AFR0
+SDL_UTILS_getID_AFR0:
+    MRC p15, #0, r0, c0, c1, #3
+    BX      lr
+
+/*==============================================================================
+*   The ID_MMFR0 provides information about the memory model, memory management,
+     and cache support operations of the processor.
+==============================================================================*/
+    .global SDL_UTILS_getID_MMFR0
+SDL_UTILS_getID_MMFR0:
+    MRC p15, #0, r0, c0, c1, #4
+    BX      lr
+
+/*==============================================================================
+*   The ID_MMFR1 provides information about the memory model, memory management,
+     and cache support operations of the processor.
+==============================================================================*/
+    .global SDL_UTILS_getID_MMFR1
+SDL_UTILS_getID_MMFR1:
+    MRC p15, #0, r0, c0, c1, #5
+    BX      lr
+
+/*==============================================================================
+*   The ID_MMFR2 provides information about the memory model, memory management,
+     and cache support operations of the processor.
+==============================================================================*/
+    .global SDL_UTILS_getID_MMFR2
+SDL_UTILS_getID_MMFR2:
+    MRC p15, #0, r0, c0, c1, #6
+    BX      lr
+
+/*==============================================================================
+*   The ID_MMFR3 provides information about the memory model, memory management,
+     and cache support operations of the processor.
+==============================================================================*/
+    .global SDL_UTILS_getID_MMFR3
+SDL_UTILS_getID_MMFR3:
+    MRC p15, #0, r0, c0, c1, #7
+    BX      lr
+
+/*==============================================================================
+*   The ID_ISAR0 Provides information about the instruction set that the processor
+    supports,beyond the basic set.
+==============================================================================*/
+    .global SDL_UTILS_getID_ISAR0
+SDL_UTILS_getID_ISAR0:
+    MRC p15, #0, r0, c0, c2, #0
+    BX      lr
+
+/*==============================================================================
+*   The ID_ISAR1 Provides information about the instruction set that the processor
+    supports,beyond the basic set.
+==============================================================================*/
+    .global SDL_UTILS_getID_ISAR1
+SDL_UTILS_getID_ISAR1:
+    MRC p15, #0, r0, c0, c2, #1
+    BX      lr
+
+/*==============================================================================
+*   The ID_ISAR2 Provides information about the instruction set that the processor
+    supports,beyond the basic set.
+==============================================================================*/
+    .global SDL_UTILS_getID_ISAR2
+SDL_UTILS_getID_ISAR2:
+    MRC p15, #0, r0, c0, c2, #2
+    BX      lr
+
+/*==============================================================================
+*   The ID_ISAR3 Provides information about the instruction set that the processor
+    supports,beyond the basic set.
+==============================================================================*/
+    .global SDL_UTILS_getID_ISAR3
+SDL_UTILS_getID_ISAR3:
+    MRC p15, #0, r0, c0, c2, #3
+    BX      lr
+
+/*==============================================================================
+*   The ID_ISAR4 Provides information about the instruction set that the processor
+    supports,beyond the basic set.
+==============================================================================*/
+    .global SDL_UTILS_getID_ISAR4
+SDL_UTILS_getID_ISAR4:
+    MRC p15, #0, r0, c0, c2, #4
+    BX      lr
+
+/*==============================================================================
+*   The ID_ISAR5 Provides information about the instruction set that the processor
+    supports,beyond the basic set.
+==============================================================================*/
+    .global SDL_UTILS_getID_ISAR5
+SDL_UTILS_getID_ISAR5:
+    MRC p15, #0, r0, c0, c2, #5
+    BX      lr
+
+/*==============================================================================
+*   The CCSIDR Provides information about the size and behavior of the
+    instruction or data cache. Architecturally, there can be up to eight levels of
+    cache, containing instruction, data, or unified caches. This processor contains
+    L1 instruction and data caches only. The CSSELR determines which CCSIDR to select.
+==============================================================================*/
+    .global SDL_UTILS_getCCSIDR
+SDL_UTILS_getCCSIDR:
+    MRC p15, #1, r0, c0, c0, #0
+    BX      lr
+
+/*==============================================================================
+*   The CLIDR have the following purpose-
+*   Indicates the cache levels that are implemented. Architecturally,
+    there can be a different number of cache levels on the instruction and data side.
+*   Captures the point-of-coherency.
+*   Captures the point-of-unification.
+==============================================================================*/
+    .global SDL_UTILS_getCLIDR
+SDL_UTILS_getCLIDR:
+    MRC p15, #1, r0, c0, c0, #1
+    BX      lr
+
+/*==============================================================================
+*   Provides additional information about the features of the processor.
+==============================================================================*/
+    .global SDL_UTILS_getAIDR
+SDL_UTILS_getAIDR:
+    MRC p15, #1, r0, c0, c0, #7
+    BX      lr
+
+/*==============================================================================
+*   Get the value that the processor uses to select the CSSELR to use
+==============================================================================*/
+    .global SDL_UTILS_getCSSELR
+SDL_UTILS_getCSSELR:
+    MRC p15, #2, r0, c0, c0, #0
+    BX      lr
+
+/*==============================================================================
+*   The SCTLR Provides control and configuration information for-
+*   memory alignment, endianness, protection, and fault behavior.
+*   MPU and cache enables and cache replacement strategy.
+*   interrupts and the behavior of interrupt latency.
+*   the location for exception vectors.
+*   program flow prediction.
+==============================================================================*/
+    .global SDL_UTILS_getSCTLR
+SDL_UTILS_getSCTLR:
+    MRC p15, #0, r0, c1, c0, #0
+    BX      lr
+
+/*==============================================================================
+*   The ACTLR Provides control for-
+*   branch prediction.
+*   performance features.
+*   error and parity logic.
+==============================================================================*/
+    .global SDL_UTILS_getACTLR
+SDL_UTILS_getACTLR:
+    MRC p15, #0, r0, c1, c0, #1
+    BX      lr
+
+/*==============================================================================
+*   The Secondary ACTLR Provides control for-
+*   branch prediction.
+*   performance features.
+*   error and parity logic.
+==============================================================================*/
+    .global SDL_UTILS_getSecondaryACTLR
+SDL_UTILS_getSecondaryACTLR:
+    MRC p15, #0, r0, c15, c0, #0
+    BX      lr
+
+/*==============================================================================
+*  The CPACR characteristics are-
+*  Sets access rights for coprocessors.
+==============================================================================*/
+    .global SDL_UTILS_getCPACR
+SDL_UTILS_getCPACR:
+    MRC p15, #0, r0, c1, c0, #2
+    BX      lr
+
+/*==============================================================================
+*  The MPU Region Base Address Register characteristics are:
+*  Describes the base address of the region specified by the Memory Region Number Register.
+==============================================================================*/
+    .global SDL_UTILS_getMPURegionBaseADDR
+SDL_UTILS_getMPURegionBaseADDR:
+    MRC p15, #0, r0, c6, c1, #0
+    BX      lr
+
+/*==============================================================================
+*  The MPU Region Size and Enable Register characteristics are:
+*  Specifies the size of the region specified by the Memory Region Number Register.
+*  Identifies the address ranges that are used for a particular region.
+*  Enables or disables the region, and its sub-regions, specified by the Memory
+    Region Number Register.
+==============================================================================*/
+    .global SDL_UTILS_getMPURegionEnableR
+SDL_UTILS_getMPURegionEnableR:
+    MRC p15, #0, r0, c6, c1, #2
+    BX      lr
+
+/*==============================================================================
+*  The MPU Region Access Control Register characteristics are:
+*  Holds the region attributes and access permissions for the region specified
+   by the Memory Region Number Register.
+==============================================================================*/
+    .global SDL_UTILS_getMPURegionAccessControlR
+SDL_UTILS_getMPURegionAccessControlR:
+    MRC p15, #0, r0, c6, c1, #4
+    BX      lr
+
+/*==============================================================================
+*  The RGNRs characteristics are:
+*  Multiple registers with one register for each memory region implemented.
+ The value contained in the RGNR determines which of the multiple registers is accessed.
+==============================================================================*/
+    .global SDL_UTILS_getRGNR
+SDL_UTILS_getRGNR:
+    MRC p15, #0, r0, c6, c2, #0
+    BX      lr
+
+/*==============================================================================
+*  The BTCM Region Register characteristics are:
+*  Holds the base address and size of the BTCM.
+*  Determines if the BTCM is enabled.
+==============================================================================*/
+    .global SDL_UTILS_getBTCMRegionR
+SDL_UTILS_getBTCMRegionR:
+    MRC p15, #0, r0, c9, c1, #0
+    BX      lr
+
+/*==============================================================================
+*  The ATCM Region Register characteristics are:
+*  Holds the base address and size of the ATCM.
+*  Determines if the ATCM is enabled.
+==============================================================================*/
+    .global SDL_UTILS_getATCMRegionR
+SDL_UTILS_getATCMRegionR:
+    MRC p15, #0, r0, c9, c1, #1
+    BX      lr
+
+/*==============================================================================
+*  The Slave Port Control Register characteristics are:
+*  Enables or disables TCM access to the AXI slave port in Privileged or User mode.
+*  Enables access to the cache RAMs through the AXI slave port.
+    See c1, Auxiliary Control Register.
+==============================================================================*/
+    .global SDL_UTILS_getSlavePortControlR
+SDL_UTILS_getSlavePortControlR:
+    MRC p15, #0, r0, c11, c0, #0
+    BX      lr
+
+/*==============================================================================
+*  The CONTEXTIDR characteristics are:
+*  Holds a process IDentification (ID) value for the running process.
+*  The Embedded Trace Macrocell (ETM) and the debug logic use this register.
+   The ETM can broadcast its value to indicate the process that is running.
+   You must program each process with a unique number.
+*   Enables process dependent breakpoints and instructions.
+==============================================================================*/
+    .global SDL_UTILS_getCONTEXTIDR
+SDL_UTILS_getCONTEXTIDR:
+    MRC p15, #0, r0, c13, c0, #1
+    BX      lr
+
+/*==============================================================================
+*  The Thread and Process ID Registers provide locations to store the IDs
+   of software threads and processes for Operating System (OS) management purposes.
+==============================================================================*/
+    .global SDL_UTILS_getThreadProcessIDR1
+SDL_UTILS_getThreadProcessIDR1:
+    MRC p15, #0, r0, c13, c0, #2
+    BX      lr
+
+/*==============================================================================
+*  The Thread and Process ID Registers provide locations to store the IDs
+   of software threads and processes for Operating System (OS) management purposes.
+==============================================================================*/
+    .global SDL_UTILS_getThreadProcessIDR2
+SDL_UTILS_getThreadProcessIDR2:
+    MRC p15, #0, r0, c13, c0, #3
+    BX      lr
+
+/*==============================================================================
+*  The Thread and Process ID Registers provide locations to store the IDs
+   of software threads and processes for Operating System (OS) management purposes.
+==============================================================================*/
+    .global SDL_UTILS_getThreadProcessIDR3
+SDL_UTILS_getThreadProcessIDR3:
+    MRC p15, #0, r0, c13, c0, #4
+    BX      lr
+
+/*==============================================================================
+*  The nVAL IRQ Enable Set Register characteristics are:
+*  Enables any of the PMXEVCNTR Registers, PMXEVCNTR0-PMXEVCNTR2, and CCNT,
+  to generate an interrupt request on overflow. If enabled, the interrupt request
+  is signaled by nVALIRQm being asserted LOW.
+==============================================================================*/
+    .global SDL_UTILS_getnVALIRQSET
+SDL_UTILS_getnVALIRQSET:
+    MRC p15, #0, r0, c15, c1, #0
+    BX      lr
+
+/*==============================================================================
+*  The nVAL FIQ Enable Set Register are:
+* Enables any of the PMXEVCNTR Registers, PMXEVCNTR0-PMXEVCNTR2, and CCNT,
+  to generate an fast interrupt request on overflow. If enabled, the interrupt
+  request is signaled by nVALFIQm being asserted LOW..
+==============================================================================*/
+    .global SDL_UTILS_getnVALFIQSET
+SDL_UTILS_getnVALFIQSET:
+    MRC p15, #0, r0, c15, c1, #1
+    BX      lr
+
+/*==============================================================================
+*  The nVAL RESET Enable Set Register are:
+* Enables any of the PMXEVCNTR Registers, PMXEVCNTR0-PMXEVCNTR2, and CCNT,
+  to generate a reset request on overflow. If enabled, the reset
+  request is signaled by nVALRESETm being asserted LOW..
+==============================================================================*/
+    .global SDL_UTILS_getnVALRESETSET
+SDL_UTILS_getnVALRESETSET:
+    MRC p15, #0, r0, c15, c1, #2
+    BX      lr
+
+/*==============================================================================
+*  The VAL Debug Request Enable Set Register characteristics are:
+* Enables any of the PMXEVCNTR Registers, PMXEVCNTR0-PMXEVCNTR2, and CCNT,
+  to generate a debug request on overflow. If enabled, the debug
+  request is signaled by VALEDBGRQm being asserted HIGH.
+==============================================================================*/
+    .global SDL_UTILS_getnVALDEBUGSET
+SDL_UTILS_getnVALDEBUGSET:
+    MRC p15, #0, r0, c15, c1, #3
+    BX      lr
+
+/*==============================================================================
+*  The VAL IRQ Enable Clear Register characteristics are:
+* Disables overflow IRQ requests from any of the PMXEVCNTR Registers,
+ PMXEVCNTR0-PMXEVCNTR2, and CCNT, for which they have been enabled.
+==============================================================================*/
+    .global SDL_UTILS_getnVALIRQCLEAR
+SDL_UTILS_getnVALIRQCLEAR:
+    MRC p15, #0, r0, c15, c1, #4
+    BX      lr
+
+/*==============================================================================
+*  The nVAL FIQ Enable Clear Register characteristics are:
+* Disables overflow FIQ requests from any of the PMXEVCNTR Registers,
+ PMXEVCNTR0-PMXEVCNTR2, and CCNT, for which they have been enabled.
+==============================================================================*/
+    .global SDL_UTILS_getnVALFIQCLEAR
+SDL_UTILS_getnVALFIQCLEAR:
+    MRC p15, #0, r0, c15, c1, #5
+    BX      lr
+
+/*==============================================================================
+* The nVAL Reset Enable Clear Register characteristics are:
+* Disables overflow reset requests from any of the PMXEVCNTR Registers,
+  PMXEVCNTR0-PMXEVCNTR2, and CCNT, that are enabled..
+==============================================================================*/
+    .global SDL_UTILS_getnVALRESETCLEAR
+SDL_UTILS_getnVALRESETCLEAR:
+    MRC p15, #0, r0, c15, c1, #6
+    BX      lr
+
+/*==============================================================================
+*  The VAL Debug Request Enable Clear Register characteristics are:
+*  Disables overflow debug requests from any of the PMXEVCNTR Registers,
+   PMXEVCNTR0-PMXEVCNTR2, and CCNT, that are enabled.
+==============================================================================*/
+    .global SDL_UTILS_getnVALDEBUGCLEAR
+SDL_UTILS_getnVALDEBUGCLEAR:
+    MRC p15, #0, r0, c15, c1, #3
+    BX      lr
+
+
+/*==============================================================================
+*  The Build Options 1 Register characteristics are:
+*  Reflects the build configuration options used to build the processor.
+==============================================================================*/
+    .global SDL_UTILS_getBuildOption1R
+SDL_UTILS_getBuildOption1R:
+    MRC p15, #0, r0, c15, c2, #0
+    BX      lr
+
+/*==============================================================================
+*  The Build Options 2 Register characteristics are:
+*  Reflects the build configuration options used to build the processor.
+==============================================================================*/
+    .global SDL_UTILS_getBuildOption2R
+SDL_UTILS_getBuildOption2R:
+    MRC p15, #0, r0, c15, c2, #1
+    BX      lr
+
+/*==============================================================================
+*  The Pin Options Register characteristics are:
+*  Describes the value of any pins that control processor options,
+   that are not visible because they:
+*  are exposed in registers.
+*  control the initial value of control registers, and are visible in that way.
+==============================================================================*/
+    .global SDL_UTILS_getPinOptionR
+SDL_UTILS_getPinOptionR:
+    MRC p15, #0, r0, c15, c2, #7
+    BX      lr
+
+/*==============================================================================
+*  The Peripheral Interface Region Register characteristics are:
+*  Describe the size and base of the interface, and contain an enable bit for
+   the interface
+   Read LLPP Normal AXI region register
+==============================================================================*/
+    .global SDL_UTILS_getLLPPnormalAXIRR
+SDL_UTILS_getLLPPnormalAXIRR:
+    MRC p15, #0, r0, c15, c0, #1
+    BX      lr
+
+/*==============================================================================
+*  The Peripheral Interface Region Register characteristics are:
+*  Describe the size and base of the interface, and contain an enable bit for
+   the interface
+    Read LLPP Virtual AXI region register
+==============================================================================*/
+    .global SDL_UTILS_getLLPPvirtualAXIRR
+SDL_UTILS_getLLPPvirtualAXIRR:
+    MRC p15, #0, r0, c15, c0, #2
+    BX      lr
+
+/*==============================================================================
+*  The Peripheral Interface Region Register characteristics are:
+*  Describe the size and base of the interface, and contain an enable bit for
+   the interface
+   Read AHB peripheral interface region register
+==============================================================================*/
+    .global SDL_UTILS_getAHBRR
+SDL_UTILS_getAHBRR:
+    MRC p15, #0, r0, c15, c0, #3
+    BX      lr
+
+
 /*==============================================================================
 *   Get Correctable Fault Location Register (CFLR) value
 ==============================================================================*/
@@ -69,6 +580,14 @@ SDL_UTILS_getDFSR:
     MRC p15, #0, r0, c5, c0, #0
     BX      lr
 
+/*==============================================================================
+*   Get Data Fault Status Register (ADFSR) value
+==============================================================================*/
+    .global SDL_UTILS_getADFSR
+SDL_UTILS_getADFSR:
+    MRC p15, #0, r0, c5, c1, #0
+    BX      lr
+
 /*==============================================================================
 *   Get Data Fault Address Register (DFAR) value
 ==============================================================================*/
@@ -85,6 +604,14 @@ SDL_UTILS_getIFSR:
     MRC p15, #0, r0, c5, c0, #1
     BX      lr
 
+/*==============================================================================
+*   Get Instruction Fault Status Register Register (AIFSR) value
+==============================================================================*/
+    .global SDL_UTILS_getAIFSR
+SDL_UTILS_getAIFSR:
+    MRC p15, #0, r0, c5, c1, #1
+    BX      lr
+
 /*==============================================================================
 *   Get Instruction Fault Address Register Register (IFAR) value
 ==============================================================================*/
@@ -96,8 +623,8 @@ SDL_UTILS_getIFAR:
 /*****************************************************************************
 * Enable Event Bus
 ******************************************************************************/
-	.global SDL_UTILS_enable_event_bus 
-SDL_UTILS_enable_event_bus: 
+	.global SDL_UTILS_enable_event_bus
+SDL_UTILS_enable_event_bus:
 	ORR r1,r1,#0x7 << 25           	/* Don't need to force dpu_tcm_check_parity_en_o */
 	MCR p15, #0, r1, c1, c0, #1   	/* ACTLR enable ECC for cache */
 	MRC p15, #0, r0, c1, c0, #0   	/* Read System Control Register */
@@ -106,12 +633,12 @@ SDL_UTILS_enable_event_bus:
 	ORR R5, R5, #0x11
 	MCR P15,#0, R5, C9, C12,#0
 	BX      lr
-	
+
 /*****************************************************************************
 * Enable Cache Event Bus
 ******************************************************************************/
-	.global SDL_UTILS_enable_cache_event_bus 
-SDL_UTILS_enable_cache_event_bus: 
+	.global SDL_UTILS_enable_cache_event_bus
+SDL_UTILS_enable_cache_event_bus:
     MRC P15,#0, R5, C9, C12,#0      /* enable export of events to Eventbus for monitoring */
     ORR R5, R5, #0x11
     MCR P15,#0, R5, C9, C12,#0
diff --git a/source/sdl/r5/v0/sdl_r5_utils.h b/source/sdl/r5/v0/sdl_r5_utils.h
index 952745338f..235c1add12 100644
--- a/source/sdl/r5/v0/sdl_r5_utils.h
+++ b/source/sdl/r5/v0/sdl_r5_utils.h
@@ -34,19 +34,274 @@
  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  */
-#include <stdint.h>
+
+/**
+ *
+ *  \defgroup SDL_R5FCPU_API SDL R5F CPU UTILS
+ *  \ingroup SDL_MODULE
+ *
+ *   Provides the APIs for R5F CPU STATIC REGISTER READ.
+ *  @{
+ */
+
+/**
+ *  \file     sdl_r5_utils.h
+ *
+ *  \brief    This file contains the prototypes of the APIs present in the
+ *            device abstraction layer file of R5F CPU static register.
+ *            This also contains some related local functions.
+ */
+
 #ifndef INCLUDE_SDL_UTILS_H_
 #define INCLUDE_SDL_UTILS_H_
 
-uint32_t SDL_UTILS_getCFLR(void);
+/* ========================================================================== */
+/*                             Include Files                                  */
+/* ========================================================================== */
 
-uint32_t SDL_UTILS_getPMOVSR(void);
+#include <stdint.h>
+#include <sdl/include/sdl_types.h>
+
+
+/**
+@defgroup SDL_R5FCPU_StaticRegisterRead_FUNCTIONS R5F CPU Static Register Read Functions
+@ingroup SDL_R5FCPU_API
+*/
+
+/**
+@defgroup SDL_R5FCPU_DATASTRUCT R5F CPU STATIC REGISTER Data Structures
+@ingroup SDL_R5FCPU_API
+*/
+
+/* ========================================================================== */
+/*                         Structures                                         */
+/* ========================================================================== */
+
+/**
+
+@addtogroup SDL_R5FCPU_DATASTRUCT
+@{
+*/
 
-uint32_t SDL_UTILS_getDFSR( void );
-uint32_t SDL_UTILS_getDFAR( void );
+/**
+ * \brief Structure containing R5F CPU Static Registers
+ *
+ * Design: PROC_SDL-6331
+ *
+ */
+typedef struct {
+    uint32_t MIDR;
+    /* MIDR register */
+    uint32_t CTR;
+    /* CTR register */
+    uint32_t TCMTR;
+    /* TCMTR register */
+    uint32_t MPUIR;
+    /* MPUIR register */
+    uint32_t MPIDR;
+    /* MPIDR register */
+    uint32_t PFR0;
+    /* PFR0 register */
+    uint32_t PFR1;
+    /* PFR1 register */
+    uint32_t ID_DFR0;
+    /* ID_DFR0 register */
+    uint32_t ID_AFR0;
+    /* ID_AFR0 register */
+    uint32_t ID_MMFR0;
+    /* ID_MMFR0 register */
+    uint32_t ID_MMFR1;
+    /* ID_MMFR1 register */
+    uint32_t ID_MMFR2;
+    /* ID_MMFR2 register */
+    uint32_t ID_MMFR3;
+    /* ID_MMFR3 register */
+    uint32_t ID_ISAR0;
+    /* ID_ISAR0 register */
+    uint32_t ID_ISAR1;
+    /* ID_ISAR1 register */
+    uint32_t ID_ISAR2;
+    /* ID_ISAR2 register */
+    uint32_t ID_ISAR3;
+    /* ID_ISAR3 register */
+    uint32_t ID_ISAR4;
+    /* ID_ISAR4 register */
+    uint32_t ID_ISAR5;
+    /* ID_ISAR5 register */
+    uint32_t CCSIDR;
+    /* CCSIDR register */
+    uint32_t CLIDR;
+    /* CLIDR register */
+    uint32_t AIDR;
+    /* AIDR register */
+    uint32_t CSSELR;
+    /* CSSELR register */
+    uint32_t SCTLR;
+    /* SCTLR register */
+    uint32_t ACTLR;
+    /* ACTLR register */
+    uint32_t SecondaryACTLR;
+    /* SecondaryACTLR register */
+    uint32_t CPACR;
+    /* CPACR register */
+    uint32_t MPURegionBaseADDR;
+    /* MPURegionBaseADDR register */
+    uint32_t MPURegionEnableR;
+    /* MPURegionEnableR register */
+    uint32_t MPURegionAccessControlR;
+    /* MPURegionAccessControlR register */
+    uint32_t RGNR;
+    /* RGNR register */
+    uint32_t BTCMRegionR;
+    /* BTCMRegionR register */
+    uint32_t ATCMRegionR;
+    /* ATCMRegionR register */
+    uint32_t SlavePortControlR;
+    /* SlavePortControlR register */
+    uint32_t CONTEXTIDR;
+    /* CONTEXTIDR register */
+    uint32_t ThreadProcessIDR1;
+    /* ThreadProcessIDR1 register */
+    uint32_t ThreadProcessIDR2;
+    /* ThreadProcessIDR2 register */
+    uint32_t ThreadProcessIDR3;
+    /* ThreadProcessIDR3 register */
+    uint32_t nVALIRQSET;
+    /* nVALIRQSET register */
+    uint32_t nVALFIQSET;
+    /* nVALFIQSET register */
+    uint32_t nVALRESETSET;
+    /* nVALRESETSET register */
+    uint32_t nVALDEBUGSET;
+    /* nVALDEBUGSET register */
+    uint32_t nVALIRQCLEAR;
+    /* nVALIRQCLEAR register */
+    uint32_t nVALFIQCLEAR;
+    /* nVALFIQCLEAR register */
+    uint32_t nVALRESETCLEAR;
+    /* nVALRESETCLEAR register */
+    uint32_t nVALDEBUGCLEAR;
+    /* nVALDEBUGCLEAR register */
+    uint32_t BuildOption1R;
+    /* BuildOption1R register */
+    uint32_t BuildOption2R;
+    /* BuildOption2R register */
+    uint32_t PinOptionR;
+    /* PinOptionR register */
+    uint32_t LLPPnormalAXIRR;
+    /* LLPPnormalAXIRR register */
+    uint32_t LLPPvirtualAXIRR;
+    /* LLPPvirtualAXIRR register */
+    uint32_t AHBRR;
+    /* AHBRR register */
+    uint32_t CFLR;
+    /* CFLR register */
+    uint32_t PMOVSR;
+    /* PMOVSR register */
+    uint32_t DFSR;
+    /* DFSR register */
+    uint32_t ADFSR;
+    /* ADFSR register */
+    uint32_t DFAR;
+    /* DFAR register */
+    uint32_t IFSR;
+    /* IFSR register */
+    uint32_t IFAR;
+    /* IFAR register */
+    uint32_t AIFSR;
+    /* AIFSR register */
+
+}SDL_R5FCPU_StaticRegs;
+
+/** @} */
+
+/* ========================================================================== */
+/*                          Function Declarations                             */
+/* ========================================================================== */
+
+/**
+
+@addtogroup SDL_R5FCPU_StaticRegisterRead_FUNCTIONS
+@{
+*/
+
+/**
+ * \brief   This API is used to get the value of static registers for R5F CPU
+ *
+ * \param   pCPUStaticRegs      Pointer to the SDL_R5FCPU_StaticRegs structure.
+ */
+int32_t SDL_CPU_staticRegisterRead(SDL_R5FCPU_StaticRegs *pCPUStaticRegs);
+
+/** @} */
+/** @} */
+
+/* ========================================================================== */
+/*                         Local Function Declarations                             */
+/* ========================================================================== */
+
+
+uint32_t SDL_UTILS_getMIDR(void);
+uint32_t SDL_UTILS_getCTR(void);
+uint32_t SDL_UTILS_getTCMTR(void);
+uint32_t SDL_UTILS_getMPUIR(void);
+uint32_t SDL_UTILS_getMPIDR(void);
+uint32_t SDL_UTILS_getPFR0(void);
+uint32_t SDL_UTILS_getPFR1(void);
+uint32_t SDL_UTILS_getID_DFR0(void);
+uint32_t SDL_UTILS_getID_AFR0(void);
+uint32_t SDL_UTILS_getID_MMFR0(void);
+uint32_t SDL_UTILS_getID_MMFR1(void);
+uint32_t SDL_UTILS_getID_MMFR2(void);
+uint32_t SDL_UTILS_getID_MMFR3(void);
+uint32_t SDL_UTILS_getID_ISAR0(void);
+uint32_t SDL_UTILS_getID_ISAR1(void);
+uint32_t SDL_UTILS_getID_ISAR2(void);
+uint32_t SDL_UTILS_getID_ISAR3(void);
+uint32_t SDL_UTILS_getID_ISAR4(void);
+uint32_t SDL_UTILS_getID_ISAR5(void);
+uint32_t SDL_UTILS_getCCSIDR(void);
+uint32_t SDL_UTILS_getCLIDR(void);
+uint32_t SDL_UTILS_getAIDR(void);
+uint32_t SDL_UTILS_getCSSELR(void);
+uint32_t SDL_UTILS_getSCTLR(void);
+uint32_t SDL_UTILS_getACTLR(void);
+uint32_t SDL_UTILS_getSecondaryACTLR(void);
+uint32_t SDL_UTILS_getCPACR(void);
+uint32_t SDL_UTILS_getMPURegionBaseADDR(void);
+uint32_t SDL_UTILS_getMPURegionEnableR(void);
+uint32_t SDL_UTILS_getMPURegionAccessControlR(void);
+uint32_t SDL_UTILS_getRGNR(void);
+uint32_t SDL_UTILS_getBTCMRegionR(void);
+uint32_t SDL_UTILS_getATCMRegionR(void);
+uint32_t SDL_UTILS_getSlavePortControlR(void);
+uint32_t SDL_UTILS_getCONTEXTIDR(void);
+uint32_t SDL_UTILS_getThreadProcessIDR1(void);
+uint32_t SDL_UTILS_getThreadProcessIDR2(void);
+uint32_t SDL_UTILS_getThreadProcessIDR3(void);
+uint32_t SDL_UTILS_getnVALIRQSET(void);
+uint32_t SDL_UTILS_getnVALFIQSET(void);
+uint32_t SDL_UTILS_getnVALRESETSET(void);
+uint32_t SDL_UTILS_getnVALDEBUGSET(void);
+uint32_t SDL_UTILS_getnVALIRQCLEAR(void);
+uint32_t SDL_UTILS_getnVALFIQCLEAR(void);
+uint32_t SDL_UTILS_getnVALRESETCLEAR(void);
+uint32_t SDL_UTILS_getnVALDEBUGCLEAR(void);
+uint32_t SDL_UTILS_getBuildOption1R(void);
+uint32_t SDL_UTILS_getBuildOption2R(void);
+uint32_t SDL_UTILS_getPinOptionR(void);
+uint32_t SDL_UTILS_getLLPPnormalAXIRR(void);
+uint32_t SDL_UTILS_getLLPPvirtualAXIRR(void);
+uint32_t SDL_UTILS_getAHBRR(void);
+uint32_t SDL_UTILS_getCFLR(void);
+uint32_t SDL_UTILS_getPMOVSR(void);
+uint32_t SDL_UTILS_getDFSR(void);
+uint32_t SDL_UTILS_getADFSR(void);
+uint32_t SDL_UTILS_getDFAR(void);
+uint32_t SDL_UTILS_getIFSR(void);
+uint32_t SDL_UTILS_getIFAR(void);
+uint32_t SDL_UTILS_getAIFSR(void);
 
-uint32_t SDL_UTILS_getIFSR( void );
-uint32_t SDL_UTILS_getIFAR( void );
+/* Some other function not related to CPU Static register*/
 void SDL_UTILS_enable_event_bus(void);
 void SDL_UTILS_enable_cache_event_bus(void);
 
diff --git a/source/sdl/r5/v0/sdl_r5f_utils.c b/source/sdl/r5/v0/sdl_r5f_utils.c
new file mode 100644
index 0000000000..fb792ad103
--- /dev/null
+++ b/source/sdl/r5/v0/sdl_r5f_utils.c
@@ -0,0 +1,246 @@
+/*
+ * SDL CPU STATIC REGISTER
+ *
+ * Software Diagnostics Library module for handling exceptions
+ *
+ *  Copyright (c) Texas Instruments Incorporated 2023
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <stddef.h>
+#include <stdbool.h>
+#include "sdl_r5_utils.h"
+
+/********************************************************************************************************
+ *   API for reading the R5F CPU static registers values
+ *********************************************************************************************************/
+
+/**
+ *  Design: PROC_SDL-6330
+ */
+
+int32_t SDL_CPU_staticRegisterRead(SDL_R5FCPU_StaticRegs *pCPUStaticRegs)
+{
+
+    int32_t sdlResult;
+
+    if (pCPUStaticRegs != NULL)
+    {
+
+        pCPUStaticRegs->MIDR = SDL_UTILS_getMIDR();
+        /* Get The MIDR register value  */
+
+        pCPUStaticRegs->CTR = SDL_UTILS_getCTR();
+        /* Get The CTR register value  */
+
+        pCPUStaticRegs->TCMTR = SDL_UTILS_getTCMTR();
+        /* Get The TCMTR register value  */
+
+        pCPUStaticRegs->MPUIR = SDL_UTILS_getMPUIR();
+        /* Get The MPUIR register value  */
+
+        pCPUStaticRegs->MPIDR = SDL_UTILS_getMPIDR();
+        /* Get The MPIDR register value  */
+
+        pCPUStaticRegs->PFR0 = SDL_UTILS_getPFR0();
+        /* Get The PFR0 register value  */
+
+        pCPUStaticRegs->PFR1 = SDL_UTILS_getPFR1();
+        /* Get The PFR1 register value  */
+
+        pCPUStaticRegs->ID_DFR0 = SDL_UTILS_getID_DFR0();
+        /* Get The ID_DFR0 register value  */
+
+        pCPUStaticRegs->ID_AFR0 = SDL_UTILS_getID_AFR0();
+        /* Get The ID_AFR0 register value  */
+
+        pCPUStaticRegs->ID_MMFR0 = SDL_UTILS_getID_MMFR0();
+        /* Get The ID_MMFR0 register value  */
+
+        pCPUStaticRegs->ID_MMFR1 = SDL_UTILS_getID_MMFR1();
+        /* Get The ID_MMFR1 register value  */
+
+        pCPUStaticRegs->ID_MMFR2 = SDL_UTILS_getID_MMFR2();
+        /* Get The ID_MMFR2 register value  */
+
+        pCPUStaticRegs->ID_MMFR3 = SDL_UTILS_getID_MMFR3();
+        /* Get The ID_MMFR3 register value  */
+
+        pCPUStaticRegs->ID_ISAR0 = SDL_UTILS_getID_ISAR0();
+        /* Get The ID_ISAR0 register value  */
+
+        pCPUStaticRegs->ID_ISAR1 = SDL_UTILS_getID_ISAR1();
+        /* Get The ID_ISAR1 register value  */
+
+        pCPUStaticRegs->ID_ISAR2 = SDL_UTILS_getID_ISAR2();
+        /* Get The ID_ISAR2 register value  */
+
+        pCPUStaticRegs->ID_ISAR3 = SDL_UTILS_getID_ISAR3();
+        /* Get The ID_ISAR3 register value  */
+
+        pCPUStaticRegs->ID_ISAR4 = SDL_UTILS_getID_ISAR4();
+        /* Get The ID_ISAR4 register value  */
+
+        pCPUStaticRegs->ID_ISAR5 = SDL_UTILS_getID_ISAR5();
+        /* Get The ID_ISAR5 register value  */
+
+        pCPUStaticRegs->CCSIDR = SDL_UTILS_getCCSIDR();
+        /* Get The CCSIDR register value  */
+
+        pCPUStaticRegs->CLIDR = SDL_UTILS_getCLIDR();
+        /* Get The CLIDR register value  */
+
+        pCPUStaticRegs->AIDR = SDL_UTILS_getAIDR();
+        /* Get The AIDR register value  */
+
+        pCPUStaticRegs->CSSELR = SDL_UTILS_getCSSELR();
+        /* Get The CSSELR register value  */
+
+        pCPUStaticRegs->SCTLR = SDL_UTILS_getSCTLR();
+        /* Get The SCTLR register value  */
+
+        pCPUStaticRegs->ACTLR = SDL_UTILS_getACTLR();
+        /* Get The ACTLR register value  */
+
+        pCPUStaticRegs->SecondaryACTLR = SDL_UTILS_getSecondaryACTLR();
+        /* Get The SecondaryACTLR register value  */
+
+        pCPUStaticRegs->CPACR = SDL_UTILS_getCPACR();
+        /* Get The CPACR register value  */
+
+        pCPUStaticRegs->MPURegionBaseADDR = SDL_UTILS_getMPURegionBaseADDR();
+        /* Get The MPURegionBaseADDR register value  */
+
+        pCPUStaticRegs->MPURegionEnableR = SDL_UTILS_getMPURegionEnableR();
+        /* Get The MPURegionEnableR register value  */
+
+        pCPUStaticRegs->MPURegionAccessControlR = SDL_UTILS_getMPURegionAccessControlR();
+        /* Get The MPURegionAccessControlR register value  */
+
+        pCPUStaticRegs->RGNR = SDL_UTILS_getRGNR();
+        /* Get The RGNR register value  */
+
+        pCPUStaticRegs->BTCMRegionR = SDL_UTILS_getBTCMRegionR();
+        /* Get The BTCMRegionR register value  */
+
+        pCPUStaticRegs->ATCMRegionR = SDL_UTILS_getATCMRegionR();
+        /* Get The ATCMRegionR register value  */
+
+        pCPUStaticRegs->SlavePortControlR = SDL_UTILS_getSlavePortControlR();
+        /* Get The SlavePortControlR register value  */
+
+        pCPUStaticRegs->CONTEXTIDR = SDL_UTILS_getCONTEXTIDR();
+        /* Get The CONTEXTIDR register value  */
+
+        pCPUStaticRegs->ThreadProcessIDR1 = SDL_UTILS_getThreadProcessIDR1();
+        /* Get The ThreadProcessIDR1 register value  */
+
+        pCPUStaticRegs->ThreadProcessIDR2 = SDL_UTILS_getThreadProcessIDR2();
+        /* Get The ThreadProcessIDR2 register value  */
+
+        pCPUStaticRegs->ThreadProcessIDR3 = SDL_UTILS_getThreadProcessIDR3();
+        /* Get The ThreadProcessIDR3 register value  */
+
+        pCPUStaticRegs->nVALIRQSET = SDL_UTILS_getnVALIRQSET();
+        /* Get The nVALIRQSET register value  */
+
+        pCPUStaticRegs->nVALFIQSET = SDL_UTILS_getnVALFIQSET();
+        /* Get The nVALFIQSET register value  */
+
+        pCPUStaticRegs->nVALRESETSET = SDL_UTILS_getnVALRESETSET();
+        /* Get The nVALRESETSET register value  */
+
+        pCPUStaticRegs->nVALDEBUGSET = SDL_UTILS_getnVALDEBUGSET();
+        /* Get The nVALDEBUGSET register value  */
+
+        pCPUStaticRegs->nVALIRQCLEAR = SDL_UTILS_getnVALIRQCLEAR();
+        /* Get The nVALIRQCLEAR register value  */
+
+        pCPUStaticRegs->nVALFIQCLEAR = SDL_UTILS_getnVALFIQCLEAR();
+        /* Get The nVALFIQCLEAR register value  */
+
+        pCPUStaticRegs->nVALRESETCLEAR = SDL_UTILS_getnVALRESETCLEAR();
+        /* Get The nVALRESETCLEAR register value  */
+
+        pCPUStaticRegs->nVALDEBUGCLEAR = SDL_UTILS_getnVALDEBUGCLEAR();
+        /* Get The nVALDEBUGCLEAR register value  */
+
+        pCPUStaticRegs->BuildOption1R = SDL_UTILS_getBuildOption1R();
+        /* Get The BuildOption1R register value  */
+
+        pCPUStaticRegs->BuildOption2R = SDL_UTILS_getBuildOption2R();
+        /* Get The BuildOption2R register value  */
+
+        pCPUStaticRegs->PinOptionR = SDL_UTILS_getPinOptionR();
+        /* Get The PinOptionR register value  */
+
+        pCPUStaticRegs->LLPPnormalAXIRR = SDL_UTILS_getLLPPnormalAXIRR();
+        /* Get The LLPPnormalAXIRR register value  */
+
+        pCPUStaticRegs->LLPPvirtualAXIRR = SDL_UTILS_getLLPPvirtualAXIRR();
+        /* Get The LLPPvirtualAXIRR register value  */
+
+        pCPUStaticRegs->AHBRR = SDL_UTILS_getAHBRR();
+        /* Get The AHBRR register value  */
+
+        pCPUStaticRegs->CFLR = SDL_UTILS_getCFLR();
+        /* Get The CFLR register value  */
+
+        pCPUStaticRegs->PMOVSR = SDL_UTILS_getPMOVSR();
+        /* Get The PMOVSR register value  */
+
+        pCPUStaticRegs->DFSR = SDL_UTILS_getDFSR();
+        /* Get The DFSR register value  */
+
+        pCPUStaticRegs->ADFSR = SDL_UTILS_getADFSR();
+        /* Get The ADFSR register value  */
+
+        pCPUStaticRegs->DFAR = SDL_UTILS_getDFAR();
+        /* Get The DFAR register value  */
+
+        pCPUStaticRegs->IFSR = SDL_UTILS_getIFSR();
+        /* Get The IFSR register value  */
+
+        pCPUStaticRegs->IFAR = SDL_UTILS_getIFAR();
+        /* Get The IFAR register value  */
+
+        pCPUStaticRegs->AIFSR = SDL_UTILS_getAIFSR();
+        /* Get The AIFSR register value  */
+
+        sdlResult = SDL_PASS;
+    }
+    else
+    {
+        sdlResult = SDL_EBADARGS;
+    }
+
+    return sdlResult;
+}
diff --git a/source/sdl/reset/soc/am273x/sdl_reset.c b/source/sdl/reset/soc/am273x/sdl_reset.c
index 97adf1483c..9b2ad11574 100644
--- a/source/sdl/reset/soc/am273x/sdl_reset.c
+++ b/source/sdl/reset/soc/am273x/sdl_reset.c
@@ -39,9 +39,6 @@
  *            This also contains some related macros and Helper APIs.
  */
 
- /**
- * Design: PROC_SDL-5821
- */
 
 #include <sdl/reset/sdl_reset.h>
 
@@ -49,7 +46,9 @@
 *   API for genrate Warm reset.
 *********************************************************************************************************/
 
-/* [PROC_SDL-3641] */
+/**
+ * Design: PROC_SDL-6024
+ */
 void SDL_generateSwWarmReset(void)
 {
     /* Unlock CONTROLSS_CTRL registers */
@@ -66,7 +65,9 @@ void SDL_generateSwWarmReset(void)
 *   API for getting the status of warm reset cause
 *********************************************************************************************************/
 
-/* [PROC_SDL-3642] */
+/**
+ * Design: PROC_SDL-6027
+ */
 uint32_t SDL_getWarmResetCause(void)
 {
     uint32_t     resetCause = 0U;
@@ -90,7 +91,9 @@ uint32_t SDL_getWarmResetCause(void)
 *   API for getting the status of R5F Core reset cause
 *********************************************************************************************************/
 
-/* [PROC_SDL-3640]  */
+/**
+ * Design: PROC_SDL-6026
+ */
 uint32_t SDL_r5fGetResetCause(void)
 {
     uint32_t     resetCauseBits = 0U;
@@ -120,7 +123,9 @@ uint32_t SDL_r5fGetResetCause(void)
 *   API to generate localized reset for C66x DSP
 *********************************************************************************************************/
 
-/* [PROC_SDL-3643]  */
+/**
+ * Design: PROC_SDL-6025
+ */
 
 void SDL_rcmDspLocalReset(void)
 {
diff --git a/source/sdl/reset/soc/awr294x/sdl_reset.c b/source/sdl/reset/soc/awr294x/sdl_reset.c
index 97adf1483c..59e74090fa 100644
--- a/source/sdl/reset/soc/awr294x/sdl_reset.c
+++ b/source/sdl/reset/soc/awr294x/sdl_reset.c
@@ -49,7 +49,9 @@
 *   API for genrate Warm reset.
 *********************************************************************************************************/
 
-/* [PROC_SDL-3641] */
+/**
+ * Design: PROC_SDL-6024
+ */
 void SDL_generateSwWarmReset(void)
 {
     /* Unlock CONTROLSS_CTRL registers */
@@ -66,7 +68,9 @@ void SDL_generateSwWarmReset(void)
 *   API for getting the status of warm reset cause
 *********************************************************************************************************/
 
-/* [PROC_SDL-3642] */
+/**
+ * Design: PROC_SDL-6027
+ */
 uint32_t SDL_getWarmResetCause(void)
 {
     uint32_t     resetCause = 0U;
@@ -90,7 +94,9 @@ uint32_t SDL_getWarmResetCause(void)
 *   API for getting the status of R5F Core reset cause
 *********************************************************************************************************/
 
-/* [PROC_SDL-3640]  */
+/**
+ * Design: PROC_SDL-6026
+ */
 uint32_t SDL_r5fGetResetCause(void)
 {
     uint32_t     resetCauseBits = 0U;
@@ -120,7 +126,9 @@ uint32_t SDL_r5fGetResetCause(void)
 *   API to generate localized reset for C66x DSP
 *********************************************************************************************************/
 
-/* [PROC_SDL-3643]  */
+/**
+ * Design: PROC_SDL-6025
+ */
 
 void SDL_rcmDspLocalReset(void)
 {
diff --git a/source/sdl/rom_checksum/sdl_ip_rom_checksum.c b/source/sdl/rom_checksum/sdl_ip_rom_checksum.c
new file mode 100644
index 0000000000..174ca11855
--- /dev/null
+++ b/source/sdl/rom_checksum/sdl_ip_rom_checksum.c
@@ -0,0 +1,279 @@
+/*********************************************************************
+ *   Copyright (c) Texas Instruments Incorporated 2023
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ *  \file     sdl_ip_rom_checksum.c
+ *
+ *  \brief    This file contains the implementation of the low level API's present in the ROM Checksum diagnostics.
+ */
+
+#include <stdint.h>
+#include "sdl_ip_rom_checksum.h"
+#include <stdbool.h>
+#include <sdl/include/sdl_types.h>
+
+#define SDL_STORE64H(x, y) \
+ 	uint8_t *y8 = (uint8_t *)y; \
+  	y8[0] = ((x>>56) & (uint8_t)255); \
+  	y8[1] = ((x>>48) & (uint8_t)255); \
+	y8[2] = ((x>>40) & (uint8_t)255); \
+	y8[3] = ((x>>32) & (uint8_t)255); \
+	y8[4] = ((x>>24) & (uint8_t)255); \
+	y8[5] = ((x>>16) & (uint8_t)255); \
+	y8[6] = ((x>>8) & (uint8_t)255); \
+	y8[7] = ((x>>0) & (uint8_t)255);
+
+#define SDL_LOAD64H(x, y)                                                      \
+		x = (((uint64_t)((y)[0] & (uint64_t)255))<<56)|(((uint64_t)((y)[1] & (uint64_t)255))<<48) | \
+		(((uint64_t)((y)[2] & (uint64_t)255))<<40)|(((uint64_t)((y)[3] & (uint64_t)255))<<32) | \
+		(((uint64_t)((y)[4] & (uint64_t)255))<<24)|(((uint64_t)((y)[5] & (uint64_t)255))<<16) | \
+		(((uint64_t)((y)[6] & (uint64_t)255))<<8)|(((uint64_t)((y)[7] & (uint64_t)255)));
+
+#define RND(a,b,c,d,e,f,g,h,i)                    \
+	t0 = h + SDL_Sigma1((uint64_t)e) + SDL_ch(e, f, g) + K[i] + W[i];   \
+	t1 = SDL_Sigma0((uint64_t)a) + SDL_Maj(a, b, c);                  \
+	d += t0;                                        \
+	h  = t0 + t1;
+/* Right rotate circular shift by y bits. */
+#define SDL_ROR64c(x, y) \
+	( ((((uint64_t)(x)&SDL_CONST64(0xFFFFFFFFFFFFFFFFU))>>((uint64_t)(y)&SDL_CONST64(63))) | \
+	   ((uint64_t)(x)<<((uint64_t)((uint64_t)64-((uint64_t)(y)&SDL_CONST64(63)))))) & SDL_CONST64(0xFFFFFFFFFFFFFFFFU))
+
+/* the K array */ //These are round constant from 0-79
+static const uint64_t K[80] = {
+    0x428A2F98D728AE22U, 0x7137449123EF65CDU, 0xB5C0FBCFEC4D3B2FU, 0xE9B5DBA58189DBBCU,
+    0x3956C25BF348B538U, 0x59F111F1B605D019U, 0x923F82A4AF194F9BU, 0xAB1C5ED5DA6D8118U,
+    0xD807AA98A3030242U, 0x12835B0145706FBEU, 0x243185BE4EE4B28CU, 0x550C7DC3D5FFB4E2U,
+    0x72BE5D74F27B896FU, 0x80DEB1FE3B1696B1U, 0x9BDC06A725C71235U, 0xC19BF174CF692694U,
+    0xE49B69C19EF14AD2U, 0xEFBE4786384F25E3U, 0x0FC19DC68B8CD5B5U, 0x240CA1CC77AC9C65U,
+    0x2DE92C6F592B0275U, 0x4A7484AA6EA6E483U, 0x5CB0A9DCBD41FBD4U, 0x76F988DA831153B5U,
+    0x983E5152EE66DFABU, 0xA831C66D2DB43210U, 0xB00327C898FB213FU, 0xBF597FC7BEEF0EE4U,
+    0xC6E00BF33DA88FC2U, 0xD5A79147930AA725U, 0x06CA6351E003826FU, 0x142929670A0E6E70U,
+    0x27B70A8546D22FFCU, 0x2E1B21385C26C926U, 0x4D2C6DFC5AC42AEDU, 0x53380D139D95B3DFU,
+    0x650A73548BAF63DEU, 0x766A0ABB3C77B2A8U, 0x81C2C92E47EDAEE6U, 0x92722C851482353BU,
+    0xA2BFE8A14CF10364U, 0xA81A664BBC423001U, 0xC24B8B70D0F89791U, 0xC76C51A30654BE30U,
+    0xD192E819D6EF5218U, 0xD69906245565A910U, 0xF40E35855771202AU, 0x106AA07032BBD1B8U,
+    0x19A4C116B8D2D0C8U, 0x1E376C085141AB53U, 0x2748774CDF8EEB99U, 0x34B0BCB5E19B48A8U,
+    0x391C0CB3C5C95A63U, 0x4ED8AA4AE3418ACBU, 0x5B9CCA4F7763E373U, 0x682E6FF3D6B2B8A3U,
+    0x748F82EE5DEFB2FCU, 0x78A5636F43172F60U, 0x84C87814A1F0AB72U, 0x8CC702081A6439ECU,
+    0x90BEFFFA23631E28U, 0xA4506CEBDE82BDE9U, 0xBEF9A3F7B2C67915U, 0xC67178F2E372532BU,
+    0xCA273ECEEA26619CU, 0xD186B8C721C0C207U, 0xEADA7DD6CDE0EB1EU, 0xF57D4F7FEE6ED178U,
+    0x06F067AA72176FBAU, 0x0A637DC5A2C898A6U, 0x113F9804BEF90DAEU, 0x1B710B35131C471BU,
+    0x28DB77F523047D84U, 0x32CAAB7B40C72493U, 0x3C9EBE0A15C9BEBCU, 0x431D67C49C100D4CU,
+    0x4CC5D4BECB3E42B6U, 0x597F299CFC657E2AU, 0x5FCB6FAB3AD6FAECU, 0x6C44198C4A475817U
+ };
+
+void SDL_memcpy(void *dest, void *src, uint32_t n){
+	/* Copy contents of src[] to dest[] */
+	unsigned char *cdest = (unsigned char *)dest;
+	unsigned char *csrc  = (unsigned char *)src;
+	for (uint32_t i=0; i < n; i++){
+    	cdest[i] = csrc[i];
+    }
+}
+/* compress 1024-bits */
+/* md -> state is 8 byte seed value.
+buf -> 16 word data each of 64 bits.
+output 8 byte seed value for next round.
+*/
+/**
+ *  Design: PROC_SDL-6265
+ */
+
+void  SDL_ROM_Checksum_compress(SDL_ROM_Checksum_obj * md, uint8_t *buf)
+{
+	uint64_t S[8], W[80], t0, t1;
+	int32_t i = 0;
+
+	/* copy state into S */
+	for (i = 0; i < 8; i++) {
+		S[i] = md->state[i];
+	}
+
+	/* copy the state into 1024-bits into W[0..15] */
+	for (i = 0; i < 16; i++) {
+		SDL_LOAD64H(W[i], buf + (8*i));
+	}
+
+	/* fill W[16..79] */
+	for (i = 16; i < 80; i++) {
+		W[i] = SDL_Gamma1(W[i - 2]) + W[i - 7] + SDL_Gamma0(W[i - 15]) + W[i - 16];
+	}
+	for (i = 0; i < 80; i += 8) {
+		RND(S[0],S[1],S[2],S[3],S[4],S[5],S[6],S[7],i+0);
+		RND(S[7],S[0],S[1],S[2],S[3],S[4],S[5],S[6],i+1);
+		RND(S[6],S[7],S[0],S[1],S[2],S[3],S[4],S[5],i+2);
+		RND(S[5],S[6],S[7],S[0],S[1],S[2],S[3],S[4],i+3);
+		RND(S[4],S[5],S[6],S[7],S[0],S[1],S[2],S[3],i+4);
+		RND(S[3],S[4],S[5],S[6],S[7],S[0],S[1],S[2],i+5);
+		RND(S[2],S[3],S[4],S[5],S[6],S[7],S[0],S[1],i+6);
+		RND(S[1],S[2],S[3],S[4],S[5],S[6],S[7],S[0],i+7);
+	}
+	/* feedback */
+	for (i = 0; i < 8; i++) {
+		md->state[i] = md->state[i] + S[i];
+	}
+}
+
+/**
+  Process a block of memory though the hash
+  @param md     The hash state
+  @param in     The data to hash
+  @param inlen  The length of the data (octets)
+  @return SDL_PASS if successful
+ */
+
+/**
+ *  Design: PROC_SDL-6263
+ */
+int32_t SDL_ROM_Checksum_process (SDL_ROM_Checksum_obj * md, uint8_t *in, uint32_t inlen)
+{
+	uint32_t n;
+	int32_t sdl_result= SDL_PASS;
+	uint8_t *in1 = in;
+	uint32_t inlen1 = inlen;
+	if ((md->curlen) >= ((uint32_t)sizeof(md->buf))) {
+		sdl_result = SDL_EFAIL;
+	}
+
+
+	if(sdl_result == SDL_PASS){
+		while (inlen1 > (uint32_t)0) {
+			if (inlen1 >= (uint32_t)SDL_BLOCK_SIZE) {
+				SDL_ROM_Checksum_compress (md, (uint8_t *)in1);
+					md->length += (SDL_BLOCK_SIZE) * (uint8_t)8;
+					in1             += 128;
+					inlen1          -= (uint32_t)SDL_BLOCK_SIZE;
+			} else {
+					n = SDL_MIN(inlen1, (SDL_BLOCK_SIZE - md->curlen));
+					SDL_memcpy(md->buf + (md->curlen), (void *)in1, n);
+					md->curlen += n;
+					in1             += (int)n;
+					inlen1          -= n;
+				}
+		}
+	}
+	return sdl_result;
+}
+
+/**
+  Initialize the hash state
+  @param md   The hash state you wish to initialize
+ */
+
+/**
+ *  Design: PROC_SDL-6262
+ */
+void SDL_ROM_Checksum_init(SDL_ROM_Checksum_obj * const md)
+{
+	md->curlen = 0;
+	md->length = 0;
+	md->state[0] = SDL_CONST64(0x6a09e667f3bcc908U);
+	md->state[1] = SDL_CONST64(0xbb67ae8584caa73bU);
+	md->state[2] = SDL_CONST64(0x3c6ef372fe94f82bU);
+	md->state[3] = SDL_CONST64(0xa54ff53a5f1d36f1U);
+	md->state[4] = SDL_CONST64(0x510e527fade682d1U);
+	md->state[5] = SDL_CONST64(0x9b05688c2b3e6c1fU);
+	md->state[6] = SDL_CONST64(0x1f83d9abfb41bd6bU);
+	md->state[7] = SDL_CONST64(0x5be0cd19137e2179U);
+}
+
+/**
+  Terminate the hash to get the digest
+  @param md  The hash state
+  @param out [out] The destination of the hash (64 bytes)
+  @return SDL_PASS if successful
+ */
+/**
+ *  Design: PROC_SDL-6266
+ */
+int32_t SDL_ROM_Checksum_done(SDL_ROM_Checksum_obj * md)
+{
+	int32_t test_result = SDL_PASS;
+
+	if ((md->curlen) >= ((uint32_t)sizeof(md->buf))) {
+			test_result = SDL_EFAIL;
+	}
+	if(test_result == SDL_PASS){
+		/* increase the length of the message */
+		md->length += md->curlen * SDL_CONST64(8);
+
+		/* append the '1' bit */
+		md->buf[md->curlen] = 0x80U;
+		md->curlen = md->curlen+(uint32_t)1;
+
+		/* pad upto 120 bytes of zeroes
+		* note: that from 112 to 120 is the 64 MSB of the length.  We assume that you won't hash
+		* > 2^64 bits of data... :-)
+		*/
+		while ((md->curlen) < ((uint32_t)120U)) {
+			md->buf[md->curlen] = 0;
+			md->curlen ++;
+		}
+
+		/* store length */
+		SDL_STORE64H(md->length, md->buf+(uint8_t)120U);
+		SDL_ROM_Checksum_compress(md, md->buf);
+	}
+	return test_result;
+
+}
+
+/*
+ Compare resultant buffer with original golden vector value.
+*/
+/**
+ *  Design: PROC_SDL-6264
+ */
+
+int32_t SDL_ROM_Checksum_compareResult (uint64_t buflen, SDL_ROM_Checksum_obj * md,  uint64_t * golden_value){
+	uint64_t test = 0;
+	int32_t sdl_result = SDL_PASS;
+	uint64_t * golden_value1 = golden_value;
+	for(uint64_t i=0; i<buflen; i++){
+		if(sdl_result == SDL_PASS){
+			test = *(golden_value1);
+			test = ((0xFF00000000000000U & test)>>56) | ((0x00FF000000000000U & test)>>40) |
+			((0x0000FF0000000000U & test)>>24) |	((0x000000FF00000000U & test)>>8) |
+			((0x00000000000000FFU & test)<<56) | ((0x000000000000FF00U & test)<<40) |
+			((0x0000000000FF0000U & test)<<24) |	((0x00000000FF000000U & test)<<8);
+			if(md->state[i]== test){
+				golden_value1++;
+			}
+			else{
+				sdl_result = SDL_EFAIL;
+			}
+		}
+	}
+	return sdl_result;
+ }
diff --git a/source/sdl/rom_checksum/sdl_ip_rom_checksum.h b/source/sdl/rom_checksum/sdl_ip_rom_checksum.h
new file mode 100644
index 0000000000..b10630ad4a
--- /dev/null
+++ b/source/sdl/rom_checksum/sdl_ip_rom_checksum.h
@@ -0,0 +1,170 @@
+/********************************************************************
+ * Copyright (C) 2023 Texas Instruments Incorporated.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ *
+ *   @file  sdl_ip_rom_checksum.h
+ *
+ *   @brief This file contains the SDL-FL API's for ROM Checksum
+ *
+ *
+ *
+ */
+#ifndef _sdl_ip_rom_checksum_H
+#define _sdl_ip_rom_checksum_H
+#include <inttypes.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Various logical functions */
+#define SDL_ch(x,y,z)       (z ^ (x & (y ^ z)))  //this function will (x AND y) XOR (NOT x AND z)
+#define SDL_Maj(x,y,z)      (((x | y) & z) | (x & y))
+#define SDL_S(x, n)         (SDL_ROR64c(x, n)) //Rotate right circular shift  by n bits
+#define SDL_R(x, n)         (((uint64_t)(x)&SDL_CONST64(0xFFFFFFFFFFFFFFFFU))>>((uint64_t)n))  // Rotate left circular shift  by n bits
+#define SDL_Sigma0(x)       (SDL_S(x, 28) ^ SDL_S(x, 34) ^ SDL_S(x, 39))
+#define SDL_Sigma1(x)       (SDL_S(x, 14) ^ SDL_S(x, 18) ^ SDL_S(x, 41))
+#define SDL_Gamma0(x)       (uint64_t)(SDL_S(x, 1) ^ SDL_S(x, 8) ^ SDL_R(x, 7)) // we perform the left and right shift after that we will perform the XOR of all the results
+#define SDL_Gamma1(x)       (uint64_t)(SDL_S(x, 19) ^ SDL_S(x, 61) ^ SDL_R(x, 6)) // we perform the left and right shift after that we will perform the XOR of all the results
+#define SDL_BLOCK_SIZE  (uint8_t)128 //Size of each block which will be processed;
+#define SDL_MIN(x, y) ( ((x)<(y))?(x):(y) )
+#define SDL_CONST64(x) (uint64_t)x
+
+
+/**
+@ingroup  SDL_ROM_CHECKSUM_API
+@defgroup SDL_ROM_CHECKSUM_IP_API ROM_CHECKSUM Low-Level API
+ */
+/**
+@defgroup SDL_IP_ROM_CHECKSUM_DATASTRUCT  ROM_Checksum Data Structures
+@ingroup SDL_ROM_CHECKSUM_IP_API
+*/
+
+/**
+@defgroup SDL_IP_ROM_CHECKSUM_FUNCTION  ROM Checksum Functions
+@ingroup SDL_ROM_CHECKSUM_IP_API
+*/
+
+/**
+ *  @addtogroup SDL_IP_ROM_CHECKSUM_DATASTRUCT
+    @{
+ *
+ */
+
+/** ---------------------------------------------------------------------------
+ * @brief   This structure is used to store the resultant value of ROM Checksum
+ *
+ * ----------------------------------------------------------------------------
+ */
+typedef struct
+{
+	/** Actual data length*/
+	uint64_t length;
+
+	/** Random seek value*/
+	uint64_t state[8];
+
+	/** Used to keep track of data length in incomplete block*/
+	uint32_t curlen;
+
+	/** Memory storage use in padding*/
+	uint8_t  buf[128];
+} SDL_ROM_Checksum_obj;
+
+/** @} */
+/********************************************************************************************************
+*   Below are the Declarations of Low Level Functions
+********************************************************************************************************/
+
+/**
+ *  @addtogroup SDL_IP_ROM_CHECKSUM_FUNCTION
+    @{
+ *
+ */
+/**
+* \brief This API will Initialize the buffer where hash value to be stored.
+*
+*/
+void SDL_ROM_Checksum_init(SDL_ROM_Checksum_obj * const md);
+
+/**
+* \brief This API is used to process the ROM region data.
+*
+* \return status Success of the ROM Checksum.
+*      Success: SDL_PASS.
+*      Fail : SDL_EFAIL.
+*
+*/
+int32_t SDL_ROM_Checksum_process (SDL_ROM_Checksum_obj * md,  uint8_t *in, uint32_t inlen);
+
+/**
+* \brief This API is used to compress the data of ROM region and store the result in md->state.
+*
+*/
+void SDL_ROM_Checksum_compress(SDL_ROM_Checksum_obj * md, uint8_t *buf);
+
+/**
+* \brief This API will increase our data length with the help of padding ( because our algorithm can compress only 1024-bit length of data at a time)  and will compress then will store final has value in md->state.
+* \return status Success of the ROM Checksum.
+*      Success: SDL_PASS.
+*      Fail : SDL_EFAIL.
+*
+*/
+int32_t SDL_ROM_Checksum_done(SDL_ROM_Checksum_obj * md);
+
+
+/**
+* \brief This API will compare the resultant hash value of golden value.
+*
+* \return status Success of the ROM Checksum.
+*     Success: SDL_PASS.
+*     Fail : SDL_EFAIL.
+*
+*/
+int32_t SDL_ROM_Checksum_compareResult (uint64_t buflen, SDL_ROM_Checksum_obj * md,  uint64_t *golden_value);
+
+/**
+* \brief This API will copy source pointer data to destination pointer.
+*
+*/
+void SDL_memcpy(void *dest, void *src, uint32_t n);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*  _sdl_ip_rom_checksum_H */
diff --git a/source/sdl/rom_checksum/sdl_rom_checksum.c b/source/sdl/rom_checksum/sdl_rom_checksum.c
new file mode 100644
index 0000000000..1f0bd215e5
--- /dev/null
+++ b/source/sdl/rom_checksum/sdl_rom_checksum.c
@@ -0,0 +1,76 @@
+/*********************************************************************
+ *   Copyright (c) Texas Instruments Incorporated 2023
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * \file  sdl_rom_checksum.c
+ *
+ * \brief  SDL implementation file for the rom checksum module.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <sdl/sdl_rom_checksum.h>
+#include <stdbool.h>
+#include <sdl/include/sdl_types.h>
+/**
+  Process full ROMChecksum for block of memory
+  @param in     Pointer to be message being hashed
+  @param inlen  The lenith of the data (octets)
+  @return SDL_PASS if successful
+ */
+
+/**
+ * Design: PROC_SDL-6002
+ */
+int32_t SDL_ROM_Checksum_compute (void)
+{
+ 	uint8_t * in = SDL_DATA_TO_BE_HASHED_POINTER;
+	uint32_t inlen = SDL_LENGTH_OF_DATA_TO_BE_HASHED;
+ 	uint64_t * golden_vector_pointer = (uint64_t *)SDL_GOLDEN_DATA_POINTER;
+	uint64_t  golden_vector_buflen =  SDL_LENGTH_OF_GOLDEN_DATA;
+	SDL_ROM_Checksum_obj md;
+	int32_t sdl_result = SDL_PASS;
+	SDL_ROM_Checksum_init(&md);
+    sdl_result = SDL_ROM_Checksum_process(&md, in, (uint32_t)inlen);
+	if(sdl_result == SDL_PASS)
+	{
+    	sdl_result = SDL_ROM_Checksum_done(&md);
+	}
+	if(sdl_result == SDL_PASS)
+	{
+		sdl_result = SDL_ROM_Checksum_compareResult (golden_vector_buflen, &md, golden_vector_pointer);
+	}
+	return sdl_result;
+}
+
+
diff --git a/source/sdl/rti/v0/soc/am263x/sdl_soc_rti.c b/source/sdl/rti/v0/soc/am263x/sdl_soc_rti.c
index a9fa769ca1..91ffa7f190 100644
--- a/source/sdl/rti/v0/soc/am263x/sdl_soc_rti.c
+++ b/source/sdl/rti/v0/soc/am263x/sdl_soc_rti.c
@@ -47,7 +47,7 @@
 #include <sdl/dpl/sdl_dpl.h>
 
 /**
- *  Design:
+ *  Design:PROC_SDL-4528
  */
 int32_t SDL_RTI_getBaseaddr(SDL_RTI_InstanceType instance,
                              uint32_t *baseAddr)
diff --git a/source/sdl/rti/v0/soc/am273x/sdl_soc_rti.c b/source/sdl/rti/v0/soc/am273x/sdl_soc_rti.c
index db1cc2434d..a0d3598c5b 100644
--- a/source/sdl/rti/v0/soc/am273x/sdl_soc_rti.c
+++ b/source/sdl/rti/v0/soc/am273x/sdl_soc_rti.c
@@ -47,7 +47,7 @@
 #include <sdl/dpl/sdl_dpl.h>
 
 /**
- *  Design:
+ *  Design:PROC_SDL-4528
  */
 int32_t SDL_RTI_getBaseaddr(SDL_RTI_InstanceType instance,
                              uint32_t *baseAddr)
diff --git a/source/sdl/rti/v0/soc/awr294x/sdl_soc_rti.c b/source/sdl/rti/v0/soc/awr294x/sdl_soc_rti.c
index db1cc2434d..a0d3598c5b 100644
--- a/source/sdl/rti/v0/soc/awr294x/sdl_soc_rti.c
+++ b/source/sdl/rti/v0/soc/awr294x/sdl_soc_rti.c
@@ -47,7 +47,7 @@
 #include <sdl/dpl/sdl_dpl.h>
 
 /**
- *  Design:
+ *  Design:PROC_SDL-4528
  */
 int32_t SDL_RTI_getBaseaddr(SDL_RTI_InstanceType instance,
                              uint32_t *baseAddr)
diff --git a/source/sdl/sdl_ecc.h b/source/sdl/sdl_ecc.h
index 7a5c928e44..4beb1dee73 100644
--- a/source/sdl/sdl_ecc.h
+++ b/source/sdl/sdl_ecc.h
@@ -66,63 +66,11 @@
 extern "C" {
 #endif
 
-/** ---------------------------------------------------------------------------
- * \brief This enumerator defines the different ECC aggregator types
- * ----------------------------------------------------------------------------
- */
-typedef enum {
-    SDL_ECC_AGGR_TYPE_INJECT_ONLY = 1,
-    /**<  Ecc aggregator inject only */
-    SDL_ECC_AGGR_TYPE_FULL_FUNCTION = 2,
-    /**<  Ecc aggregator full funtionality */
-} SDL_ECC_AggregatorType;
-
-
-/** ---------------------------------------------------------------------------
- * \brief      ECC Inject error types
- *
- * ----------------------------------------------------------------------------
- */
-typedef enum {
-    /** No error */
-    SDL_INJECT_ECC_NO_ERROR = 0,
-    /** 1-Bit ECC Error forcing once */
-    SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE = 1,
-    /** 2-Bit ECC Error forcing once */
-    SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE = 2,
-    /** 1-Bit ECC Error Force once on next any Ram read */
-    SDL_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_ONCE = 3,
-    /** 2-Bit ECC Error Force once on  next Ram read */
-    SDL_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_ONCE = 4,
-    /** 1-Bit ECC Error forcing once */
-    SDL_INJECT_ECC_ERROR_FORCING_1BIT_REPEAT = 5,
-    /** 2-Bit ECC Error forcing once */
-    SDL_INJECT_ECC_ERROR_FORCING_2BIT_REPEAT = 6,
-    /** 1-Bit ECC Error Force once on next any Ram read */
-    SDL_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_REPEAT = 7,
-    /** 2-Bit ECC Error Force once on  next Ram read */
-    SDL_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_REPEAT = 8,
-} SDL_ECC_InjectErrorType;
-
-
-/** ---------------------------------------------------------------------------
- * \brief This enumerator defines the different ECC RAM ID types
- * ----------------------------------------------------------------------------
- */
-typedef enum {
-    SDL_ECC_RAM_ID_TYPE_WRAPPER = 0,
-    /**<  Ecc RAM ID Wrapper type */
-    SDL_ECC_RAM_ID_TYPE_INTERCONNECT = 1,
-    /**<  Ecc RAM ID Interconnect/CBASS type */
-} SDL_ECC_RamIdType;
-
-/** ---------------------------------------------------------------------------
- * \brief This enumerator indicate ECC memory type
+/**
+ *  @addtogroup SDL_ECC_AGGR_MACROS
+    @{
  *
- * ----------------------------------------------------------------------------
  */
-typedef uint32_t SDL_ECC_MemType;
-
 #if defined(SOC_AM263X)
 
 #define SDL_SOC_ECC_AGGR                                            (0U)
@@ -140,26 +88,26 @@ typedef uint32_t SDL_ECC_MemType;
 #define SDL_ECC_MEMTYPE_MAX                                         (SDL_CPSW3GCSS_ECC_AGGR + 1U)
 
 /* Parity */
-#define SDL_R5SS0_CPU0_TCM        	(0U)
-#define SDL_R5SS1_CPU0_TCM        	(1U)
+#define SDL_R5SS0_CPU0_TCM                                          (0U)
+#define SDL_R5SS1_CPU0_TCM                                          (1U)
 /* SDL_R5SS0_CPU0_TCM */
-#define SDL_R5FSS0_CORE0_ATCM0		(1U)
-#define SDL_R5FSS0_CORE0_B0TCM0		(3U)
-#define SDL_R5FSS0_CORE0_B1TCM0		(5U)
+#define SDL_R5FSS0_CORE0_ATCM0                                      (1U)
+#define SDL_R5FSS0_CORE0_B0TCM0                                     (3U)
+#define SDL_R5FSS0_CORE0_B1TCM0                                     (5U)
 /* SDL_R5SS0_CPU10_TCM */
-#define SDL_R5FSS0_CORE1_ATCM1		(2U)
-#define SDL_R5FSS0_CORE1_B0TCM1		(4U)
-#define SDL_R5FSS0_CORE1_B1TCM1		(6U)
+#define SDL_R5FSS0_CORE1_ATCM1                                      (2U)
+#define SDL_R5FSS0_CORE1_B0TCM1                                     (4U)
+#define SDL_R5FSS0_CORE1_B1TCM1                                     (6U)
 /* SDL_R5SS1_CPU0_TCM */
-#define SDL_R5FSS1_CORE0_ATCM0		(7U)
-#define SDL_R5FSS1_CORE0_B0TCM0		(9U)
-#define SDL_R5FSS1_CORE0_B1TCM0		(11U)
+#define SDL_R5FSS1_CORE0_ATCM0                                      (7U)
+#define SDL_R5FSS1_CORE0_B0TCM0                                     (9U)
+#define SDL_R5FSS1_CORE0_B1TCM0                                     (11U)
 /* SDL_R5SS1_CPU1_TCM */
-#define SDL_R5FSS1_CORE1_ATCM1		(8U)
-#define SDL_R5FSS1_CORE1_B0TCM1		(10U)
-#define SDL_R5FSS1_CORE1_B1TCM1		(12U)
+#define SDL_R5FSS1_CORE1_ATCM1                                      (8U)
+#define SDL_R5FSS1_CORE1_B0TCM1                                     (10U)
+#define SDL_R5FSS1_CORE1_B1TCM1                                     (12U)
 /* TPCC */
-#define SDL_TPCC0        			(2)
+#define SDL_TPCC0                                                   (2)
 #endif
 
 #if defined(SOC_AM273X) || defined(SOC_AWR294X)
@@ -172,67 +120,67 @@ typedef uint32_t SDL_ECC_MemType;
 #define SDL_CPSW3GCSS_ECC_AGGR                                      (6U)
 #define SDL_ECC_MEMTYPE_MAX                                         (SDL_CPSW3GCSS_ECC_AGGR + 1U)
 /* TCM PARITY */
-#define SDL_TCM_PARITY_ATCM0		(1U)
-#define SDL_TCM_PARITY_ATCM1		(2U)
-#define SDL_TCM_PARITY_B0TCM0		(3U)
-#define SDL_TCM_PARITY_B0TCM1		(4U)
-#define SDL_TCM_PARITY_B1TCM0		(5U)
-#define SDL_TCM_PARITY_B1TCM1		(6U)
+#define SDL_TCM_PARITY_ATCM0                                        (1U)
+#define SDL_TCM_PARITY_ATCM1                                        (2U)
+#define SDL_TCM_PARITY_B0TCM0                                       (3U)
+#define SDL_TCM_PARITY_B0TCM1                                       (4U)
+#define SDL_TCM_PARITY_B1TCM0                                       (5U)
+#define SDL_TCM_PARITY_B1TCM1                                       (6U)
 
 /* TPCC */
-#define SDL_TPCC0A        	(2U)
-#define SDL_TPCC0B        	(3U)
-#define SDL_DSS_TPCCA       (4U)
-#define SDL_DSS_TPCCB       (5U)
-#define SDL_DSS_TPCCC       (6U)
+#define SDL_TPCC0A                                                  (2U)
+#define SDL_TPCC0B                                                  (3U)
+#define SDL_DSS_TPCCA                                               (4U)
+#define SDL_DSS_TPCCB                                               (5U)
+#define SDL_DSS_TPCCC                                               (6U)
 #endif
 
 #if defined(SOC_AM64X) || defined(SOC_AM243X)
-#define SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR 								                                                              (0u)
-#define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM 								                                                              (1u)
-#define SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR 							                                                              (2u)
-#define SDL_ECC_AGGR1  								                                                                                    (3u)
-#define SDL_ECC_AGGR0                      								                                                                (4u)
-#define SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR 								                                                                (5u)
-#define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR								                                                              (6u)
-#define SDL_DMASS0_DMSS_AM64_ECCAGGR 									                                                                    (7u)
-#define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM 								                                                              (8u)
-#define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR 							                                                              (9u)
-#define SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR 								                                                    (10u)
-#define SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR 								                                                    (11u)
-#define SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR 									                                                          (12u)
-#define SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR 							                                                            (13u)
-#define SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR  								                                                      (14u)
-#define SDL_GICSS0_GIC500SS_1_2_ECC_AGGR                      						                                                (15u)
-#define SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR  								                                                        (16u)
-#define SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR 								                                                        (17u)
-#define SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A__ECC_AGGR 						                                                (19u)
-#define SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR 								                                                                (19u)
-#define SDL_DMSC0_DMSC_LITE_ECC_AGGR_TXMEM 							                                                                  (20u)
-#define SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_TXMEM 								                                                      (21u)
-#define SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR 								                                                            (22u)
-#define SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR 									                                                          (23u)
-#define SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR 									                                                          (24u)
-#define SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR 							                                                              (25u)
-#define SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR  								                                                            (26u)
-#define SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR                      				                                                (27u)
-#define SDL_MCU_M4FSS0_BLAZAR_ECCAGGR 								                                                                    (28u)
-#define SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR								                                                                  (29u)
-#define SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM                                                                           (30u)
-#define SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM                                                                           (31u)
-#define SDL_VTM0_K3VTM_N16FFC_ECCAGGR                                                                                     (32u)
-#define SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR                                                                              (33u)
-#define SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR                                                                              (34u)
-#define SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR                                                                              (35u)
-#define SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR                                                                              (36u)
+#define SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR                                                                                 (0u)
+#define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM                                                                                 (1u)
+#define SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR                                                                               (2u)
+#define SDL_ECC_AGGR1                                                                                                       (3u)
+#define SDL_ECC_AGGR0                                                                                                       (4u)
+#define SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR                                                                                  (5u)
+#define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR                                                                               (6u)
+#define SDL_DMASS0_DMSS_AM64_ECCAGGR                                                                                        (7u)
+#define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM                                                                                 (8u)
+#define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR                                                                               (9u)
+#define SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR                                                                       (10u)
+#define SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR                                                                       (11u)
+#define SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR                                                                               (12u)
+#define SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR                                                                            (13u)
+#define SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR                                                                         (14u)
+#define SDL_GICSS0_GIC500SS_1_2_ECC_AGGR                                                                                    (15u)
+#define SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR                                                                            (16u)
+#define SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR                                                                           (17u)
+#define SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A__ECC_AGGR                                                               (18u)
+#define SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR                                                                                   (19u)
+#define SDL_DMSC0_DMSC_LITE_ECC_AGGR_TXMEM                                                                                  (20u)
+#define SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_TXMEM                                                                         (21u)
+#define SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR                                                                               (22u)
+#define SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR                                                                               (23u)
+#define SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR                                                                               (24u)
+#define SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR                                                                               (25u)
+#define SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR                                                                               (26u)
+#define SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR                                                                               (27u)
+#define SDL_MCU_M4FSS0_BLAZAR_ECCAGGR                                                                                       (28u)
+#define SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR                                                                                   (29u)
+#define SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM                                                                             (30u)
+#define SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM                                                                             (31u)
+#define SDL_VTM0_K3VTM_N16FFC_ECCAGGR                                                                                       (32u)
+#define SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR                                                                                (33u)
+#define SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR                                                                                (34u)
+#define SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR                                                                                (35u)
+#define SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR                                                                                (36u)
 #if defined(SOC_AM64X)
-#define SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0 				(37u)
-#define SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC 			(38u)
-#define SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1 				(39u)
-#define SDL_ECC_MEMTYPE_MAX                                                                                               (SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1 + 1U)
+#define SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0           (37u)
+#define SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC         (38u)
+#define SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1           (39u)
+#define SDL_ECC_MEMTYPE_MAX                                                                                                 (SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1 + 1U)
 #endif
 #if defined(SOC_AM243X)
-#define SDL_ECC_MEMTYPE_MAX                                                                                               (SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR + 1U)
+#define SDL_ECC_MEMTYPE_MAX                                                                                                 (SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR + 1U)
 #endif
 #endif
 
@@ -271,6 +219,63 @@ typedef uint32_t SDL_ECC_MemType;
 /** \brief Select memory subtype VIM RAM */
 #define SDL_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID (SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID)
 #endif
+/** @} */
+
+
+/**
+ *  @addtogroup SDL_ECC_AGGR_ENUM
+    @{
+ *
+ */
+/** ---------------------------------------------------------------------------
+ * \brief This enumerator defines the different ECC aggregator types
+ * ----------------------------------------------------------------------------
+ */
+typedef enum {
+    SDL_ECC_AGGR_TYPE_INJECT_ONLY = 1,
+    /**<  Ecc aggregator inject only */
+    SDL_ECC_AGGR_TYPE_FULL_FUNCTION = 2,
+    /**<  Ecc aggregator full funtionality */
+} SDL_ECC_AggregatorType;
+
+
+/** ---------------------------------------------------------------------------
+ * \brief      ECC Inject error types
+ *
+ * ----------------------------------------------------------------------------
+ */
+typedef enum {
+    /** No error */
+    SDL_INJECT_ECC_NO_ERROR = 0,
+    /** 1-Bit ECC Error forcing once */
+    SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE = 1,
+    /** 2-Bit ECC Error forcing once */
+    SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE = 2,
+    /** 1-Bit ECC Error Force once on next any Ram read */
+    SDL_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_ONCE = 3,
+    /** 2-Bit ECC Error Force once on  next Ram read */
+    SDL_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_ONCE = 4,
+    /** 1-Bit ECC Error forcing once */
+    SDL_INJECT_ECC_ERROR_FORCING_1BIT_REPEAT = 5,
+    /** 2-Bit ECC Error forcing once */
+    SDL_INJECT_ECC_ERROR_FORCING_2BIT_REPEAT = 6,
+    /** 1-Bit ECC Error Force once on next any Ram read */
+    SDL_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_REPEAT = 7,
+    /** 2-Bit ECC Error Force once on  next Ram read */
+    SDL_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_REPEAT = 8,
+} SDL_ECC_InjectErrorType;
+
+
+/** ---------------------------------------------------------------------------
+ * \brief This enumerator defines the different ECC RAM ID types
+ * ----------------------------------------------------------------------------
+ */
+typedef enum {
+    SDL_ECC_RAM_ID_TYPE_WRAPPER = 0,
+    /**<  Ecc RAM ID Wrapper type */
+    SDL_ECC_RAM_ID_TYPE_INTERCONNECT = 1,
+    /**<  Ecc RAM ID Interconnect/CBASS type */
+} SDL_ECC_RamIdType;
 
 /** ---------------------------------------------------------------------------
  * \brief This enumerator indicate ECC memory Sub Type
@@ -279,13 +284,26 @@ typedef uint32_t SDL_ECC_MemType;
  */
 typedef uint32_t SDL_ECC_MemSubType;
 
+/** ---------------------------------------------------------------------------
+ * \brief This enumerator indicate ECC memory type
+ *
+ * ----------------------------------------------------------------------------
+ */
+typedef uint32_t SDL_ECC_MemType;
+
+/** @} */
+
 /** /brief Format of ECC error Call back function */
 typedef void (*SDL_ECC_ErrorCallback_t) (uint32_t errorSrc, uint32_t address);
 
 /** /brief Format of VIM DED vector function */
 typedef void (*SDL_ECC_VIMDEDVector_t) (void);
 
-
+/**
+ *  @addtogroup SDL_ECC_AGGR_DATASTRUCT
+    @{
+ *
+ */
 /** ---------------------------------------------------------------------------
  * \brief This structure defines the elements of ECC  Init configuration
  * ----------------------------------------------------------------------------
@@ -335,8 +353,15 @@ typedef struct SDL_ECC_ErrorInfo_s
     /**< bit error offset */
 } SDL_ECC_ErrorInfo_t;
 
-/** ============================================================================*
+/** @} */
+
+/**
+ *  @addtogroup SDL_ECC_AGGR_FUNCTION
+    @{
  *
+ */
+/** ============================================================================*
+ * 
  * \brief   Initializes an  module for usage with ECC module
  *
  * \param   esmInstType: Instance of
@@ -535,6 +560,86 @@ int32_t SDL_cleartcmStatusRegs(uint32_t clearVal);
  */
 int32_t SDL_ECC_tcmParity(SDL_ECC_MemSubType memSubType,
 							  uint32_t bitValue);
+
+/***********************************************************************
+ *
+ * \brief   DSS L2 parity init
+ *
+ * \param1  void
+ * @return  void
+ **********************************************************************/
+void SDL_ECC_dss_l2_parity_init(void);
+
+/***********************************************************************
+ *
+ * \brief   DSS L2 parity error inject
+ *
+ * \param1  injectError : single bit inject for parity error
+ * \param2  injectErrAdd: Inject memory address
+ * \param3  value       : Initial value before injecting
+ * @return  void
+ **********************************************************************/
+void SDL_ECC_dss_l2_parity_errorInject(uint32_t injectError, uint32_t injectErrAdd, uint32_t value);
+
+/***********************************************************************
+ *
+ * \brief   The single-bit error correction and double-bit error
+ *          detection errors from the memories of L1 and L2 using EDC
+ *          Mask and FLG registers
+ *
+ * \param1  exception_mask_flag : Register value used to enable
+ *                                propagation of particular exceptions
+ * @return  void
+ **********************************************************************/
+void SDL_ECC_DSP_Aggregated_EDC_Errors(uint32_t exception_mask_flag);
+
+/***********************************************************************
+ *
+ * \brief   EDC Command Enable for L1P memory
+ *
+ * \param1  void
+ * @return  SDL_PASS or SDL_EFAIL
+ **********************************************************************/
+int32_t SDL_ECC_dss_l1p_edc_CMD_EN(void);
+
+/***********************************************************************
+ *
+ * \brief   EDC Command Suspend for L1P memory
+ *
+ * \param1  void
+ * @return  SDL_PASS or SDL_EFAIL
+ **********************************************************************/
+int32_t SDL_ECC_dss_l1p_CMD_SUSP(void);
+
+/***********************************************************************
+ *
+ * \brief   EDC Command Enable for L2 memory
+ *
+ * \param1  void
+ * @return  SDL_PASS or SDL_EFAIL
+ **********************************************************************/
+int32_t SDL_ECC_dss_l2_edc_CMD_EN(void);
+
+/***********************************************************************
+ *
+ * \brief   EDC Command Suspend for L2 memory
+ *
+ * \param1  void
+ * @return  SDL_PASS or SDL_EFAIL
+ **********************************************************************/
+int32_t SDL_ECC_dss_l2_CMD_SUSP(void);
+
+/***********************************************************************
+ *
+ * \brief   IDMA 1 Transfer function
+ *
+ * \param1  srcAddr : Source address of the IDMA 1 transfer
+ * \param2  destAddr: Destination address of the IDMA 1 transfer
+ *
+ * @return  void
+ **********************************************************************/
+void SDL_ECC_IDMA1_transfer(uint32_t srcAddr, uint32_t destAddr);
+
 #endif
 
 
@@ -553,6 +658,8 @@ int32_t SDL_ECC_tpccParity(SDL_ECC_MemType eccMemType,
 							  uint32_t paramregvalue,
 							  uint32_t regval);
 
+/** @} */
+
 #ifdef __cplusplus
 }
 #endif  /* extern "C" */
diff --git a/source/sdl/sdl_pbist.h b/source/sdl/sdl_pbist.h
index 24e21cfb90..18a7aec5c5 100644
--- a/source/sdl/sdl_pbist.h
+++ b/source/sdl/sdl_pbist.h
@@ -113,7 +113,6 @@ typedef enum {
  */
 int32_t SDL_PBIST_selfTest(SDL_PBIST_inst instance, SDL_PBIST_testType testType,
                            uint32_t timeout, bool *pResult);
-
 /** @} */
 
 #ifdef __cplusplus
diff --git a/source/sdl/sdl_rom_checksum.h b/source/sdl/sdl_rom_checksum.h
new file mode 100644
index 0000000000..022c84161f
--- /dev/null
+++ b/source/sdl/sdl_rom_checksum.h
@@ -0,0 +1,120 @@
+/* Copyright (C) 2023 Texas Instruments Incorporated.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+/**
+ *  @file  sdl_rom_checksum.h
+ *
+ *  @brief This file contains the SDL ROM Checksum API's
+ */
+
+/**
+ *   @ingroup SDL_MODULE
+ *   @defgroup SDL_ROM_CHECKSUM_API ROM_CHECKSUM API
+ *
+ *   Provides the APIs for ROM Checksum.
+ */
+#ifndef SDL_ROM_CHECKSUM_H_
+#define SDL_ROM_CHECKSUM_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include <sdl/include/soc_config.h>
+#if defined (IP_VERSION_ROMCHECKSUM_V0)
+#include <sdl/rom_checksum/sdl_ip_rom_checksum.h>
+#endif
+
+/**
+* @defgroup SDL_ROM_CHECKSUM_FUNCTION  ROM Checksum Functions
+* @ingroup SDL_ROM_CHECKSUM_API
+*/
+
+/**
+* @defgroup SDL_ROM_CHECKSUM_MACROS ROM Checksum MACROS
+* @ingroup SDL_ROM_CHECKSUM_API
+*/
+
+/**
+ *  @addtogroup SDL_ROM_CHECKSUM_MACROS
+    @{
+ *
+ */
+
+/**
+ * \brief  Macro defines the length of data to be hashed.
+ *          data to be hashed length is taken from known location of ROM.
+ */
+#define SDL_LENGTH_OF_DATA_TO_BE_HASHED ((uint32_t)196544)
+
+/**
+ * \brief  Macro defines the length of golden data.
+ *         Golden data length is taken from known location of ROM.
+ */
+#define SDL_LENGTH_OF_GOLDEN_DATA ((uint64_t)8)
+
+/**
+ * \brief  Macro defines the pointer of golden data.
+ *          Golden data pointer is taken from known location of ROM.
+ */
+#define SDL_GOLDEN_DATA_POINTER (uint64_t *)(0x004182FFC0)
+
+/**
+ * \brief  Macro defines the pointer of data to be hashed.
+ *         data to be hashed pointer is  taken from known location of ROM.
+ */
+#define SDL_DATA_TO_BE_HASHED_POINTER (uint8_t *)(0x0041800000)
+
+/** @} */
+
+/**
+ *  @addtogroup SDL_ROM_CHECKSUM_FUNCTION
+    @{
+ *
+ */
+
+/**
+ *  \brief This function will compute Checksum of ROM.
+ *
+ *  \return The SDL error code for the API.
+ *                          If failed: SDL_EFAIL
+ *                          If pointer is invalid: SDL_EBADARGS
+ *                          If  Length is Invalid: SDL_EBADARGS
+ *                          Success: SDL_PASS
+ *
+ */
+int32_t SDL_ROM_Checksum_compute (void);
+
+/** @} */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SDL_ROM_CHECKSUM_H_ */
\ No newline at end of file
diff --git a/source/sdl/sdl_vtm.h b/source/sdl/sdl_vtm.h
index 94e3dc8f9f..ee1894913f 100644
--- a/source/sdl/sdl_vtm.h
+++ b/source/sdl/sdl_vtm.h
@@ -48,9 +48,7 @@ extern "C" {
 
 #include <stdint.h>
 #include <stdbool.h>
-
 #include <sdl/include/soc_config.h>
-
 #if defined (IP_VERSION_VTM_V0)
 #include <sdl/vtm/v0/sdlr_vtm.h>
 #include <sdl/vtm/v0/sdl_ip_vtm.h>
@@ -58,7 +56,7 @@ extern "C" {
 
 /**
  *
- *   @defgroup SDL_VTM_API Voltage and Thermal Monitor(VTM)
+ *   @defgroup SDL_VTM_API APIs for VTM
  *   Provides the APIs for VTM.
  */
 
@@ -71,11 +69,9 @@ extern "C" {
 @ingroup SDL_VTM_API
 */
 
-
-/** ===========================================================================
+/**
  *  @addtogroup SDL_VTM_DATASTRUCT
     @{
- * ============================================================================
  */
 
 
@@ -151,11 +147,11 @@ typedef struct {
     uint32_t                    vtm_ts_th2;
 } SDL_VTM_staticRegsTs;
 
+/** @} */
 
-/** ============================================================================
+/**
  *  @addtogroup SDL_VTM_FUNCTION
     @{
- * ============================================================================
  */
 
 /**
@@ -294,3 +290,4 @@ int32_t SDL_VTM_getStaticRegistersTs(SDL_VTM_InstTs instance, SDL_VTM_staticRegs
 #endif  /* extern "C" */
 
 #endif  /* end of SDL_VTM_H definition */
+/** @} */
\ No newline at end of file
diff --git a/source/sdl/stc/v0/sdl_stc.h b/source/sdl/stc/v0/sdl_stc.h
index cc77fd9cda..0796097915 100644
--- a/source/sdl/stc/v0/sdl_stc.h
+++ b/source/sdl/stc/v0/sdl_stc.h
@@ -161,8 +161,9 @@ typedef struct
     /** Scan mode configuration. Fixed Configuration – Only this configuration value is supported  */
     uint32_t scanEnHighCap_idleCycle;
 
-}__attribute__((packed))
-SDL_STC_ScanModeconfig;
+}SDL_STC_ScanModeconfig;
+
+
 
 typedef struct
 {
@@ -183,14 +184,14 @@ typedef struct
     /** Configure scan mode configuration */
     SDL_STC_ScanModeconfig modeConfig;
 
-} __attribute__((packed))
-SDL_STC_Config;
+}SDL_STC_Config;
+
 
 /** @} */
 
 /**
 
-@addtogroup SDL_DCC_ENUM
+@addtogroup SDL_STC_ENUM
 @{
 */
 
diff --git a/source/sdl/stc/v0/soc/am263x/sdl_stc_soc.c b/source/sdl/stc/v0/soc/am263x/sdl_stc_soc.c
index 21ca92b087..cecf348800 100644
--- a/source/sdl/stc/v0/soc/am263x/sdl_stc_soc.c
+++ b/source/sdl/stc/v0/soc/am263x/sdl_stc_soc.c
@@ -39,9 +39,6 @@
  *            This also contains some related macros and Helper APIs.
  */
 
- /**
- * Design: PROC_SDL-1021
- */
 
 
 #include <sdl/stc/v0/sdl_stc.h>
@@ -51,7 +48,9 @@
 /********************************************************************************************************
 *   API for getting the status of specified STC instance
 *********************************************************************************************************/
-
+/**
+ *  Design:PROC_SDL-6019
+ */
 
 int32_t SDL_STC_getStatus(SDL_STC_Inst instance)
 {
@@ -113,6 +112,9 @@ int32_t SDL_STC_getStatus(SDL_STC_Inst instance)
 /********************************************************************************************************
 * Helper  API for Configuring instance specified STC instance
 *********************************************************************************************************/
+/**
+ *  Design:PROC_SDL-6022
+ */
 
 static int32_t SDL_STC_configure(SDL_STC_Inst instance, SDL_STC_Config *pConfig, SDL_STC_TestType testType)
 {
@@ -196,6 +198,10 @@ static int32_t SDL_STC_configure(SDL_STC_Inst instance, SDL_STC_Config *pConfig,
 * Helper  API for Configuring to enable test for  specified STC instance
 *********************************************************************************************************/
 
+/**
+ *  Design:PROC_SDL-6023
+ */
+
 static int32_t  SDL_STC_runTest(SDL_STC_Inst instance )
 {
    int32_t sdlResult = SDL_EFAIL;
@@ -276,8 +282,9 @@ static void  __attribute__((noinline)) SDL_Delay(void)
 *   API for Performing STC test for specified STC instance
 *********************************************************************************************************/
 /**
- *  Design: PROC_SDL-3442
+ *  Design: PROC_SDL-6021
  */
+
 int32_t   SDL_STC_selfTest(SDL_STC_Inst instance, SDL_STC_TestType testType, SDL_STC_Config *pConfig )
 {
     int32_t sdlResult= SDL_EFAIL;
diff --git a/source/sdl/stc/v0/soc/am273x/sdl_stc_soc.c b/source/sdl/stc/v0/soc/am273x/sdl_stc_soc.c
index d53e219e9b..bf8c73ed85 100644
--- a/source/sdl/stc/v0/soc/am273x/sdl_stc_soc.c
+++ b/source/sdl/stc/v0/soc/am273x/sdl_stc_soc.c
@@ -39,10 +39,6 @@
  *            This also contains some related macros and Helper APIs.
  */
 
- /**
- * Design: PROC_SDL-1021
- */
-
 
 #include <sdl/stc/v0/sdl_stc.h>
 
@@ -52,7 +48,9 @@
 /********************************************************************************************************
 *   API for getting the status of specified STC instance
 *********************************************************************************************************/
-
+/**
+ *  Design:PROC_SDL-6019
+ */
 
 int32_t SDL_STC_getStatus(SDL_STC_Inst instance)
 {
@@ -114,6 +112,9 @@ int32_t SDL_STC_getStatus(SDL_STC_Inst instance)
 /********************************************************************************************************
 * Helper  API for Configuring instance specified STC instance
 *********************************************************************************************************/
+/**
+ *  Design:PROC_SDL-6022
+ */
 
 static int32_t SDL_STC_configure(SDL_STC_Inst instance, SDL_STC_Config *pConfig, SDL_STC_TestType testType)
 {
@@ -196,6 +197,10 @@ static int32_t SDL_STC_configure(SDL_STC_Inst instance, SDL_STC_Config *pConfig,
 * Helper  API for Configuring to enable test for  specified STC instance
 *********************************************************************************************************/
 
+/**
+ *  Design:PROC_SDL-6023
+ */
+
 static int32_t  SDL_STC_runTest(SDL_STC_Inst instance )
 {
    int32_t sdlResult = SDL_EFAIL;
@@ -278,8 +283,9 @@ static void  __attribute__((noinline)) SDL_Delay(void)
 *   API for Performing STC test for specified STC instance
 *********************************************************************************************************/
 /**
- *  Design: PROC_SDL-3442
+ *  Design: PROC_SDL-6021
  */
+
 int32_t   SDL_STC_selfTest(SDL_STC_Inst instance, SDL_STC_TestType testType,SDL_STC_Config *pConfig)
 {
     int32_t sdlResult= SDL_EFAIL;
@@ -308,6 +314,9 @@ int32_t   SDL_STC_selfTest(SDL_STC_Inst instance, SDL_STC_TestType testType,SDL_
 /********************************************************************************************************
 *   API for Performing DSP Init for STC test performing.
 *********************************************************************************************************/
+/**
+ *  Design:PROC_SDL-6020
+ */
 
 void SDL_STC_dspInit(void)
 {
diff --git a/source/sdl/stc/v0/soc/awr294x/sdl_stc_soc.c b/source/sdl/stc/v0/soc/awr294x/sdl_stc_soc.c
index 956e7a1504..9f36aa4428 100644
--- a/source/sdl/stc/v0/soc/awr294x/sdl_stc_soc.c
+++ b/source/sdl/stc/v0/soc/awr294x/sdl_stc_soc.c
@@ -39,10 +39,6 @@
  *            This also contains some related macros and Helper APIs.
  */
 
- /**
- * Design: PROC_SDL-1021
- */
-
 
 #include <sdl/stc/v0/sdl_stc.h>
 
@@ -52,6 +48,9 @@
 /********************************************************************************************************
 *   API for getting the status of specified STC instance
 *********************************************************************************************************/
+/**
+ *  Design:PROC_SDL-6019
+ */
 
 
 int32_t SDL_STC_getStatus(SDL_STC_Inst instance)
@@ -113,6 +112,10 @@ int32_t SDL_STC_getStatus(SDL_STC_Inst instance)
 /********************************************************************************************************
 * Helper  API for Configuring instance specified STC instance
 *********************************************************************************************************/
+/**
+ *  Design:PROC_SDL-6022
+ */
+
 
 static int32_t SDL_STC_configure(SDL_STC_Inst instance, SDL_STC_Config *pConfig, SDL_STC_TestType testType)
 {
@@ -195,6 +198,11 @@ static int32_t SDL_STC_configure(SDL_STC_Inst instance, SDL_STC_Config *pConfig,
 * Helper  API for Configuring to enable test for  specified STC instance
 *********************************************************************************************************/
 
+/**
+ *  Design:PROC_SDL-6023
+ */
+
+
 static int32_t  SDL_STC_runTest(SDL_STC_Inst instance )
 {
    int32_t sdlResult = SDL_EFAIL;
@@ -277,7 +285,7 @@ static void  __attribute__((noinline)) SDL_Delay(void)
 *   API for Performing STC test for specified STC instance
 *********************************************************************************************************/
 /**
- *  Design: PROC_SDL-3442
+ *  Design:  PROC_SDL-6021
  */
 int32_t   SDL_STC_selfTest(SDL_STC_Inst instance, SDL_STC_TestType testType,SDL_STC_Config *pConfig)
 {
diff --git a/source/sdl/vtm/v0/sdl_ip_vtm.h b/source/sdl/vtm/v0/sdl_ip_vtm.h
index 1c0518230e..1b8fc9fbb1 100644
--- a/source/sdl/vtm/v0/sdl_ip_vtm.h
+++ b/source/sdl/vtm/v0/sdl_ip_vtm.h
@@ -48,29 +48,19 @@ extern "C" {
 #include <sdl/vtm/v0/soc/am243x/sdl_soc_vtm.h>
 #endif
 /**
- *  @ingroup SDL_IP_MODULE
- *  @defgroup SDL_IP_VTM_API VTM Low-Level API
+ *  \defgroup SDL_IP_VTM_API VTM Low-Level API
+ *  \ingroup SDL_VTM_API
  *
- *  Provides the APIs for VTM IP.
+ *  This module contains the Low-Level APIs to program and use the VTM module.
+ *
+ *  @{
  */
 
 /**
-@defgroup SDL_IP_VTM_DATASTRUCT  VTM Data Structures
-@ingroup SDL_IP_VTM_API
-*/
-/**
-@defgroup SDL_IP_VTM_FUNCTION  VTM Functions
-@ingroup SDL_IP_VTM_API
-*/
-/**
-@defgroup SDL_IP_VTM_ENUMS VTM Enum Data defines
-@ingroup SDL_IP_VTM_API
-*/
-
-/** ===========================================================================
- *  @addtogroup SDL_IP_VTM_ENUMS
-    @{
- * ============================================================================
+ * \ingroup SDL_VTM_API
+ * \defgroup SDL_IP_VTM_Enum VTM IP Enumerated Data Types
+ * @{
+ *  Provides the APIs for VTM IP.
  */
 
 /**
@@ -87,7 +77,6 @@ typedef uint8_t SDL_VTM_configVdCtrl;
  * \brief This enumerator define for VTM TS configuration valid map
  *
  *  \anchor SDL_VTM_configTsCtrl
- *  \name   VTM temperature sensor STAT read valid map
  */
 
 typedef uint8_t SDL_VTM_configTsCtrl;
@@ -101,7 +90,6 @@ typedef uint8_t SDL_VTM_configTsCtrl;
  *        voltage domain supply voltages
  *
  *  \anchor SDL_VTM_vid_opp
- *  \name VTM OPP VID Codes
  *
  */
 
@@ -122,7 +110,6 @@ typedef  uint8_t SDL_VTM_vid_opp;
  * \brief This enumerator defines the core voltage domain mapping of VTM VD
  *
  *  \anchor SDL_VTM_ts_stat_vd_map
- *  \name VTM Core Voltage domain map
  */
 typedef  uint8_t SDL_VTM_ts_stat_vd_map;
     /** RTC Voltage Domain map */
@@ -141,8 +128,6 @@ typedef  uint8_t SDL_VTM_ts_stat_vd_map;
  * \brief This enumerator define for VTM Voltage domain threshold interrupt control
  *
  *  \anchor SDL_VTM_intrCtrl
- *  \name VTM Voltage domain threshold interrupt control
- *
  */
 
 typedef uint16_t SDL_VTM_intrCtrl;
@@ -166,7 +151,6 @@ typedef uint16_t SDL_VTM_intrCtrl;
  * \brief This enumerator define for VTM Voltage domain Event selection set
  *
  *  \anchor SDL_VTM_vdEvtSel_set
- *  \name VTM Voltage domain Event selection set
  */
 
 typedef uint16_t SDL_VTM_vdEvtSel_set;
@@ -186,7 +170,6 @@ typedef uint16_t SDL_VTM_vdEvtSel_set;
  *         update of the fields in the temperature sensor control field.
  *
  *  \anchor SDL_VTM_tsGlobal_ctrl_valid_map
- *  \name VTM temperature sensor id
  *
  */
 
@@ -204,7 +187,6 @@ typedef uint32_t SDL_VTM_tsGlobal_ctrl_valid_map;
  *        select options
  *
  *  \anchor SDL_VTM_tsGlobal_clkSel
- *  \name VTM Temperature Sensor global control clock select
  *
  */
 
@@ -219,7 +201,6 @@ typedef uint8_t SDL_VTM_tsGlobal_clkSel;
  *        divide options
  *
  *  \anchor SDL_VTM_tsGlobal_clkDiv
- *  \name VTM Temperature Sensor global control clock divide
  *
  */
 
@@ -295,8 +276,6 @@ typedef uint8_t SDL_VTM_tsGlobal_clkDiv;
  *        max temperature alert enable control
  *
  *  \anchor SDL_VTM_tsGlobal_any_maxt_outrg_alert_en
- *  \name VTM Temperature Sensor global control any
- *        maximum temperature alert enable
  *
  */
 
@@ -310,8 +289,6 @@ typedef uint8_t  SDL_VTM_tsGlobal_any_maxt_outrg_alert_en;
  *        samples per count
  *
  *  \anchor SDL_VTM_tsGlobal_samples_per_count
- *  \name VTM Temperature Sensor global control samples per count
- *
  */
 
 typedef uint16_t SDL_VTM_tsGlobal_samples_per_count;
@@ -321,7 +298,6 @@ typedef uint16_t SDL_VTM_tsGlobal_samples_per_count;
  * \brief This enumerator define for VTM Temperature sensor control valid map
  *
  *  \anchor SDL_VTM_tsCtrl_valid_map
- *  \name VTM Temperature Sensor control valid map
  *
  */
 typedef uint8_t SDL_VTM_tsCtrl_valid_map;
@@ -336,8 +312,6 @@ typedef uint8_t SDL_VTM_tsCtrl_valid_map;
  *        maximum temperature out of range alert control
  *
  *  \anchor SDL_VTM_tsCtrl_max_outrg_alert
- *  \name   VTM temperature sensor band gap maximum temperature
- *          out of range alert control
  *
  */
 
@@ -351,8 +325,6 @@ typedef uint8_t  SDL_VTM_tsCtrl_max_outrg_alert;
  *        VTM temperature sensor band gap reset  control bits
  *
  *  \anchor SDL_VTM_tsCtrl_resetCtrl
- *  \name   VTM temperature sensor band gap reset  control bits
- *
  */
 
 typedef  uint8_t SDL_VTM_tsCtrl_resetCtrl;
@@ -365,8 +337,6 @@ typedef  uint8_t SDL_VTM_tsCtrl_resetCtrl;
  *        VTM temperature sensor mode control bits
  *
  *  \anchor SDL_VTM_tsCtrl_mode
- *  \name   VTM temperature sensor mode control bits
- *
  */
 
 typedef  uint8_t    SDL_VTM_tsCtrl_mode;
@@ -380,8 +350,6 @@ typedef  uint8_t    SDL_VTM_tsCtrl_mode;
  *        VTM temperature sensor band gap single shot mode start of conversion trigger
  *
  *  \anchor SDL_VTM_tsCtrl_singleshot_conv_stat
- *  \name   VTM temperature sensor band gap single shot mode start of conversion trigger
- *
  */
 
 typedef  uint8_t SDL_VTM_tsCtrl_singleshot_conv_stat;
@@ -394,8 +362,6 @@ typedef  uint8_t SDL_VTM_tsCtrl_singleshot_conv_stat;
  *        VTM Temperature Sensor thresholds valid bit map
  *
  *  \anchor SDL_VTM_thr_valid_map
- *  \name   VTM Temperature Sensor thresholds valid bit map
- *
  */
 
 typedef uint8_t  SDL_VTM_thr_valid_map;
@@ -409,8 +375,6 @@ typedef uint8_t  SDL_VTM_thr_valid_map;
  *        VTM temperature sensor STAT read valid map
  *
  *  \anchor SDL_VTM_Stat_read_ctrl
- *  \name   VTM temperature sensor STAT read valid map
- *
  */
 
 typedef uint8_t SDL_VTM_Stat_read_ctrl;
@@ -427,7 +391,6 @@ typedef uint8_t SDL_VTM_Stat_read_ctrl;
  *        This is the data_out value of the temperature sensor stat register
  *
  *  \anchor SDL_VTM_adc_code
- *  \name   VTM temperature sensor ADC code
  */
 
 typedef  int16_t SDL_VTM_adc_code;
@@ -437,7 +400,6 @@ typedef  int16_t SDL_VTM_adc_code;
  * \brief This enumerator define for VTM Voltage domain event status
  *
  *  \anchor SDL_VTM_vdEvt_status
- *  \name VTM Voltage domain event status
  *
  */
 
@@ -448,11 +410,12 @@ typedef uint8_t SDL_VTM_vdEvt_status;
 #define SDL_VTM_VD_EVT_STAT_GT_TH1_ALERT                  (1u)
 #define SDL_VTM_VD_EVT_STAT_GT_TH2_ALERT                  (2u)
 
-
-/** ============================================================================
- *  @addtogroup SDL_IP_VTM_DATASTRUCT
-    @{
- * ============================================================================
+/** @} */
+/**
+ * \ingroup SDL_VTM_API
+ * \defgroup SDL_IP_VTM_DATASTRUCT VTM IP Data Structures
+ * @{
+ *  Provides the APIs for VTM IP.
  */
 
 /** \brief VTM Global Configuration Registers
@@ -575,12 +538,13 @@ typedef struct {
     SDL_VTM_adc_code           data_out;
 } SDL_VTM_Stat_val;
 
+/** @} */
 
-/** ============================================================================
- *  @addtogroup SDL_IP_VTM_FUNCTION
-    @{
- * ============================================================================
- */
+/**
+* \defgroup SDL_IP_VTM_FUNCTION  VTM IP Functions
+* \ingroup SDL_VTM_API
+* @{
+*/
 
 /**
  *  \brief get sensor and VD count
@@ -822,7 +786,9 @@ int32_t SDL_VTM_tsSetMaxTOutRgAlertThr(const SDL_VTM_cfg2Regs    	*p_cfg2,
                                       int32_t               low_temp_in_milli_degree_celcius);
 
 
+/** @} */
+/** @} */
 #ifdef __cplusplus
 }
 #endif  /* extern "C" */
-#endif  /* end of SDL_IP_VTM_H definition */
+#endif  /* end of SDL_IP_VTM_H definition */
\ No newline at end of file
diff --git a/source/sdl/vtm/v0/soc/am243x/sdl_soc_vtm.h b/source/sdl/vtm/v0/soc/am243x/sdl_soc_vtm.h
index 7a1d11a8cc..7c571f8c0f 100644
--- a/source/sdl/vtm/v0/soc/am243x/sdl_soc_vtm.h
+++ b/source/sdl/vtm/v0/soc/am243x/sdl_soc_vtm.h
@@ -42,28 +42,6 @@ extern "C"
 {
 #endif
 
-/**
- *
- * @ingroup  SDL_MODULE
- * @defgroup SDL_VTM_API Voltage and Thermal Monitor(VTM)
- *
- * 
- */
-
-/**
-@defgroup SDL_VTM_ENUM VTM Enum Data defines
-@ingroup SDL_VTM_API
-*/
-
-/** ===========================================================================
- *  @addtogroup SDL_VTM_ENUM
-    @{
- * ============================================================================
- */
-
-/*
-* SDL definitions for SoC VTM Instances:
-*/
 /** ---------------------------------------------------------------------------
  * @brief This enumerator defines the VTM Temperature sensor
  *
diff --git a/source/sdl/vtm/v0/soc/am64x/sdl_soc_vtm.c b/source/sdl/vtm/v0/soc/am64x/sdl_soc_vtm.c
index 61c2ef1fe7..327d4c0079 100644
--- a/source/sdl/vtm/v0/soc/am64x/sdl_soc_vtm.c
+++ b/source/sdl/vtm/v0/soc/am64x/sdl_soc_vtm.c
@@ -70,9 +70,7 @@ bool SDL_VTM_getBaseAddr(SDL_VTM_cfgReg cfgReg, uint32_t *vtmBaseAddr)
             default:
                 break;
         }
+	    *vtmBaseAddr = (uint32_t)SDL_DPL_addrTranslate(*vtmBaseAddr, size);
     }
-
-    *vtmBaseAddr = (uint32_t)SDL_DPL_addrTranslate(*vtmBaseAddr, size);
-
     return (instValid);
 }
\ No newline at end of file
diff --git a/source/sdl/vtm/v0/soc/am64x/sdl_soc_vtm.h b/source/sdl/vtm/v0/soc/am64x/sdl_soc_vtm.h
index 14f20a0313..e539674ef9 100644
--- a/source/sdl/vtm/v0/soc/am64x/sdl_soc_vtm.h
+++ b/source/sdl/vtm/v0/soc/am64x/sdl_soc_vtm.h
@@ -42,28 +42,6 @@ extern "C"
 {
 #endif
 
-/**
- *
- * @ingroup  SDL_MODULE
- * @defgroup SDL_VTM_API Voltage and Thermal Monitor(VTM)
- *
- *
- */
-
-/**
-@defgroup SDL_VTM_ENUM VTM Enum Data defines
-@ingroup SDL_VTM_API
-*/
-
-/** ===========================================================================
- *  @addtogroup SDL_VTM_ENUM
-    @{
- * ============================================================================
- */
-
-/*
-* SDL definitions for SoC VTM Instances:
-*/
 /** ---------------------------------------------------------------------------
  * @brief This enumerator defines the VTM Temperature sensor
  *
