Brief: Serial Interface related macro definitions
icss_pin_macros.inc time_macros.inc
Read 1 data packet from the SPI interface.
PEAK cycles: ~ cycle
Pseudo code:
dataReg = 0
bitId = PACKETSIZE - 1
loop: READ_PACKET
set SCLK_PIN
wait 16 cycles
clear SCLK_PIN
dataReg | To store read serial data packet |
PACKETSIZE | Size of data packet in bits |
bitId | To track Bit index (8 bits wide) |
SCLK_PIN | PRU Pin number for SCLK |
SDI_PIN | PRU Pin number for SDI |
DELAY_COMPEN_1 | PRU cycles to wait for while SCLK is high |
DELAY_COMPEN_2 | PRU cycles to wait for while SCLK is low |
Read 1 data packet from the SPI interface.
PEAK cycles: ~ cycle
Pseudo code:
dataReg = 0
bitId = PACKETSIZE - 1
loop: READ_PACKET
set SCLK_PIN
wait 16 cycles
clear SCLK_PIN
dataReg | To store read serial data packet |
PACKETSIZE | Size of data packet in bits |
bitId | To track Bit index (8 bits wide) |
SCLK_PIN | PRU Pin number for SCLK |
SDI_PIN | PRU Pin number for SDI |
DELAY_COMPEN_1 | PRU cycles to wait for while SCLK is high |
DELAY_COMPEN_2 | PRU cycles to wait for while SCLK is low |
Read 1 data packet from the SPI interface.
PEAK cycles: ~ cycle
Pseudo code:
dataReg = 0
bitId = PACKETSIZE - 1
loop: READ_PACKET
set SCLK_PIN
wait 16 cycles
clear SCLK_PIN
dataReg | To store read serial data packet |
PACKETSIZE | Size of data packet in bits |
bitId | To track Bit index (8 bits wide) |
SDI_PIN | PRU Pin number for SDI |
temp_reg | temporary register |
IEP_INST | IEP Instance being used for SCLK |
SYNC_SIGNAL | IEP Sync out signal being used for SCLK |
DELAY_COMPEN_1 | PRU cycles to wait for before reading PRU pins |
DELAY_COMPEN_2 | PRU cycles to wait for to sync with SCLK period |
Read 1 data packet from the SPI interface.
PEAK cycles: ~ cycle
Pseudo code:
dataReg = 0
bitId = PACKETSIZE - 1
loop: READ_PACKET
set SCLK_PIN
wait 16 cycles
clear SCLK_PIN
dataReg | To store read serial data packet |
PACKETSIZE | Size of data packet in bits |
bitId | To track Bit index (8 bits wide) |
SDI_PIN | PRU Pin number for SDI |
temp_reg | temporary register |
IEP_INST | IEP Instance being used for SCLK |
SYNC_SIGNAL | IEP Sync out signal being used for SCLK |
DELAY_COMPEN_1 | PRU cycles to wait for before reading PRU pins |
DELAY_COMPEN_2 | PRU cycles to wait for to sync with SCLK period |
Send 1 data packet through the SPI interface.
PEAK cycles: ~ cycle
Pseudo code:
dataReg = 0
bitId = PACKETSIZE - 1
loop: READ_PACKET
set SCLK_PIN
wait 16 cycles
clear SCLK_PIN
dataReg | Contains data packet to send |
PACKETSIZE | Size of data packet in bits |
bitId | To track Bit index (8 bits wide) |
SCLK_PIN | PRU Pin number for SCLK |
SDO_PIN | PRU Pin number for SDO |
DELAY_COMPEN_1 | PRU cycles to wait for while SCLK is high |
DELAY_COMPEN_2 | PRU cycles to wait for while SCLK is low |
Send 1 data packet through the SPI interface.
PEAK cycles: ~ cycle
Pseudo code:
dataReg = 0
bitId = PACKETSIZE - 1
loop: READ_PACKET
set SCLK_PIN
wait 16 cycles
clear SCLK_PIN
dataReg | Contains data packet to send |
PACKETSIZE | Size of data packet in bits |
bitId | To track Bit index (8 bits wide) |
SCLK_PIN | PRU Pin number for SCLK |
SDO_PIN | PRU Pin number for SDO |
DELAY_COMPEN_1 | PRU cycles to wait for while SCLK is high |
DELAY_COMPEN_2 | PRU cycles to wait for while SCLK is low |
Send 1 data packet through the SPI interface.
PEAK cycles: ~ cycle
Pseudo code:
dataReg = 0
bitId = PACKETSIZE - 1
loop: READ_PACKET
set SCLK_PIN
wait 16 cycles
clear SCLK_PIN
dataReg | Contains data packet to send |
PACKETSIZE | Size of data packet in bits |
bitId | To track Bit index (8 bits wide) |
SDO_PIN | PRU Pin number for SDO |
temp_reg | temporary register |
IEP_INST | IEP Instance being used for SCLK |
SYNC_SIGNAL | IEP Sync out signal being used for SCLK |
DELAY_COMPEN_1 | PRU cycles to wait for before sending data, to sync with IEP signal |
DELAY_COMPEN_2 | PRU cycles to wait for to sync with SCLK period |
Send 1 data packet through the SPI interface.
PEAK cycles: ~ cycle
Pseudo code:
dataReg = 0
bitId = PACKETSIZE - 1
loop: READ_PACKET
set SCLK_PIN
wait 16 cycles
clear SCLK_PIN
dataReg | Contains data packet to send |
PACKETSIZE | Size of data packet in bits |
bitId | To track Bit index (8 bits wide) |
SDO_PIN | PRU Pin number for SDO |
temp_reg | temporary register |
IEP_INST | IEP Instance being used for SCLK |
SYNC_SIGNAL | IEP Sync out signal being used for SCLK |
DELAY_COMPEN_1 | PRU cycles to wait for before sending data, to sync with IEP SCLK signal |
DELAY_COMPEN_2 | PRU cycles to wait for to sync with SCLK period |
Send 1 data packet through the serial interface.
SPI Mode | CPOL | CPHA | Idle State Clock Polarity | Clock Phase Used to Sample and/or Shift the Data
0 | 0 | 0 | Logic low | Data sampled on rising edge and shifted out on the falling edge
1 | 0 | 1 | Logic low | Data sampled on the falling edge and shifted out on the rising edge
2 | 1 | 0 | Logic high | Data sampled on the rising edge and shifted out on the falling edge
3 | 1 | 1 | Logic high | Data sampled on the falling edge and shifted out on the rising edge
PEAK cycles: ~ cycle
Pseudo code:
dataReg = 0
bitId = PACKETSIZE - 1
loop: READ_PACKET
set SCLK_PIN
wait 16 cycles
clear SCLK_PIN
dataReg | Contains data packet to send |
MODE | SPI MODE: MODE0, MODE1, MODE2, MODE3 |
ENDIAN | MSB: MSB First, LSB: LSB First |
SCLK_TRGR | IEP_SYNC: Use IEP Sync_out for SCLK, BIT_BANG: Drive PRU GPO using R30 |
CONFIG | Dependent on the invoked macro |
Read 1 data packet through the serial interface.
SPI Mode | CPOL | CPHA | Idle State Clock Polarity | Clock Phase Used to Sample and/or Shift the Data
0 | 0 | 0 | Logic low | Data sampled on rising edge and shifted out on the falling edge
1 | 0 | 1 | Logic low | Data sampled on the falling edge and shifted out on the rising edge
2 | 1 | 0 | Logic high | Data sampled on the rising edge and shifted out on the falling edge
3 | 1 | 1 | Logic high | Data sampled on the falling edge and shifted out on the rising edge
PEAK cycles: ~ cycle
Pseudo code:
dataReg = 0
bitId = PACKETSIZE - 1
loop: READ_PACKET
set SCLK_PIN
wait 16 cycles
clear SCLK_PIN
dataReg | To store read data packet |
MODE | SPI MODE: MODE0, MODE1, MODE2, MODE3 |
ENDIAN | MSB: MSB First, LSB: LSB First |
SCLK_TRGR | IEP_SYNC: Use IEP Sync_out for SCLK, BIT_BANG: Drive PRU GPO using R30 |
CONFIG | Dependent on the invoked macro |
Read 1 data packet from the serial interface.
PEAK cycles: ~ cycle
Pseudo code:
dataReg = 0
bitId = PACKETSIZE - 1
loop: READ_PACKET
set SCLK_PIN
wait 16 cycles
clear SCLK_PIN
NO_OF_PACKETS | Number of data packets per frame |
WAIT_CSRD | Delay required between CS and SCLK trigger |
tempDataReg | To store read serial data packet temporarily |
packetId | To track Packet indices (8 bits wide) |
dataRegBaseAddr | (8 bits) Address of starting data register => register R1.bx must be used |
CONFIG | Dependent on the invoked macro |