AESCTRXXF3.h

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/*
 * Copyright (c) 2021-2026, Texas Instruments Incorporated
 * All rights reserved.
 *
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 *
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 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
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 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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 */
#ifndef ti_drivers_aesctr_AESCTRXXF3__include
#define ti_drivers_aesctr_AESCTRXXF3__include

#include <stdbool.h>
#include <stdint.h>

#include <ti/drivers/AESCTR.h>
#include <ti/drivers/cryptoutils/aes/AESCommonXXF3.h>
#include <ti/drivers/cryptoutils/sharedresources/CryptoResourceXXF3.h>

#include <ti/devices/DeviceFamily.h>

#if (DeviceFamily_PARENT != DeviceFamily_PARENT_CC35XX)
    #include DeviceFamily_constructPath(driverlib/aes.h)
#endif

#ifdef __cplusplus
extern "C" {
#endif

/*
 * Default AES CTR auto config:
 *  ECB SRC as BUF
 *  Trigger points for auto ECB as RDTX3 and WRBUF3S
 *   (the first encryption starts by writing BUF3, the successive ones by reading TXT3)
 *  Counter size as 128-bits
 *  Counter endianness as Big Endian
 *  BUSHALT enabled
 */
#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0) || (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX)
    #define AESCTRXXF3_DEFAULT_AUTOCFG                                                \
        ((uint32_t)AES_AUTOCFG_AESSRC_BUF | (uint32_t)AES_AUTOCFG_TRGAES_WRBUF3S |    \
         (uint32_t)AES_AUTOCFG_TRGAES_RDTXT3 | (uint32_t)AES_AUTOCFG_CTRSIZE_CTR128 | \
         (uint32_t)AES_AUTOCFG_CTRENDN_BIGENDIAN | (uint32_t)AES_AUTOCFG_BUSHALT_EN)
#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC35XX)
    /* Not used for CC35XX */
#else
    #error "Unsupported DeviceFamily_Parent for AESCTRXXF3!"
#endif

/*
 * AES CTR auto config for handling processing of the last
 * block of input to avoid starting encryption of the next counter block and
 * incrementing the counter value when the output is read from TXT3.
 *
 *  ECB SRC as BUF
 *  Trigger for auto ECB as WRBUF3S
 *   (the first encryption starts by writing BUF3)
 *  Counter size as 128-bits
 *  Counter endianness as Big Endian
 *  BUSHALT enabled
 */
#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0) || (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX)
    #define AESCTRXXF3_LAST_BLOCK_AUTOCFG                                                 \
        ((uint32_t)AES_AUTOCFG_AESSRC_BUF | (uint32_t)AES_AUTOCFG_TRGAES_WRBUF3S |        \
         (uint32_t)AES_AUTOCFG_CTRSIZE_CTR128 | (uint32_t)AES_AUTOCFG_CTRENDN_BIGENDIAN | \
         (uint32_t)AES_AUTOCFG_BUSHALT_EN)
#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC35XX)
    /* Not used for CC35XX */
#else
    #error "Unsupported DeviceFamily_Parent for AESCTRXXF3!"
#endif

typedef AESCommonXXF3_HWAttrs AESCTRXXF3_HWAttrs;

typedef struct
{
    /* Common member first to allow struct to be cast to the common type */
    AESCommonXXF3_Object common;
    volatile uint32_t counter[AES_BLOCK_SIZE_WORDS];
    const uint8_t *input;
    uint8_t *output;
    size_t inputLength;
    size_t inputLengthRemaining;
    AESCTR_OperationUnion *operation;
    AESCTR_CallbackFxn callbackFxn;
    AESCTR_OperationType operationType;
    bool threadSafe;
#if ((DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) || (DeviceFamily_PARENT == DeviceFamily_PARENT_CC35XX))

    int_fast16_t hsmStatus;
    uint32_t keyAssetID;
    /* Intentionally use implementation-independent uint32_t datatype for
     * keyLocation to avoid user dependencies on any implementation-specific
     * headers (e.g. mbedTLS). This data type must be large enough to hold any
     * implementation-specific keyLocation data.
     */
    uint32_t keyLocation;
    /* To indicate whether a segmented operation is in progress */
    bool segmentedOperationInProgress;
#endif
} AESCTRXXF3_Object;

void AESCTRXXF3_processData(const uint8_t *input, uint8_t *output, size_t inputLength, bool isOneStepOrFinalOperation);
#if (DeviceFamily_PARENT != DeviceFamily_PARENT_CC35XX)

size_t AESCTRXXF3_configDataDMA(AESCommonXXF3_Object *object,
                                const uint8_t *input,
                                uint8_t *output,
                                size_t inputLength);

__STATIC_INLINE void AESCTRXXF3_readCounter(uint32_t counterOut[AES_BLOCK_SIZE_WORDS])
{
    /* Read the latest counter value from the AES engine */
    AESReadBUF32(&counterOut[0]);
}

__STATIC_INLINE void AESCTRXXF3_writeCounter(uint32_t counterIn[AES_BLOCK_SIZE_WORDS])
{
    AESWriteBUF32(&counterIn[0]);
}

__STATIC_INLINE bool AESCTR_acquireLock(AESCTR_Handle handle, uint32_t timeout)
{
    return CryptoResourceXXF3_acquireLock(timeout);
}
__STATIC_INLINE void AESCTR_releaseLock(AESCTR_Handle handle)
{
    CryptoResourceXXF3_releaseLock();
}
__STATIC_INLINE void AESCTR_enableThreadSafety(AESCTR_Handle handle)
{
    AESCTRXXF3_Object *object = (AESCTRXXF3_Object *)handle->object;
    object->threadSafe        = true;
}
__STATIC_INLINE void AESCTR_disableThreadSafety(AESCTR_Handle handle)
{
    AESCTRXXF3_Object *object = (AESCTRXXF3_Object *)handle->object;
    object->threadSafe        = false;
}
#endif /* (DeviceFamily_PARENT != DeviceFamily_PARENT_CC35XX) */

#ifdef __cplusplus
}
#endif

#endif /* ti_drivers_aesctr_AESCTRXXF3__include */