GPIOWFF3.h File Reference

Detailed Description

GPIO driver implementation for WiFi F3 devices.

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Overview

The GPIO header file should be included in an application as follows:

#include <ti/drivers/GPIO.h>
#include <ti/drivers/gpio/GPIOWFF3.h>

Refer to GPIO.h for a complete description of the GPIO driver APIs provided and examples of their use.

There are some WiFi F3 device-specific configuration values that can be used when calling GPIO_setConfig or GPIO_setConfigAndMux, listed below. All other macros should be used directly from GPIO.h.

There are some WiFi F3 device-specific mux values that can be used when calling GPIO_setConfigAndMux listed below.

IO Multiplexing

If an IO is multiplexed to an output signal or an analog signal, the IO must be configured with GPIO_CFG_NO_DIR. The output will automatically be enabled when needed. If an IO is multiplexed to a digital input or bi-directional signal, the IO must be configured as an input using GPIO_CFG_INPUT, GPIO_CFG_IN_PU etc. to ensure that the input buffer of the IO is enabled.

For IOs supporting analog signals, an additional mux setting GPIOWFF3_MUX_ANALOG can be used with GPIO_setConfigAndMux().

Software Controlled IO

Independently of the muxing, the IO can also be controlled/overriden by software. This means that if the IO is configured as an output (for example using GPIO_CFG_OUTPUT), then the output state of the IO is controlled by the software. The signal the IO is muxed to is ignored. This is useful for some scenarios, for example setting the sleep state of the IO before entering sleep. When the IO is only intended to be used as a software controlled IO, it is recommended to use the GPIO_MUX_GPIO mux setting.

#include <ti/drivers/GPIO.h>
#include <ti/devices/DeviceFamily.h>
#include <DeviceFamily_constructPath(inc/hw_iomux.h)>

Include dependency graph for GPIOWFF3.h:

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Go to the source code of this file.

Macros
WiFi F3 Device-Specific Mux Macros
#define	GPIOWFF3_MUX_ANALOG
	Mux IO to analog signal. More...
WiFi F3 Device-Specific GPIO_PinConfig Macros
#define	GPIOWFF3_DO_NOT_CONFIG
	Do not configure this pin. More...
Macros Used Internally by WiFi F3 GPIO Driver.
Do not use any of these macros.
#define	GPIO_CFG_DO_NOT_CONFIG_INTERNAL   GPIOWFF3_DO_NOT_CONFIG
#define	GPIO_MUX_GPIO_INTERNAL   (0x0D)
#define	GPIOWFF3_MUX_ANALOG_INTERNAL   (0x100)
#define	GPIOWFF3_CFG_CFG_S   (0)
#define	GPIOWFF3_CFG_CFG_M
#define	GPIOWFF3_CFG_PULLCTL_S   (0)
#define	GPIOWFF3_CFG_PULLCTL_M   ((IOMUX_GPIO2PCTL_CTL_M) << GPIOWFF3_CFG_PULLCTL_S)
#define	GPIOWFF3_CFG_CTL_S   (0)
#define	GPIOWFF3_CFG_CTL_M   ((IOMUX_GPIO2CTL_OUTOVREN_M | IOMUX_GPIO2CTL_OUT_M) << GPIOWFF3_CFG_CTL_S)
#define	GPIOWFF3_CFG_EVTCTL_S   (16)
#define	GPIOWFF3_CFG_EVTCTL_M   ((IOMUX_GPIO37ECTL_EVTDETCFG_M | IOMUX_GPIO2ECTL_TRGLVL_M) << GPIOWFF3_CFG_EVTCTL_S)
#define	GPIOWFF3_CFG_IOMUX_COMB_M   (GPIOWFF3_CFG_CFG_M | GPIOWFF3_CFG_PULLCTL_M | GPIOWFF3_CFG_CTL_M | GPIOWFF3_CFG_EVTCTL_M)
#define	GPIOWFF3_CFG_INTERNAL_M   ~GPIOWFF3_CFG_IOMUX_COMB_M
#define	GPIO_CFG_NO_DIR_INTERNAL   ((IOMUX_GPIO2CFG_OUTDISOVREN_DISABLE << GPIOWFF3_CFG_CFG_S) | (IOMUX_GPIO2CFG_IE_DISABLE << GPIOWFF3_CFG_CFG_S))
#define	GPIO_CFG_INPUT_INTERNAL   ((IOMUX_GPIO2CFG_OUTDISOVREN_DISABLE << GPIOWFF3_CFG_CFG_S) | (IOMUX_GPIO2CFG_IE_ENABLE << GPIOWFF3_CFG_CFG_S))
#define	GPIO_CFG_OUTPUT_INTERNAL
#define	GPIO_CFG_OUTPUT_DEFAULT_HIGH_INTERNAL   (IOMUX_GPIO2CTL_OUT_HIGH << GPIOWFF3_CFG_CTL_S)
#define	GPIO_CFG_OUTPUT_DEFAULT_LOW_INTERNAL   (IOMUX_GPIO2CTL_OUT_LOW << GPIOWFF3_CFG_CTL_S)
#define	GPIO_CFG_PULL_NONE_INTERNAL   (IOMUX_GPIO2PCTL_CTL_IPCTRL << GPIOWFF3_CFG_PULLCTL_S)
#define	GPIO_CFG_PULL_UP_INTERNAL   (IOMUX_GPIO2PCTL_CTL_UP << GPIOWFF3_CFG_PULLCTL_S)
#define	GPIO_CFG_PULL_DOWN_INTERNAL   (IOMUX_GPIO2PCTL_CTL_DOWN << GPIOWFF3_CFG_PULLCTL_S)
#define	GPIO_CFG_INT_NONE_INTERNAL   0
#define	GPIO_CFG_INT_FALLING_INTERNAL   (IOMUX_GPIO2ECTL_EVTDETCFG_NEG_EDGE << GPIOWFF3_CFG_EVTCTL_S)
#define	GPIO_CFG_INT_RISING_INTERNAL   (IOMUX_GPIO2ECTL_EVTDETCFG_POS_EDGE << GPIOWFF3_CFG_EVTCTL_S)
#define	GPIO_CFG_INT_LOW_INTERNAL   ((IOMUX_GPIO2ECTL_EVTDETCFG_LEVEL << GPIOWFF3_CFG_EVTCTL_S) | (IOMUX_GPIO2ECTL_TRGLVL_LOW << GPIOWFF3_CFG_EVTCTL_S))
#define	GPIO_CFG_INT_HIGH_INTERNAL
#define	GPIO_CFG_DRVSTR_LOW_INTERNAL   (IOMUX_GPIO20CFG_IOSTR_LOW << GPIOWFF3_CFG_CFG_S)
#define	GPIO_CFG_DRVSTR_HIGH_INTERNAL   (IOMUX_GPIO20CFG_IOSTR_HIGH << GPIOWFF3_CFG_CFG_S)
#define	GPIO_CFG_SHUTDOWN_WAKE_OFF_INTERNAL   0
#define	GPIO_CFG_SHUTDOWN_WAKE_HIGH_INTERNAL   0
#define	GPIO_CFG_SHUTDOWN_WAKE_LOW_INTERNAL   0
#define	GPIO_CFG_INT_ENABLE_INTERNAL   0x10
#define	GPIO_CFG_INT_DISABLE_INTERNAL   0
#define	GPIO_CFG_OUTPUT_OPEN_DRAIN_INTERNAL   GPIOWFF3_CFG_OPTION_NOT_SUPPORTED
#define	GPIO_CFG_OUT_OPEN_SOURCE_INTERNAL   GPIOWFF3_CFG_OPTION_NOT_SUPPORTED
#define	GPIO_CFG_INT_BOTH_EDGES_INTERNAL   GPIOWFF3_CFG_OPTION_NOT_SUPPORTED
#define	GPIO_CFG_DRVSTR_MED_INTERNAL   GPIOWFF3_CFG_OPTION_NOT_SUPPORTED
#define	GPIO_CFG_INVERT_OFF_INTERNAL   GPIOWFF3_CFG_OPTION_NOT_SUPPORTED
#define	GPIO_CFG_INVERT_ON_INTERNAL   GPIOWFF3_CFG_OPTION_NOT_SUPPORTED
#define	GPIO_CFG_HYSTERESIS_OFF_INTERNAL   GPIOWFF3_CFG_OPTION_NOT_SUPPORTED
#define	GPIO_CFG_HYSTERESIS_ON_INTERNAL   GPIOWFF3_CFG_OPTION_NOT_SUPPORTED
#define	GPIO_CFG_SLEW_NORMAL_INTERNAL   GPIOWFF3_CFG_OPTION_NOT_SUPPORTED
#define	GPIO_CFG_SLEW_REDUCED_INTERNAL   GPIOWFF3_CFG_OPTION_NOT_SUPPORTED

Macro Definition Documentation

GPIOWFF3_MUX_ANALOG

#define GPIOWFF3_MUX_ANALOG

Mux IO to analog signal.

Each IO supporting analog signals has a single analog signal associated with it. With this mux setting, the IO will be muxed to that analog signal.

Warning

The IO must be configured as GPIO_CFG_NO_DIR when using this mux setting.

Only use this mux setting for IOs supporting analog signals.

Note

Only the least significant bits are written to the IOMUX registers to select the muxing. This results in the digital IO being muxed to "Hi-Z" as if GPIO_MUX_GPIO is used. Bit 8 is used to inform the GPIO driver that the analog switch of the IO shall be controlled by the analog peripheral.

GPIOWFF3_DO_NOT_CONFIG

#define GPIOWFF3_DO_NOT_CONFIG

Do not configure this pin.

GPIO_setConfig and GPIO_setConfigAndMux calls will return immediately.

GPIO_CFG_DO_NOT_CONFIG_INTERNAL

#define GPIO_CFG_DO_NOT_CONFIG_INTERNAL   GPIOWFF3_DO_NOT_CONFIG

GPIO_MUX_GPIO_INTERNAL

#define GPIO_MUX_GPIO_INTERNAL   (0x0D)

GPIOWFF3_MUX_ANALOG_INTERNAL

#define GPIOWFF3_MUX_ANALOG_INTERNAL   (0x100)

GPIOWFF3_CFG_CFG_S

#define GPIOWFF3_CFG_CFG_S   (0)

GPIOWFF3_CFG_CFG_M

#define GPIOWFF3_CFG_CFG_M

Value:

((IOMUX_GPIO2CFG_IE_M | IOMUX_GPIO2CFG_OUTDIS_M | IOMUX_GPIO2CFG_OUTDISOVREN_M | IOMUX_GPIO20CFG_IOSTR_M) \
     << GPIOWFF3_CFG_CFG_S)

GPIOWFF3_CFG_PULLCTL_S

#define GPIOWFF3_CFG_PULLCTL_S   (0)

GPIOWFF3_CFG_PULLCTL_M

#define GPIOWFF3_CFG_PULLCTL_M   ((IOMUX_GPIO2PCTL_CTL_M) << GPIOWFF3_CFG_PULLCTL_S)

GPIOWFF3_CFG_CTL_S

#define GPIOWFF3_CFG_CTL_S   (0)

GPIOWFF3_CFG_CTL_M

#define GPIOWFF3_CFG_CTL_M   ((IOMUX_GPIO2CTL_OUTOVREN_M | IOMUX_GPIO2CTL_OUT_M) << GPIOWFF3_CFG_CTL_S)

GPIOWFF3_CFG_EVTCTL_S

#define GPIOWFF3_CFG_EVTCTL_S   (16)

GPIOWFF3_CFG_EVTCTL_M

#define GPIOWFF3_CFG_EVTCTL_M   ((IOMUX_GPIO37ECTL_EVTDETCFG_M | IOMUX_GPIO2ECTL_TRGLVL_M) << GPIOWFF3_CFG_EVTCTL_S)

GPIOWFF3_CFG_IOMUX_COMB_M

#define GPIOWFF3_CFG_IOMUX_COMB_M   (GPIOWFF3_CFG_CFG_M | GPIOWFF3_CFG_PULLCTL_M | GPIOWFF3_CFG_CTL_M | GPIOWFF3_CFG_EVTCTL_M)

GPIOWFF3_CFG_INTERNAL_M

#define GPIOWFF3_CFG_INTERNAL_M   ~GPIOWFF3_CFG_IOMUX_COMB_M

GPIO_CFG_NO_DIR_INTERNAL

#define GPIO_CFG_NO_DIR_INTERNAL   ((IOMUX_GPIO2CFG_OUTDISOVREN_DISABLE << GPIOWFF3_CFG_CFG_S) | (IOMUX_GPIO2CFG_IE_DISABLE << GPIOWFF3_CFG_CFG_S))

GPIO_CFG_INPUT_INTERNAL

#define GPIO_CFG_INPUT_INTERNAL   ((IOMUX_GPIO2CFG_OUTDISOVREN_DISABLE << GPIOWFF3_CFG_CFG_S) | (IOMUX_GPIO2CFG_IE_ENABLE << GPIOWFF3_CFG_CFG_S))

GPIO_CFG_OUTPUT_INTERNAL

#define GPIO_CFG_OUTPUT_INTERNAL

Value:

((IOMUX_GPIO2CFG_OUTDISOVREN_ENABLE << GPIOWFF3_CFG_CFG_S) |                                               \
     (IOMUX_GPIO2CFG_OUTDIS_ENABLE << GPIOWFF3_CFG_CFG_S) | (IOMUX_GPIO2CFG_IE_ENABLE << GPIOWFF3_CFG_CFG_S) | \
     (IOMUX_GPIO2CTL_OUTOVREN_ENABLE << GPIOWFF3_CFG_CTL_S))

GPIO_CFG_OUTPUT_DEFAULT_HIGH_INTERNAL

#define GPIO_CFG_OUTPUT_DEFAULT_HIGH_INTERNAL   (IOMUX_GPIO2CTL_OUT_HIGH << GPIOWFF3_CFG_CTL_S)

GPIO_CFG_OUTPUT_DEFAULT_LOW_INTERNAL

#define GPIO_CFG_OUTPUT_DEFAULT_LOW_INTERNAL   (IOMUX_GPIO2CTL_OUT_LOW << GPIOWFF3_CFG_CTL_S)

GPIO_CFG_PULL_NONE_INTERNAL

#define GPIO_CFG_PULL_NONE_INTERNAL   (IOMUX_GPIO2PCTL_CTL_IPCTRL << GPIOWFF3_CFG_PULLCTL_S)

GPIO_CFG_PULL_UP_INTERNAL

#define GPIO_CFG_PULL_UP_INTERNAL   (IOMUX_GPIO2PCTL_CTL_UP << GPIOWFF3_CFG_PULLCTL_S)

GPIO_CFG_PULL_DOWN_INTERNAL

#define GPIO_CFG_PULL_DOWN_INTERNAL   (IOMUX_GPIO2PCTL_CTL_DOWN << GPIOWFF3_CFG_PULLCTL_S)

GPIO_CFG_INT_NONE_INTERNAL

#define GPIO_CFG_INT_NONE_INTERNAL   0

GPIO_CFG_INT_FALLING_INTERNAL

#define GPIO_CFG_INT_FALLING_INTERNAL   (IOMUX_GPIO2ECTL_EVTDETCFG_NEG_EDGE << GPIOWFF3_CFG_EVTCTL_S)

GPIO_CFG_INT_RISING_INTERNAL

#define GPIO_CFG_INT_RISING_INTERNAL   (IOMUX_GPIO2ECTL_EVTDETCFG_POS_EDGE << GPIOWFF3_CFG_EVTCTL_S)

GPIO_CFG_INT_LOW_INTERNAL

#define GPIO_CFG_INT_LOW_INTERNAL   ((IOMUX_GPIO2ECTL_EVTDETCFG_LEVEL << GPIOWFF3_CFG_EVTCTL_S) | (IOMUX_GPIO2ECTL_TRGLVL_LOW << GPIOWFF3_CFG_EVTCTL_S))

GPIO_CFG_INT_HIGH_INTERNAL

#define GPIO_CFG_INT_HIGH_INTERNAL

Value:

((IOMUX_GPIO2ECTL_EVTDETCFG_LEVEL << GPIOWFF3_CFG_EVTCTL_S) | \
     (IOMUX_GPIO2ECTL_TRGLVL_HIGH << GPIOWFF3_CFG_EVTCTL_S))

GPIO_CFG_DRVSTR_LOW_INTERNAL

#define GPIO_CFG_DRVSTR_LOW_INTERNAL   (IOMUX_GPIO20CFG_IOSTR_LOW << GPIOWFF3_CFG_CFG_S)

GPIO_CFG_DRVSTR_HIGH_INTERNAL

#define GPIO_CFG_DRVSTR_HIGH_INTERNAL   (IOMUX_GPIO20CFG_IOSTR_HIGH << GPIOWFF3_CFG_CFG_S)

GPIO_CFG_SHUTDOWN_WAKE_OFF_INTERNAL

#define GPIO_CFG_SHUTDOWN_WAKE_OFF_INTERNAL   0

GPIO_CFG_SHUTDOWN_WAKE_HIGH_INTERNAL

#define GPIO_CFG_SHUTDOWN_WAKE_HIGH_INTERNAL   0

GPIO_CFG_SHUTDOWN_WAKE_LOW_INTERNAL

#define GPIO_CFG_SHUTDOWN_WAKE_LOW_INTERNAL   0

GPIO_CFG_INT_ENABLE_INTERNAL

#define GPIO_CFG_INT_ENABLE_INTERNAL   0x10

GPIO_CFG_INT_DISABLE_INTERNAL

#define GPIO_CFG_INT_DISABLE_INTERNAL   0

GPIO_CFG_OUTPUT_OPEN_DRAIN_INTERNAL

#define GPIO_CFG_OUTPUT_OPEN_DRAIN_INTERNAL   GPIOWFF3_CFG_OPTION_NOT_SUPPORTED

GPIO_CFG_OUT_OPEN_SOURCE_INTERNAL

#define GPIO_CFG_OUT_OPEN_SOURCE_INTERNAL   GPIOWFF3_CFG_OPTION_NOT_SUPPORTED

GPIO_CFG_INT_BOTH_EDGES_INTERNAL

#define GPIO_CFG_INT_BOTH_EDGES_INTERNAL   GPIOWFF3_CFG_OPTION_NOT_SUPPORTED

GPIO_CFG_DRVSTR_MED_INTERNAL

#define GPIO_CFG_DRVSTR_MED_INTERNAL   GPIOWFF3_CFG_OPTION_NOT_SUPPORTED

GPIO_CFG_INVERT_OFF_INTERNAL

#define GPIO_CFG_INVERT_OFF_INTERNAL   GPIOWFF3_CFG_OPTION_NOT_SUPPORTED

GPIO_CFG_INVERT_ON_INTERNAL

#define GPIO_CFG_INVERT_ON_INTERNAL   GPIOWFF3_CFG_OPTION_NOT_SUPPORTED

GPIO_CFG_HYSTERESIS_OFF_INTERNAL

#define GPIO_CFG_HYSTERESIS_OFF_INTERNAL   GPIOWFF3_CFG_OPTION_NOT_SUPPORTED

GPIO_CFG_HYSTERESIS_ON_INTERNAL

#define GPIO_CFG_HYSTERESIS_ON_INTERNAL   GPIOWFF3_CFG_OPTION_NOT_SUPPORTED

GPIO_CFG_SLEW_NORMAL_INTERNAL

#define GPIO_CFG_SLEW_NORMAL_INTERNAL   GPIOWFF3_CFG_OPTION_NOT_SUPPORTED

GPIO_CFG_SLEW_REDUCED_INTERNAL

#define GPIO_CFG_SLEW_REDUCED_INTERNAL   GPIOWFF3_CFG_OPTION_NOT_SUPPORTED