31:23

Reserved

RO

0x000

22:20

FSRC

Which part of the monitor bus enter event F:
0x0. event_f_input = mon_in_en[31:0];
0x1. event_f_input = mon_in_en[47:16];
0x2. event_f_input = mon_in_en[63:32];
0x3. event_f_input = mon_in_en[79:48];
0x4. event_f_input = mon_in_en[95:64];
0x5. event_f_input = {mon_in_en[95:80], mon_in_en[15:0]};

RW

0x0

19

Reserved

RO

0

18:16

ESRC

Which part of the monitor bus enter event E:
0x0. event_e_input = mon_in_en[31:0];
0x1. event_e_input = mon_in_en[47:16];
0x2. event_e_input = mon_in_en[63:32];
0x3. event_e_input = mon_in_en[79:48];
0x4. event_e_input = mon_in_en[95:64];
0x5. event_e_input = {mon_in_en[95:80], mon_in_en[15:0]};

RW

0x0

15

DMOD

Event D mode:
0. Equal
1. Great then

RW

0

14:12

DSRC

Which part of the monitor bus enter event D:
0x0. event_d_input = mon_in_en[31:0];
0x1. event_d_input = mon_in_en[47:16];
0x2. event_d_input = mon_in_en[63:32];
0x3. event_d_input = mon_in_en[79:48];
0x4. event_d_input = mon_in_en[95:64];
0x5. event_d_input = {mon_in_en[95:80], mon_in_en[15:0]};

RW

0x0

11

CMOD

Event C mode:
0. Equal
1. Great then

RW

0

10:8

CSRC

Which part of the monitor bus enter event C:
0x0. event_c_input = mon_in_en[31:0];
0x1. event_c_input = mon_in_en[47:16];
0x2. event_c_input = mon_in_en[63:32];
0x3. event_c_input = mon_in_en[79:48];
0x4. event_c_input = mon_in_en[95:64];
0x5. event_c_input = {mon_in_en[95:80], mon_in_en[15:0]};

RW

0x0

7

BMOD

Event B mode:
0. Equal
1. Great then

RW

0

6:4

BSRC

Which part of the monitor bus enter event B:
0x0. event_b_input = mon_in_en[31:0];
0x1. event_b_input = mon_in_en[47:16];
0x2. event_b_input = mon_in_en[63:32];
0x3. event_b_input = mon_in_en[79:48];
0x4. event_b_input = mon_in_en[95:64];
0x5. event_b_input = {mon_in_en[95:80], mon_in_en[15:0]};

RW

0x0

3

AMOD

Event A mode:
0. Equal
1. Great then

RW

0

2:0

ASRC

Which part of the monitor bus enter event A:
0x0. event_a_input = mon_in_en[31:0];
0x1. event_a_input = mon_in_en[47:16];
0x2. event_a_input = mon_in_en[63:32];
0x3. event_a_input = mon_in_en[79:48];
0x4. event_a_input = mon_in_en[95:64];
0x5. event_a_input = {mon_in_en[95:80], mon_in_en[15:0]};

RW

0x0

31:0

MASK

mask bit which set to 0 is mask

RW

0x0000 0000

31:0

COMP

Compare value for event A

RW

0x0000 0000

31:0

MASK

mask bit which set to 0 is mask

RW

0x0000 0000

31:0

COMP

Compare value for event B

RW

0x0000 0000

31:0

MASK

mask bit which set to 0 is mask

RW

0x0000 0000

31:0

COMP

Compare value for event C

RW

0x0000 0000

31:0

MASK

mask bit which set to 0 is mask

RW

0x0000 0000

31:0

COMP

Compare value for event F

RW

0x0000 0000

31:14

Reserved

RO

0x0 0000

13:8

NOT

Which event will have not

RW

0x00

7:6

Reserved

RO

0x0

5:0

AND

Which event will be in the and

RW

0x00

31:14

Reserved

RO

0x0 0000

13:8

NOT

Which event will have not

RW

0x00

7:6

Reserved

RO

0x0

5:0

AND

Which event will be in the and

RW

0x00

31:14

RESERVED_0

RO

0x0 0000

13:8

NOT

Which event will have not

RW

0x00

7:6

RESERVED_1

RO

0x0

5:0

AND

Which event will be in the and

RW

0x00

31:2

Reserved

RO

0bxx xxxx xxxx xxxx x0xx xx00 0000 0000

1:0

MOD

Clock Mode:
0. No CLK
1. CLK40
2. RF CLK
3. Illegal
NOTE: move between CLK should be through zero (No CLK)

RW

0x0

31:16

RESERVED_0

RO

0x0000

15:12

TINV

which of the sub triggers will be invert for trigger1.
The sub_triggers order is {W,Z,Y,X}
to make ~X & Y use 4'h1

RW

0x0

11:8

TAND

Which of the sub triggers will make the trigger2
The sub_triggers order is {W,Z,Y,X}
to make ~X & Y use 4'h3.

RW

0x0

7:4

INV

Which of the sub triggers will be invert for trigger1.
The sub_triggers order is {W,Z,Y,X}
to make ~X & Y use 4'h1

RW

0x0

3:0

AND

Which of the sub triggers will make the trigger1
The sub_triggers order is {W,Z,Y,X}
to make ~X & Y use 4'h3.

RW

0x0

31:26

Reserved

RO

0x00

25:0

TIME

use for:
1. For time between events for mode which check time between two events.
2. Number of event for modes that check number of event.

RW

0x000 0000

31:24

Reserved

RO

0x00

23

MAXMIN

For max_time function can change it to min time by:
max = 0, min = 1.

RW

0

22

ADDRSW2D

Save the mem_sw on the bits [31:24]

RW

0

21:18

Reserved

RO

0x0

17:16

D2SAVE

This do shift down to the monitor which saved (not the triggers)
0: monitor as it is.
1: Shift right 16 bits
for mode of 32 bits monitor[47:16]
for mode of 16 bits monitor[31:16]
for mode of 8 bits monitor[24:16].
2: Shift right 32 bits
for mode of 32 bits monitor[63:32]
for mode of 16 bits monitor[47:32]
for mode of 8 bits monitor[39:32].
3: Shift right 64 bits
Don't use in 64bits mode
for mode of 32 bits monitor[95:64]
for mode of 16 bits monitor[79:64]
for mode of 8 bits monitor[71:64].
for IQ save mode 14
0 : output is iq_save_in[63:0]
1: output is iq_save_in[127:64]
2: output is iq_save_in[127:0]

RW

0x0

15

SWTCIQDIN

Switch between IQ_SAVE data in and debug bus in.
This enable to do all triggers and save data on iq_in.

RW

0

14

SWTCHIGH

At mode which switch iq with din (bit 15) take bits from 127 to 32 when this bit is one otherwise take 97:0.

RW

0

13

Reserved

RO

0

12:10

PARAMMOD

not in use.

RW

0x0

9:8

DATAMOD

// 0: save 64bits each cycle
// 1: save 32bits each cycle (write to memory every two cycles)
// 2: save 16LSB each cycle (write to the ram every 4 cycles)
// 3: save 8LSB each cycle (write to the ram every 8 cycles)
// for IQ save/inject modes
// look at mode description.

RW

0x0

7:6

Reserved

RO

0x0

5

EN

Enable the OCLA should be the last write

RW

0

4:0

IQMOD

// 0: event1 happened
// 1: check time between last event_a to first event_b if it's bigger then mem_time event
// 2: check time between last event_a high to first event_b high if it's smaller then mem_time event
// 3: check the time from first event a to first event b if it's bigger then mem_time event
// 4: check the time from first event a to first event b if it's smaller then mem_time event
// 5: event1 happened T times
// 6: timestamp mode save events and timestamp
// 7: event1 happened but event2 didn't happened for T cycles
// 8: trigger A happened and next cycle trigger B happened sample monitor after timestamp once (as timestamp mode)
// 9: SW event when the mem_sw_info == 16'hffff
// 10: Save monitor bus and time stamp when monitor change masking from F trigger
// 11: Save T amount of samples when event1 happened
// 12: Save each time one of the trigger (A-F) happened
// 13: IQ Save 64 bit every cycle - 32LSB monitor bus,
// 32 MSB bits are 32 LSB from IQ bus
// 14: IQ save
// 32/64/128 bits IQ save mode
// If (mem_data_save_mode = 0)
// case (mem_data_to_save)
// 0: ocla_dout[63:0] <= #1 ocla_iq_save_in[63:0];
// 1: ocla_dout[63:0] <= #1 ocla_iq_save_in[127:64];
// 2: ocla_dout[127:0] <= #1 ocla_iq_save_in[127:0]; // save each cycle
// If (mem_data_save_mode = 1)
// case (mem_data_to_save)
// 0: ocla_dout[31:0] <= #1 ocla_iq_save_in[31:0];
// 1: ocla_dout[31:0] <= #1 ocla_iq_save_in[63:32];
// 2: ocla_dout[31:0] <= #1 ocla_iq_save_in[95:64];
// 3: ocla_dout[31:0] <= #1 ocla_iq_save_in[127:96];
// 15: IQ inject
// 16: ocla debug write to the RAM {14'h3333, ocla_addr[17:0], 14'h2222, ocla_addr[17:0],
14'h1111, ocla_addr[17:0], 14'h0000, ocla_addr[17:0]}

RW

0x00

31:8

Reserved

RO

0x00 0000

7:0

SIZE

The last address in the memory OCLA use.
this is the 8 MSB out of 18 bits of 128bit wide lines.
(concatenated with 0x3FF to form the last address).

RW

0x00

31:18

RESERVED_0

RO

0x0000

17:0

SIZE

Number of writes (128bit wide each) to the memory after the event

RW

0x0 0000

31:19

RESERVED_0

RO

0x0000

18

SWINFO_SAMPLE

signal to force re-sampling of the sw_info data into the recorded bus,

RW

0

17

SWINFO_TRIGGER

raise bit to issue sw trigger.

RW

0

16

SWINFO_EN

When this bit is one and at ocla mode of not 6, 10 save the data.

RW

0

15:0

SWINFO

Data save in memory .
not in mode : 6 , 10.
At mode of 64bits save it as MSB when en is high.

RW

0x0000

31:28

Reserved

RO

0x0

27:26

STATESTA

State machine:
0: looking for the event.
1: event found.
2: finish.

RO

0x0

25:8

EVTPTR

the address of the memory when event happened.

RO

0x0 0000

7:4

DATEVT

This is as LSB of the event_ptr when use mode other then 64bits
0 event happened when the building of the 64bits was full.
1 event happened when the building of the 64 bits was on 8 bits.
2 event happened when the building of the 64 bits was on 16 bits.
...

RO

0x0

3

FIRSTFILL

Indicates if this is the first time that the RAM is fill and therefore part of the RAM is unknown.
This value should be read when OCLA is finished working, before disabling the OCLA, because it is reset when OCLA is disabled.

RO

1

2:0

INTRS

To read the OCLA state
ocla_mem_phase[1] - before or after the event
event_t_reg,
event_reg

RO

0x0

31:0

31TO0

32 LSBs

RO

0x0000 0000

31:0

63TO32

63 to 32 Bits.

RO

0x0000 0000

31:26

Reserved

RO

0x00

25:0

MAXTIME

Value of the counter of max/min read

RO

0x000 0000

31:13

Reserved

RO

0x0 0000

12:8

SAMPRATE

Sample to the RAM once each X times

RW

0x00

7:0

STARTADDR

Which address the RAM start, change only for the 8 MSB, the 10 LSB is always 0.

RW

0x00

31:17

Reserved

STOP INJECT

RO

0bxxx xxxx xxxx xxxx

16

MODE

Inject Mode:
0. Single INJECT mode (Stop when Address=Max address)
1. Multi INJECT mode (stop when Wr to "stop" field)

RW

0

15:2

Reserved

RO

0bxx xx00 0000 0000

1

STOP

Which address the RAM start, change only for the 8 MSB, the 10 LSB is always 0.

WO

0

0

START

Start INJECT

WO

0

31:0

BIT0SEL

Bit 0.

RW

0xAAAA AAAA

31:0

BIT1SEL

Bit 1.

RW

0xCCCC CCCC

31:0

BIT2SEL

Bit 2.

RW

0xF0F0 F0F0

31:0

BIT3SEL

Bit 3.

RW

0xFF00 FF00

31:0

BIT4SEL

Bit 4.

RW

0xFFFF 0000

31:0

SEL

Each bit select which TP1 or TP2 would connect to OCLA bus bits[63:32]
0. select TP2
1. select TP1
Note: OCLA bus [31:0] is TP1

RW

0x0000 0000

31:11

Reserved

RO

0x00 0000

10:8

TP2SEL

Select which debug port used by OCLA for TP2 --> [63:32]
0x0. select PHY Debug Port
0x1. select WSOC Debug Port
0x2. select TOP Debug Port
0x3. select BLE Debug Port
0x4. select Peripheral Debug Port

RW

0x0

7:3

Reserved

RO

0x00

2:0

TP1SEL

Select which debug port used by OCLA for TP1 --> [31:0]
0x0. select PHY Debug Port
0x1. select WSOC Debug Port
0x2. select TOP Debug Port
0x3. select BLE Debug Port
0x4. select Peripheral Debug Port

RW

0x0

31:0

MEM_OUTSEL

per bit selection
0. GPIO
1. debug port

RW

0x0000 0000

31:0

OUTVAL_WROPT

GPIO out read/write value.

RW

0x0000 0000

31:0

OUTVAL_SET_WRCL

writing 1 to a bit will set the [OUTVAL.VAL]. writing 0 is ignored

RW

0x0000 0000

31:0

OUTVAL_CLR_WRCL

writing 1 to a bit will clr a bit [OUTVAL.VAL]

RW

0x0000 0000

31:0

OUTVAL_TGL_WRCL

writing 1 to a bit will toggle a bit at [OUTVAL.VAL].

RW

0x0000 0000

31:0

OUTVAL_PLS_WRCL

writing 1 to a bit will create a pulse for the same bit at [OUTVAL.VAL]
( Pulse is equal to toggle twice )

RW

0x0000 0000

31:0

TIMESTAMP

TSF time stamp samled on trigger.

RO

0x0000 0000