SOC_IC

SOC_IC

This section provides information on the SOC_IC Module Instance within this product. Each of the registers within the Module Instance is described separately below.

SOC_IC Registers Mapping Summary

:SOC_IC Common Register Mapping Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset
PRIO0	RW	32	0x16A6 CCD1	0x0000 0000
PRIO0_1	RW	32	0x1C46 468B	0x0000 0004
PRIO0_2	RW	32	0x1176 AB19	0x0000 0008
PRIO0_3	RW	32	0x2C86 2B1C	0x0000 000C
PRIO0_4	RW	32	0x0000 001A	0x0000 0010
ERRSTA1	RW	32	0x0000 0000	0x0000 0014
ERRSTA2	RW	32	0x0000 0000	0x0000 0018
ADDRCFG1	RW	32	0x0000 0000	0x0000 001C
ADDRCFG2	RW	32	0x0000 0000	0x0000 0020
ADDRCFG3	RW	32	0x0000 0000	0x0000 0024
ADDRCFG4	RW	32	0x0000 0000	0x0000 0028
ADDRSTA1	RW	32	0x0000 0000	0x0000 002C
ADDRSTA2	RW	32	0x0000 0000	0x0000 0030
TOMSTCFG	RW	32	0x0001 0084	0x0000 0034
TOSLVCFG	RW	32	0x0001 0088	0x0000 0038

SOC_IC Instances Register Mapping Summary

SOC_IC Register Descriptions

:SOC_IC Common Register Descriptions

:SOC_IC:PRIO0

Address offset	0x0000 0000
Description	SOC Interconnect priority registers. Define the priority in which master will be arbitered toward each slave.
Type	RW

Bits	Field Name	Description			Type	Reset
31:30	Reserved				RO	0x0
29:27	HMCUI2S	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x2
26:24	HMCUDMAWR	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x6
23:21	HMCUDMARD	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x5
20:18	HMCUWSOCIC	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x1
17:15	L3HSM	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x5
14:12	L3I2S	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x4
11:9	L3HMCU	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x6
8:6	L3DMAWR	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x3
5:3	L3DMARD	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x2
2:0	L3WSOCIC	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x1

:SOC_IC:PRIO0_1

Address offset	0x0000 0004
Description	SOC Interconnect priority registers. Define the priority in which master will be arbitered toward each slave.
Type	RW

Bits	Field Name	Description			Type	Reset
31:30	Reserved				RO	0x0
29:27	COREHSM	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x3
26:24	COREHMCU	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x4
23:21	COREDMAWR	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x2
20:18	COREDMARD	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x1
17:15	SPHSM	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x4
14:12	SPHMCU	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x4
11:9	SPDMAWR	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x3
8:6	SPDMARD	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x2
5:3	SPWSOCIC	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x1
2:0	HMCUHSM	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x3

:SOC_IC:PRIO0_2

Address offset	0x0000 0008
Description	SOC Interconnect priority registers. Define the priority in which master will be arbitered toward each slave.
Type	RW

Bits	Field Name	Description			Type	Reset
31:30	Reserved				RO	0x0
29:27	HSMDMAWR	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x2
26:24	HSMDMARD	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x1
23:21	HSMWSOCIC	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x3
20:19	HDMAHSM	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x2
18:17	HDMAHOSTMCU	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x3
16:15	HDMAWSOCIC	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x1
14:12	XIPHSM	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x2
11:9	XIPHMCU	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x5
8:6	XIPDMAWR	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x4
5:3	XIPDMARD	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x3
2:0	XIPWSOCIC	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x1

:SOC_IC:PRIO0_3

Address offset	0x0000 000C
Description	SOC Interconnect priority registers. Define the priority in which master will be arbitered toward each slave.
Type	RW

Bits	Field Name	Description			Type	Reset
31:30	Reserved				RO	0x0
29:27	CAONDMAWR	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x5
26:24	CAONDMARD	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x4
23:21	CAONHMCU	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x4
20:18	CAONWSOCIC	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x1
17:15	HMCUHMCU	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x4
14:12	A2NHSM	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x2
11:9	A2NHMCU	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x5
8:6	A2NDMAWR	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x4
5:3	A2NDMARD	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x3
2:0	HSMHMCU	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x4

:SOC_IC:PRIO0_4

Address offset	0x0000 0010
Description	SOC Interconnect priority registers. Define the priority in which master will be arbitered toward each slave.
Type	RW

Bits	Field Name	Description			Type	Reset
31:6	Reserved				RO	0x000 0000
5:3	CAONHSM	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x3
2:0	CAONI2S	Set the priority for specific Master transaction toward a specific slave. priority values: 0 - N.A 1 - Lowest priority 2 - Higher priority 3- ... N - Highest priority where N is NUM_OF_MASTERS			RW	0x2

:SOC_IC:ERRSTA1

Address offset	0x0000 0014
Description	OCP Slave serror and Time-out Status 1. status bits when ocp slave response with serror clear on write sticky - catch the first error, until register is cleared to 0
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	STA1	status bits when ocp slave response with serror clear on write sticky - catch the first error, until register is cleared to 0 [31:0] - maddr *note - can only clear on write to 32'b0 writing 1 byte will clear all 4 bytes			RW	0x0000 0000

:SOC_IC:ERRSTA2

Address offset	0x0000 0018
Description	OCP Slave serror and Time-out Status 2.
Type	RW

Bits	Field Name	Description			Type	Reset
31:10	Reserved				RO	0x00 0000
9:0	STA2	status bits when ocp slave response with serror or timeout: clear on write sticky - catch the first error, until register is cleared to 0 for serror and timeout handeling: [9:6] cause [5:4] mcmd - command type: 2=RD ; 1=WR [3:0] masterid cause mapping: 0 - masters 1 - core aon 2 - hsm 3 - host xip 4 - host dma 5 - host mcu 6 - shared periph 7 - app2nab 8 - core wsocic 9 - l3 slaves if cuase is 'masters' - masterid mapped as it mapped in [TOMSTCFG.SEL]. else - masterid mapping: 0 - M33NS 1 - M33S 6 - Core (wsoc_ic) 8 - I2S/HSM M33NS access 9 - I2S/HSM M33S access 10 - I2S/HSM Core access 12 - DMA M33NS access 13 - DMA M33S access 14 - DMA Core access *note - can only clear on write to 10'b0 writing 1 byte will clear all 2 bytes			RW	0x000

:SOC_IC:ADDRCFG1

Address offset	0x0000 001C
Description	Address Watch Configuration 1.
Type	RW

Bits	Field Name	Description			Type	Reset
31:4	Reserved				RO	0x000 0000
3:0	SEL	select which slave port of ocp_ic is checked in address-watch: 0 - core_aon 1 - hsm 2 - host_xip_cfg 3 - host_dma 4 - host_mcu 5 - shared_periph (all shared peripheral I2C,UART,I2S,SDMMC,SPI,CAN,PDM,GPTIMERS,AFA,ADC,SDIO) 6 - app2nab 7 - core_wsocic 8 - all l3 peripherals under bridge (COEX,IOMUX,PRCM,SCRTCHPAD,PRCM_AON,CKM,FUSE_FARM,GPADC_CTRL,DEBUGSS, SOC_IC,SOC_AON_SECURED/NON_SECURED,RTC,OCLA,MEMSS_GLOBALPORT,HOST_AON,SYSREASOURCES,SYSTIMER)			RW	0x0

:SOC_IC:ADDRCFG2

Address offset	0x0000 0020
Description	Address Watch Configuration 2.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	LOW	lower maddr threshold for address-watch addr_hit = (maddr >= thr_low) & (maddr <= thr_high)			RW	0x0000 0000

:SOC_IC:ADDRCFG3

Address offset	0x0000 0024
Description	Address Watch Configuration 3.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	HIGH	upper maddr threshold for address-watch addr_hit = (maddr >= thr_low) & (maddr <= thr_high)			RW	0x0000 0000

:SOC_IC:ADDRCFG4

Address offset	0x0000 0028
Description	Address Watch Configuration 4.
Type	RW

Bits	Field Name	Description			Type	Reset
31:16	MSTIDRD	each bit enables check on MCMD=RD per MASTERID for example value of 0x0120 will enable check of masterid=5 and masterid=8 if check_wr=0x0000 and check_rd=0x0000 then the clock for address-watch is disabled locally to save power			RW	0x0000
15:0	MSTIDWR	each bit enables check on MCMD=WR per MASTERID for example value of 0x0120 will enable check of masterid=5 and masterid=8 if check_wr=0x0000 and check_rd=0x0000 then the clock for address-watch is disabled locally to save power			RW	0x0000

:SOC_IC:ADDRSTA1

Address offset	0x0000 002C
Description	Address Watch Status 1.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	OCP_IC_ADDRSTA1_WROPT	keep when hit - Clear on Write [31:0] - maddr			RW	0x0000 0000

:SOC_IC:ADDRSTA2

Address offset	0x0000 0030
Description	Address Watch Status 2.
Type	RW

Bits	Field Name	Description			Type	Reset
31:5	Reserved				RO	0x000 0000
4:0	OCP_IC_ADDRSTA2_WROPT	keep when hit - Clear on Write [4] - command type: 0=RD ; 1=WR [3:0] - masterid masterid mapping: 0 - M33NS 1 - M33S 6 - Core (wsoc_ic) 8 - I2S/HSM M33NS access 9 - I2S/HSM M33S access 10 - I2S/HSM Core access 12 - DMA M33NS access 13 - DMA M33S access 14 - DMA Core access			RW	0x00

:SOC_IC:TOMSTCFG

Address offset	0x0000 0034
Description	Time-out Masters Configuration.
Type	RW

Bits	Field Name	Description			Type	Reset
31:14	Reserved				RO	0x0 0004
13:10	SEL	select master for timeout by masterid. 0x0. M33NS 0x1. M33S 0x6. Core (wsoc_ic) 0x8. I2S/HSM M33NS access 0x9. I2S/HSM M33S access 0xA. I2S/HSM Core access 0xC. DMA M33NS access 0xD. DMA M33S access 0xE. DMA Core access			RW	0x0
9	Reserved				RO	0
8:4	VAL	value for timeout for all slaves: valid value - 0x0- 0x1F if value is 0 timeout feature is disabled for all slaves Granulation is double word (64b): 1 - means 16 clocks period, 2 - means 32 clocks period... in h/w the value in FIELD is shifted left 4 times (x16). example: 0x08 => 0x80 (8 means 128)			RW	0x08
3:0	Reserved				RO	0x4

:SOC_IC:TOSLVCFG

Address offset	0x0000 0038
Description	Time-out Slave Configuration.
Type	RW

Bits	Field Name	Description			Type	Reset
31:9	Reserved				RO	0x00 0080
8:4	VAL	value for timeout for all slaves: valid value - 0x0- 0x1F if value is 0 timeout feature is disabled for all slaves Granulation is double word (64b): 1 - means 16 clocks period, 2 - means 32 clocks period... in h/w the value in FIELD is shifted left 4 times (x16). example: 0x08 => 0x80 (8 means 128)			RW	0x08
3:0	Reserved				RO	0x8