31:27

Reserved

Reserved

RO

0x00

26

Reserved

Reserved

RO

0

25

FN1RDY

Function 1 Ready

RW

0

24:19

Reserved

Reserved

RO

0x00

18

Reserved

Reserved

RO

0

17

FN1EN

Enable Function 1

RW

0

16:12

Reserved

Reserved

RO

0x00

11:8

SD

SD Format Version number

RO

0x3

7:4

SDIO

SDIO Specification Revision number

RO

0x4

3:0

CCCR

4 CCCRx bits defines the version used by CCCR and the FBR format it supports

RO

0x3

31

CD_DISABLE

Connect/Disconnect (0/1) the pull-up resistor on SDIO data line 3

RW

0

30:26

Reserved

Reserved

RO

0x00

25:24

BUS_WIDTH

Defines SDIO data bus width

RW

0x0

23:20

Reserved

Reserved

RO

0x0

19

SDIO_RESET_REQ

reset sdio IP due to a SDIO Card Reset command

WO

0

18:16

SDIO_ABORT

Abort read or write transaction and free the SDIO bus.

WO

0x0

15:11

Reserved

Reserved

RO

0x00

10

Reserved

Reserved

RO

0

9

FN1_INT_PEND

Interrupt pending for function 1

RO

0

8:3

Reserved

Reserved

RO

0x00

2

Reserved

Reserved

RO

0

1

FN1_INT_EN

Interrupt Enable for function 1

RW

0

0

MASTER_INT_EN

Interrupt Enable controller

RW

0

31:16

CISPTR1

Bits 23:8 of cards common CIS pointer

RO

0x0010

15:8

CISPTR0

Bits 7:0 of cards common CIS pointer

RO

0x00

7

BLS4

4 bit support for low speed cards

RO

0

6

LSC

Card is a low speed card

RO

0

5

E4MI

Enable interrupt between blocks of data in SDIO 4 bit mode

RW

0

4

S4MI

Supports interrupt between blocks of data in SDIO 4 bit mode

RO

1

3

SBS

Card support Suspend/Resume

RO

0

2

SRW

Card support read wait

RO

0

1

SMB

Card support Multi-Block

RO

1

0

SDC

Card support direct commands during data transfer

RO

0

31:26

Reserved

Reserved

RO

0x00

25

EHS

Enable High Speed

RW

0

24

SHS

Support High Speed

RO

1

23:12

Reserved

Reserved

RO

0x000

11:0

FN0_BLK_SIZE

Function 0 block size

RW

0x000

31:18

Reserved

Reserved

RO

0x0000

17

EAI

Enable Asynchronous Interrupt: Enable bit of asynchronous interrupt. When Sai is set to 0, writing to this bit is ignored and always indicates 0. This bit is effective in in SD 4-bit mode.

RW

0

16

SAI

Support Asynchronous Interrupt: Support bit of Asynchronous Interrupt. If the card supports asynchronous interrupt in SD 4-bit mode, this bit is set to 1.

RO

1

15:0

Reserved

Reserved

RO

0x0000

31:17

Reserved

Reserved

RO

0x0000

16

FN1_ELP_STS

Enter Low Power mode Status bit

RW

1

15:0

Reserved

Reserved

RO

0x0000

31:30

Reserved

Reserved

RO

0x0

29:24

FN1_GPI_CLR

General Purpose clear Interrupt sources. Write "1" to clear the desire source.
bit 0 - ELP signal transition from "0" to "1"
bit 1 - ELP signal transition from "1" to "0"
bit 2 - Host write to IOE1 register (Function 0 address 0x2)
bit 3 - Host write to function 0 CCCR area
bit 4 - Function 1 data block completion
bit 5 - Function 1 data block with CRC error

WO

0x00

23

Reserved

Reserved

RO

0

22:16

FN1_GPI_STS

General Purpose Interrupt sources status.
bit 0 - ELP signal transition from "0" to "1"
bit 1 - ELP signal transition from "1" to "0"
bit 2 - Host write to IOE1 register (Function 0 address 0x2)
bit 3 - Host write to function 0 CCCR area
bit 4 - Function 1 data block completion
bit 5 - Function 1 data block with CRC error
bit 6 - Autonomous mode: cmd 53 valid WR command to data FIFO

RO

0x00

15

FN1_STS

Function 1 interrupt status.

RO

0

14:8

FN1_GPI_MSK

General Purpose Interrupt source mask.
bit 0 - ELP signal transition from "0" to "1"
bit 1 - ELP signal transition from "1" to "0"
bit 2 - Host write to IOE1 register (Function 0 address 0x2)
bit 3 - Host write to function 0 CCCR area
bit 4 - Function 1 data block completion
bit 5 - Function 1 data block with CRC error
bit 6 - Autonomous mode: cmd 53 valid WR command to data FIFO

RW

0x7F

7:2

Reserved

Reserved

RO

0x00

1

FN1_OBI_INV

Invert Out Band Interrupt polarity

RW

0

0

FN1_OBI_EN

Enable Out Band Interrupt

RW

1

31:2

Reserved

Reserved

RO

0x0000 0000

1

FN1_BUSY_OVERRIDE

Override function 1 busy signal value.
0 - Do not override.
1 - Override.

RW

0

0

FN1_BUSY

Set function 1 busy signal override value

RW

0

31:17

Reserved

Reserved_1

RO

0x0000

16

Reserved

Reserved_1

RO

0

15:0

Reserved

Reserved

RO

0x0000

31:21

Reserved

Reserved

RO

0x000

20:16

Reserved

Reserved

RO

0x00

15

Reserved

Reserved

RO

0

14

Reserved

Reserved

RO

0

13

Reserved

Reserved

RO

0

12:8

Reserved

Reserved

RO

0x00

7:6

Reserved

Reserved

RO

0x0

5:4

Reserved

Reserved

RO

0x0

3:2

Reserved

Reserved

RO

0x0

1

Reserved

Reserved

RO

0

0

Reserved

Reserved

RO

0

31:27

Reserved

Reserved

RO

0x00

26

Reserved

Reserved

RO

0

25

Reserved

Reserved

RO

0

24:22

Reserved

Reserved

RO

0x0

21:16

CMD_ERROR

Bit map:
0 - Address error
1 - Function number error
2 - General error
3 - Illegal command error
4 - CRC error
5 - Out of range error

RO

0x00

15:2

Reserved

Reserved

RO

0x0000

1

Reserved

Reserved

RO

0

0

Reserved

Reserved

RO

0

31:24

Reserved

Reserved

RO

0x00

23:0

OCR

Bits 23:0 of Operation Conditions Register

RW

0xFF FFC0

31:30

Reserved

Reserved_1

RO

0x0

29:26

SDIO_DAT2_STATE

Data line 2 state machine

RO

0x2

25:21

SDIO_DAT1_STATE

Data line 1 state machine

RO

0x0B

20:16

SDIO_DAT0_STATE

Data line 0 state machine

RO

0x01

15:12

Reserved

Reserved

RO

0x0

11:8

SDIO_DAT3_STATE

Data line 3 state machine

RO

0x1

7:5

SDIO_RESP_STATE

Response state machine

RO

0x1

4:0

SDIO_CMD_STATE

SDIO command decoder state machine

RO

0x01

31:16

RCA

Relative Card Address

RO

0x0000

15:5

Reserved

Reserved

RO

0x000

4

WSPI_ERROR

WSPI error status

RO

0

3:0

WSPI_STATE

WSPI command state machine

RO

0x0

31:5

Reserved

Reserved

RO

0x000 0000

4

WSPI_FBR_OVRD

Override Fixed Busy Response settings

RO

0

3:1

WSPI_FBR_REG

Set the number of busy words

RO

0x0

0

WSPI_FBR_EN

Enable WSPI Fixed Busy Response mechanism

RO

0

31:28

Reserved

Reserved_1

RO

0x0

27:16

WSPI_IRQ_LEN_THR_OCP

EOT length threshold

RO

0x000

15:3

Reserved

Reserved

RO

0x0000

2

WSPI_IRQ_CFG_OCP_2

Disable transaction address threshold comparison

RO

0

1

WSPI_IRQ_CFG_OCP_1

Disable transaction length threshold comparison

RO

0

0

WSPI_IRQ_CFG_OCP_0

Enable EOT interrupt

RO

0

31:17

Reserved

Reserved

RO

0x0000

16

WSPI_IRQ_ADDR_FILT_OCP_16

EOT base address MSB threshold

RO

0

15:0

WSPI_IRQ_ADDR_FILT_OCP_15_0

EOT base address LSB threshold. The value will be updated only after write transaction to function 0 address 0x4B.

RO

0x060C

31:17

Reserved

Reserved

RO

0x0000

16

WSPI_IRQ_ADDR_MASK_OCP_16

EOT offset address MSB threshold

RO

0

15:0

WSPI_IRQ_ADDR_MASK_OCP_15_0

EOT offset address LSB threshold. The value will be updated only after write transaction to function 0 address 0x4D.

RO

0x0004

31

WSPI_NEW_RD_ADDR

EOT hit status. Clear on read.
0 - Old
1 - New

RO

0

30:16

WSPI_IRQ_RD_ADDR

EOT read address hit

RO

0x0000

15

WSPI_NEW_WR_ADDR

EOT hit status. Clear on read.
0 - Old
1 - New

RO

0

14:0

WSPI_IRQ_WR_ADDR

EOT write address hit

RO

0x0000

31:24

Reserved

Reserved

RO

0x00

23:20

OCP_STATUS_7_4

ocp status 7-4
OCP read command status. Clear on read

RO

0x0

19:16

OCP_STATUS_3_0

ocp status 3-0
OCP write command status. Clear on read

RO

0x0

15:0

Reserved

Reserved

RO

0x0000

31:21

Reserved

Reserved

RO

0x000

20:16

Reserved

Reserved

RO

0x00

15:14

Reserved

Reserved

RO

0x0

13:8

USEC_TIMER_VAL

Set usec timer count value. This timer is running at sys_ocp_clk_aod_i clock.

RW

0x27

7:5

Reserved

Reserved

RO

0x0

4:0

RAW_TIMER_VAL

Determine the duration between write and read request in CMD52 raw.

RW

0x1F

31:24

SPARE_BYTE_03

Not in use
(Previously aimed to bit[7:0] - sdio_wr_fifo_vacant_th)

RW

0x00

23:22

SPARE_BYTE_02

Not in use
(Previously aimed to bit[7:0] - sdio_wr_fifo_busy_th)

RW

0x0

21

WUAUT

WAKEUP DUE HOST CMD AUT:
0: Do not Wakeup upon arrival of host command in an Autonomous manner
1: Wakeup due to host command arrival in an Autonomous manner (default)

RW

1

20

WUELP

WAKEUP DUE KNOWN ADDRESS:
0: Do not wakeup due to SDIO cmd 52 or SPI wr to ELP reg (default)
1: Wakeup due to SDIO cmd 52 or SPI wr to ELP reg

RW

0

19

WUADDR

WAKEUP DUE KNOWN ADDRESS:
0: Wakeup regardless to address parsing
1: Wakeup due to command toward known address (default)

RW

1

18

WUHOSTWR

WAKEUP DUE HOST WR:
0: Do not Wakeup due host Write
1: Wakeup due to host Write (default)

RW

1

17

WUHOSTRD

WAKEUP DUE HOST RD:
0: Do not wakeup due host Read
1: Wakeup due to host Read (default)

RW

1

16

WUCMD53

WAKEUP DUE CMD 53 ONLY:
0: Wakeup due to command 53 Or command 52
1: Wakeup due to command 53 only (default)

RW

1

15:8

SPARE_BYTE_01

bit [0] - addr_logic_enable:
0 (disabled) - Access the actual Lx Core addresses with regions as standard SDIO/SPI transaction.
The result will be either the actual data in the requested address if
SDIO_SPI_WRAPPER_ACCESS_MODE_CFG register is full access enabled,
or an OUT_OF_RANGE error otherwise.
1 (default value) - If receiving an SDIO/SPI transaction function 2 with well-known addresses
- activate SDIO/SPI wrapper logic that is based on well-known addresses for function 2 (e.g. Ctrl or Addr).
bits [7:1] - Unused

RW

0x01

7:0

SPARE_BYTE_00

bit [0] - Enable asynchronous in-band interrupt
bit [1] - Force pull-up when the asynchronous in-band interrupt is in idle state
bit [2] - SDIO clock idle polarity (0 = low, 1 = high)
bits [7:3] - Unused

RW

0x00

31:13

Reserved

Reserved

RO

0x0 0000

12:8

Reserved

Reserved

RO

0x00

7

Reserved

Reserved

RO

0

6:0

FN1_GPI_STS

General Purpose Interrupt sources status.
bit 0 - ELP signal transition from "0" to "1"
bit 1 - ELP signal transition from "1" to "0"
bit 2 - Host write to IOE1 register (Function 0 address 0x2)
bit 3 - Host write to function 0 CCCR area
bit 4 - Function 1 data block completion
bit 5 - Function 1 data block with CRC error
bit 6 - Autonomous mode: cmd 53 valid WR command to data FIFO

RO

0x00

31:7

Reserved

Reserved

RO

0x000 0000

6

CSA

Function 1 Supports CSA

RO

0

5:4

Reserved

Reserved

RO

0x0

3:0

SDIO

SDIO standard function 1 interface code

RO

0x2

31:16

CISPTR1

Bits 23:8 of address pointer to function 1 CIS

RO

0x0020

15:8

CISPTR0

Bits 7:0 of address pointer to function 1 CIS

RO

0x00

7:0

Reserved

Reserved

RO

0x00

31:12

Reserved

Reserved

RO

0x0 0000

11:0

FN_BLK_SIZE

function 1 block size register

RW

0x000

31:7

Reserved

Reserved

RO

0x000 0000

6

CSA

Function 2 Supports CSA

RO

0

5:4

Reserved

Reserved

RO

0x0

3:0

SDIO

SDIO standard function 2 interface code

RO

0x0

31:16

CISPTR1

Bits 23:8 of address pointer to function 2 CIS

RO

0x0000

15:8

CISPTR0

Bits 7:0 of address pointer to function 2 CIS

RO

0x30

7:0

Reserved

Reserved

RO

0x00

31:12

Reserved

Reserved

RO

0x0 0000

11:0

FN_BLK_SIZE

function 2 block size register

RW

0x000

31:24

Reserved

RO

0x00

23:16

PATCH1_DATA

CIS data patch 1

RW

0x00

15:0

PATCH1_ADDRESS

CIS address patch 1

RW

0x0000

31:24

Reserved

RO

0x00

23:16

PATCH2_DATA

CIS data patch 2

RW

0x00

15:0

PATCH2_ADDRESS

CIS address patch 2

RW

0x0000

31:24

Reserved

RO

0x00

23:16

PATCH3_DATA

CIS data patch 3

RW

0x00

15:0

PATCH3_ADDRESS

CIS address patch 3

RW

0x0000

31:24

Reserved

RO

0x00

23:16

PATCH4_DATA

CIS data patch 4

RW

0x00

15:0

PATCH4_ADDRESS

CIS address patch 4

RW

0x0000

31:24

Reserved

RO

0x00

23:16

PATCH5_DATA

CIS data patch 5

RW

0x00

15:0

PATCH5_ADDRESS

CIS address patch 5

RW

0x0000