SDIO_CARD_FN1

SDIO_CARD_FN1

This section provides information on the SDIO_CARD_FN1 Module Instance within this product. Each of the registers within the Module Instance is described separately below.

SDIO_CARD_FN1 Registers Mapping Summary

:SDIO_CARD_FN1 Common Register Mapping Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset
FLUSHCMD	RW	32	0x0000 0000	0x0000 0000
RXTHR	RW	32	0x0000 0004	0x0000 0004
TXIRQTHR	RW	32	0x0000 0080	0x0000 000C
DMABLKTHR	RW	32	0x0002 0002	0x0000 0010
IRQSTA	RO	32	0x0000 0000	0x0000 0014
IRQMASK	RW	32	0x0000 3FFF	0x0000 0018
CTRL	RW	32	0x0000 0007	0x0000 001C
RXPACS	RO	32	0x0000 0000	0x0000 0020
RXBBUF	RW	32	0x0000 0000	0x0000 0024
RXBLFT	RO	32	0x0000 0000	0x0000 0028
RETCTL	RW	32	0x0000 0001	0x0000 002C
C2HMSG	RW	32	0x0000 0000	0x0000 0030
H2CMSG	RO	32	0x0000 0000	0x0000 0034
CLKEN	RW	32	0x0000 0000	0x0000 0038
SPAREREG	RW	32	0x0000 0000	0x0000 003C
IRQCLR	RW	32	0x0000 0000	0x0000 0040
RSTREQ	RW	32	0x0000 0000	0x0000 0044
DATAFIFO	RW	32	0x0000 0000	0x0000 1000

SDIO_CARD_FN1 Instances Register Mapping Summary

SDIO_CARD_FN1 Register Descriptions

:SDIO_CARD_FN1 Common Register Descriptions

:SDIO_CARD_FN1:FLUSHCMD

Address offset	0x0000 0000
Description	A write only register. Flush command of the RX / TX buffers
Type	RW

Bits	Field Name	Description			Type	Reset
31:2	Reserved				RO	0x0000 0000
1	TXBUF	TX BUFFER FLUSH: Writing to this address triggers the flush command of the TX buffer (data value is irrelevant).			WO	0
0	RXBUF	RX BUFFER FLUSH: Writing to this address triggers the flush command of the RX buffer (data value is irrelevant).			WO	0

:SDIO_CARD_FN1:RXTHR

Address offset	0x0000 0004
Description	A R/W register that stores one of the RX buffer thresholds.
Type	RW

Bits	Field Name	Description			Type	Reset
31:8	Reserved				RO	0x00 0000
7:2	RXTHR	Buffer almost full threshold - When passing threshold an interrupt is generated (used by the software to indicate packets in buffer) The threshold is configured to allow receiving a completer packet header including packet length. Typical packet header could be 1 - 128 Bytes however the threshold must be 32bits aligned since SDIO FIFO supports 32bits aligned read only.			RW	0x01
1:0	Reserved				RO	0x0

:SDIO_CARD_FN1:TXIRQTHR

Address offset	0x0000 000C
Description	TX IRQ TRIG THR: A R/W register that stores the Threshold in bytes to raise host irq.
Type	RW

Bits	Field Name	Description			Type	Reset
31:8	Reserved				RO	0x00 0000
7:0	MEM_TXIRQTHR	8-bit value describing the number of bytes needed to trigger host irq 1. If HCI packet length > SDIO block (128-bytes) trigger is set to 128 Byte (entire block) 2. If HCI packet length < SDIO block, FW sets packet length in bytes as the trigger value			RW	0x80

:SDIO_CARD_FN1:DMABLKTHR

Address offset	0x0000 0010
Description	A R/W register setting the BLOCK SIZE for the RX and TX DMA flow control
Type	RW

Bits	Field Name	Description			Type	Reset
31:19	Reserved				RO	0x0000
18:16	TXDMABLK	TX DMA BLOCK SIZE SEL: HOST reads from FIFO Determine when to assert flow control to DMA. The flow should be asserted when FIFO has enough free buffer >= Threshold. The threshold is determined according to the DMA block size 0 - 4 Bytes 1 - 8 Bytes 2 - 16 Bytes (Default) 3 - 32 Bytes 4 - 64 Bytes 5 - 128 Bytes 6,7 - Reserved			RW	0x2
15:3	Reserved				RO	0x0000
2:0	RXDMABLK	RX DMA BLOCK SIZE SEL: HOST Writes to FIFO Determine when to assert flow control to DMA. The flow should be asserted when num of bytes in FIFO > Threshold. The threshold is determined according to the DMA block size 0 - 4 Bytes 1 - 8 Bytes 2 - 16 Bytes (Default) 3 - 32 Bytes 4 - 64 Bytes 5 - 128 Bytes 6,7 - Reserved HOST Writes to FIFO Determine when to assert flow control to DMA. The flow should be asserted when num of bytes in FIFO > Threshold. The threshold is determined according to the DMA block size 0 - 4 Bytes 1 - 8 Bytes 2 - 16 Bytes (Default) 3 - 32 Bytes 4 - 64 Bytes 5 - 128 Bytes 6,7 - Reserved			RW	0x2

:SDIO_CARD_FN1:IRQSTA

Address offset	0x0000 0014
Description	A RO register. Holds the status of the different interrupts of the SDIO. This register is cleared by writing to IRQCLR register Each interrupt is set when the event is active. In the case of ACKINT the software has to read the ACKNAK bit value to see if an ACK event was received or a read retry is starting.
Type	RO

Bits	Field Name	Description			Type	Reset
31:14	Reserved				RO	0x0 0000
13	HOST2CORE	Host to Card 15 bit message ready indication			RO	0
12	CRCERR	'1' = CRC Error was detected for rx flow			RO	0
11	PHYINT	SDIO PHY interrupt			RO	0
10	CARDRST	Card Reset interrupt			RO	0
9	PHYIFERR	Error in the OCP interface of the SDIO PHY			RO	0
8	HCIWRRET	HCI packet write retry			RO	0
7	HCINACK	HCI packet NACK interrupt			RO	0
6	HCIACK	HCI packet ACK interrupt			RO	0
5	TXBUFUNR	TX Buffer under-run interrupt			RO	0
4	TXBUFOVR	TX Buffer overrun interrupt			RO	0
3	RXBUFUNR	RX Buffer under-run interrupt			RO	0
2	RXBUFOVR	RX Buffer overrun interrupt			RO	0
1	FN1EN	Function #1 enable interrupt			RO	0
0	RXALMSFULL	RX Buffer almost full interrupt			RO	0

:SDIO_CARD_FN1:IRQMASK

Address offset	0x0000 0018
Description	A R/W register. Holds the mask bits of the different interrupts of the SDIO.
Type	RW

Bits	Field Name	Description			Type	Reset
31:14	Reserved				RO	0x0 0000
13	HOST2CORE	Host to Card 15 bit message ready indication			RW	1
12	CRCERR	'1' = CRC Error was detected for rx flow			RW	1
11	PHYMASK	SDIO PHY interrupt			RW	1
10	CARDRST	Card Reset interrupt			RW	1
9	PHYIFERR	Error in the OCP interface of the SDIO PHY			RW	1
8	HCIWRRET	HCI packet write retry			RW	1
7	HCINACK	HCI packet NACK interrupt			RW	1
6	HCIACK	HCI packet ACK interrupt			RW	1
5	TXBUFUNR	TX Buffer under-run interrupt			RW	1
4	TXBUFOVR	TX Buffer overrun interrupt			RW	1
3	RXBUFUNR	RX Buffer under-run interrupt			RW	1
2	RXBUFOVR	RX Buffer overrun interrupt			RW	1
1	FN1EN	Function #1 enable interrupt			RW	1
0	RXALMSFULL	RX Buffer almost full interrupt			RW	1

:SDIO_CARD_FN1:CTRL

Address offset	0x0000 001C
Description	A R/W register to control SDIO operation.
Type	RW

Bits	Field Name	Description			Type	Reset
31:4	Reserved				RO	0x000 0000
3	HIRQSYNC	HOST IRQ SYNCHRONIZATION: This bit controls the synchronization of the host interrupt (interrupt from BT to host through the PHY). '1' - interrupt is synchronized to sdio_clk. '0' - interrupt is not synchronized to sdio_clk (and thus synchronized to ocp_clk)			RW	0
2	TXBUF_EN	TX BUFFER FLUSH EN: Enables the module to flush the TX buffer after receiving packet-read-retry indication (ACK or NACK). When this bit is '0', FW must flush the buffer manually (by writing to FLUSHCMD register) upon receiving ACK/NACK interrupt. It is needed for the correct operation of the TX FIFO			RW	1
1	BACE	BUSY AFTER CRC ERROR: Enables the module to activate the busy signal after CRC error on data only if sdio_enable was set			RW	1
0	SDIOEN	SDIO enable - Enable SDIO after CRC error. Cleared by HW after CRC error; Set by FW to de-assert the busy signal			RW	1

:SDIO_CARD_FN1:RXPACS

Address offset	0x0000 0020
Description	RX SDIO PACKET SIZE: A read only register. Holds the length of the current received SDIO packet. Updated at the beginning of each SDIO packet.
Type	RO

Bits	Field Name	Description			Type	Reset
31:10	Reserved				RO	0x00 0000
9:0	RXPACS	Length of the current received SDIO packet. Updated at the beginning of each SDIO packet			RO	0x000

:SDIO_CARD_FN1:RXBBUF

Address offset	0x0000 0024
Description	RX BYTES IN BUFF: A read only status register. Holds the current number of bytes in SDIO RX buffer.
Type	RW

Bits	Field Name	Description			Type	Reset
31:11	Reserved				RO	0x00 0000
10:0	RXBBUFFER	Current number of bytes in SDIO RX buffer			RO	0x000

:SDIO_CARD_FN1:RXBLFT

Address offset	0x0000 0028
Description	RX BYTES LEFT: A read only status register. A down-count counter. Holds the number of bytes in current SDIO packet that were not transmitted to RX buffer yet. Please notice: Before reading this register, the FW MUST read RXBBUFFER register.
Type	RO

Bits	Field Name	Description			Type	Reset
31:16	Reserved				RO	0x0000
15	BLIL	BYTES LEFT IS LOCKED: When '0' - the value that is read from rx_bytes_left is the current number of bytes left to transfer to the end of the block. When '1' - the value that is read from rx_bytes_left is the number of bytes left to transfer to the end of the block that was locked on the last read from RXBBUF.			RO	0
14:11	Reserved				RO	0x0
10:0	RXBLFT	A counter that is loaded with SDIO packet length and decremented the same as the incrementing of bytes-in-buffer status register			RO	0x000

:SDIO_CARD_FN1:RETCTL

Address offset	0x0000 002C
Description	A read/write register. The value states if the BT-SDIO is working with Retry Control mechanism as specified in SDIO spec.
Type	RW

Bits	Field Name	Description			Type	Reset
31:1	Reserved				RO	0x0000 0000
0	RETCTL	When FW writes '1' to this bit, it states that the BT-SDIO is using retry control mechanism. When FW reads this bit, it actually reads the value of the Function 1's RETRY_CONTROL register (the value that the host configured). Default value is '1' because BT FW MUST have retry control mechanism working			RW	1

:SDIO_CARD_FN1:C2HMSG

Address offset	0x0000 0030
Description	IRQ2Host Message 16b
Type	RW

Bits	Field Name	Description			Type	Reset
31:17	Reserved				RO	0x0000
16	C2HIRQ	CARD TO HOST IRQ: To Host: 16bits MMR which can be written/read by M33 and read/clear (bit map) by host			WO	0
15:0	C2HSTS	CARD TO HOST STS: To Host: 16bits MMR which can be written/read by M33 and read/clear (bit map) by host Cleared by HOST writing to CLINTERD (Interrupt Clear 0x13)			RW	0x0000

:SDIO_CARD_FN1:H2CMSG

Address offset	0x0000 0034
Description	IRQ from Host to card Message 16b
Type	RO

Bits	Field Name	Description			Type	Reset
31:15	Reserved				RO	0x0 0000
14:0	H2CSTS	HOST TO CARD STS: From Host: 15bits MMR which can be written by host and read/clear (bit map) by M33. (bit 16 is the host_to_card_irq that is generated by the HOST and goes to [IRQSTA.HOST_TO_CARD_INT])			RO	0x0000

:SDIO_CARD_FN1:CLKEN

Address offset	0x0000 0038
Description	Clock gating control
Type	RW

Bits	Field Name	Description			Type	Reset
31:1	Reserved				RO	0x0000 0000
0	VAL	1'b0 - disable clk 1'b1 - enable clk			RW	0

:SDIO_CARD_FN1:SPAREREG

Address offset	0x0000 003C
Description	A read/write 8-bit register that serves for future debug only.
Type	RW

Bits	Field Name	Description			Type	Reset
31:8	Reserved				RO	0x00 0000
7:0	SPAREREG	spare			RW	0x00

:SDIO_CARD_FN1:IRQCLR

Address offset	0x0000 0040
Description	A write-only register. When written, it clears all SDIO pending interrupts
Type	RW

Bits	Field Name	Description			Type	Reset
31:14	Reserved				RO	0x0 0000
13	HOST2CORE	Host to Card 15 bit message ready indication			WO	0
12	CRCERR	CRC Error clear			WO	0
11	PHYCLEAR	SDIO PHY interrupt clear			WO	0
10	CARDRST	Card Reset interrupt clear			WO	0
9	PHYIFERR	Error in the OCP interface of the SDIO PHY clear			WO	0
8	HCIWRRET	HCI packet write retry clear			WO	0
7	HCINACK	HCI packet NACK interrupt clear			WO	0
6	HCIACK	HCI packet ACK interrupt clear			WO	0
5	TXBUFUNR	TX Buffer under-run interrupt clear			WO	0
4	TXBUFOVR	TX Buffer overrun interrupt clear			WO	0
3	RXBUFUNR	RX Buffer under-run interrupt clear			WO	0
2	RXBUFOVR	RX Buffer overrun interrupt clear			WO	0
1	FN1EN	Function #1 enable interrupt			WO	0
0	RXALMSFULL	RX Buffer almost full interrupt clear			WO	0

:SDIO_CARD_FN1:RSTREQ

Address offset	0x0000 0044
Description	reset sdio IP due to a SDIO Card Reset command: 0 - do not reset / de-assert initiated sdio reset 1 - initiate reset sdio reset (both PHY and SDIO System)
Type	RW

Bits	Field Name	Description			Type	Reset
31:1	Reserved				RO	0x0000 0000
0	EN	Function #1 enable interrupt			RW	0

:SDIO_CARD_FN1:DATAFIFO

Address offset	0x0000 1000
Description	Common shadow register to access SDIO-Card RX-Fifo or TX-Fifo
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	RDRXWRTX	Common access for either: 1. Reading 'sdio_rxfifo' 2. Writing 'sdio_txfifo' Can be used either as local ocp rd/wr commands, or transactions through DMA machine.			RW	0x0000 0000