PLL_SHARING

This section provides information on the PLL_SHARING Module Instance within this product. Each of the registers within the Module Instance is described separately below.

PLL SHARING CONTROL REGISTERS

PLL_SHARING Registers Mapping Summary

:PLL_SHARING Common Register Mapping Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset
WCSPLLM	RW	32	0x0000 00A0	0x0000 0000
WCSPLLN	RW	32	0x0000 0014	0x0000 0004
WCSQFACCFG	RW	32	0x0000 0000	0x0000 0008
WCSPFACCFG	RW	32	0x0000 0000	0x0000 000C
WCSPLLSWAL	RW	32	0x0000 0012	0x0000 0010
WCSPLLCFG	RW	32	0x012A 0270	0x0000 0014
CR	RW	32	0x0000 0000	0x0000 0018
GEN	RW	32	0x0008 015E	0x0000 001C
WCSCFG	RW	32	0x0004 5100	0x0000 0020
GENCFG	RW	32	0x0000 0000	0x0000 0024
LOCK	RW	32	0x0000 0000	0x0000 0028
SOPBM	RW	32	0x0000 0000	0x0000 002C
DBGSS	RW	32	0x0000 0000	0x0000 0030
ICG	RW	32	0x0000 0050	0x0000 0034

PLL_SHARING Instances Register Mapping Summary

PLL_SHARING Register Descriptions

:PLL_SHARING Common Register Descriptions

:PLL_SHARING:WCSPLLM

Address offset	0x0000 0000
Description	WCS PLL M divider configuration for WCS PLL - primary reference
Type	RW

Bits	Field Name	Description	Type	Reset
31:9	Reserved		RO	0x00 0000
8:0	MEM_WCSPLLM	In all modes value should be 160	RW	0x0A0

:PLL_SHARING:WCSPLLN

Address offset	0x0000 0004
Description	WCS PLL N pre divider configuration for WCS PLL - primary reference
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	Reserved		RO	0x00 0000
7	MEM_WCSPLLN_SEL	N SELECTOR '1' - use MMR N value '0' - use HW auto detection (default)	RW	0
6:0	MEM_WCSPLLN	10MHz - 5 26MHz - 13 40MHz - 20 52MHz - 26	RW	0x14

:PLL_SHARING:WCSQFACCFG

Address offset	0x0000 0008
Description	WCS Q FACTOR CONFIG swallowing logic configuration for WCS PLL for primary reference clock input - 16 LSB : 16.2MHz - 801 : 16.368MHz - 3751 : 16.8MHz - disabled : 19.2MHz - disabled : 26MHz - disabled : 32.736MHz - 3751 : 33.6MHz - disabled : 38.4MHz - disabled : 52MHz - disabled
Type	RW

Bits	Field Name	Description	Type	Reset
31:24	Reserved		RO	0x00
23:0	SWAL	SWALLOWING swallowing logic configuration Q factor	RW	0x00 0000

:PLL_SHARING:WCSPFACCFG

Address offset	0x0000 000C
Description	WCS P FACTOR CONFIG swallowing logic configuration for WCS PLL for primary reference clock input - 16 LSB : P factor 16 LSB : 16.2MHz - 4 : 16.368MHz - 4 : 16.8MHz - disabled : 19.2MHz - disabled : 26MHz - disabled : 32.736MHz - 4 : 33.6MHz - disabled : 38.4MHz - disabled : 52MHz - disabled
Type	RW

Bits	Field Name	Description	Type	Reset
31:20	Reserved		RO	0x000
19:0	SWAL	SWALLOWING swallowing logic configuration P factor	RW	0x0 0000

:PLL_SHARING:WCSPLLSWAL

Address offset	0x0000 0010
Description	WCS PLL swallowing logic gen cfg
Type	RW

Bits	Field Name	Description	Type	Reset
31:6	Reserved		RO	0x000 0000
5:4	CONSWAL	CONSECUTIVE SWALLOWING valid values (1-3) - number of consecutive clock swallows once accumulator reached Q value for WCS PLL	RW	0x1
3	PRBSGN	PRBS GAIN 1: prbs addition is 5 bits to the right of MSB 0: prbs addition is 3 bits to the right of MSB	RW	0
2	PRBSEN	enable prbs for adding randomization (jittering)- disable by default	RW	0
1	BYP	bypass the swallowing logic	RW	1
0	EN	enable the swallowing logic - disable when not using the bypass option	RW	0

:PLL_SHARING:WCSPLLCFG

Address offset	0x0000 0014
Description	WCS PLL CONFIG gen cfg for WCS PLL
Type	RW

Bits	Field Name	Description	Type	Reset
31:25	Reserved		RO	0x00
24	PHASEOV	PHASE OVERRIDE '1' - Overrideing phase control implementation.	RW	1
23:19	PHSEL	PHASE SELECT the following values should be used: 10MHz - up to decimal 0..31 26MHz - up to decimal 0..11 40MHz - up to decimal 0..7 52MHz - up to decimal 0..5 notes: delayes are set in 320MHz clk due to sync issues delay could get +1 of the setting value	RW	0x05
18	CLRVCOSLP	CLEAR VCO DURING SLEEP '1' - during sleep VCO 300-400MHz will be gated '0' - during sleep VCO 300-400MHz will stay high	RW	0
17	HFREQMODEN	HIGH FREQUENCY MODE ENABLE connected to WCS PLL HIGHFREQ_MODE_EN input : 0: 300M-500M ICO disabled : 1: 300M-400M/400M-500M ICO enabled : based on CONTROL bits [7:6]	RW	1
16	LFREQMODEN	LOW FREQUENCY MODE ENABLE connected to WCS PLL LOWFREQ_MODE_EN input : 0:Normal mode : 1: Divide by 2 the PLL clock out	RW	0
15:14	LOCKOV	LOCK OVERRIDE override option for WCS PLL lock indication - should be used when using the override option for PLL enable	RW	0x0
13	FCLKFSOV	FREF CLOCK FUSE OVERRIDE '1' - override the PLL_BYPASS fuse with PLL_BYPASS MMR: mem_pllsh_fref_clk_sel; '0' do not override	RW	0
12	GLMFCLKSEL	GLITCH LESS MUX FREF CLOCK SELECT select bypass option to use external clock in case PLL not working	RW	0
11	FCLKSEL	FREF CLOCK SELECT select bypass option to use external clock in case PLL not working	RW	0
10:8	DISCNT	DISABLE COUNTER time (sclk) from pll request goes low to the time PLL input will go low - keep >= 2	RW	0x2
7	USELOCKMON	USE LOCKMON Do not enable this bit because Analog APLL design might have lock stays '1' even when FREF is dropped to OFF. From safety POV, No DCC is used in Osprey, so having a counter based for PLL assumed Lock is ok for the level of safety required 1: use the PLL lock indication for lock 0: use the timer (mem_pllsh_wcs_pll_lock_cnt) for the lock	RW	0
6:3	LOCKCNT	LOCK COUNT time (sclk) from enabling the PLL until valid signal will rise. Default is 14 since the PLL lock can go up to 200us and assuming untrimmed slow clk is 15us we need at least 14 cycles This value can be optimized by half by s/w (Once we have trimmed slow clk)	RW	0xE
2:1	OV	override register for WCS PLL enable	RW	0x0
0	EN	enable like any other IP request	RW	0

:PLL_SHARING:CR

Address offset	0x0000 0018
Description	CORE configuration for PLL Sharing
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	MEM_CR	PLL ENABLE register for Core to enable PLLs according to the type instead of using HW request core_pll_en	RW	0

:PLL_SHARING:GEN

Address offset	0x0000 001C
Description	GENERAL PLL divider configuration
Type	RW

Bits	Field Name	Description	Type	Reset
31:25	Reserved		RO	0x00
24	UALGNPHYCR	UNALIGNED PHY TO CORE 1: PHY and core clk will get phase difference	RW	0
23	Reserved		RO	0
22	PHYICGOV	PHY ICG OVERRIDE 1: ICG of PLL to PHY is forced enable : 0: ICG is enabled according to elp request and phy_pll_en	RW	0
21	CRICGOV	CORE ICG OVERRIDE 1: ICG of PLL to Core is forced enable : 0: ICG is enabled according to elp request and core_pll_en	RW	0
20	GPADCICGOV	GPADC ICG OVERRIDE '1' - enable gpadc clk '0' - disable clock	RW	0
19	PICGOV	PSCON ICG OVERRIDE Default is 1	RW	1
18	HICGOV	HOST ICG OVERRIDE '0' - No Override '1' - Enables HOST CLKs	RW	0
17	SOCICGOV	SOC ICG OVERRIDE '0' - No Override '1' - Enables SOC 80MHz CLK	RW	0
16	CRM3ICGOV	CORE M3 ICG OVERRIDE '0' - No Override '1' - Enables CORE M3 80MHz CLK	RW	0
15:10	Reserved		RO	0x00
9	PHYDIV2OV	PHY DIVIDER 2 OVERRIDE 1: no division (80MHz clock) : 0: divide by 2 (40MHz clock)	RW	0
8	PDIVEN	PSCON DIVIDER ENABLE divider enable. Default is 1. Enabled.	RW	1
7	PCLKSRCCNG	PSCON CLOCK SOURCE CHANGE Change divider input clock	RW	0
6	PPLLLDDIVV	PSCON PLL LOAD DIVIDER VALUE Load div value indication. Default is 1	RW	1
5:4	PPLLDIVVAL	PSCON PLL DIVIDER OVERRIDE 0: no division (80MHz clock) : PSCON div val. Set the PSCON clock period: 0-1us; 1-2us; 2-4us; 3-16us	RW	0x1
3	Reserved		RO	1
2	SOCDIV2OV	SOC DIVIDER 2 OVERRIDE 1: no division (80MHz clock) : 0: divide by 2 (40MHz clock)	RW	1
1	CRM3DIV2OV	CORE M3 DIVIDER OVERRIDE 1: no division (80MHz clock) : 0: divide by 2 (40MHz clock)	RW	1
0	CRDIV2OV	CORE DIVIDER 2 OVERRIDE 1: no division (80MHz clock) : 0: divide by 2 (40MHz clock)	RW	0

:PLL_SHARING:WCSCFG

Address offset	0x0000 0020
Description	WCS CONFIG WCS PLL control input : Refer to WCSPLL spec
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	MEM_WCSCFG	CONTROL			RW	0x0004 5100

:PLL_SHARING:GENCFG

Address offset	0x0000 0024
Description	GENERAL CONFIGURATION PLL sharing module general configurations
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	DFTWCSPICGOV	DFT WCS PLL ICG OVERRIDE control WCS PLL clock toward test ctrl	RW	0

:PLL_SHARING:LOCK

Address offset	0x0000 0028
Description	Lock status reg
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1	MONSTS	LOCK MONITOR STATUS PLL Lock status register	RO	0
0	STS	STATUS PLL Timer for Lock status register in case MEM_USE_LOCKMON = 1 - this indication is similar to LOCKMON_STS in case MEM_USE_LOCKMON = 0 - this indication reflect the Lock Timer (configured by PLL_LOCK_CNT) status (1 means elapsed)	RO	0

:PLL_SHARING:SOPBM

Address offset	0x0000 002C
Description	SOP MASK PLL sharing module SOP mask config
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	MEM_SOPBM_BYP_SEL	BYPASS SELECTOR SOP mask - Mask SOPs Bypass so PLL Bypass can be can be bypassed by SoC PLL. Default is 0 - "do not mask SOP"	RW	0
1	MEM_SOPBM_FREF_SEL	FREF SELECTOR SOP mask - Mask SOPs Bypass so PLL FREF selected from HFXT over DIO pin. Default is 0 - "do not mask SOP"	RW	0
0	MEM_SOPBM_PLL_EN	PLL ENABLE SOP mask - Mask SOPs Bypass so PLL can be enabled. Default is 0 - "do not mask SOP"	RW	0

:PLL_SHARING:DBGSS

Address offset	0x0000 0030
Description	DEBUGSS
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	MEM_DBGSS	FAST SELECTOR Lock status register; clear upon read by S/W	RW	0

:PLL_SHARING:ICG

Address offset	0x0000 0034
Description	ICG
Type	RW

Bits	Field Name	Description	Type	Reset
31:7	Reserved		RO	0x000 0000
6	SOCPSWLDIS	SOC PSWL DISABLE ICG Disable control '1' - disable '0' - enable	RW	1
5	PHYDIS	PHY DISABLE ICG Disable control '1' - disable '0' - enable	RW	0
4	PLL32DIS	PLL 32 DISABLE ICG control '1' - disable '0' - enable	RW	1
3	HDIS	HOST DISABLE ICG Disable control '1' - disable '0' - enable	RW	0
2	SOCDIS	SOC DISABLE ICG Disable control '1' - disable '0' - enable	RW	0
1	CRDIS	CORE ICS DISABLE ICG Disable control '1' - disable '0' - enable	RW	0
0	CRM3DIS	CORE M3 DISABLE ICG Disable control '1' - disable '0' - enable	RW	0