HSM_SEC

HSM_SEC

This section provides information on the HSM_SEC Module Instance within this product. Each of the registers within the Module Instance is described separately below.

HSM_SEC Registers Mapping Summary

:HSM_SEC Common Register Mapping Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset
CLKCTL	RW	32	0x0000 0000	0x0000 0000
SRSTCTL	RW	32	0x0000 0000	0x0000 0004
PKACTL	RW	32	0x0000 0000	0x0000 0008
DBGCTL	RW	32	0x0000 0000	0x0000 000C
DFTCTL	RW	32	0x0000 0000	0x0000 0010
CLKFRODIV	RW	32	0x0000 0002	0x0000 0014
SLPCTL	RW	32	0x0000 0000	0x0000 0018

HSM_SEC Instances Register Mapping Summary

HSM_SEC Register Descriptions

:HSM_SEC Common Register Descriptions

:HSM_SEC:CLKCTL

Address offset	0x0000 0000
Description	Clock Control Secured Register. This register is used for enabling clock to the module.
Type	RW

Bits	Field Name	Description			Type	Reset
31:7	Reserved	Reads to this field return zero, writes to this field are ignored.			RO	0x000 0000
6	CTR_CLKBUSY	When 1b, indicates that the counter clock domain is active. This signal is always asserted (set to '1'), except when the counter module is in reset (ctr_reset_n set to '0').			RO	0
5	SLV_CLKBUSY	When 1b indicates the Host interface is active and busy with Host bus transfers.			RO	0
4	CLKBUSY	when 1b, indicates that the module is active and busy with processing data and tokens.			RO	0
3	CLKDISREQ	This bit is set to disable all clock sources.			RW	0
		1	DIS Write 1 to disable clock
2	CNTCLKGO	Write this bit to enable counter clock			RW	0
		0	DIS Write 0 to disable clock
		1	EN Write 1 to enable clock
1	HIFCLKGO	Write this bit to enable host interface clock			RW	0
		0	DIS Write 0 to disable clock
		1	EN Write 1 to enable clock
0	CLKGO	Write this bit to enable clock to the module			RW	0
		0	DIS Write 0 to disable clock
		1	EN Write 1 to enable clock

:HSM_SEC:SRSTCTL

Address offset	0x0000 0004
Description	Soft Reset Control. This register is used for controlling soft reset mechanism.
Type	RW

Bits	Field Name	Description			Type	Reset
31:7	Reserved	Reads to this field return zero, writes to this field are ignored.			RO	0x000 0000
6:4	STATE	It indicates state of soft reset assertion.			RO	0x0
		Read 0x0	IDLE soft reset is not requested
		Read 0x1	REQ Soft reset is requested
		Read 0x2	ACK Soft reset is acknowledged.
		Read 0x3	ASSERT Soft reset can be asserted
		Read 0x4	SET soft reset is set
3	STA	When 1b, soft reset is asserted to the module			RO	0
2	FRCACK	Write 1b, to forcely assert soft reset without waiting for abort acknowledge from EIP.			WO	0
		Write 1	EN To force soft reset
1	ABORTACK	when 1b, indicates abort request is acknowledged by EIP and soft reset is asserted			RO	0
0	ABORTREQ	Write this bit to request soft reset. It is a write-clear or auto clear register.			WO	0
		Write 1	REQ To enable Abort request

:HSM_SEC:PKACTL

Address offset	0x0000 0008
Description	PKA Abort Control Secured Register. This register is used for aborting PKA operation.
Type	RW

Bits	Field Name	Description			Type	Reset
31:2	Reserved	Reads to this field return zero, writes to this field are ignored.			RO	0x0000 0000
1	NSMASKREQ	This bit is used to mask PKA abort request generated by non-secure controller.			RW	0
		1	MASK Mask request
0	ABORT	Write 1 to Abort.			RW	0
		1	ABORT Write 1 to this bit to abort PKA operation

:HSM_SEC:DBGCTL

Address offset	0x0000 000C
Description	Debug Control. This register is used for HSM memory and asset debug through OCP only if TI debug access is enabled
Type	RW

Bits	Field Name	Description			Type	Reset
31:7	Reserved	Reads to this field return zero, writes to this field are ignored.			RO	0x000 0000
6:0	SEL	This register enables debug through OCP. To enable FIFO0 , bit0 should be set. To enable FIFO1 , bit1 should be set. To enable MBIN , bit2 should be set. To enable MBOUT, bit3 should be set. To enable OTP , bit4 should be set. To enable DRAM , bit5 should be set. To enable PROM , bit6 should be set.			RW	0x00

:HSM_SEC:DFTCTL

Address offset	0x0000 0010
Description	DFT Control. This register is used for enabling FRO controls if TI test access is enabled
Type	RW

Bits	Field Name	Description			Type	Reset
31:8	Reserved	Reads to this field return zero, writes to this field are ignored.			RO	0x00 0000
7	DLY	Delay chain length selection for FRO selected by tst_fro_select. This input should only be changed while tst_fro_enable is LOW.			RW	0
6	ENABLE	Active HIGH enable signal for FRO selected by tst_fro_select			RW	0
5	CTLEN	Active HIGH enable signal for FRO characterization (enables the tst_fro_select, tst_fro_enable and tst_fro_delay inputs). This is a combinatorial function. The TRNG module clocks do not need to run for this to work.			RW	0
4:0	SEL	FRO selection input. A selected FRO will have its fro_testin input forced low. Valid value to select FRO's is 0-7.			RW	0x00

:HSM_SEC:CLKFRODIV

Address offset	0x0000 0014
Description	Clock FRO Divide Configuration. This register is used for controlling FRO clock measurements.
Type	RW

Bits	Field Name	Description			Type	Reset
31:8	RESERVED8	Reads to this field return zero, writes to this field are ignored.			RO	0x00 0000
7	EN	It is write enable signal used for loading division value onto divider. It should be disable and re-enable after changing the mem_value			RW	0
6:0	VAL	It is used for dividing FRO clock withe the division value specified by this register. Division value should be from 2-80.			RW	0x02

:HSM_SEC:SLPCTL

Address offset	0x0000 0018
Description	Sleep Control.
Type	RW

Bits	Field Name	Description			Type	Reset
31:2	RESERVED2	Reads to this field return zero, writes to this field are ignored.			RO	0x0000 0000
1	SRCVAL	power_mode_in source select MMR 0-power_mode_in comes from logic 1-power_mode_in comes from mem_slp_ovr_val			RW	0
0	OVRVAL	power_mode_in override value by FW. FW can set to 1 after cold boot			RW	0