HOST_MCU

HOST_MCU

This section provides information on the HOST_MCU Module Instance within this product. Each of the registers within the Module Instance is described separately below.

HOST_MCU Registers Mapping Summary

:HOST_MCU Common Register Mapping Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset
TRACECFG	RW	32	0x0000 0002	0x0000 0000
SPARE	RW	32	0x0000 0000	0x0000 0004
WRRARB	RW	32	0x0000 0002	0x0000 0008
AGENT0CFG	RW	32	0x0001 0004	0x0000 0010
AGENT1CFG	RW	32	0x0000 0004	0x0000 0014
SWIRQ	RW	32	0x0000 0000	0x0000 0018
NSSWIRQ	RW	32	0x0000 0000	0x0000 001C
SWIRQCM3	RW	32	0x0000 0000	0x0000 0020
ARBPOL	RW	32	0x0000 0003	0x0000 0024
DBGSS	RW	32	0x0000 0000	0x0000 0028
DBGSS_IF_LOCK	RW	32	0x0000 0000	0x0000 002C
DBGSS_IF_LOCK_COND_MASK	RW	32	0x0000 0000	0x0000 0030
DBGSS_IF_LOCK_COND_STATUS	RW	32	0x0000 0000	0x0000 0034

HOST_MCU Instances Register Mapping Summary

HOST_MCU Register Descriptions

:HOST_MCU Common Register Descriptions

:HOST_MCU:TRACECFG

Address offset	0x0000 0000
Description	Trace Configuration. Configuration register for CortexM3-TPIU (TRACE ports i/o unit)
Type	RW

Bits	Field Name	Description			Type	Reset
31:9	RESERVED2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior			RO	0x00 0000
8	CLKDIVEN	Set this register to load [CLKDIVVAL]			WO	0
		Write 0	DIS Magillem Info : Information not available in the IP-XACT file
		Write 1	EN Disable
7:2	RESERVED2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior			RO	0x00
1:0	CLKDIVVAL	Configure TRACE-CLOCK divider value, for (TPIU - input clock) [1] - Divide by 2 - 'tpiu_trace_clk_in' = 40MHz [2] - Divide by 4 - 'tpiu_trace_clk_in' = 20MHz (Default) [0,3] - are not supported (do not use) AFTER setting this value - set [CLKDIVEN] to active this value			RW	0x2
		0x0	DIV_2 Divide by 2
		0x1	DIV_4 Divide by 4

:HOST_MCU:SPARE

Address offset	0x0000 0004
Description	Spare
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	MEM_SPARE	Spare			RW	0x0000 0000

:HOST_MCU:WRRARB

Address offset	0x0000 0008
Description	WRR Arbiter Enable Register
Type	RW

Bits	Field Name	Description			Type	Reset
31:2	RESERVED2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior			RO	0x0000 0000
1	POLICY	Field to configure the priority policy 0 - Fixed Priority 1 - Round Robin (Default)			RW	1
		0	FIXED Fixed priority
		1	ROUNDROBIN Round Robin (Default)
0	MEM_WRRARB	Field to enable/select the arbitration logic 0 - Disabled, use SIE-200 arbitration logic. 1 - Enable, use wrapper arbitration logic.			RW	0
		0	DIS Use SIE-200 arbitration logic
		1	EN Use wrapper arbitration logic

:HOST_MCU:AGENT0CFG

Address offset	0x0000 0010
Description	WRR Arbiter - Agent 0 Configuration
Type	RW

Bits	Field Name	Description			Type	Reset
31:29	RESERVED2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior			RO	0x0
28:24	TRANSDLY	Number of cycle before starting to serve next agent in line. Up to 32 cycles.			RW	0x00
23:18	RESERVED2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior			RO	0x00
17:16	FIXPRI	Field to select the fixed priority level 0 - Highest 1 - Medium 2 - Lowest (default) 3 - Not in Use			RW	0x1
		0x0	SEL_0 Highest Priority
		0x1	SEL_1 Medium Priority
		0x2	SEL_2 Lowest priority (default)
15:13	RESERVED2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior			RO	0x0
12:0	NUMOFBLK	Number of words to be served in each arbitration grant. Up to 8,192 words (32KB). Value must be greater then 0.			RW	0x0004

:HOST_MCU:AGENT1CFG

Address offset	0x0000 0014
Description	WRR Arbiter - Agent 1 Configuration
Type	RW

Bits	Field Name	Description			Type	Reset
31:29	RESERVED2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior			RO	0x0
28:24	TRANSDLY	Number of cycle before starting to serve next agent in line. Up to 32 cycles.			RW	0x00
23:18	RESERVED2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior			RO	0x00
17:16	FIXPRI	Field to select the fixed priority level 0 - Highest 1 - Medium 2 - Lowest (default) 3 - Not in Use			RW	0x0
		0x0	SEL_0 Highest priority
		0x1	SEL_1 Medium priority
		0x2	SEL_2 Lowest priority (default)
15:13	RESERVED2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior			RO	0x0
12:0	NUMOFBLK	Number of words to be served in each arbitration grant. Up to 8,192 words (32KB). Value must be greater then 0.			RW	0x0004

:HOST_MCU:SWIRQ

Address offset	0x0000 0018
Description	Software Timestamp Interrupt Register
Type	RW

Bits	Field Name	Description			Type	Reset
31:16	RESERVED2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior			RO	0x0000
15:0	MEM_SWIRQ	Field to write timestamp for ET bus.			RW	0x0000

:HOST_MCU:NSSWIRQ

Address offset	0x0000 001C
Description	Non Secure Software Interrupt
Type	RW

Bits	Field Name	Description			Type	Reset
31:4	RESERVED2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior			RO	0x000 0000
3:0	MEM_NSSWIRQ	Non Secure context of CM33 can use this register to interrupt secure context of CM33.			RW	0x0

:HOST_MCU:SWIRQCM3

Address offset	0x0000 0020
Description	Software Interrupt to CM3
Type	RW

Bits	Field Name	Description			Type	Reset
31:1	RESERVED2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior			RO	0x0000 0000
0	MEM_SWIRQCM3	Non Secure context of CM33 can use this register to interrupt CM3.			RW	0

:HOST_MCU:ARBPOL

Address offset	0x0000 0024
Description	Arbiter Policy. Arbiter Policy for the arbiters(x2) located just before MEMSS Portion A and Portion B
Type	RW

Bits	Field Name	Description			Type	Reset
31:10	RESERVED2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior			RO	0x00 0000
9:8	MEM_S1_PRIORITY_M1	This bit field takes affect when Fixed Priority is selected for the arbiter before MEMSS Portion B. This field is used to configure the priority of ocp.			RW	0x0
7:6	MEM_S1_PRIORITY_M0	This bit field takes affect when Fixed Priority is selected for the arbiter before MEMSS Portion B. This field is used to configure the priority of udma/sahb.			RW	0x0
5:4	MEM_S0_PRIORITY_M1	This bit field takes affect when Fixed Priority is selected for the arbiter before MEMSS Portion A. This field is used to configure the priority of ocp.			RW	0x0
3:2	MEM_S0_PRIORITY_M0	This bit field takes affect when Fixed Priority is selected for the arbiter before MEMSS Portion A. This field is used to configure the priority of udma/sahb.			RW	0x0
1	MEM_ROUND_ROBIN_S1	Field to select the arbitration policy of second arbiter (MEMSS Portion ) 1 -> Round Robin is enabled 0 -> Fixed priority is enabled			RW	1
		0	FIXED Fixed priority
		1	ROUNDROBIN Round Robin priority
0	MEM_ROUND_ROBIN_S0	Field to select the arbitration policy of second arbiter (MEMSS Portion A) 1 -> Round Robin is enabled 0 -> Fixed priority is enabled			RW	1
		0	FIXED Fixed priority
		1	ROUNDROBIN Round Robin priority

:HOST_MCU:DBGSS

Address offset	0x0000 0028
Description	DBGSS Control Register.
Type	RW

Bits	Field Name	Description			Type	Reset
31:1	RESERVED2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior			RO	0x0000 0000
0	MEM_HOST_DBGSS_PWRDWNDESIRED	Non Secure context of CM33 can use this register to interrupt CM3.			RW	0

:HOST_MCU:DBGSS_IF_LOCK

Address offset	0x0000 002C
Description	DBGSS Interface Lock.
Type	RW

Bits	Field Name	Description			Type	Reset
31:1	RESERVED2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior			RO	0x0000 0000
0	DBGSS_IF_LOCK_WRDCL	The method: Obtain lock by Read. Following are all s/w operation possibilities: When reading '1' - lock is obtained. (i.e. no debugss request was active during the rd transaction). When reading '0' - lock is not obtained. Try to read again. (i.e. at least debugss request event was active during the rd transaction). when writing '1' - lock will be obtained regardless to debugss request status when writing '0' - lock will be released. Type: Write/Read-Clear			RW	0

:HOST_MCU:DBGSS_IF_LOCK_COND_MASK

Address offset	0x0000 0030
Description	DBGSS Interface Lock Condition Mask
Type	RW

Bits	Field Name	Description			Type	Reset
31:2	RESERVED2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior			RO	0x0000 0000
1	MEM_DBGSS_IF_LOCK_COND_MASK	Masks Debugss Force-active Set 1 - Mask request during lock check. Set 0 - O.W.			RW	0
		0	SET_0 O.W
		1	SET_1 Mask request during lock check
0	RESERVED2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior			RO	0

:HOST_MCU:DBGSS_IF_LOCK_COND_STATUS

Address offset	0x0000 0034
Description	DBGSS Interface Lock Condition Status
Type	RW

Bits	Field Name	Description			Type	Reset
31:2	RESERVED2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior			RO	0x0000 0000
1	DBGSS_HOST_FORCEACTIVE	DBGSS HOST Force Active			RO	0
		Read 0	CLR Not in use
		Read 1	SET Debugss host force active is set
0	DBGSS_HOST_CSYSPWRUPREQ	DBGSS HOST C SYS Power Request			RO	0
		Read 0	CLR Not in use
		Read 1	SET Debugss host c sys power requested