HOST_DMA

This section provides information on the HOST_DMA Module Instance within this product. Each of the registers within the Module Instance is described separately below.

HOST_DMA Registers Mapping Summary

:HOST_DMA Common Register Mapping Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset
CHCTL0	RW	32	0x0000 0000	0x0000 0000
CHCTL0_1	RW	32	0x0000 0000	0x0000 0004
PRIOCFG	RW	32	0x1F0F 0F00	0x0000 0018
CH0STA	RO	32	0x0000 0000	0x0000 1000
CH0TIPTR	RW	32	0x0000 0000	0x0000 1004
CH0OPTR	RW	32	0x0000 0000	0x0000 1008
CH0TCTL	RW	32	0x0000 0000	0x0000 100C
CH0TCTL2	RW	32	0x0000 0000	0x0000 1010
CH0TSTA	RO	32	0x0000 0000	0x0000 1014
CH0JCTL	RW	32	0x0000 0000	0x0000 101C
CH1STA	RO	32	0x0000 0000	0x0000 2000
CH1TIPTR	RW	32	0x0000 0000	0x0000 2004
CH1TOPTR	RW	32	0x0000 0000	0x0000 2008
CH1TCTL	RW	32	0x0000 0000	0x0000 200C
CH1TCTRL2	RW	32	0x0000 0000	0x0000 2010
CH1TSTA	RO	32	0x0000 0000	0x0000 2014
CH1JCTL	RW	32	0x0000 0000	0x0000 201C
CH2STA	RO	32	0x0000 0000	0x0000 3000
CH2TIPTR	RW	32	0x0000 0000	0x0000 3004
CH2TOPTR	RW	32	0x0000 0000	0x0000 3008
CH2TCTL	RW	32	0x0000 0000	0x0000 300C
CH2TCTL2	RW	32	0x0000 0000	0x0000 3010
CH2TSTA	RO	32	0x0000 0000	0x0000 3014
CH2JCTL	RW	32	0x0000 0000	0x0000 301C
CH3STA	RO	32	0x0000 0000	0x0000 4000
CH3TIPTR	RW	32	0x0000 0000	0x0000 4004
CH3TOPTR	RW	32	0x0000 0000	0x0000 4008
CH3TCTL	RW	32	0x0000 0000	0x0000 400C
CH3TCTL2	RW	32	0x0000 0000	0x0000 4010
CH3TSTA	RO	32	0x0000 0000	0x0000 4014
CH3JCTL	RW	32	0x0000 0000	0x0000 401C
CH4STA	RO	32	0x0000 0000	0x0000 5000
CH4TIPTR	RW	32	0x0000 0000	0x0000 5004
CH4TOPTR	RW	32	0x0000 0000	0x0000 5008
CH4TCTL	RW	32	0x0000 0000	0x0000 500C
CH4TCTL2	RW	32	0x0000 0000	0x0000 5010
CH4TSTA	RO	32	0x0000 0000	0x0000 5014
CH4JCTL	RW	32	0x0000 0000	0x0000 501C
CH5STA	RO	32	0x0000 0000	0x0000 6000
CH5TIPTR	RW	32	0x0000 0000	0x0000 6004
CH5TOPTR	RW	32	0x0000 0000	0x0000 6008
CH5TCTL	RW	32	0x0000 0000	0x0000 600C
CH5TCTL2	RW	32	0x0000 0000	0x0000 6010
CH5TSTA	RO	32	0x0000 0000	0x0000 6014
CH5JCTL	RW	32	0x0000 0000	0x0000 601C
CH6STA	RO	32	0x0000 0000	0x0000 7000
CH6TIPTR	RW	32	0x0000 0000	0x0000 7004
CH6TOPTR	RW	32	0x0000 0000	0x0000 7008
CH6TCTL	RW	32	0x0000 0000	0x0000 700C
CH6TCTL2	RW	32	0x0000 0000	0x0000 7010
CH6TSTA	RO	32	0x0000 0000	0x0000 7014
CH6JCTL	RW	32	0x0000 0000	0x0000 701C
CH7STA	RO	32	0x0000 0000	0x0000 8000
CH7TIPTR	RW	32	0x0000 0000	0x0000 8004
CH7TOPTR	RW	32	0x0000 0000	0x0000 8008
CH7TCTL	RW	32	0x0000 0000	0x0000 800C
CH7TCTL2	RW	32	0x0000 0000	0x0000 8010
CH7TSTA	RO	32	0x0000 0000	0x0000 8014
CH7JCTL	RW	32	0x0000 0000	0x0000 801C
CH8STA	RO	32	0x0000 0000	0x0000 9000
CH8TIPTR	RW	32	0x0000 0000	0x0000 9004
CH8TOPTR	RW	32	0x0000 0000	0x0000 9008
CH8TCTL	RW	32	0x0000 0000	0x0000 900C
CH8TCTL2	RW	32	0x0000 0000	0x0000 9010
CH8TSTA	RO	32	0x0000 0000	0x0000 9014
CH8JCTL	RW	32	0x0000 0000	0x0000 901C
CH9STA	RO	32	0x0000 0000	0x0000 A000
CH9TIPTR	RW	32	0x0000 0000	0x0000 A004
CH9TOPTR	RW	32	0x0000 0000	0x0000 A008
CH9TCTL	RW	32	0x0000 0000	0x0000 A00C
CH9TCTL2	RW	32	0x0000 0000	0x0000 A010
CH9TSTA	RO	32	0x0000 0000	0x0000 A014
CH9JCTL	RW	32	0x0000 0000	0x0000 A01C
CH1STA0	RO	32	0x0000 0000	0x0000 B000
CH1TIPTR0	RW	32	0x0000 0000	0x0000 B004
CH1TOPTR0	RW	32	0x0000 0000	0x0000 B008
CH1TCTL0	RW	32	0x0000 0000	0x0000 B00C
CH1TCTRL20	RW	32	0x0000 0000	0x0000 B010
CH1TSTA0	RO	32	0x0000 0000	0x0000 B014
CH1JCTL0	RW	32	0x0000 0000	0x0000 B01C
CH1STA1	RO	32	0x0000 0000	0x0000 C000
CH1TIPTR1	RW	32	0x0000 0000	0x0000 C004
CH1TOPTR1	RW	32	0x0000 0000	0x0000 C008
CH1TCTL1	RW	32	0x0000 0000	0x0000 C00C
CH1TCTRL21	RW	32	0x0000 0000	0x0000 C010
CH1TSTA1	RO	32	0x0000 0000	0x0000 C014
CH1JCTL1	RW	32	0x0000 0000	0x0000 C01C
CH1STA2	RO	32	0x0000 0000	0x0000 D000
CH1TIPTR2	RW	32	0x0000 0000	0x0000 D004
CH1TOPTR2	RW	32	0x0000 0000	0x0000 D008
CH1TCTL2	RW	32	0x0000 0000	0x0000 D00C
CH1TCTRL22	RW	32	0x0000 0000	0x0000 D010
CH1TSTA2	RO	32	0x0000 0000	0x0000 D014
CH1JCTL2	RW	32	0x0000 0000	0x0000 D01C
CH1STA3	RO	32	0x0000 0000	0x0000 E000
CH1TIPTR3	RW	32	0x0000 0000	0x0000 E004
CH1TOPTR3	RW	32	0x0000 0000	0x0000 E008
CH1TCTL3	RW	32	0x0000 0000	0x0000 E00C
CH1TCTRL23	RW	32	0x0000 0000	0x0000 E010
CH1TSTA3	RO	32	0x0000 0000	0x0000 E014
CH1JCTL3	RW	32	0x0000 0000	0x0000 E01C

HOST_DMA Instances Register Mapping Summary

HOST_DMA Register Descriptions

:HOST_DMA Common Register Descriptions

:HOST_DMA:CHCTL0

Address offset	0x0000 0000
Description	Host DMA Channel Controlled by Defined Peripheral. The value of each fields concats with [HOST_DMA:JOBCTLCHx.SRCDSTCFG] (when x is channel num) if [CHCTL0.CHx] = 4 and [JOBCTLCHx.SRCDSTCFG] = 1 (value = 0100_1 = 9) then flow control signals of channel x are connected to periph number 9 flow control signals Note: [CHCTL0.CHx] = 0xF is forbidden. This configuration should be only used for Dynamic Switch
Type	RW

Bits	Field Name	Description		Type	Reset
31:28	CH7	Channel 7 Control. Flow control signals: 25 UART2 TX 24 UART2 RX 23 HIF TX 22 HIF RX 21 Not Valid - PDM has only read 20 PDM 19 Not Valid - ADC has only read 18 ADC 17 MCAN TX 16 MCAN RX 15 SDIO TX 14 SDIO RX 13 SDMMC TX 12 SDMMC RX 11 I2C1 TX 10 I2C1 RX 9 I2C0 TX 8 I2C0 RX 7 SPI1 TX 6 SPI1 RX 5 SPI0 TX 4 SPI0 RX 3 UART1 TX 2 UART1 RX 1 UART0 TX 0 UART0 RX		RW	0x0
		0x0	UART0 UART0 peripheral
		0x1	UART1 UART1 peripheral
		0x2	SPIO SPI0 peripheral
		0x3	SPI1 SPI1 peripheral
		0x4	I2C0 I2C0 peripheral
		0x5	I2C1 I2C1 peripheral
		0x6	SDMMC SDMMC peripheral
		0x7	SDIO SDIO peripheral
		0x8	MCAN MCAN peripheral
		0x9	ADC ADC peripheral
		0xA	PDM PDM peripheral
		0xB	HIF HIF peripheral
		0xC	UART2 UART2 peripheral
27:24	CH6	Channel 6 Control. Flow control signals: 25 UART2 TX 24 UART2 RX 23 HIF TX 22 HIF RX 21 Not Valid - PDM has only read 20 PDM 19 Not Valid - ADC has only read 18 ADC 17 MCAN TX 16 MCAN RX 15 SDIO TX 14 SDIO RX 13 SDMMC TX 12 SDMMC RX 11 I2C1 TX 10 I2C1 RX 9 I2C0 TX 8 I2C0 RX 7 SPI1 TX 6 SPI1 RX 5 SPI0 TX 4 SPI0 RX 3 UART1 TX 2 UART1 RX 1 UART0 TX 0 UART0 RX		RW	0x0
		0x0	UART0 UART0 peripheral
		0x1	UART1 UART1 peripheral
		0x2	SPIO SPI0 peripheral
		0x3	SPI1 SPI1 peripheral
		0x4	I2C0 I2C0 peripheral
		0x5	I2C1 I2C1 peripheral
		0x6	SDMMC SDMMC peripheral
		0x7	SDIO SDIO peripheral
		0x8	MCAN MCAN peripheral
		0x9	ADC ADC peripheral
		0xA	PDM PDM peripheral
		0xB	HIF HIF peripheral
		0xC	UART2 UART2 peripheral
23:20	CH5	Channel 5 Control. Flow control signals: 25 UART2 TX 24 UART2 RX 23 HIF TX 22 HIF RX 21 Not Valid - PDM has only read 20 PDM 19 Not Valid - ADC has only read 18 ADC 17 MCAN TX 16 MCAN RX 15 SDIO TX 14 SDIO RX 13 SDMMC TX 12 SDMMC RX 11 I2C1 TX 10 I2C1 RX 9 I2C0 TX 8 I2C0 RX 7 SPI1 TX 6 SPI1 RX 5 SPI0 TX 4 SPI0 RX 3 UART1 TX 2 UART1 RX 1 UART0 TX 0 UART0 RX		RW	0x0
		0x0	UART0 UART0 peripheral
		0x1	UART1 UART1 peripheral
		0x2	SPIO SPI0 peripheral
		0x3	SPI1 SPI1 peripheral
		0x4	I2C0 I2C0 peripheral
		0x5	I2C1 I2C1 peripheral
		0x6	SDMMC SDMMC peripheral
		0x7	SDIO SDIO peripheral
		0x8	MCAN MCAN peripheral
		0x9	ADC ADC peripheral
		0xA	PDM PDM peripheral
		0xB	HIF HIF peripheral
		0xC	UART2 UART2 peripheral
19:16	CH4	Channel 4 Control. Flow control signals: 25 UART2 TX 24 UART2 RX 23 HIF TX 22 HIF RX 21 Not Valid - PDM has only read 20 PDM 19 Not Valid - ADC has only read 18 ADC 17 MCAN TX 16 MCAN RX 15 SDIO TX 14 SDIO RX 13 SDMMC TX 12 SDMMC RX 11 I2C1 TX 10 I2C1 RX 9 I2C0 TX 8 I2C0 RX 7 SPI1 TX 6 SPI1 RX 5 SPI0 TX 4 SPI0 RX 3 UART1 TX 2 UART1 RX 1 UART0 TX 0 UART0 RX		RW	0x0
		0x0	UART0 UART0 peripheral
		0x1	UART1 UART1 peripheral
		0x2	SPIO SPI0 peripheral
		0x3	SPI1 SPI1 peripheral
		0x4	I2C0 I2C0 peripheral
		0x5	I2C1 I2C1 peripheral
		0x6	SDMMC SDMMC peripheral
		0x7	SDIO SDIO peripheral
		0x8	MCAN MCAN peripheral
		0x9	ADC ADC peripheral
		0xA	PDM PDM peripheral
		0xB	HIF HIF peripheral
		0xC	UART2 UART2 peripheral
15:12	CH3	Channel 3 Control. Flow control signals: 25 UART2 TX 24 UART2 RX 23 HIF TX 22 HIF RX 21 Not Valid - PDM has only read 20 PDM 19 Not Valid - ADC has only read 18 ADC 17 MCAN TX 16 MCAN RX 15 SDIO TX 14 SDIO RX 13 SDMMC TX 12 SDMMC RX 11 I2C1 TX 10 I2C1 RX 9 I2C0 TX 8 I2C0 RX 7 SPI1 TX 6 SPI1 RX 5 SPI0 TX 4 SPI0 RX 3 UART1 TX 2 UART1 RX 1 UART0 TX 0 UART0 RX		RW	0x0
		0x0	UART0 UART0 peripheral
		0x1	UART1 UART1 peripheral
		0x2	SPIO SPI0 peripheral
		0x3	SPI1 SPI1 peripheral
		0x4	I2C0 I2C0 peripheral
		0x5	I2C1 I2C1 peripheral
		0x6	SDMMC SDMMC peripheral
		0x7	SDIO SDIO peripheral
		0x8	MCAN MCAN peripheral
		0x9	ADC ADC peripheral
		0xA	PDM PDM peripheral
		0xB	HIF HIF peripheral
		0xC	UART2 UART2 peripheral
11:8	CH2	Channel 2 Control. Flow control signals: 25 UART2 TX 24 UART2 RX 23 HIF TX 22 HIF RX 21 Not Valid - PDM has only read 20 PDM 19 Not Valid - ADC has only read 18 ADC 17 MCAN TX 16 MCAN RX 15 SDIO TX 14 SDIO RX 13 SDMMC TX 12 SDMMC RX 11 I2C1 TX 10 I2C1 RX 9 I2C0 TX 8 I2C0 RX 7 SPI1 TX 6 SPI1 RX 5 SPI0 TX 4 SPI0 RX 3 UART1 TX 2 UART1 RX 1 UART0 TX 0 UART0 RX		RW	0x0
		0x0	UART0 UART0 peripheral
		0x1	UART1 UART1 peripheral
		0x2	SPIO SPI0 peripheral
		0x3	SPI1 SPI1 peripheral
		0x4	I2C0 I2C0 peripheral
		0x5	I2C1 I2C1 peripheral
		0x6	SDMMC SDMMC peripheral
		0x7	SDIO SDIO peripheral
		0x8	MCAN MCAN peripheral
		0x9	ADC ADC peripheral
		0xA	PDM PDM peripheral
		0xB	HIF HIF peripheral
		0xC	UART2 UART2 peripheral
7:4	CH1	Channel 1 Control. Flow control signals: 25 UART2 TX 24 UART2 RX 23 HIF TX 22 HIF RX 21 Not Valid - PDM has only read 20 PDM 19 Not Valid - ADC has only read 18 ADC 17 MCAN TX 16 MCAN RX 15 SDIO TX 14 SDIO RX 13 SDMMC TX 12 SDMMC RX 11 I2C1 TX 10 I2C1 RX 9 I2C0 TX 8 I2C0 RX 7 SPI1 TX 6 SPI1 RX 5 SPI0 TX 4 SPI0 RX 3 UART1 TX 2 UART1 RX 1 UART0 TX 0 UART0 RX		RW	0x0
		0x0	UART0 UART0 peripheral
		0x1	UART1 UART1 peripheral
		0x2	SPIO SPI0 peripheral
		0x3	SPI1 SPI1 peripheral
		0x4	I2C0 I2C0 peripheral
		0x5	I2C1 I2C1 peripheral
		0x6	SDMMC SDMMC peripheral
		0x7	SDIO SDIO peripheral
		0x8	MCAN MCAN peripheral
		0x9	ADC ADC peripheral
		0xA	PDM PDM peripheral
		0xB	HIF HIF peripheral
		0xC	UART2 UART2 peripheral
3:0	CH0	Channel 0 Control. Flow control signals: 25 UART2 TX 24 UART2 RX 23 HIF TX 22 HIF RX 21 Not Valid - PDM has only read 20 PDM 19 Not Valid - ADC has only read 18 ADC 17 MCAN TX 16 MCAN RX 15 SDIO TX 14 SDIO RX 13 SDMMC TX 12 SDMMC RX 11 I2C1 TX 10 I2C1 RX 9 I2C0 TX 8 I2C0 RX 7 SPI1 TX 6 SPI1 RX 5 SPI0 TX 4 SPI0 RX 3 UART1 TX 2 UART1 RX 1 UART0 TX 0 UART0 RX		RW	0x0
		0x0	UART0 UART0 peripheral
		0x1	UART1 UART1 peripheral
		0x2	SPIO SPI0 peripheral
		0x3	SPI1 SPI1 peripheral
		0x4	I2C0 I2C0 peripheral
		0x5	I2C1 I2C1 peripheral
		0x6	SDMMC SDMMC peripheral
		0x7	SDIO SDIO peripheral
		0x8	MCAN MCAN peripheral
		0x9	ADC ADC peripheral
		0xA	PDM PDM peripheral
		0xB	HIF HIF peripheral
		0xC	UART2 UART2 peripheral

:HOST_DMA:CHCTL0_1

Address offset	0x0000 0004
Description	Host DMA Channel Controlled by Defined Peripheral. The value of each fields concats with [HOST_DMA:JOBCTLCHx.SRCDSTCFG] (when x is channel num) if [CHCTL1.CHx] = 4 and [JOBCTLCHx.SRCDSTCFG] = 1 (value = 0100_1 = 9) then flow control signals of channel x are connected to periph number 9 flow control signals Note: [CHCTL0.CHx] = 0xF is forbidden. This configuration should be only used for Dynamic Switch
Type	RW

Bits	Field Name	Description		Type	Reset
31:24	Reserved			RO	0x00
23:20	CH13	Channel 13 Control. Flow control signals: 25 UART2 TX 24 UART2 RX 23 HIF TX 22 HIF RX 21 Not Valid - PDM has only read 20 PDM 19 Not Valid - ADC has only read 18 ADC 17 MCAN TX 16 MCAN RX 15 SDIO TX 14 SDIO RX 13 SDMMC TX 12 SDMMC RX 11 I2C1 TX 10 I2C1 RX 9 I2C0 TX 8 I2C0 RX 7 SPI1 TX 6 SPI1 RX 5 SPI0 TX 4 SPI0 RX 3 UART1 TX 2 UART1 RX 1 UART0 TX 0 UART0 RX		RW	0x0
		0x0	UART0 UART0 peripheral
		0x1	UART1 UART1 peripheral
		0x2	SPIO SPI0 peripheral
		0x3	SPI1 SPI1 peripheral
		0x4	I2C0 I2C0 peripheral
		0x5	I2C1 I2C1 peripheral
		0x6	SDMMC SDMMC peripheral
		0x7	SDIO SDIO peripheral
		0x8	MCAN MCAN peripheral
		0x9	ADC ADC peripheral
		0xA	PDM PDM peripheral
		0xB	HIF HIF peripheral
		0xC	UART2 UART2 peripheral
19:16	CH12	Channel 12 Control. Flow control signals: 25 UART2 TX 24 UART2 RX 23 HIF TX 22 HIF RX 21 Not Valid - PDM has only read 20 PDM 19 Not Valid - ADC has only read 18 ADC 17 MCAN TX 16 MCAN RX 15 SDIO TX 14 SDIO RX 13 SDMMC TX 12 SDMMC RX 11 I2C1 TX 10 I2C1 RX 9 I2C0 TX 8 I2C0 RX 7 SPI1 TX 6 SPI1 RX 5 SPI0 TX 4 SPI0 RX 3 UART1 TX 2 UART1 RX 1 UART0 TX 0 UART0 RX		RW	0x0
		0x0	UART0 UART0 peripheral
		0x1	UART1 UART1 peripheral
		0x2	SPIO SPI0 peripheral
		0x3	SPI1 SPI1 peripheral
		0x4	I2C0 I2C0 peripheral
		0x5	I2C1 I2C1 peripheral
		0x6	SDMMC SDMMC peripheral
		0x7	SDIO SDIO peripheral
		0x8	MCAN MCAN peripheral
		0x9	ADC ADC peripheral
		0xA	PDM PDM peripheral
		0xB	HIF HIF peripheral
		0xC	UART2 UART2 peripheral
15:12	CH11	Channel 11 Control. Flow control signals: 25 UART2 TX 24 UART2 RX 23 HIF TX 22 HIF RX 21 Not Valid - PDM has only read 20 PDM 19 Not Valid - ADC has only read 18 ADC 17 MCAN TX 16 MCAN RX 15 SDIO TX 14 SDIO RX 13 SDMMC TX 12 SDMMC RX 11 I2C1 TX 10 I2C1 RX 9 I2C0 TX 8 I2C0 RX 7 SPI1 TX 6 SPI1 RX 5 SPI0 TX 4 SPI0 RX 3 UART1 TX 2 UART1 RX 1 UART0 TX 0 UART0 RX		RW	0x0
		0x0	UART0 UART0 peripheral
		0x1	UART1 UART1 peripheral
		0x2	SPIO SPI0 peripheral
		0x3	SPI1 SPI1 peripheral
		0x4	I2C0 I2C0 peripheral
		0x5	I2C1 I2C1 peripheral
		0x6	SDMMC SDMMC peripheral
		0x7	SDIO SDIO peripheral
		0x8	MCAN MCAN peripheral
		0x9	ADC ADC peripheral
		0xA	PDM PDM peripheral
		0xB	HIF HIF peripheral
		0xC	UART2 UART2 peripheral
11:8	CH10	Channel 10 Control. Flow control signals: 25 UART2 TX 24 UART2 RX 23 HIF TX 22 HIF RX 21 Not Valid - PDM has only read 20 PDM 19 Not Valid - ADC has only read 18 ADC 17 MCAN TX 16 MCAN RX 15 SDIO TX 14 SDIO RX 13 SDMMC TX 12 SDMMC RX 11 I2C1 TX 10 I2C1 RX 9 I2C0 TX 8 I2C0 RX 7 SPI1 TX 6 SPI1 RX 5 SPI0 TX 4 SPI0 RX 3 UART1 TX 2 UART1 RX 1 UART0 TX 0 UART0 RX		RW	0x0
		0x0	UART0 UART0 peripheral
		0x1	UART1 UART1 peripheral
		0x2	SPIO SPI0 peripheral
		0x3	SPI1 SPI1 peripheral
		0x4	I2C0 I2C0 peripheral
		0x5	I2C1 I2C1 peripheral
		0x6	SDMMC SDMMC peripheral
		0x7	SDIO SDIO peripheral
		0x8	MCAN MCAN peripheral
		0x9	ADC ADC peripheral
		0xA	PDM PDM peripheral
		0xB	HIF HIF peripheral
		0xC	UART2 UART2 peripheral
7:4	CH9	Channel 9 Control. Flow control signals: 25 UART2 TX 24 UART2 RX 23 HIF TX 22 HIF RX 21 Not Valid - PDM has only read 20 PDM 19 Not Valid - ADC has only read 18 ADC 17 MCAN TX 16 MCAN RX 15 SDIO TX 14 SDIO RX 13 SDMMC TX 12 SDMMC RX 11 I2C1 TX 10 I2C1 RX 9 I2C0 TX 8 I2C0 RX 7 SPI1 TX 6 SPI1 RX 5 SPI0 TX 4 SPI0 RX 3 UART1 TX 2 UART1 RX 1 UART0 TX 0 UART0 RX		RW	0x0
		0x0	UART0 UART0 peripheral
		0x1	UART1 UART1 peripheral
		0x2	SPIO SPI0 peripheral
		0x3	SPI1 SPI1 peripheral
		0x4	I2C0 I2C0 peripheral
		0x5	I2C1 I2C1 peripheral
		0x6	SDMMC SDMMC peripheral
		0x7	SDIO SDIO peripheral
		0x8	MCAN MCAN peripheral
		0x9	ADC ADC peripheral
		0xA	PDM PDM peripheral
		0xB	HIF HIF peripheral
		0xC	UART2 UART2 peripheral
3:0	CH8	Channel 8 Control. Flow control signals: 25 UART2 TX 24 UART2 RX 23 HIF TX 22 HIF RX 21 Not Valid - PDM has only read 20 PDM 19 Not Valid - ADC has only read 18 ADC 17 MCAN TX 16 MCAN RX 15 SDIO TX 14 SDIO RX 13 SDMMC TX 12 SDMMC RX 11 I2C1 TX 10 I2C1 RX 9 I2C0 TX 8 I2C0 RX 7 SPI1 TX 6 SPI1 RX 5 SPI0 TX 4 SPI0 RX 3 UART1 TX 2 UART1 RX 1 UART0 TX 0 UART0 RX		RW	0x0
		0x0	UART0 UART0 peripheral
		0x1	UART1 UART1 peripheral
		0x2	SPIO SPI0 peripheral
		0x3	SPI1 SPI1 peripheral
		0x4	I2C0 I2C0 peripheral
		0x5	I2C1 I2C1 peripheral
		0x6	SDMMC SDMMC peripheral
		0x7	SDIO SDIO peripheral
		0x8	MCAN MCAN peripheral
		0x9	ADC ADC peripheral
		0xA	PDM PDM peripheral
		0xB	HIF HIF peripheral
		0xC	UART2 UART2 peripheral

:HOST_DMA:PRIOCFG

Address offset	0x0000 0018
Description	Priority Channel Configuration.
Type	RW

Bits	Field Name	Description	Type	Reset
31:29	Reserved		RO	0x0
28:24	MAXBLOCKS	Maximum consecutive priority blocks. Maximum consecutive block transactions of "priority channels" . After this number of consecutive blocks one of "roubd robin" channels will win arbitration. 31 means there is no limitation on number of consecutive priority blocks	RW	0x1F
23:20	Reserved		RO	0x0
19:16	CH2ND	Second priority channel. channel with second highest prioriry	RW	0xF
15:12	Reserved		RO	0x0
11:8	CH1ST	First priority channel. channel with highest prioriry	RW	0xF
7:1	Reserved		RO	0x00
0	PRIOEN	Enable priority channel. Enable one channel to be prioritize - no round rubin would be done	RW	0

:HOST_DMA:CH0STA

Address offset	0x0000 1000
Description	Channel Status FSM state and run indication.
Type	RO

Bits	Field Name	Description	Type	Reset
31:17	Reserved		RO	0x0000
16	RUN	Indication that channel is currently transfering data and is not idle. Channels that are waiting on arbitration are considered running.	RO	0
15:12	Reserved		RO	0x0
11:8	FSMSTATE	FSM state: 0x0. IDLE 0x2. EXCEPTION 0x3. DRAIN 0x4. ABORT 0x8. PENDING ARB 0x9. COPY 0xA. COPY LAST 0xC. DONE 0xD. SAVE CTX 0xE. WAIT NEXT TRANS 0xF. LAST	RO	0x0
7:3	Reserved		RO	0x00
2:0	HWEVENT	HW event status. Channel status is a bit mask. Multiple bits can be set at the same time 0. PROCESSING 1. TRANS DONE 2. ABORT 4. EXCEPTION	RO	0x0

:HOST_DMA:CH0TIPTR

Address offset	0x0000 1004
Description	Input Pointer Channel Transaction. 32 bit address pointer of channel current input.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	IPTR	Transaction input pointer. 32 bit address pointer of channel current input.			RW	0x0000 0000

:HOST_DMA:CH0OPTR

Address offset	0x0000 1008
Description	Output Pointer Channel Transaction. 32 bit address pointer of channel current output.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	OPTR	Transaction output pointer. 32 bit address pointer of channel current output.			RW	0x0000 0000

:HOST_DMA:CH0TCTL

Address offset	0x0000 100C
Description	Transaction control
Type	RW

Bits	Field Name	Description	Type	Reset
31:26	Reserved		RO	0x00
25:24	ENDIANESS	0 -no endianess, 1 - byte endianess, 2 - bit endianess	RW	0x0
23:18	Reserved		RO	0x00
17	SPARE	spare	RW	0
16	BURSTREQ	Use burst request. In case number of words to tranfer smaller than block size, DMA would use signle request and work with block size of 1 word. In case we know request would be set on altough number of words to tranfer is smaller than block size, we can set this field on and DMA will wait for block_request and transact all remaining words in one block.	RW	0
15:14	Reserved		RO	0x0
13:0	TRANSB	Transaction bytes number. Number of bytes of the transaction to move from source to destination.	RW	0x0000

:HOST_DMA:CH0TCTL2

Address offset	0x0000 1010
Description	DMA command interface
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2:0	CMD	1 - run command. Start a transaction. 2- abort command - stop reansaction. 4- init command - init new transaction afet abort/error. Type:Write-Clear.	WO	0x0

:HOST_DMA:CH0TSTA

Address offset	0x0000 1014
Description	Transaction Status. Job completion reason - either last transaction or exception
Type	RO

Bits	Field Name	Description	Type	Reset
31:30	Reserved		RO	0x0
29:16	REMAINB	Remain bytes number. Number of bytes remaining to complete the transaction.	RO	0x0000
15:8	OFFSET	Word offset. Offset in words from block boundary. Actually number of word have been transferred in this block	RO	0x00
7:1	Reserved		RO	0x00
0	STA	channel OCP rstatus recieved at one of the primary ports. Once an error is encountered the channel will enter an Exception state and stay the until an init command is recieved. ICLR does not affect this status.	RO	0

:HOST_DMA:CH0JCTL

Address offset	0x0000 101C
Description	Job control register
Type	RW

Bits	Field Name	Description	Type	Reset
31	Reserved		RO	0
30	ENCLR	Enable DMA to set a rd/wr clear pulse at the beginning of a job (one cycle after run cmd)	RW	0
29	SRCDSTCFG	0 - Sorce is periph: transaction from periph to memory. 1 - Destination is periph :transaction from Memory to periph	RW	0
28	FIFOMODD	Destination pointer fifo mode	RW	0
27	FIFOMODS	Source pointer fifo mode	RW	0
26	DMASIGBPS	Tie high channel DMA req signal. This is useful for memory to memort transaction	RW	0
25	BLKMODEDST	Destination pointer wrap around mode 0: no wrap around(non block mode) 1: with wrap around(block mode)	RW	0
24	BLKMODESRC	source pointer wrap around mode 0: no wrap around(non block mode) 1: with wrap around(block mode)	RW	0
23:22	Reserved		RO	0x0
21:16	BLKSIZE	size of the block in words. If block mode is enabled, defines the address wrap around. Since channel arbitration decisions are made every block, this also effect how much bandwidth is given to a specific channel.	RW	0x00
15:2	Reserved		RO	0x0000
1:0	WORDSIZE	00 -word size is 32 bits 01 -word size is 16 bits 10 -word size is 8 bits	RW	0x0

:HOST_DMA:CH1STA

Address offset	0x0000 2000
Description	Channel Status FSM state and run indication.
Type	RO

Bits	Field Name	Description	Type	Reset
31:17	Reserved		RO	0x0000
16	RUN	Indication that channel is currently transfering data and is not idle. Channels that are waiting on arbitration are considered running.	RO	0
15:12	Reserved		RO	0x0
11:8	FSMSTATE	FSM state: 0x0. IDLE 0x2. EXCEPTION 0x3. DRAIN 0x4. ABORT 0x8. PENDING ARB 0x9. COPY 0xA. COPY LAST 0xC. DONE 0xD. SAVE CTX 0xE. WAIT NEXT TRANS 0xF. LAST	RO	0x0
7:3	Reserved		RO	0x00
2:0	HWEVENT	HW event status. Channel status is a bit mask. Multiple bits can be set at the same time 0. PROCESSING 1. TRANS DONE 2. ABORT 4. EXCEPTION	RO	0x0

:HOST_DMA:CH1TIPTR

Address offset	0x0000 2004
Description	32 bit address pointer of channel current input.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	IPTR	32 bit address pointer of channel current input.			RW	0x0000 0000

:HOST_DMA:CH1TOPTR

Address offset	0x0000 2008
Description	32 bit address pointer of channel current output.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	OPTR	32 bit address pointer of channel current output.			RW	0x0000 0000

:HOST_DMA:CH1TCTL

Address offset	0x0000 200C
Description	Transaction control
Type	RW

Bits	Field Name	Description	Type	Reset
31:26	Reserved		RO	0x00
25:24	ENDIANESS	0 -no endianess, 1 - byte endianess, 2 - bit endianess	RW	0x0
23:18	Reserved		RO	0x00
17	SPARE	spare	RW	0
16	BURSTREQ	In case number of words to tranfer smaller than block size, DMA would use signle request and work with block size of 1 word. In case we know request would be set on altough number of words to tranfer is smaller than block size, we can set this field on and DMA will wait for block_request and transact all remaining words in one block.	RW	0
15:14	Reserved		RO	0x0
13:0	TRANSB	Number of bytes of the transaction to move from source to destination.	RW	0x0000

:HOST_DMA:CH1TCTRL2

Address offset	0x0000 2010
Description	DMA command interface
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2:0	CMD	1 - run command. Start a transaction. 2- abort command - stop reansaction. 4- init command - init new transaction afet abort/error.	WO	0x0

:HOST_DMA:CH1TSTA

Address offset	0x0000 2014
Description	Job completion reason - either last transaction or exception
Type	RO

Bits	Field Name	Description	Type	Reset
31:30	Reserved		RO	0x0
29:16	REMAINB	Number of bytes remaining to complete the transaction.	RO	0x0000
15:8	OFFSET	Offset in words from block boundary. Actually number of word have been transferred in this block	RO	0x00
7:1	Reserved		RO	0x00
0	STA	channel OCP rstatus recieved at one of the primary ports. Once an error is encountered the channel will enter an Exception state and stay the until an init command is recieved. ICLR does not affect this status.	RO	0

:HOST_DMA:CH1JCTL

Address offset	0x0000 201C
Description	Job control register
Type	RW

Bits	Field Name	Description	Type	Reset
31	Reserved		RO	0
30	ENCLR	Enable DMA to set a rd/wr clear pulse at the beginning of a job (one cycle after run cmd)	RW	0
29	SRCDSTCFG	0 - Sorce is periph: transaction from periph to memory. 1 - Destination is periph :transaction from Memory to periph	RW	0
28	FIFOMODD	Destination pointer fifo mode	RW	0
27	FIFOMODS	Source pointer fifo mode	RW	0
26	DMASIGBPS	Tie high channel DMA req signal. This is useful for memory to memort transaction	RW	0
25	BLKMODEDST	Destination pointer wrap around mode 0: no wrap around(non block mode) 1: with wrap around(block mode)	RW	0
24	BLKMODESRC	source pointer wrap around mode 0: no wrap around(non block mode) 1: with wrap around(block mode)	RW	0
23:22	Reserved		RO	0x0
21:16	BLKSIZE	size of the block in words. If block mode is enabled, defines the address wrap around. Since channel arbitration decisions are made every block, this also effect how much bandwidth is given to a specific channel.	RW	0x00
15:2	Reserved		RO	0x0000
1:0	WORDSIZE	00 -word size is 32 bits 01 -word size is 16 bits 10 -word size is 8 bits	RW	0x0

:HOST_DMA:CH2STA

Address offset	0x0000 3000
Description	Channel Status FSM state and run indication.
Type	RO

Bits	Field Name	Description	Type	Reset
31:17	Reserved		RO	0x0000
16	RUN	Indication that channel is currently transfering data and is not idle. Channels that are waiting on arbitration are considered running.	RO	0
15:12	Reserved		RO	0x0
11:8	FSMSTATE	FSM state: 0x0. IDLE 0x2. EXCEPTION 0x3. DRAIN 0x4. ABORT 0x8. PENDING ARB 0x9. COPY 0xA. COPY LAST 0xC. DONE 0xD. SAVE CTX 0xE. WAIT NEXT TRANS 0xF. LAST	RO	0x0
7:3	Reserved		RO	0x00
2:0	HWEVENT	HW event status. Channel status is a bit mask. Multiple bits can be set at the same time 0. PROCESSING 1. TRANS DONE 2. ABORT 4. EXCEPTION	RO	0x0

:HOST_DMA:CH2TIPTR

Address offset	0x0000 3004
Description	32 bit address pointer of channel current input.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	IPTR	32 bit address pointer of channel current input.			RW	0x0000 0000

:HOST_DMA:CH2TOPTR

Address offset	0x0000 3008
Description	32 bit address pointer of channel current output.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	OPTR	32 bit address pointer of channel current output.			RW	0x0000 0000

:HOST_DMA:CH2TCTL

Address offset	0x0000 300C
Description	Transaction control
Type	RW

Bits	Field Name	Description	Type	Reset
31:26	Reserved		RO	0x00
25:24	ENDIANESS	0 -no endianess, 1 - byte endianess, 2 - bit endianess	RW	0x0
23:18	Reserved		RO	0x00
17	SPARE	spare	RW	0
16	BURSTREQ	In case number of words to tranfer smaller than block size, DMA would use signle request and work with block size of 1 word. In case we know request would be set on altough number of words to tranfer is smaller than block size, we can set this field on and DMA will wait for block_request and transact all remaining words in one block.	RW	0
15:14	Reserved		RO	0x0
13:0	TRANSB	Number of bytes of the transaction to move from source to destination.	RW	0x0000

:HOST_DMA:CH2TCTL2

Address offset	0x0000 3010
Description	DMA command interface
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2:0	CMD	1 - run command. Start a transaction. 2- abort command - stop reansaction. 4- init command - init new transaction afet abort/error.	WO	0x0

:HOST_DMA:CH2TSTA

Address offset	0x0000 3014
Description	Job completion reason - either last transaction or exception
Type	RO

Bits	Field Name	Description	Type	Reset
31:30	Reserved		RO	0x0
29:16	REMAINB	Number of bytes remaining to complete the transaction.	RO	0x0000
15:8	OFFSET	Offset in words from block boundary. Actually number of word have been transferred in this block	RO	0x00
7:1	Reserved		RO	0x00
0	STA	channel OCP rstatus recieved at one of the primary ports. Once an error is encountered the channel will enter an Exception state and stay the until an init command is recieved. ICLR does not affect this status.	RO	0

:HOST_DMA:CH2JCTL

Address offset	0x0000 301C
Description	Job control register
Type	RW

Bits	Field Name	Description	Type	Reset
31	Reserved		RO	0
30	ENCLR	Enable DMA to set a rd/wr clear pulse at the beginning of a job (one cycle after run cmd)	RW	0
29	SRCDSTCFG	0 - Sorce is periph: transaction from periph to memory. 1 - Destination is periph :transaction from Memory to periph	RW	0
28	FIFOMODD	Destination pointer fifo mode	RW	0
27	FIFOMODS	Source pointer fifo mode	RW	0
26	DMASIGBPS	Tie high channel DMA req signal. This is useful for memory to memort transaction	RW	0
25:22	Reserved		RO	0x0
21:16	BLKSIZE	size of the block in words. If block mode is enabled, defines the address wrap around. Since channel arbitration decisions are made every block, this also effect how much bandwidth is given to a specific channel.	RW	0x00
15:2	Reserved		RO	0x0000
1:0	WORDSIZE	00 -word size is 32 bits 01 -word size is 16 bits 10 -word size is 8 bits	RW	0x0

:HOST_DMA:CH3STA

Address offset	0x0000 4000
Description	Channel Status FSM state and run indication.
Type	RO

Bits	Field Name	Description	Type	Reset
31:17	Reserved		RO	0x0000
16	RUN	Indication that channel is currently transfering data and is not idle. Channels that are waiting on arbitration are considered running.	RO	0
15:12	Reserved		RO	0x0
11:8	FSMSTATE	FSM state: 0x0. IDLE 0x2. EXCEPTION 0x3. DRAIN 0x4. ABORT 0x8. PENDING ARB 0x9. COPY 0xA. COPY LAST 0xC. DONE 0xD. SAVE CTX 0xE. WAIT NEXT TRANS 0xF. LAST	RO	0x0
7:3	Reserved		RO	0x00
2:0	HWEVENT	HW event status. Channel status is a bit mask. Multiple bits can be set at the same time 0. PROCESSING 1. TRANS DONE 2. ABORT 4. EXCEPTION	RO	0x0

:HOST_DMA:CH3TIPTR

Address offset	0x0000 4004
Description	32 bit address pointer of channel current input.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	IPTR	32 bit address pointer of channel current input.			RW	0x0000 0000

:HOST_DMA:CH3TOPTR

Address offset	0x0000 4008
Description	32 bit address pointer of channel current output.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	OPTR	32 bit address pointer of channel current output.			RW	0x0000 0000

:HOST_DMA:CH3TCTL

Address offset	0x0000 400C
Description	Transaction control
Type	RW

Bits	Field Name	Description	Type	Reset
31:26	Reserved		RO	0x00
25:24	ENDIANESS	0 -no endianess, 1 - byte endianess, 2 - bit endianess	RW	0x0
23:18	Reserved		RO	0x00
17	SPARE	spare	RW	0
16	BURSTREQ	In case number of words to tranfer smaller than block size, DMA would use signle request and work with block size of 1 word. In case we know request would be set on altough number of words to tranfer is smaller than block size, we can set this field on and DMA will wait for block_request and transact all remaining words in one block.	RW	0
15:14	Reserved		RO	0x0
13:0	TRANSB	Number of bytes of the transaction to move from source to destination.	RW	0x0000

:HOST_DMA:CH3TCTL2

Address offset	0x0000 4010
Description	DMA command interface
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2:0	CMD	1 - run command. Start a transaction. 2- abort command - stop reansaction. 4- init command - init new transaction afet abort/error.	WO	0x0

:HOST_DMA:CH3TSTA

Address offset	0x0000 4014
Description	Job completion reason - either last transaction or exception
Type	RO

Bits	Field Name	Description	Type	Reset
31:30	Reserved		RO	0x0
29:16	REMAINB	Number of bytes remaining to complete the transaction.	RO	0x0000
15:8	OFFSET	Offset in words from block boundary. Actually number of word have been transferred in this block	RO	0x00
7:1	Reserved		RO	0x00
0	STA	channel OCP rstatus recieved at one of the primary ports. Once an error is encountered the channel will enter an Exception state and stay the until an init command is recieved. ICLR does not affect this status.	RO	0

:HOST_DMA:CH3JCTL

Address offset	0x0000 401C
Description	Job control register
Type	RW

Bits	Field Name	Description	Type	Reset
31	Reserved		RO	0
30	ENCLR	Enable DMA to set a rd/wr clear pulse at the beginning of a job (one cycle after run cmd)	RW	0
29	SRCDSTCFG	0 - Sorce is periph: transaction from periph to memory. 1 - Destination is periph :transaction from Memory to periph	RW	0
28	FIFOMODD	Destination pointer fifo mode	RW	0
27	FIFOMODS	Source pointer fifo mode	RW	0
26	DMASIGBPS	Tie high channel DMA req signal. This is useful for memory to memort transaction	RW	0
25:22	Reserved		RO	0x0
21:16	BLKSIZE	size of the block in words. If block mode is enabled, defines the address wrap around. Since channel arbitration decisions are made every block, this also effect how much bandwidth is given to a specific channel.	RW	0x00
15:2	Reserved		RO	0x0000
1:0	WORDSIZE	00 -word size is 32 bits 01 -word size is 16 bits 10 -word size is 8 bits	RW	0x0

:HOST_DMA:CH4STA

Address offset	0x0000 5000
Description	Channel Status FSM state and run indication.
Type	RO

Bits	Field Name	Description	Type	Reset
31:17	Reserved		RO	0x0000
16	RUN	Indication that channel is currently transfering data and is not idle. Channels that are waiting on arbitration are considered running.	RO	0
15:12	Reserved		RO	0x0
11:8	FSMSTATE	FSM state: 0x0. IDLE 0x2. EXCEPTION 0x3. DRAIN 0x4. ABORT 0x8. PENDING ARB 0x9. COPY 0xA. COPY LAST 0xC. DONE 0xD. SAVE CTX 0xE. WAIT NEXT TRANS 0xF. LAST	RO	0x0
7:3	Reserved		RO	0x00
2:0	HWEVENT	HW event status. Channel status is a bit mask. Multiple bits can be set at the same time 0. PROCESSING 1. TRANS DONE 2. ABORT 4. EXCEPTION	RO	0x0

:HOST_DMA:CH4TIPTR

Address offset	0x0000 5004
Description	32 bit address pointer of channel current input.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	INPTR	32 bit address pointer of channel current input.			RW	0x0000 0000

:HOST_DMA:CH4TOPTR

Address offset	0x0000 5008
Description	32 bit address pointer of channel current output.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	OPTR	32 bit address pointer of channel current output.			RW	0x0000 0000

:HOST_DMA:CH4TCTL

Address offset	0x0000 500C
Description	Transaction control
Type	RW

Bits	Field Name	Description	Type	Reset
31:26	Reserved		RO	0x00
25:24	ENDIANESS	0 -no endianess, 1 - byte endianess, 2 - bit endianess	RW	0x0
23:18	Reserved		RO	0x00
17	SPARE	spare	RW	0
16	BURSTREQ	In case number of words to tranfer smaller than block size, DMA would use signle request and work with block size of 1 word. In case we know request would be set on altough number of words to tranfer is smaller than block size, we can set this field on and DMA will wait for block_request and transact all remaining words in one block.	RW	0
15:14	Reserved		RO	0x0
13:0	TRANSB	Number of bytes of the transaction to move from source to destination.	RW	0x0000

:HOST_DMA:CH4TCTL2

Address offset	0x0000 5010
Description	DMA command interface
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2:0	CMD	1 - run command. Start a transaction. 2- abort command - stop reansaction. 4- init command - init new transaction afet abort/error.	WO	0x0

:HOST_DMA:CH4TSTA

Address offset	0x0000 5014
Description	Job completion reason - either last transaction or exception
Type	RO

Bits	Field Name	Description	Type	Reset
31:30	Reserved		RO	0x0
29:16	REMAINB	Number of bytes remaining to complete the transaction.	RO	0x0000
15:8	OFFSET	Offset in words from block boundary. Actually number of word have been transferred in this block	RO	0x00
7:1	Reserved		RO	0x00
0	STA	channel OCP rstatus recieved at one of the primary ports. Once an error is encountered the channel will enter an Exception state and stay the until an init command is recieved. ICLR does not affect this status.	RO	0

:HOST_DMA:CH4JCTL

Address offset	0x0000 501C
Description	Job control register
Type	RW

Bits	Field Name	Description	Type	Reset
31	Reserved		RO	0
30	ENCLR	Enable DMA to set a rd/wr clear pulse at the beginning of a job (one cycle after run cmd)	RW	0
29	SRCDSTCFG	0 - Sorce is periph: transaction from periph to memory. 1 - Destination is periph :transaction from Memory to periph	RW	0
28	FIFOMODD	Destination pointer fifo mode	RW	0
27	FIFOMODS	Source pointer fifo mode	RW	0
26	DMASIGBPS	Tie high channel DMA req signal. This is useful for memory to memort transaction	RW	0
25:22	Reserved		RO	0x0
21:16	BLKSIZE	size of the block in words. If block mode is enabled, defines the address wrap around. Since channel arbitration decisions are made every block, this also effect how much bandwidth is given to a specific channel.	RW	0x00
15:2	Reserved		RO	0x0000
1:0	WORDSIZE	00 -word size is 32 bits 01 -word size is 16 bits 10 -word size is 8 bits	RW	0x0

:HOST_DMA:CH5STA

Address offset	0x0000 6000
Description	Channel Status FSM state and run indication.
Type	RO

Bits	Field Name	Description	Type	Reset
31:17	Reserved		RO	0x0000
16	RUN	Indication that channel is currently transfering data and is not idle. Channels that are waiting on arbitration are considered running.	RO	0
15:12	Reserved		RO	0x0
11:8	FSMSTATE	FSM state: 0x0. IDLE 0x2. EXCEPTION 0x3. DRAIN 0x4. ABORT 0x8. PENDING ARB 0x9. COPY 0xA. COPY LAST 0xC. DONE 0xD. SAVE CTX 0xE. WAIT NEXT TRANS 0xF. LAST	RO	0x0
7:3	Reserved		RO	0x00
2:0	HWEVENT	HW event status. Channel status is a bit mask. Multiple bits can be set at the same time 0. PROCESSING 1. TRANS DONE 2. ABORT 4. EXCEPTION	RO	0x0

:HOST_DMA:CH5TIPTR

Address offset	0x0000 6004
Description	32 bit address pointer of channel current input.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	IPTR	32 bit address pointer of channel current input.			RW	0x0000 0000

:HOST_DMA:CH5TOPTR

Address offset	0x0000 6008
Description	32 bit address pointer of channel current output.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	OPTR	32 bit address pointer of channel current output.			RW	0x0000 0000

:HOST_DMA:CH5TCTL

Address offset	0x0000 600C
Description	Transaction control
Type	RW

Bits	Field Name	Description	Type	Reset
31:26	Reserved		RO	0x00
25:24	ENDIANESS	0 -no endianess, 1 - byte endianess, 2 - bit endianess	RW	0x0
23:18	Reserved		RO	0x00
17	SPARE	spare	RW	0
16	BURSTREQ	In case number of words to tranfer smaller than block size, DMA would use signle request and work with block size of 1 word. In case we know request would be set on altough number of words to tranfer is smaller than block size, we can set this field on and DMA will wait for block_request and transact all remaining words in one block.	RW	0
15:14	Reserved		RO	0x0
13:0	TRANSB	Number of bytes of the transaction to move from source to destination.	RW	0x0000

:HOST_DMA:CH5TCTL2

Address offset	0x0000 6010
Description	DMA command interface
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2:0	CMD	1 - run command. Start a transaction. 2- abort command - stop reansaction. 4- init command - init new transaction afet abort/error.	WO	0x0

:HOST_DMA:CH5TSTA

Address offset	0x0000 6014
Description	Job completion reason - either last transaction or exception
Type	RO

Bits	Field Name	Description	Type	Reset
31:30	Reserved		RO	0x0
29:16	REMAINB	Number of bytes remaining to complete the transaction.	RO	0x0000
15:8	OFFSET	Offset in words from block boundary. Actually number of word have been transferred in this block	RO	0x00
7:1	Reserved		RO	0x00
0	STA	channel OCP rstatus recieved at one of the primary ports. Once an error is encountered the channel will enter an Exception state and stay the until an init command is recieved. ICLR does not affect this status.	RO	0

:HOST_DMA:CH5JCTL

Address offset	0x0000 601C
Description	Job control register
Type	RW

Bits	Field Name	Description	Type	Reset
31	Reserved		RO	0
30	ENCLR	Enable DMA to set a rd/wr clear pulse at the beginning of a job (one cycle after run cmd)	RW	0
29	SRCDSTCFG	0 - Sorce is periph: transaction from periph to memory. 1 - Destination is periph :transaction from Memory to periph	RW	0
28	FIFOMODD	Destination pointer fifo mode	RW	0
27	FIFOMODS	Source pointer fifo mode	RW	0
26	DMASIGBPS	Tie high channel DMA req signal. This is useful for memory to memort transaction	RW	0
25:22	Reserved		RO	0x0
21:16	BLKSIZE	size of the block in words. If block mode is enabled, defines the address wrap around. Since channel arbitration decisions are made every block, this also effect how much bandwidth is given to a specific channel.	RW	0x00
15:2	Reserved		RO	0x0000
1:0	WORDSIZE	00 -word size is 32 bits 01 -word size is 16 bits 10 -word size is 8 bits	RW	0x0

:HOST_DMA:CH6STA

Address offset	0x0000 7000
Description	Channel Status FSM state and run indication.
Type	RO

Bits	Field Name	Description	Type	Reset
31:17	Reserved		RO	0x0000
16	RUN	Indication that channel is currently transfering data and is not idle. Channels that are waiting on arbitration are considered running.	RO	0
15:12	Reserved		RO	0x0
11:8	FSMSTATE	FSM state: 0x0. IDLE 0x2. EXCEPTION 0x3. DRAIN 0x4. ABORT 0x8. PENDING ARB 0x9. COPY 0xA. COPY LAST 0xC. DONE 0xD. SAVE CTX 0xE. WAIT NEXT TRANS 0xF. LAST	RO	0x0
7:3	Reserved		RO	0x00
2:0	HWEVENT	HW event status. Channel status is a bit mask. Multiple bits can be set at the same time 0. PROCESSING 1. TRANS DONE 2. ABORT 4. EXCEPTION	RO	0x0

:HOST_DMA:CH6TIPTR

Address offset	0x0000 7004
Description	32 bit address pointer of channel current input.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	IPTR	32 bit address pointer of channel current input.			RW	0x0000 0000

:HOST_DMA:CH6TOPTR

Address offset	0x0000 7008
Description	32 bit address pointer of channel current output.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	OPTR	32 bit address pointer of channel current output.			RW	0x0000 0000

:HOST_DMA:CH6TCTL

Address offset	0x0000 700C
Description	Transaction control
Type	RW

Bits	Field Name	Description	Type	Reset
31:26	Reserved		RO	0x00
25:24	ENDIANESS	0 -no endianess, 1 - byte endianess, 2 - bit endianess	RW	0x0
23:18	Reserved		RO	0x00
17	SPARE	spare	RW	0
16	BURSTREQ	In case number of words to tranfer smaller than block size, DMA would use signle request and work with block size of 1 word. In case we know request would be set on altough number of words to tranfer is smaller than block size, we can set this field on and DMA will wait for block_request and transact all remaining words in one block.	RW	0
15:14	Reserved		RO	0x0
13:0	TRANSB	Number of bytes of the transaction to move from source to destination.	RW	0x0000

:HOST_DMA:CH6TCTL2

Address offset	0x0000 7010
Description	DMA command interface
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2:0	CMD	1 - run command. Start a transaction. 2- abort command - stop reansaction. 4- init command - init new transaction afet abort/error.	WO	0x0

:HOST_DMA:CH6TSTA

Address offset	0x0000 7014
Description	Job completion reason - either last transaction or exception
Type	RO

Bits	Field Name	Description	Type	Reset
31:30	Reserved		RO	0x0
29:16	REMAINB	Number of bytes remaining to complete the transaction.	RO	0x0000
15:8	WORDOFFSET	Offset in words from block boundary. Actually number of word have been transferred in this block	RO	0x00
7:1	Reserved		RO	0x00
0	STA	channel OCP rstatus recieved at one of the primary ports. Once an error is encountered the channel will enter an Exception state and stay the until an init command is recieved. ICLR does not affect this status.	RO	0

:HOST_DMA:CH6JCTL

Address offset	0x0000 701C
Description	Job control register
Type	RW

Bits	Field Name	Description	Type	Reset
31	Reserved		RO	0
30	ENCLR	Enable DMA to set a rd/wr clear pulse at the beginning of a job (one cycle after run cmd)	RW	0
29	SRCDSTCFG	0 - Sorce is periph: transaction from periph to memory. 1 - Destination is periph :transaction from Memory to periph	RW	0
28	FIFOMODD	Destination pointer fifo mode	RW	0
27	FIFOMODS	Source pointer fifo mode	RW	0
26	DMASIGBPS	Tie high channel DMA req signal. This is useful for memory to memort transaction	RW	0
25:22	Reserved		RO	0x0
21:16	BLKSIZE	size of the block in words. If block mode is enabled, defines the address wrap around. Since channel arbitration decisions are made every block, this also effect how much bandwidth is given to a specific channel.	RW	0x00
15:2	Reserved		RO	0x0000
1:0	WORDSIZE	00 -word size is 32 bits 01 -word size is 16 bits 10 -word size is 8 bits	RW	0x0

:HOST_DMA:CH7STA

Address offset	0x0000 8000
Description	Channel Status FSM state and run indication.
Type	RO

Bits	Field Name	Description	Type	Reset
31:17	Reserved		RO	0x0000
16	RUN	Indication that channel is currently transfering data and is not idle. Channels that are waiting on arbitration are considered running.	RO	0
15:12	Reserved		RO	0x0
11:8	FSMSTATE	FSM state: 0x0. IDLE 0x2. EXCEPTION 0x3. DRAIN 0x4. ABORT 0x8. PENDING ARB 0x9. COPY 0xA. COPY LAST 0xC. DONE 0xD. SAVE CTX 0xE. WAIT NEXT TRANS 0xF. LAST	RO	0x0
7:3	Reserved		RO	0x00
2:0	HWEVENT	HW event status. Channel status is a bit mask. Multiple bits can be set at the same time 0. PROCESSING 1. TRANS DONE 2. ABORT 4. EXCEPTION	RO	0x0

:HOST_DMA:CH7TIPTR

Address offset	0x0000 8004
Description	32 bit address pointer of channel current input.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	IPTR	32 bit address pointer of channel current input.			RW	0x0000 0000

:HOST_DMA:CH7TOPTR

Address offset	0x0000 8008
Description	32 bit address pointer of channel current output.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	OPTR	32 bit address pointer of channel current output.			RW	0x0000 0000

:HOST_DMA:CH7TCTL

Address offset	0x0000 800C
Description	Transaction control
Type	RW

Bits	Field Name	Description	Type	Reset
31:26	Reserved		RO	0x00
25:24	ENDIANESS	0 -no endianess, 1 - byte endianess, 2 - bit endianess	RW	0x0
23:18	Reserved		RO	0x00
17	SPARE	spare	RW	0
16	BURSTREQ	In case number of words to tranfer smaller than block size, DMA would use signle request and work with block size of 1 word. In case we know request would be set on altough number of words to tranfer is smaller than block size, we can set this field on and DMA will wait for block_request and transact all remaining words in one block.	RW	0
15:14	Reserved		RO	0x0
13:0	TRANSB	Number of bytes of the transaction to move from source to destination.	RW	0x0000

:HOST_DMA:CH7TCTL2

Address offset	0x0000 8010
Description	DMA command interface
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2:0	CMD	1 - run command. Start a transaction. 2- abort command - stop reansaction. 4- init command - init new transaction afet abort/error.	WO	0x0

:HOST_DMA:CH7TSTA

Address offset	0x0000 8014
Description	Job completion reason - either last transaction or exception
Type	RO

Bits	Field Name	Description	Type	Reset
31:30	Reserved		RO	0x0
29:16	REMAINB	Number of bytes remaining to complete the transaction.	RO	0x0000
15:8	OFFSET	Offset in words from block boundary. Actually number of word have been transferred in this block	RO	0x00
7:1	Reserved		RO	0x00
0	STA	channel OCP rstatus recieved at one of the primary ports. Once an error is encountered the channel will enter an Exception state and stay the until an init command is recieved. ICLR does not affect this status.	RO	0

:HOST_DMA:CH7JCTL

Address offset	0x0000 801C
Description	Job control register
Type	RW

Bits	Field Name	Description	Type	Reset
31	Reserved		RO	0
30	ENCLR	Enable DMA to set a rd/wr clear pulse at the beginning of a job (one cycle after run cmd)	RW	0
29	SRCDSTCFG	0 - Sorce is periph: transaction from periph to memory. 1 - Destination is periph :transaction from Memory to periph	RW	0
28	FIFOMODD	Destination pointer fifo mode	RW	0
27	FIFOMODS	Source pointer fifo mode	RW	0
26	DMASIGBPS	Tie high channel DMA req signal. This is useful for memory to memort transaction	RW	0
25:22	Reserved		RO	0x0
21:16	BLKSIZE	size of the block in words. If block mode is enabled, defines the address wrap around. Since channel arbitration decisions are made every block, this also effect how much bandwidth is given to a specific channel.	RW	0x00
15:2	Reserved		RO	0x0000
1:0	WORDSIZE	00 -word size is 32 bits 01 -word size is 16 bits 10 -word size is 8 bits	RW	0x0

:HOST_DMA:CH8STA

Address offset	0x0000 9000
Description	Channel Status FSM state and run indication.
Type	RO

Bits	Field Name	Description	Type	Reset
31:17	Reserved		RO	0x0000
16	RUN	Indication that channel is currently transfering data and is not idle. Channels that are waiting on arbitration are considered running.	RO	0
15:12	Reserved		RO	0x0
11:8	FSMSTATE	FSM state: 0x0. IDLE 0x2. EXCEPTION 0x3. DRAIN 0x4. ABORT 0x8. PENDING ARB 0x9. COPY 0xA. COPY LAST 0xC. DONE 0xD. SAVE CTX 0xE. WAIT NEXT TRANS 0xF. LAST	RO	0x0
7:3	Reserved		RO	0x00
2:0	HWEVENT	HW event status. Channel status is a bit mask. Multiple bits can be set at the same time 0. PROCESSING 1. TRANS DONE 2. ABORT 4. EXCEPTION	RO	0x0

:HOST_DMA:CH8TIPTR

Address offset	0x0000 9004
Description	32 bit address pointer of channel current input.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	IPTR	32 bit address pointer of channel current input.			RW	0x0000 0000

:HOST_DMA:CH8TOPTR

Address offset	0x0000 9008
Description	32 bit address pointer of channel current output.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	OPTR	32 bit address pointer of channel current output.			RW	0x0000 0000

:HOST_DMA:CH8TCTL

Address offset	0x0000 900C
Description	Transaction control
Type	RW

Bits	Field Name	Description	Type	Reset
31:26	Reserved		RO	0x00
25:24	ENDIANESS	0 -no endianess, 1 - byte endianess, 2 - bit endianess	RW	0x0
23:18	Reserved		RO	0x00
17	SPARE	spare	RW	0
16	BURSTREQ	In case number of words to tranfer smaller than block size, DMA would use signle request and work with block size of 1 word. In case we know request would be set on altough number of words to tranfer is smaller than block size, we can set this field on and DMA will wait for block_request and transact all remaining words in one block.	RW	0
15:14	Reserved		RO	0x0
13:0	TRANSB	Number of bytes of the transaction to move from source to destination.	RW	0x0000

:HOST_DMA:CH8TCTL2

Address offset	0x0000 9010
Description	DMA command interface
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2:0	CMD	1 - run command. Start a transaction. 2- abort command - stop reansaction. 4- init command - init new transaction afet abort/error.	WO	0x0

:HOST_DMA:CH8TSTA

Address offset	0x0000 9014
Description	Job completion reason - either last transaction or exception
Type	RO

Bits	Field Name	Description	Type	Reset
31:30	Reserved		RO	0x0
29:16	REMAINB	Number of bytes remaining to complete the transaction.	RO	0x0000
15:8	OFFSET	Offset in words from block boundary. Actually number of word have been transferred in this block	RO	0x00
7:1	Reserved		RO	0x00
0	STA	channel OCP rstatus recieved at one of the primary ports. Once an error is encountered the channel will enter an Exception state and stay the until an init command is recieved. ICLR does not affect this status.	RO	0

:HOST_DMA:CH8JCTL

Address offset	0x0000 901C
Description	Job control register
Type	RW

Bits	Field Name	Description	Type	Reset
31	Reserved		RO	0
30	ENCLR	Enable DMA to set a rd/wr clear pulse at the beginning of a job (one cycle after run cmd)	RW	0
29	SRCDSTCFG	0 - Sorce is periph: transaction from periph to memory. 1 - Destination is periph :transaction from Memory to periph	RW	0
28	FIFOMODD	Destination pointer fifo mode	RW	0
27	FIFOMODS	Source pointer fifo mode	RW	0
26	DMASIGBPS	Tie high channel DMA req signal. This is useful for memory to memort transaction	RW	0
25:22	Reserved		RO	0x0
21:16	BLKSIZE	size of the block in words. If block mode is enabled, defines the address wrap around. Since channel arbitration decisions are made every block, this also effect how much bandwidth is given to a specific channel.	RW	0x00
15:2	Reserved		RO	0x0000
1:0	WORDSIZE	00 -word size is 32 bits 01 -word size is 16 bits 10 -word size is 8 bits	RW	0x0

:HOST_DMA:CH9STA

Address offset	0x0000 A000
Description	Channel Status FSM state and run indication.
Type	RO

Bits	Field Name	Description	Type	Reset
31:17	Reserved		RO	0x0000
16	RUN	Indication that channel is currently transfering data and is not idle. Channels that are waiting on arbitration are considered running.	RO	0
15:12	Reserved		RO	0x0
11:8	FSMSTATE	FSM state: 0x0. IDLE 0x2. EXCEPTION 0x3. DRAIN 0x4. ABORT 0x8. PENDING ARB 0x9. COPY 0xA. COPY LAST 0xC. DONE 0xD. SAVE CTX 0xE. WAIT NEXT TRANS 0xF. LAST	RO	0x0
7:3	Reserved		RO	0x00
2:0	HWEVENT	HW event status. Channel status is a bit mask. Multiple bits can be set at the same time 0. PROCESSING 1. TRANS DONE 2. ABORT 4. EXCEPTION	RO	0x0

:HOST_DMA:CH9TIPTR

Address offset	0x0000 A004
Description	32 bit address pointer of channel current input.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	IPTR	32 bit address pointer of channel current input.			RW	0x0000 0000

:HOST_DMA:CH9TOPTR

Address offset	0x0000 A008
Description	32 bit address pointer of channel current output.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	OPTR	32 bit address pointer of channel current output.			RW	0x0000 0000

:HOST_DMA:CH9TCTL

Address offset	0x0000 A00C
Description	Transaction control
Type	RW

Bits	Field Name	Description	Type	Reset
31:26	Reserved		RO	0x00
25:24	ENDIANESS	0 -no endianess, 1 - byte endianess, 2 - bit endianess	RW	0x0
23:18	Reserved		RO	0x00
17	SPARE	spare	RW	0
16	BURSTREQ	In case number of words to tranfer smaller than block size, DMA would use signle request and work with block size of 1 word. In case we know request would be set on altough number of words to tranfer is smaller than block size, we can set this field on and DMA will wait for block_request and transact all remaining words in one block.	RW	0
15:14	Reserved		RO	0x0
13:0	TRANSB	Number of bytes of the transaction to move from source to destination.	RW	0x0000

:HOST_DMA:CH9TCTL2

Address offset	0x0000 A010
Description	DMA command interface
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2:0	CMD	1 - run command. Start a transaction. 2- abort command - stop reansaction. 4- init command - init new transaction afet abort/error.	WO	0x0

:HOST_DMA:CH9TSTA

Address offset	0x0000 A014
Description	Job completion reason - either last transaction or exception
Type	RO

Bits	Field Name	Description	Type	Reset
31:30	Reserved		RO	0x0
29:16	REMAINB	Number of bytes remaining to complete the transaction.	RO	0x0000
15:8	OFFSET	Offset in words from block boundary. Actually number of word have been transferred in this block	RO	0x00
7:1	Reserved		RO	0x00
0	STA	channel OCP rstatus recieved at one of the primary ports. Once an error is encountered the channel will enter an Exception state and stay the until an init command is recieved. ICLR does not affect this status.	RO	0

:HOST_DMA:CH9JCTL

Address offset	0x0000 A01C
Description	Job control register
Type	RW

Bits	Field Name	Description	Type	Reset
31	Reserved		RO	0
30	ENCLR	Enable DMA to set a rd/wr clear pulse at the beginning of a job (one cycle after run cmd)	RW	0
29	SRCDSTCFG	0 - Sorce is periph: transaction from periph to memory. 1 - Destination is periph :transaction from Memory to periph	RW	0
28	FIFOMODD	Destination pointer fifo mode	RW	0
27	FIFOMODS	Source pointer fifo mode	RW	0
26	DMASIGBPS	Tie high channel DMA req signal. This is useful for memory to memort transaction	RW	0
25:22	Reserved		RO	0x0
21:16	BLKSIZE	size of the block in words. If block mode is enabled, defines the address wrap around. Since channel arbitration decisions are made every block, this also effect how much bandwidth is given to a specific channel.	RW	0x00
15:2	Reserved		RO	0x0000
1:0	WORDSIZE	00 -word size is 32 bits 01 -word size is 16 bits 10 -word size is 8 bits	RW	0x0

:HOST_DMA:CH1STA0

Address offset	0x0000 B000
Description	Channel Status FSM state and run indication.
Type	RO

Bits	Field Name	Description	Type	Reset
31:17	Reserved		RO	0x0000
16	RUN	Indication that channel is currently transfering data and is not idle. Channels that are waiting on arbitration are considered running.	RO	0
15:12	Reserved		RO	0x0
11:8	FSMSTATE	FSM state: 0x0. IDLE 0x2. EXCEPTION 0x3. DRAIN 0x4. ABORT 0x8. PENDING ARB 0x9. COPY 0xA. COPY LAST 0xC. DONE 0xD. SAVE CTX 0xE. WAIT NEXT TRANS 0xF. LAST	RO	0x0
7:3	Reserved		RO	0x00
2:0	HWEVENT	HW event status. Channel status is a bit mask. Multiple bits can be set at the same time 0. PROCESSING 1. TRANS DONE 2. ABORT 4. EXCEPTION	RO	0x0

:HOST_DMA:CH1TIPTR0

Address offset	0x0000 B004
Description	32 bit address pointer of channel current input.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	IPTR	32 bit address pointer of channel current input.			RW	0x0000 0000

:HOST_DMA:CH1TOPTR0

Address offset	0x0000 B008
Description	32 bit address pointer of channel current output.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	OPTR	32 bit address pointer of channel current output.			RW	0x0000 0000

:HOST_DMA:CH1TCTL0

Address offset	0x0000 B00C
Description	Transaction control
Type	RW

Bits	Field Name	Description	Type	Reset
31:26	Reserved		RO	0x00
25:24	ENDIANESS	0 -no endianess, 1 - byte endianess, 2 - bit endianess	RW	0x0
23:18	Reserved		RO	0x00
17	SPARE	spare	RW	0
16	BURSTREQ	In case number of words to tranfer smaller than block size, DMA would use signle request and work with block size of 1 word. In case we know request would be set on altough number of words to tranfer is smaller than block size, we can set this field on and DMA will wait for block_request and transact all remaining words in one block.	RW	0
15:14	Reserved		RO	0x0
13:0	TRANSB	Number of bytes of the transaction to move from source to destination.	RW	0x0000

:HOST_DMA:CH1TCTRL20

Address offset	0x0000 B010
Description	DMA command interface
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2:0	CMD	1 - run command. Start a transaction. 2- abort command - stop reansaction. 4- init command - init new transaction afet abort/error.	WO	0x0

:HOST_DMA:CH1TSTA0

Address offset	0x0000 B014
Description	Job completion reason - either last transaction or exception
Type	RO

Bits	Field Name	Description	Type	Reset
31:30	Reserved		RO	0x0
29:16	REMAINB	Number of bytes remaining to complete the transaction.	RO	0x0000
15:8	OFFSET	Offset in words from block boundary. Actually number of word have been transferred in this block	RO	0x00
7:1	Reserved		RO	0x00
0	STA	channel OCP rstatus recieved at one of the primary ports. Once an error is encountered the channel will enter an Exception state and stay the until an init command is recieved. ICLR does not affect this status.	RO	0

:HOST_DMA:CH1JCTL0

Address offset	0x0000 B01C
Description	Job control register
Type	RW

Bits	Field Name	Description	Type	Reset
31	Reserved		RO	0
30	ENCLR	Enable DMA to set a rd/wr clear pulse at the beginning of a job (one cycle after run cmd)	RW	0
29	SRCDSTCFG	0 - Sorce is periph: transaction from periph to memory. 1 - Destination is periph :transaction from Memory to periph	RW	0
28	FIFOMODD	Destination pointer fifo mode	RW	0
27	FIFOMODS	Source pointer fifo mode	RW	0
26	DMASIGBPS	Tie high channel DMA req signal. This is useful for memory to memort transaction	RW	0
25:24	Reserved		RO	0x0
23:16	BLKSIZE	size of the block in words. If block mode is enabled, defines the address wrap around. Since channel arbitration decisions are made every block, this also effect how much bandwidth is given to a specific channel.	RW	0x00
15:2	Reserved		RO	0x0000
1:0	WORDSIZE	00 -word size is 32 bits 01 -word size is 16 bits 10 -word size is 8 bits	RW	0x0

:HOST_DMA:CH1STA1

Address offset	0x0000 C000
Description	Channel Status FSM state and run indication.
Type	RO

Bits	Field Name	Description	Type	Reset
31:17	Reserved		RO	0x0000
16	RUN	Indication that channel is currently transfering data and is not idle. Channels that are waiting on arbitration are considered running.	RO	0
15:12	Reserved		RO	0x0
11:8	FSMSTATE	FSM state: 0x0. IDLE 0x2. EXCEPTION 0x3. DRAIN 0x4. ABORT 0x8. PENDING ARB 0x9. COPY 0xA. COPY LAST 0xC. DONE 0xD. SAVE CTX 0xE. WAIT NEXT TRANS 0xF. LAST	RO	0x0
7:3	Reserved		RO	0x00
2:0	HWEVENT	HW event status. Channel status is a bit mask. Multiple bits can be set at the same time 0. PROCESSING 1. TRANS DONE 2. ABORT 4. EXCEPTION	RO	0x0

:HOST_DMA:CH1TIPTR1

Address offset	0x0000 C004
Description	32 bit address pointer of channel current input.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	IPTR	32 bit address pointer of channel current input.			RW	0x0000 0000

:HOST_DMA:CH1TOPTR1

Address offset	0x0000 C008
Description	32 bit address pointer of channel current output.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	OPTR	32 bit address pointer of channel current output.			RW	0x0000 0000

:HOST_DMA:CH1TCTL1

Address offset	0x0000 C00C
Description	Transaction control
Type	RW

Bits	Field Name	Description	Type	Reset
31:26	Reserved		RO	0x00
25:24	ENDIANESS	0 -no endianess, 1 - byte endianess, 2 - bit endianess	RW	0x0
23:18	Reserved		RO	0x00
17	SPARE	spare	RW	0
16	BURSTREQ	In case number of words to tranfer smaller than block size, DMA would use signle request and work with block size of 1 word. In case we know request would be set on altough number of words to tranfer is smaller than block size, we can set this field on and DMA will wait for block_request and transact all remaining words in one block.	RW	0
15:14	Reserved		RO	0x0
13:0	TRANSB	Number of bytes of the transaction to move from source to destination.	RW	0x0000

:HOST_DMA:CH1TCTRL21

Address offset	0x0000 C010
Description	DMA command interface
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2:0	CMD	1 - run command. Start a transaction. 2- abort command - stop reansaction. 4- init command - init new transaction afet abort/error.	WO	0x0

:HOST_DMA:CH1TSTA1

Address offset	0x0000 C014
Description	Job completion reason - either last transaction or exception
Type	RO

Bits	Field Name	Description	Type	Reset
31:30	Reserved		RO	0x0
29:16	REMAINB	Number of bytes remaining to complete the transaction.	RO	0x0000
15:8	OFFSET	Offset in words from block boundary. Actually number of word have been transferred in this block	RO	0x00
7:1	Reserved		RO	0x00
0	STA	channel OCP rstatus recieved at one of the primary ports. Once an error is encountered the channel will enter an Exception state and stay the until an init command is recieved. ICLR does not affect this status.	RO	0

:HOST_DMA:CH1JCTL1

Address offset	0x0000 C01C
Description	Job control register
Type	RW

Bits	Field Name	Description	Type	Reset
31	Reserved		RO	0
30	ENCLR	Enable DMA to set a rd/wr clear pulse at the beginning of a job (one cycle after run cmd)	RW	0
29	SRCDSTCFG	0 - Sorce is periph: transaction from periph to memory. 1 - Destination is periph :transaction from Memory to periph	RW	0
28	FIFOMODD	Destination pointer fifo mode	RW	0
27	FIFOMODS	Source pointer fifo mode	RW	0
26	DMASIGBPS	Tie high channel DMA req signal. This is useful for memory to memort transaction	RW	0
25:22	Reserved		RO	0x0
21:16	BLKSIZE	size of the block in words. If block mode is enabled, defines the address wrap around. Since channel arbitration decisions are made every block, this also effect how much bandwidth is given to a specific channel.	RW	0x00
15:2	Reserved		RO	0x0000
1:0	WORDSIZE	00 -word size is 32 bits 01 -word size is 16 bits 10 -word size is 8 bits	RW	0x0

:HOST_DMA:CH1STA2

Address offset	0x0000 D000
Description	Channel Status FSM state and run indication.
Type	RO

Bits	Field Name	Description	Type	Reset
31:17	Reserved		RO	0x0000
16	RUN	Indication that channel is currently transfering data and is not idle. Channels that are waiting on arbitration are considered running.	RO	0
15:12	Reserved		RO	0x0
11:8	FSMSTATE	FSM state: 0x0. IDLE 0x2. EXCEPTION 0x3. DRAIN 0x4. ABORT 0x8. PENDING ARB 0x9. COPY 0xA. COPY LAST 0xC. DONE 0xD. SAVE CTX 0xE. WAIT NEXT TRANS 0xF. LAST	RO	0x0
7:3	Reserved		RO	0x00
2:0	HWEVENT	HW event status. Channel status is a bit mask. Multiple bits can be set at the same time 0. PROCESSING 1. TRANS DONE 2. ABORT 4. EXCEPTION	RO	0x0

:HOST_DMA:CH1TIPTR2

Address offset	0x0000 D004
Description	32 bit address pointer of channel current input.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	IPTR	32 bit address pointer of channel current input.			RW	0x0000 0000

:HOST_DMA:CH1TOPTR2

Address offset	0x0000 D008
Description	32 bit address pointer of channel current output.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	OPTR	32 bit address pointer of channel current output.			RW	0x0000 0000

:HOST_DMA:CH1TCTL2

Address offset	0x0000 D00C
Description	Transaction control
Type	RW

Bits	Field Name	Description	Type	Reset
31:26	Reserved		RO	0x00
25:24	ENDIANESS	0 -no endianess, 1 - byte endianess, 2 - bit endianess	RW	0x0
23:18	Reserved		RO	0x00
17	SPARE	spare	RW	0
16	BURSTREQ	In case number of words to tranfer smaller than block size, DMA would use signle request and work with block size of 1 word. In case we know request would be set on altough number of words to tranfer is smaller than block size, we can set this field on and DMA will wait for block_request and transact all remaining words in one block.	RW	0
15:14	Reserved		RO	0x0
13:0	TRANSB	Number of bytes of the transaction to move from source to destination.	RW	0x0000

:HOST_DMA:CH1TCTRL22

Address offset	0x0000 D010
Description	DMA command interface
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2:0	CMD	1 - run command. Start a transaction. 2- abort command - stop reansaction. 4- init command - init new transaction afet abort/error.	WO	0x0

:HOST_DMA:CH1TSTA2

Address offset	0x0000 D014
Description	Job completion reason - either last transaction or exception
Type	RO

Bits	Field Name	Description	Type	Reset
31:30	Reserved		RO	0x0
29:16	REMAINB	Number of bytes remaining to complete the transaction.	RO	0x0000
15:8	OFFSET	Offset in words from block boundary. Actually number of word have been transferred in this block	RO	0x00
7:1	Reserved		RO	0x00
0	STA	channel OCP rstatus recieved at one of the primary ports. Once an error is encountered the channel will enter an Exception state and stay the until an init command is recieved. ICLR does not affect this status.	RO	0

:HOST_DMA:CH1JCTL2

Address offset	0x0000 D01C
Description	Job control register
Type	RW

Bits	Field Name	Description	Type	Reset
31	Reserved		RO	0
30	ENCLR	Enable DMA to set a rd/wr clear pulse at the beginning of a job (one cycle after run cmd)	RW	0
29	SRCDSTCFG	0 - Sorce is periph: transaction from periph to memory. 1 - Destination is periph :transaction from Memory to periph	RW	0
28	FIFOMODD	Destination pointer fifo mode	RW	0
27	FIFOMODS	Source pointer fifo mode	RW	0
26	DMASIGBPS	Tie high channel DMA req signal. This is useful for memory to memort transaction	RW	0
25:22	Reserved		RO	0x0
21:16	BLKSIZE	size of the block in words. If block mode is enabled, defines the address wrap around. Since channel arbitration decisions are made every block, this also effect how much bandwidth is given to a specific channel.	RW	0x00
15:2	Reserved		RO	0x0000
1:0	WORDSIZE	00 -word size is 32 bits 01 -word size is 16 bits 10 -word size is 8 bits	RW	0x0

:HOST_DMA:CH1STA3

Address offset	0x0000 E000
Description	Channel Status FSM state and run indication.
Type	RO

Bits	Field Name	Description	Type	Reset
31:17	Reserved		RO	0x0000
16	RUN	Indication that channel is currently transfering data and is not idle. Channels that are waiting on arbitration are considered running.	RO	0
15:12	Reserved		RO	0x0
11:8	FSMSTATE	FSM state: 0x0. IDLE 0x2. EXCEPTION 0x3. DRAIN 0x4. ABORT 0x8. PENDING ARB 0x9. COPY 0xA. COPY LAST 0xC. DONE 0xD. SAVE CTX 0xE. WAIT NEXT TRANS 0xF. LAST	RO	0x0
7:3	Reserved		RO	0x00
2:0	HWEVENT	HW event status. Channel status is a bit mask. Multiple bits can be set at the same time 0. PROCESSING 1. TRANS DONE 2. ABORT 4. EXCEPTION	RO	0x0

:HOST_DMA:CH1TIPTR3

Address offset	0x0000 E004
Description	32 bit address pointer of channel current input.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	IPTR	32 bit address pointer of channel current input.			RW	0x0000 0000

:HOST_DMA:CH1TOPTR3

Address offset	0x0000 E008
Description	32 bit address pointer of channel current output.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	OPTR	32 bit address pointer of channel current output.			RW	0x0000 0000

:HOST_DMA:CH1TCTL3

Address offset	0x0000 E00C
Description	Transaction control
Type	RW

Bits	Field Name	Description	Type	Reset
31:26	Reserved		RO	0x00
25:24	ENDIANESS	0 -no endianess, 1 - byte endianess, 2 - bit endianess	RW	0x0
23:18	Reserved		RO	0x00
17	SPARE	spare	RW	0
16	BURSTREQ	In case number of words to tranfer smaller than block size, DMA would use signle request and work with block size of 1 word. In case we know request would be set on altough number of words to tranfer is smaller than block size, we can set this field on and DMA will wait for block_request and transact all remaining words in one block.	RW	0
15:14	Reserved		RO	0x0
13:0	TRANSB	Number of bytes of the transaction to move from source to destination.	RW	0x0000

:HOST_DMA:CH1TCTRL23

Address offset	0x0000 E010
Description	DMA command interface
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2:0	CMD	1 - run command. Start a transaction. 2- abort command - stop reansaction. 4- init command - init new transaction afet abort/error.	WO	0x0

:HOST_DMA:CH1TSTA3

Address offset	0x0000 E014
Description	Job completion reason - either last transaction or exception
Type	RO

Bits	Field Name	Description	Type	Reset
31:30	Reserved		RO	0x0
29:16	REMAINB	Number of bytes remaining to complete the transaction.	RO	0x0000
15:8	OFFSET	Offset in words from block boundary. Actually number of word have been transferred in this block	RO	0x00
7:1	Reserved		RO	0x00
0	STA	channel OCP rstatus recieved at one of the primary ports. Once an error is encountered the channel will enter an Exception state and stay the until an init command is recieved. ICLR does not affect this status.	RO	0

:HOST_DMA:CH1JCTL3

Address offset	0x0000 E01C
Description	Job control register
Type	RW

Bits	Field Name	Description	Type	Reset
31	Reserved		RO	0
30	ENCLR	Enable DMA to set a rd/wr clear pulse at the beginning of a job (one cycle after run cmd)	RW	0
29	SRCDSTCFG	0 - Sorce is periph: transaction from periph to memory. 1 - Destination is periph :transaction from Memory to periph	RW	0
28	FIFOMODD	Destination pointer fifo mode	RW	0
27	FIFOMODS	Source pointer fifo mode	RW	0
26	DMASIGBPS	Tie high channel DMA req signal. This is useful for memory to memort transaction	RW	0
25:22	Reserved		RO	0x0
21:16	BLKSIZE	size of the block in words. If block mode is enabled, defines the address wrap around. Since channel arbitration decisions are made every block, this also effect how much bandwidth is given to a specific channel.	RW	0x00
15:2	Reserved		RO	0x0000
1:0	WORDSIZE	00 -word size is 32 bits 01 -word size is 16 bits 10 -word size is 8 bits	RW	0x0