i2c.h

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/******************************************************************************
 *  Filename:       i2c.h
 *
 *  Description:    Prototypes and defines for the I2C API.
 *
 *  Copyright (c) 2023-2024 Texas Instruments Incorporated
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1) Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *  2) Redistributions in binary form must reproduce the above copyright notice,
 *     this list of conditions and the following disclaimer in the documentation
 *     and/or other materials provided with the distribution.
 *
 *  3) Neither the name of the copyright holder nor the names of its
 *     contributors may be used to endorse or promote products derived from this
 *     software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************/

#ifndef __I2C_H__
#define __I2C_H__

//*****************************************************************************
//
//
//*****************************************************************************

//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C" {
#endif

#include <stdbool.h>
#include <stdint.h>
#include "../inc/hw_types.h"
#include "../inc/hw_ints.h"
#include "../inc/hw_memmap.h"
#include "../inc/hw_i2c.h"
#include "debug.h"
#include "interrupt.h"
#include "cpu.h"

//*****************************************************************************
//
//
//*****************************************************************************
#define I2C_CONTROLLER_CMD_SINGLE_SEND       (I2C_CCTR_BURSTRUN_EN | I2C_CCTR_START_EN_START | I2C_CCTR_STOP_EN_STOP)
#define I2C_CONTROLLER_CMD_SINGLE_RECEIVE    (I2C_CCTR_BURSTRUN_EN | I2C_CCTR_START_EN_START | I2C_CCTR_STOP_EN_STOP)
#define I2C_CONTROLLER_CMD_BURST_SEND_START  (I2C_CCTR_BURSTRUN_EN | I2C_CCTR_START_EN_START)
#define I2C_CONTROLLER_CMD_BURST_SEND_CONT   (I2C_CCTR_BURSTRUN_EN)
#define I2C_CONTROLLER_CMD_BURST_SEND_FINISH (I2C_CCTR_BURSTRUN_EN | I2C_CCTR_STOP_EN_STOP)
#define I2C_CONTROLLER_CMD_BURST_RECEIVE_START \
    (I2C_CCTR_BURSTRUN_EN | I2C_CCTR_START_EN_START | I2C_CCTR_ACK_EN_ACK | I2C_CCTR_CACKOEN_EN)
#define I2C_CONTROLLER_CMD_BURST_RECEIVE_CONT   (I2C_CCTR_BURSTRUN_EN | I2C_CCTR_ACK_EN_ACK | I2C_CCTR_CACKOEN_EN)
#define I2C_CONTROLLER_CMD_BURST_RECEIVE_FINISH (I2C_CCTR_BURSTRUN_EN | I2C_CCTR_STOP_EN_STOP)
#define I2C_CONTROLLER_CMD_BURST_FINISH         (I2C_CCTR_BURSTRUN_EN | I2C_CCTR_STOP_EN_STOP)

//*****************************************************************************
//
//
//*****************************************************************************
#define I2C_CONTROLLER_TRANSACTION_LENGTH_MAX    0xFFF
#define I2C_CONTROLLER_TRANSACTION_LENGTH_SINGLE 0x001
#define I2C_CONTROLLER_TRANSACTION_LENGTH_NONE   0x000

//*****************************************************************************
//
//
//*****************************************************************************
#define I2C_CONTROLLER_CONFIG_DEFAULT                    0
#define I2C_CONTROLLER_CONFIG_CLOCK_STRETCHING_DETECTION I2C_CCR_CLKSTRETCH_EN
#define I2C_CONTROLLER_CONFIG_MULTI_CONTROLLER_MODE      I2C_CCR_MCST_EN
#define I2C_CONTROLLER_CONFIG_LOOPBACK                   I2C_CCR_LPBK_EN

//*****************************************************************************
//
//
//*****************************************************************************
#define I2C_CONTROLLER_DIR_RECEIVE  I2C_CSA_DIR_RECEIVE
#define I2C_CONTROLLER_DIR_TRANSMIT I2C_CSA_DIR_TRANSMIT

//*****************************************************************************
//
//
//*****************************************************************************
#define I2C_CONTROLLER_ERR_NONE     0
#define I2C_CONTROLLER_ERR_ADDR_ACK I2C_CSR_ADRACK_SET
#define I2C_CONTROLLER_ERR_DATA_ACK I2C_CSR_DATACK_SET
#define I2C_CONTROLLER_ERR_ARB_LOST I2C_CSR_ARBLST_SET

//*****************************************************************************
//
//
//*****************************************************************************
#define I2C_INT_ALL 0xFFFFFFFF

//*****************************************************************************
//
//
//*****************************************************************************
#define I2C_CONTROLLER_INT_RX_DONE         I2C_EVENT0_IMASK_CRXDONE
#define I2C_CONTROLLER_INT_TX_DONE         I2C_EVENT0_IMASK_CTXDONE
#define I2C_CONTROLLER_INT_RX_FIFO_TRIGGER I2C_EVENT0_IMASK_RXFIFOTRGC
#define I2C_CONTROLLER_INT_TX_FIFO_TRIGGER I2C_EVENT0_IMASK_TXFIFOTRGC
#define I2C_CONTROLLER_INT_RX_FIFO_FULL    I2C_EVENT0_IMASK_RXFIFOFULLC
#define I2C_CONTROLLER_INT_TX_FIFO_FULL    I2C_EVENT0_IMASK_TXFIFOFULLC
#define I2C_CONTROLLER_INT_TX_FIFO_EMPTY   I2C_EVENT0_IMASK_TXEMPTYC
#define I2C_CONTROLLER_INT_NACK            I2C_EVENT0_IMASK_CNACK
#define I2C_CONTROLLER_INT_START           I2C_EVENT0_IMASK_CSTART
#define I2C_CONTROLLER_INT_STOP            I2C_EVENT0_IMASK_CSTOP
#define I2C_CONTROLLER_INT_ARB_LOST        I2C_EVENT0_IMASK_CARBLOST

//*****************************************************************************
//
//
//*****************************************************************************
#define I2C_TARGET_INT_RX_DONE           I2C_EVENT0_IMASK_TRXDONE
#define I2C_TARGET_INT_TX_DONE           I2C_EVENT0_IMASK_TTXDONE
#define I2C_TARGET_INT_RX_FIFO_TRIGGER   I2C_EVENT0_IMASK_RXFIFOTRGT
#define I2C_TARGET_INT_TX_FIFO_TRIGGER   I2C_EVENT0_IMASK_TXFIFOTRGT
#define I2C_TARGET_INT_RX_FIFO_FULL      I2C_EVENT0_IMASK_RXFIFOFULLT
#define I2C_TARGET_INT_TX_FIFO_FULL      I2C_EVENT0_IMASK_TXFIFOFULLT
#define I2C_TARGET_INT_TX_FIFO_EMPTY     I2C_EVENT0_IMASK_TXEMPTYT
#define I2C_TARGET_INT_START             I2C_EVENT0_IMASK_TSTART
#define I2C_TARGET_INT_STOP              I2C_EVENT0_IMASK_TSTOP
#define I2C_TARGET_INT_GEN_CALL          I2C_EVENT0_IMASK_TGENCALL
#define I2C_TARGET_INT_TX_FIFO_UNDERFLOW I2C_EVENT0_IMASK_TX_UNFL_T
#define I2C_TARGET_INT_ARB_LOST          I2C_EVENT0_IMASK_CARBLOST

//*****************************************************************************
//
//
//*****************************************************************************
#define I2C_MODE_STANDARD  0
#define I2C_MODE_FAST      1
#define I2C_MODE_FAST_PLUS 2

//*****************************************************************************
//
//
//*****************************************************************************
#define I2C_CONTROLLER_ADDR_MODE_7_BIT  I2C_CSA_CMODE_SEVEN_BIT
#define I2C_CONTROLLER_ADDR_MODE_10_BIT I2C_CSA_CMODE_TEN_BIT

//*****************************************************************************
//
//
//*****************************************************************************
#define I2C_TARGET_ADDR_MODE_7_BIT  I2C_TOAR_MODE_SEVEN_BIT
#define I2C_TARGET_ADDR_MODE_10_BIT I2C_TOAR_MODE_TEN_BIT

//*****************************************************************************
//
//
//*****************************************************************************
#define I2C_RX_FIFO_SIZE (I2C_FIFOSR_RXFIFOCNT_MAXIMUM >> I2C_FIFOSR_RXFIFOCNT_S)
#define I2C_TX_FIFO_SIZE (I2C_FIFOSR_TXFIFOCNT_MAXIMUM >> I2C_FIFOSR_TXFIFOCNT_S)

//*****************************************************************************
//
// API Functions and prototypes
//
//*****************************************************************************

#ifdef DRIVERLIB_DEBUG
//*****************************************************************************
//
//
//*****************************************************************************
static bool I2CIsBaseValid(uint32_t base)
{
    return (base == I2C0_BASE || base == I2C1_BASE);
}
#endif

//*****************************************************************************
//
//
//*****************************************************************************
extern void I2CControllerInit(uint32_t base, uint32_t config, uint32_t mode);

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void I2CControllerSetCommand(uint32_t base, uint32_t cmd, uint16_t transactionLength)
{
    // Check the arguments.
    ASSERT(I2CIsBaseValid(base));
    ASSERT((cmd == I2C_CONTROLLER_CMD_SINGLE_SEND) ||
           //     (cmd == I2C_CONTROLLER_CMD_SINGLE_RECEIVE) || -> Equal to SINGLE_SEND
           (cmd == I2C_CONTROLLER_CMD_BURST_SEND_START) || (cmd == I2C_CONTROLLER_CMD_BURST_SEND_CONT) ||
           (cmd == I2C_CONTROLLER_CMD_BURST_SEND_FINISH) || (cmd == I2C_CONTROLLER_CMD_BURST_RECEIVE_START) ||
           (cmd == I2C_CONTROLLER_CMD_BURST_RECEIVE_CONT)
           //     (cmd == I2C_CONTROLLER_CMD_BURST_RECEIVE_FINISH) || -> Equal to I2C_CONTROLLER_CMD_BURST_SEND_FINISH
           //     (cmd == I2C_CONTROLLER_CMD_BURST_FINISH) || -> Equal to I2C_CONTROLLER_CMD_BURST_SEND_FINISH
    );
    ASSERT(transactionLength <= 0xFFF);

    // Set the command.
    HWREG(base + I2C_O_CCTR) = cmd | ((transactionLength << I2C_CCTR_MBLEN_S) & I2C_CCTR_MBLEN_M);
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void I2CControllerSetTargetAddr(uint32_t base,
                                                uint32_t addressMode,
                                                uint16_t targetAddr,
                                                uint32_t direction)
{
    // Check the arguments.
    ASSERT(I2CIsBaseValid(base));
    ASSERT((addressMode == I2C_CONTROLLER_ADDR_MODE_7_BIT) || (addressMode == I2C_CONTROLLER_ADDR_MODE_10_BIT));
    ASSERT(!(targetAddr & 0xFF80) || (addressMode == I2C_CONTROLLER_ADDR_MODE_10_BIT));
    ASSERT(!(targetAddr & 0xFC00));
    ASSERT((direction == I2C_CONTROLLER_DIR_RECEIVE) || (direction == I2C_CONTROLLER_DIR_TRANSMIT));

    // Set the address mode and the address of the target with which the
    // controller will communicate, and set the direction.
    // Note: The possible values for addressMode and direction are defined in
    // in terms of the enums for their corresponding fields in MSA, so they can
    // be added directly without any modification.
    HWREG(base + I2C_O_CSA) = (targetAddr << I2C_CSA_TADDR_S) | addressMode | direction;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void I2CControllerEnable(uint32_t base)
{
    // Check the arguments.
    ASSERT(I2CIsBaseValid(base));

    // Write to MCR register
    HWREG(base + I2C_O_CCR) |= I2C_CCR_ACTIVE_EN;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void I2CControllerDisable(uint32_t base)
{
    // Check the arguments.
    ASSERT(I2CIsBaseValid(base));

    // Disable the clock for the controller.
    HWREG(base + I2C_O_CCR) &= ~I2C_CCR_ACTIVE_EN;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE bool I2CControllerIsBusy(uint32_t base)
{
    // Check the arguments.
    ASSERT(I2CIsBaseValid(base));

    // Return the busy status.
    if ((HWREG(base + I2C_O_CSR) & I2C_CSR_BUSY_M) == I2C_CSR_BUSY_SET)
    {
        return (true);
    }
    else
    {
        return (false);
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE bool I2CControllerIsBusBusy(uint32_t base)
{
    // Check the arguments.
    ASSERT(I2CIsBaseValid(base));

    // Return the bus busy status.
    if ((HWREG(base + I2C_O_CSR) & I2C_CSR_BUSBSY_M) == I2C_CSR_BUSBSY_SET)
    {
        return (true);
    }
    else
    {
        return (false);
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
extern uint32_t I2CControllerGetError(uint32_t base);

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE uint32_t I2CGetTxFifoCount(uint32_t base)
{
    // Check the arguments.
    ASSERT(I2CIsBaseValid(base));

    // TXFIFOCNT contains the number of bytes that can be written to the TX
    // FIFO. This function needs to return the number of byte already in the TX
    // FIFO.
    return (I2C_FIFOSR_TXFIFOCNT_MAXIMUM - (HWREG(base + I2C_O_FIFOSR) & I2C_FIFOSR_TXFIFOCNT_M)) >>
            I2C_FIFOSR_TXFIFOCNT_S;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE uint32_t I2CGetRxFifoCount(uint32_t base)
{
    // Check the arguments.
    ASSERT(I2CIsBaseValid(base));

    // RXFIFOCNT contains the number of bytes that can be read from the RX FIFO
    // I.e. the number of bytes in the RX FIFO
    return (HWREG(base + I2C_O_FIFOSR) & I2C_FIFOSR_RXFIFOCNT_M) >> I2C_FIFOSR_RXFIFOCNT_S;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE bool I2CIsTxFifoEmpty(uint32_t base)
{
    // Check the arguments.
    ASSERT(I2CIsBaseValid(base));

    // If the maximum number of bytes can be put into the TX FIFO, then it is
    // empty
    return (HWREG(base + I2C_O_FIFOSR) & I2C_FIFOSR_TXFIFOCNT_M) == I2C_FIFOSR_TXFIFOCNT_MAXIMUM;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE bool I2CIsRxFifoEmpty(uint32_t base)
{
    // Check the arguments.
    ASSERT(I2CIsBaseValid(base));

    // If the no bytes can be read from the RX FIFO, then it is empty
    return (HWREG(base + I2C_O_FIFOSR) & I2C_FIFOSR_RXFIFOCNT_M) == I2C_FIFOSR_RXFIFOCNT_MINIMUM;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE bool I2CIsTxFifoFull(uint32_t base)
{
    // Check the arguments.
    ASSERT(I2CIsBaseValid(base));

    // If no bytes can be put into the TX FIFO, then it is full
    return (HWREG(base + I2C_O_FIFOSR) & I2C_FIFOSR_TXFIFOCNT_M) == I2C_FIFOSR_TXFIFOCNT_MINIMUM;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE bool I2CIsRxFifoFull(uint32_t base)
{
    // Check the arguments.
    ASSERT(I2CIsBaseValid(base));

    // If the maximum number of bytes can be read from the RX FIFO,
    // then it is full
    return (HWREG(base + I2C_O_FIFOSR) & I2C_FIFOSR_RXFIFOCNT_M) == I2C_FIFOSR_RXFIFOCNT_MAXIMUM;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void I2CSetTxFifoTrigger(uint32_t base, uint8_t level)
{
    // Check the arguments.
    ASSERT(I2CIsBaseValid(base));
    ASSERT(level <= 7);

    // Read FIFOCTL register
    uint32_t fifoCtlTmp = HWREG(base + I2C_O_FIFOCTL);

    // Clear bits in TXTRIG field
    fifoCtlTmp &= ~I2C_FIFOCTL_TXTRIG_M;

    // Set TXTRIG field to the specified trigger level
    fifoCtlTmp |= (level << I2C_FIFOCTL_TXTRIG_S) & I2C_FIFOCTL_TXTRIG_M;

    // Write back to FIFOCTL register
    HWREG(base + I2C_O_FIFOCTL) = fifoCtlTmp;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void I2CSetRxFifoTrigger(uint32_t base, uint8_t level)
{
    // Check the arguments.
    ASSERT(I2CIsBaseValid(base));
    ASSERT(1 <= level && level <= 8);

    // Read FIFOCTL register
    uint32_t fifoCtlTmp = HWREG(base + I2C_O_FIFOCTL);

    // Clear bits in RXTRIG field
    fifoCtlTmp &= ~I2C_FIFOCTL_RXTRIG_M;

    // Set RXTRIG field to the specified trigger level
    fifoCtlTmp |= ((level - 1) << I2C_FIFOCTL_RXTRIG_S) & I2C_FIFOCTL_RXTRIG_M;

    // Write back to FIFOCTL register
    HWREG(base + I2C_O_FIFOCTL) = fifoCtlTmp;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void I2CFlushTxFifo(uint32_t base)
{
    // Check the arguments.
    ASSERT(I2CIsBaseValid(base));

    // Flush TX FIFO
    HWREG(base + I2C_O_FIFOCTL) |= I2C_FIFOCTL_TXFLUSH_EN;

    // Wait until TX FIFO is empty
    while (I2CIsTxFifoEmpty(base) != true) {}

    // Disable TX FIFO flushing
    HWREG(base + I2C_O_FIFOCTL) &= ~I2C_FIFOCTL_TXFLUSH_EN;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void I2CFlushRxFifo(uint32_t base)
{
    // Check the arguments.
    ASSERT(I2CIsBaseValid(base));

    // Flush RX FIFO
    HWREG(base + I2C_O_FIFOCTL) |= I2C_FIFOCTL_RXFLUSH_EN;

    // Wait until RX FIFO is empty
    while (I2CIsRxFifoEmpty(base) != true) {}

    // Disable RX FIFO flushing
    HWREG(base + I2C_O_FIFOCTL) &= ~I2C_FIFOCTL_RXFLUSH_EN;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void I2CFlushFifos(uint32_t base)
{
    // Check the arguments.
    ASSERT(I2CIsBaseValid(base));

    // Flush TX and RX FIFOs
    HWREG(base + I2C_O_FIFOCTL) |= I2C_FIFOCTL_TXFLUSH_EN | I2C_FIFOCTL_RXFLUSH_EN;

    // Wait until both FIFOs are empty.
    while ((HWREG(base + I2C_O_FIFOSR) & (I2C_FIFOSR_TXFIFOCNT_M | I2C_FIFOSR_RXFIFOCNT_M)) !=
            (I2C_FIFOSR_TXFIFOCNT_MAXIMUM | I2C_FIFOSR_RXFIFOCNT_MINIMUM))
    {}

    // Disable TX and RX FIFO flushing
    HWREG(base + I2C_O_FIFOCTL) &= ~(I2C_FIFOCTL_TXFLUSH_EN | I2C_FIFOCTL_RXFLUSH_EN);
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void I2CGetData(uint32_t base, uint8_t *data)
{
    // Check the arguments.
    ASSERT(I2CIsBaseValid(base));

    // Wait until there is data to be read.
    while (I2CIsRxFifoEmpty(base)) {}

    // Read a byte from I2C RX FIFO.
    *data = HWREGB(base + I2C_O_RXDATA);
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE uint32_t I2CGetDataNonBlocking(uint32_t base, uint8_t *data)
{
    // Check the arguments.
    ASSERT(I2CIsBaseValid(base));

    // Check if there is data to be read
    if (I2CIsRxFifoEmpty(base))
    {
        return 0;
    }
    else
    {
        // Read a byte from I2C RX FIFO.
        *data = HWREGB(base + I2C_O_RXDATA);
        return 1;
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void I2CPutData(uint32_t base, uint8_t data)
{
    // Check the arguments.
    ASSERT(I2CIsBaseValid(base));

    // Wait until space is available.
    while (I2CIsTxFifoFull(base)) {}

    // Write the byte.
    HWREGB(base + I2C_O_TXDATA) = data;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE uint32_t I2CPutDataNonBlocking(uint32_t base, uint8_t data)
{
    // Check the arguments.
    ASSERT(I2CIsBaseValid(base));

    // Check if there is space available.
    if (I2CIsTxFifoFull(base))
    {
        return 0;
    }
    else
    {
        // Write the byte.
        HWREGB(base + I2C_O_TXDATA) = data;
        return 1;
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void I2CEnableInt(uint32_t base, uint32_t intFlags)
{
    // Check the arguments.
    ASSERT(I2CIsBaseValid(base));

    // Enable the specified interrupts.
    HWREG(base + I2C_O_EVENT0_IMEN) = intFlags;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void I2CDisableInt(uint32_t base, uint32_t intFlags)
{
    // Check the arguments.
    ASSERT(I2CIsBaseValid(base));

    // Disable the specified interrupts.
    HWREG(base + I2C_O_EVENT0_IMDIS) = intFlags;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void I2CClearInt(uint32_t base, uint32_t intFlags)
{
    // Check the arguments.
    ASSERT(I2CIsBaseValid(base));

    // Clear the specified I2C interrupt sources.
    HWREG(base + I2C_O_EVENT0_IDIS) = intFlags;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE uint32_t I2CIntStatus(uint32_t base, bool masked)
{
    // Check the arguments.
    ASSERT(I2CIsBaseValid(base));

    // Return either the masked interrupt status or the raw interrupt status as
    // requested.
    if (masked)
    {
        return (HWREG(base + I2C_O_EVENT0_MIS));
    }
    else
    {
        return (HWREG(base + I2C_O_EVENT0_RIS));
    }
}

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif

//*****************************************************************************
//
//
//*****************************************************************************

#endif // __I2C_H__