CC35xxDriverLibrary
hw_wsoc_ocla.h
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1 /******************************************************************************
2 * Filename: hw_wsoc_ocla.h
3 *
4 * Description: Defines and prototypes for the WSOC_OCLA peripheral.
5 *
6 * Copyright (c) 2023, Texas Instruments Incorporated
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions are met:
11 *
12 * 1) Redistributions of source code must retain the above copyright notice,
13 * this list of conditions and the following disclaimer.
14 *
15 * 2) Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 *
19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may
20 * be used to endorse or promote products derived from this software without
21 * specific prior written permission.
22 *
23  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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35 ******************************************************************************/
36 #ifndef __HW_WSOC_OCLA_H__
37 #define __HW_WSOC_OCLA_H__
38 /*-------------------------------------------------------------------------------
39 
40 This section defines the register offsets of the WSOC_OCLA component
41 
42 --------------------------------------------------------------------------------- */
43 
44 //Events Mode and Source
45 #define WSOC_OCLA_O_EVTMOD 0x00000000U
46 
47 //OCLA Event A Mask
48 #define WSOC_OCLA_O_AMASK 0x00000004U
49 
50 //OCLA Event A Compare
51 #define WSOC_OCLA_O_ACOMP 0x00000008U
52 
53 //OCLA Event B Mask
54 #define WSOC_OCLA_O_BMASK 0x0000000CU
55 
56 //OCLA Event B Compare
57 #define WSOC_OCLA_O_BCOMP 0x00000010U
58 
59 //OCLA Event C Mask
60 #define WSOC_OCLA_O_CMASK 0x00000014U
61 
62 //OCLA Event C Compare
63 #define WSOC_OCLA_O_CCOMP 0x00000018U
64 
65 //OCLA Event F Mask
66 #define WSOC_OCLA_O_FMASK 0x0000002CU
67 
68 //OCLA Event F Compare
69 #define WSOC_OCLA_O_FCOMP 0x00000030U
70 
71 //make sub trigger from the events (A,B,C,D,E,F)
72 #define WSOC_OCLA_O_SUBTRIGX 0x00000034U
73 
74 //make sub trigger from the events (A,B,C,D,E,F)
75 #define WSOC_OCLA_O_SUBTRIGY 0x00000038U
76 
77 //make sub trigger from the events (A,B,C,D,E,F)
78 #define WSOC_OCLA_O_SUBTRIGZ 0x0000003CU
79 
80 //OCLA Clk Configuration
81 #define WSOC_OCLA_O_CLKCFG 0x00000040U
82 
83 //Triggers
84 #define WSOC_OCLA_O_TRIGS 0x00000044U
85 
86 //OCLA Time
87 #define WSOC_OCLA_O_TIME 0x00000048U
88 
89 //main mode configurations, memory params, and output params
90 #define WSOC_OCLA_O_MODE 0x0000004CU
91 
92 //OCLA Memory Size
93 #define WSOC_OCLA_O_MEMSIZE 0x00000050U
94 
95 //Memory Size After Event
96 #define WSOC_OCLA_O_MEMSIZEEVT 0x00000054U
97 
98 //Memory SW Info
99 #define WSOC_OCLA_O_MEMSWINF 0x00000058U
100 
101 //Hold the pointer to the place in memory which event happened
102 #define WSOC_OCLA_O_STATESTA 0x0000005CU
103 
104 //Read Debug 0
105 #define WSOC_OCLA_O_RDDBG0 0x00000060U
106 
107 //Read Debug 1
108 #define WSOC_OCLA_O_RDDBG1 0x00000064U
109 
110 //Read Max Time
111 #define WSOC_OCLA_O_RDMAXTIME 0x0000006CU
112 
113 //Memory Start Address
114 #define WSOC_OCLA_O_MEMCTL 0x00000070U
115 
116 //OCLA Inject Control
117 #define WSOC_OCLA_O_INJECTCTL 0x00000074U
118 
119 //Debug Port CFG 0
120 #define WSOC_OCLA_O_PORTCFG0 0x00000078U
121 
122 //Debug Port CFG 1
123 #define WSOC_OCLA_O_PORTCFG1 0x0000007CU
124 
125 //Debug Port CFG 2
126 #define WSOC_OCLA_O_PORTCFG2 0x00000080U
127 
128 //Debug Port CFG 3
129 #define WSOC_OCLA_O_PORTCFG3 0x00000084U
130 
131 //Debug Port CFG 4
132 #define WSOC_OCLA_O_PORTCFG4 0x00000088U
133 
134 //Debug Port TP1 or TP2
135 #define WSOC_OCLA_O_TPSEL 0x0000008CU
136 
137 //Debug Port Selector
138 #define WSOC_OCLA_O_PORTSEL 0x00000090U
139 
140 //Debug Out Selector
141 #define WSOC_OCLA_O_OUTSEL 0x00000094U
142 
143 //GPIO Out Value
144 #define WSOC_OCLA_O_OUTVAL 0x00000098U
145 
146 //GPIO Out Value Set
147 #define WSOC_OCLA_O_OUTVALSET 0x0000009CU
148 
149 //GPIO Out Value Clear
150 #define WSOC_OCLA_O_OUTVALCLR 0x000000A0U
151 
152 //GPIO Out Value Toggle
153 #define WSOC_OCLA_O_OUTVALTGL 0x000000A4U
154 
155 //GPIO Out Value Pulse
156 #define WSOC_OCLA_O_OUTVALPLS 0x000000A8U
157 
158 //TSF on Trigger
159 #define WSOC_OCLA_O_TFSONTRG 0x000000B0U
160 
161 
162 
163 /*-----------------------------------REGISTER------------------------------------
164  Register name: EVTMOD
165  Offset name: WSOC_OCLA_O_EVTMOD
166  Relative address: 0x0
167  Description: Events Mode and Source.
168  Default Value: 0x00000000
169 
170  Field: ASRC
171  From..to bits: 0...2
172  DefaultValue: 0x0
173  Access type: read-write
174  Description: Which part of the monitor bus enter event A:
175  0x0. event_a_input = mon_in_en[31:0];
176  0x1. event_a_input = mon_in_en[47:16];
177  0x2. event_a_input = mon_in_en[63:32];
178  0x3. event_a_input = mon_in_en[79:48];
179  0x4. event_a_input = mon_in_en[95:64];
180  0x5. event_a_input = {mon_in_en[95:80], mon_in_en[15:0]};
181 
182 */
183 #define WSOC_OCLA_EVTMOD_ASRC_W 3U
184 #define WSOC_OCLA_EVTMOD_ASRC_M 0x00000007U
185 #define WSOC_OCLA_EVTMOD_ASRC_S 0U
186 /*
187 
188  Field: AMOD
189  From..to bits: 3...3
190  DefaultValue: 0x0
191  Access type: read-write
192  Description: Event A mode:
193 
194  0. Equal
195  1. Great then
196 
197 */
198 #define WSOC_OCLA_EVTMOD_AMOD 0x00000008U
199 #define WSOC_OCLA_EVTMOD_AMOD_M 0x00000008U
200 #define WSOC_OCLA_EVTMOD_AMOD_S 3U
201 /*
202 
203  Field: BSRC
204  From..to bits: 4...6
205  DefaultValue: 0x0
206  Access type: read-write
207  Description: Which part of the monitor bus enter event B:
208  0x0. event_b_input = mon_in_en[31:0];
209  0x1. event_b_input = mon_in_en[47:16];
210  0x2. event_b_input = mon_in_en[63:32];
211  0x3. event_b_input = mon_in_en[79:48];
212  0x4. event_b_input = mon_in_en[95:64];
213  0x5. event_b_input = {mon_in_en[95:80], mon_in_en[15:0]};
214 
215 */
216 #define WSOC_OCLA_EVTMOD_BSRC_W 3U
217 #define WSOC_OCLA_EVTMOD_BSRC_M 0x00000070U
218 #define WSOC_OCLA_EVTMOD_BSRC_S 4U
219 /*
220 
221  Field: BMOD
222  From..to bits: 7...7
223  DefaultValue: 0x0
224  Access type: read-write
225  Description: Event B mode:
226 
227  0. Equal
228  1. Great then
229 
230 */
231 #define WSOC_OCLA_EVTMOD_BMOD 0x00000080U
232 #define WSOC_OCLA_EVTMOD_BMOD_M 0x00000080U
233 #define WSOC_OCLA_EVTMOD_BMOD_S 7U
234 /*
235 
236  Field: CSRC
237  From..to bits: 8...10
238  DefaultValue: 0x0
239  Access type: read-write
240  Description: Which part of the monitor bus enter event C:
241  0x0. event_c_input = mon_in_en[31:0];
242  0x1. event_c_input = mon_in_en[47:16];
243  0x2. event_c_input = mon_in_en[63:32];
244  0x3. event_c_input = mon_in_en[79:48];
245  0x4. event_c_input = mon_in_en[95:64];
246  0x5. event_c_input = {mon_in_en[95:80], mon_in_en[15:0]};
247 
248 */
249 #define WSOC_OCLA_EVTMOD_CSRC_W 3U
250 #define WSOC_OCLA_EVTMOD_CSRC_M 0x00000700U
251 #define WSOC_OCLA_EVTMOD_CSRC_S 8U
252 /*
253 
254  Field: CMOD
255  From..to bits: 11...11
256  DefaultValue: 0x0
257  Access type: read-write
258  Description: Event C mode:
259 
260  0. Equal
261  1. Great then
262 
263 */
264 #define WSOC_OCLA_EVTMOD_CMOD 0x00000800U
265 #define WSOC_OCLA_EVTMOD_CMOD_M 0x00000800U
266 #define WSOC_OCLA_EVTMOD_CMOD_S 11U
267 /*
268 
269  Field: DSRC
270  From..to bits: 12...14
271  DefaultValue: 0x0
272  Access type: read-write
273  Description: Which part of the monitor bus enter event D:
274  0x0. event_d_input = mon_in_en[31:0];
275  0x1. event_d_input = mon_in_en[47:16];
276  0x2. event_d_input = mon_in_en[63:32];
277  0x3. event_d_input = mon_in_en[79:48];
278  0x4. event_d_input = mon_in_en[95:64];
279  0x5. event_d_input = {mon_in_en[95:80], mon_in_en[15:0]};
280 
281 */
282 #define WSOC_OCLA_EVTMOD_DSRC_W 3U
283 #define WSOC_OCLA_EVTMOD_DSRC_M 0x00007000U
284 #define WSOC_OCLA_EVTMOD_DSRC_S 12U
285 /*
286 
287  Field: DMOD
288  From..to bits: 15...15
289  DefaultValue: 0x0
290  Access type: read-write
291  Description: Event D mode:
292 
293  0. Equal
294  1. Great then
295 
296 */
297 #define WSOC_OCLA_EVTMOD_DMOD 0x00008000U
298 #define WSOC_OCLA_EVTMOD_DMOD_M 0x00008000U
299 #define WSOC_OCLA_EVTMOD_DMOD_S 15U
300 /*
301 
302  Field: ESRC
303  From..to bits: 16...18
304  DefaultValue: 0x0
305  Access type: read-write
306  Description: Which part of the monitor bus enter event E:
307  0x0. event_e_input = mon_in_en[31:0];
308  0x1. event_e_input = mon_in_en[47:16];
309  0x2. event_e_input = mon_in_en[63:32];
310  0x3. event_e_input = mon_in_en[79:48];
311  0x4. event_e_input = mon_in_en[95:64];
312  0x5. event_e_input = {mon_in_en[95:80], mon_in_en[15:0]};
313 
314 */
315 #define WSOC_OCLA_EVTMOD_ESRC_W 3U
316 #define WSOC_OCLA_EVTMOD_ESRC_M 0x00070000U
317 #define WSOC_OCLA_EVTMOD_ESRC_S 16U
318 /*
319 
320  Field: FSRC
321  From..to bits: 20...22
322  DefaultValue: 0x0
323  Access type: read-write
324  Description: Which part of the monitor bus enter event F:
325  0x0. event_f_input = mon_in_en[31:0];
326  0x1. event_f_input = mon_in_en[47:16];
327  0x2. event_f_input = mon_in_en[63:32];
328  0x3. event_f_input = mon_in_en[79:48];
329  0x4. event_f_input = mon_in_en[95:64];
330  0x5. event_f_input = {mon_in_en[95:80], mon_in_en[15:0]};
331 
332 */
333 #define WSOC_OCLA_EVTMOD_FSRC_W 3U
334 #define WSOC_OCLA_EVTMOD_FSRC_M 0x00700000U
335 #define WSOC_OCLA_EVTMOD_FSRC_S 20U
336 
337 
338 /*-----------------------------------REGISTER------------------------------------
339  Register name: AMASK
340  Offset name: WSOC_OCLA_O_AMASK
341  Relative address: 0x4
342  Description: OCLA Event A Mask.
343  Default Value: 0x00000000
344 
345  Field: MASK
346  From..to bits: 0...31
347  DefaultValue: 0x0
348  Access type: read-write
349  Description: mask bit which set to 0 is mask
350 
351 */
352 #define WSOC_OCLA_AMASK_MASK_W 32U
353 #define WSOC_OCLA_AMASK_MASK_M 0xFFFFFFFFU
354 #define WSOC_OCLA_AMASK_MASK_S 0U
355 
356 
357 /*-----------------------------------REGISTER------------------------------------
358  Register name: ACOMP
359  Offset name: WSOC_OCLA_O_ACOMP
360  Relative address: 0x8
361  Description: OCLA Event A Compare.
362  Default Value: 0x00000000
363 
364  Field: COMP
365  From..to bits: 0...31
366  DefaultValue: 0x0
367  Access type: read-write
368  Description: Compare value for event A
369 
370 */
371 #define WSOC_OCLA_ACOMP_COMP_W 32U
372 #define WSOC_OCLA_ACOMP_COMP_M 0xFFFFFFFFU
373 #define WSOC_OCLA_ACOMP_COMP_S 0U
374 
375 
376 /*-----------------------------------REGISTER------------------------------------
377  Register name: BMASK
378  Offset name: WSOC_OCLA_O_BMASK
379  Relative address: 0xC
380  Description: OCLA Event B Mask.
381  Default Value: 0x00000000
382 
383  Field: MASK
384  From..to bits: 0...31
385  DefaultValue: 0x0
386  Access type: read-write
387  Description: mask bit which set to 0 is mask
388 
389 */
390 #define WSOC_OCLA_BMASK_MASK_W 32U
391 #define WSOC_OCLA_BMASK_MASK_M 0xFFFFFFFFU
392 #define WSOC_OCLA_BMASK_MASK_S 0U
393 
394 
395 /*-----------------------------------REGISTER------------------------------------
396  Register name: BCOMP
397  Offset name: WSOC_OCLA_O_BCOMP
398  Relative address: 0x10
399  Description: OCLA Event B Compare.
400  Default Value: 0x00000000
401 
402  Field: COMP
403  From..to bits: 0...31
404  DefaultValue: 0x0
405  Access type: read-write
406  Description: Compare value for event B
407 
408 */
409 #define WSOC_OCLA_BCOMP_COMP_W 32U
410 #define WSOC_OCLA_BCOMP_COMP_M 0xFFFFFFFFU
411 #define WSOC_OCLA_BCOMP_COMP_S 0U
412 
413 
414 /*-----------------------------------REGISTER------------------------------------
415  Register name: CMASK
416  Offset name: WSOC_OCLA_O_CMASK
417  Relative address: 0x14
418  Description: OCLA Event C Mask.
419  Default Value: 0x00000000
420 
421  Field: MASK
422  From..to bits: 0...31
423  DefaultValue: 0x0
424  Access type: read-write
425  Description: mask bit which set to 0 is mask
426 
427 */
428 #define WSOC_OCLA_CMASK_MASK_W 32U
429 #define WSOC_OCLA_CMASK_MASK_M 0xFFFFFFFFU
430 #define WSOC_OCLA_CMASK_MASK_S 0U
431 
432 
433 /*-----------------------------------REGISTER------------------------------------
434  Register name: CCOMP
435  Offset name: WSOC_OCLA_O_CCOMP
436  Relative address: 0x18
437  Description: OCLA Event C Compare.
438  Default Value: 0x00000000
439 
440  Field: COMP
441  From..to bits: 0...31
442  DefaultValue: 0x0
443  Access type: read-write
444  Description: Compare value for event C
445 
446 */
447 #define WSOC_OCLA_CCOMP_COMP_W 32U
448 #define WSOC_OCLA_CCOMP_COMP_M 0xFFFFFFFFU
449 #define WSOC_OCLA_CCOMP_COMP_S 0U
450 
451 
452 /*-----------------------------------REGISTER------------------------------------
453  Register name: FMASK
454  Offset name: WSOC_OCLA_O_FMASK
455  Relative address: 0x2C
456  Description: OCLA Event F Mask.
457  Default Value: 0x00000000
458 
459  Field: MASK
460  From..to bits: 0...31
461  DefaultValue: 0x0
462  Access type: read-write
463  Description: mask bit which set to 0 is mask
464 
465 */
466 #define WSOC_OCLA_FMASK_MASK_W 32U
467 #define WSOC_OCLA_FMASK_MASK_M 0xFFFFFFFFU
468 #define WSOC_OCLA_FMASK_MASK_S 0U
469 
470 
471 /*-----------------------------------REGISTER------------------------------------
472  Register name: FCOMP
473  Offset name: WSOC_OCLA_O_FCOMP
474  Relative address: 0x30
475  Description: OCLA Event F Compare.
476  Default Value: 0x00000000
477 
478  Field: COMP
479  From..to bits: 0...31
480  DefaultValue: 0x0
481  Access type: read-write
482  Description: Compare value for event F
483 
484 */
485 #define WSOC_OCLA_FCOMP_COMP_W 32U
486 #define WSOC_OCLA_FCOMP_COMP_M 0xFFFFFFFFU
487 #define WSOC_OCLA_FCOMP_COMP_S 0U
488 
489 
490 /*-----------------------------------REGISTER------------------------------------
491  Register name: SUBTRIGX
492  Offset name: WSOC_OCLA_O_SUBTRIGX
493  Relative address: 0x34
494  Description: make sub trigger from the events (A,B,C,D,E,F)
495  And and not on the events which will case for example:
496  A & B & ~C.
497  For this configure the AND to 6'h7 (C,B,A)
498  and the not to 6'h4 (C)
499  The order of the events are {F,E,D,C,B,A}.
500  Default Value: 0x00000000
501 
502  Field: AND
503  From..to bits: 0...5
504  DefaultValue: 0x0
505  Access type: read-write
506  Description: Which event will be in the and
507 
508 */
509 #define WSOC_OCLA_SUBTRIGX_AND_W 6U
510 #define WSOC_OCLA_SUBTRIGX_AND_M 0x0000003FU
511 #define WSOC_OCLA_SUBTRIGX_AND_S 0U
512 /*
513 
514  Field: NOT
515  From..to bits: 8...13
516  DefaultValue: 0x0
517  Access type: read-write
518  Description: Which event will have not
519 
520 */
521 #define WSOC_OCLA_SUBTRIGX_NOT_W 6U
522 #define WSOC_OCLA_SUBTRIGX_NOT_M 0x00003F00U
523 #define WSOC_OCLA_SUBTRIGX_NOT_S 8U
524 
525 
526 /*-----------------------------------REGISTER------------------------------------
527  Register name: SUBTRIGY
528  Offset name: WSOC_OCLA_O_SUBTRIGY
529  Relative address: 0x38
530  Description: make sub trigger from the events (A,B,C,D,E,F)
531  And and not on the events which will case for example:
532  A & B & ~C.
533  For this configure the AND to 6'h7 (C,B,A)
534  and the not to 6'h4 (C)
535  The order of the events are {F,E,D,C,B,A}.
536  Default Value: 0x00000000
537 
538  Field: AND
539  From..to bits: 0...5
540  DefaultValue: 0x0
541  Access type: read-write
542  Description: Which event will be in the and
543 
544 */
545 #define WSOC_OCLA_SUBTRIGY_AND_W 6U
546 #define WSOC_OCLA_SUBTRIGY_AND_M 0x0000003FU
547 #define WSOC_OCLA_SUBTRIGY_AND_S 0U
548 /*
549 
550  Field: NOT
551  From..to bits: 8...13
552  DefaultValue: 0x0
553  Access type: read-write
554  Description: Which event will have not
555 
556 */
557 #define WSOC_OCLA_SUBTRIGY_NOT_W 6U
558 #define WSOC_OCLA_SUBTRIGY_NOT_M 0x00003F00U
559 #define WSOC_OCLA_SUBTRIGY_NOT_S 8U
560 
561 
562 /*-----------------------------------REGISTER------------------------------------
563  Register name: SUBTRIGZ
564  Offset name: WSOC_OCLA_O_SUBTRIGZ
565  Relative address: 0x3C
566  Description: make sub trigger from the events (A,B,C,D,E,F)
567  And and not on the events which will case for example:
568  A & B & ~C.
569  For this configure the AND to 6'h7 (C,B,A)
570  and the not to 6'h4 (C)
571  The order of the events are {F,E,D,C,B,A}.
572  Default Value: 0x00000000
573 
574  Field: AND
575  From..to bits: 0...5
576  DefaultValue: 0x0
577  Access type: read-write
578  Description: Which event will be in the and
579 
580 */
581 #define WSOC_OCLA_SUBTRIGZ_AND_W 6U
582 #define WSOC_OCLA_SUBTRIGZ_AND_M 0x0000003FU
583 #define WSOC_OCLA_SUBTRIGZ_AND_S 0U
584 /*
585 
586  Field: NOT
587  From..to bits: 8...13
588  DefaultValue: 0x0
589  Access type: read-write
590  Description: Which event will have not
591 
592 */
593 #define WSOC_OCLA_SUBTRIGZ_NOT_W 6U
594 #define WSOC_OCLA_SUBTRIGZ_NOT_M 0x00003F00U
595 #define WSOC_OCLA_SUBTRIGZ_NOT_S 8U
596 
597 
598 /*-----------------------------------REGISTER------------------------------------
599  Register name: CLKCFG
600  Offset name: WSOC_OCLA_O_CLKCFG
601  Relative address: 0x40
602  Description: OCLA Clk Configuration.
603  Default Value: 0x00000000
604 
605  Field: MOD
606  From..to bits: 0...1
607  DefaultValue: 0x0
608  Access type: read-write
609  Description: Clock Mode:
610 
611  0. No CLK
612  1. CLK40
613  2. RF CLK
614  3. Illegal
615 
616  NOTE: move between CLK should be through zero (No CLK)
617 
618 */
619 #define WSOC_OCLA_CLKCFG_MOD_W 2U
620 #define WSOC_OCLA_CLKCFG_MOD_M 0x00000003U
621 #define WSOC_OCLA_CLKCFG_MOD_S 0U
622 
623 
624 /*-----------------------------------REGISTER------------------------------------
625  Register name: TRIGS
626  Offset name: WSOC_OCLA_O_TRIGS
627  Relative address: 0x44
628  Description: Triggers.
629 
630  configure the two triggers
631  Default Value: 0x00000000
632 
633  Field: AND
634  From..to bits: 0...3
635  DefaultValue: 0x0
636  Access type: read-write
637  Description: Which of the sub triggers will make the trigger1
638  The sub_triggers order is {W,Z,Y,X}
639  to make ~X & Y use 4'h3.
640 
641 */
642 #define WSOC_OCLA_TRIGS_AND_W 4U
643 #define WSOC_OCLA_TRIGS_AND_M 0x0000000FU
644 #define WSOC_OCLA_TRIGS_AND_S 0U
645 /*
646 
647  Field: INV
648  From..to bits: 4...7
649  DefaultValue: 0x0
650  Access type: read-write
651  Description: Which of the sub triggers will be invert for trigger1.
652  The sub_triggers order is {W,Z,Y,X}
653  to make ~X & Y use 4'h1
654 
655 */
656 #define WSOC_OCLA_TRIGS_INV_W 4U
657 #define WSOC_OCLA_TRIGS_INV_M 0x000000F0U
658 #define WSOC_OCLA_TRIGS_INV_S 4U
659 /*
660 
661  Field: TAND
662  From..to bits: 8...11
663  DefaultValue: 0x0
664  Access type: read-write
665  Description: Which of the sub triggers will make the trigger2
666  The sub_triggers order is {W,Z,Y,X}
667  to make ~X & Y use 4'h3.
668 
669 */
670 #define WSOC_OCLA_TRIGS_TAND_W 4U
671 #define WSOC_OCLA_TRIGS_TAND_M 0x00000F00U
672 #define WSOC_OCLA_TRIGS_TAND_S 8U
673 /*
674 
675  Field: TINV
676  From..to bits: 12...15
677  DefaultValue: 0x0
678  Access type: read-write
679  Description: which of the sub triggers will be invert for trigger1.
680  The sub_triggers order is {W,Z,Y,X}
681  to make ~X & Y use 4'h1
682 
683 */
684 #define WSOC_OCLA_TRIGS_TINV_W 4U
685 #define WSOC_OCLA_TRIGS_TINV_M 0x0000F000U
686 #define WSOC_OCLA_TRIGS_TINV_S 12U
687 
688 
689 /*-----------------------------------REGISTER------------------------------------
690  Register name: TIME
691  Offset name: WSOC_OCLA_O_TIME
692  Relative address: 0x48
693  Description: OCLA Time.
694  Default Value: 0x00000000
695 
696  Field: TIME
697  From..to bits: 0...25
698  DefaultValue: 0x0
699  Access type: read-write
700  Description: use for:
701  1. For time between events for mode which check time between two events.
702  2. Number of event for modes that check number of event.
703 
704 */
705 #define WSOC_OCLA_TIME_TIME_W 26U
706 #define WSOC_OCLA_TIME_TIME_M 0x03FFFFFFU
707 #define WSOC_OCLA_TIME_TIME_S 0U
708 
709 
710 /*-----------------------------------REGISTER------------------------------------
711  Register name: MODE
712  Offset name: WSOC_OCLA_O_MODE
713  Relative address: 0x4C
714  Description: main mode configurations, memory params, and output params.
715  Default Value: 0x00000000
716 
717  Field: IQMOD
718  From..to bits: 0...4
719  DefaultValue: 0x0
720  Access type: read-write
721  Description: // 0: event1 happened
722  // 1: check time between last event_a to first event_b if it's bigger then mem_time event
723  // 2: check time between last event_a high to first event_b high if it's smaller then mem_time event
724  // 3: check the time from first event a to first event b if it's bigger then mem_time event
725  // 4: check the time from first event a to first event b if it's smaller then mem_time event
726  // 5: event1 happened T times
727  // 6: timestamp mode save events and timestamp
728  // 7: event1 happened but event2 didn't happened for T cycles
729  // 8: trigger A happened and next cycle trigger B happened sample monitor after timestamp once (as timestamp mode)
730  // 9: SW event when the mem_sw_info == 16'hffff
731  // 10: Save monitor bus and time stamp when monitor change masking from F trigger
732  // 11: Save T amount of samples when event1 happened
733  // 12: Save each time one of the trigger (A-F) happened
734  // 13: IQ Save 64 bit every cycle - 32LSB monitor bus,
735  // 32 MSB bits are 32 LSB from IQ bus
736  // 14: IQ save
737  // 32/64/128 bits IQ save mode
738  // If (mem_data_save_mode = 0)
739  // case (mem_data_to_save)
740  // 0: ocla_dout[63:0] <= #1 ocla_iq_save_in[63:0];
741  // 1: ocla_dout[63:0] <= #1 ocla_iq_save_in[127:64];
742  // 2: ocla_dout[127:0] <= #1 ocla_iq_save_in[127:0]; // save each cycle
743  // If (mem_data_save_mode = 1)
744  // case (mem_data_to_save)
745  // 0: ocla_dout[31:0] <= #1 ocla_iq_save_in[31:0];
746  // 1: ocla_dout[31:0] <= #1 ocla_iq_save_in[63:32];
747  // 2: ocla_dout[31:0] <= #1 ocla_iq_save_in[95:64];
748  // 3: ocla_dout[31:0] <= #1 ocla_iq_save_in[127:96];
749  // 15: IQ inject
750  // 16: ocla debug write to the RAM {14'h3333, ocla_addr[17:0], 14'h2222, ocla_addr[17:0],
751  14'h1111, ocla_addr[17:0], 14'h0000, ocla_addr[17:0]}
752 
753 */
754 #define WSOC_OCLA_MODE_IQMOD_W 5U
755 #define WSOC_OCLA_MODE_IQMOD_M 0x0000001FU
756 #define WSOC_OCLA_MODE_IQMOD_S 0U
757 /*
758 
759  Field: EN
760  From..to bits: 5...5
761  DefaultValue: 0x0
762  Access type: read-write
763  Description: Enable the OCLA should be the last write
764 
765 */
766 #define WSOC_OCLA_MODE_EN 0x00000020U
767 #define WSOC_OCLA_MODE_EN_M 0x00000020U
768 #define WSOC_OCLA_MODE_EN_S 5U
769 /*
770 
771  Field: DATAMOD
772  From..to bits: 8...9
773  DefaultValue: 0x0
774  Access type: read-write
775  Description: // 0: save 64bits each cycle
776  // 1: save 32bits each cycle (write to memory every two cycles)
777  // 2: save 16LSB each cycle (write to the ram every 4 cycles)
778  // 3: save 8LSB each cycle (write to the ram every 8 cycles)
779 
780  // for IQ save/inject modes
781  // look at mode description.
782 
783 */
784 #define WSOC_OCLA_MODE_DATAMOD_W 2U
785 #define WSOC_OCLA_MODE_DATAMOD_M 0x00000300U
786 #define WSOC_OCLA_MODE_DATAMOD_S 8U
787 /*
788 
789  Field: PARAMMOD
790  From..to bits: 10...12
791  DefaultValue: 0x0
792  Access type: read-write
793  Description: not in use.
794 
795 */
796 #define WSOC_OCLA_MODE_PARAMMOD_W 3U
797 #define WSOC_OCLA_MODE_PARAMMOD_M 0x00001C00U
798 #define WSOC_OCLA_MODE_PARAMMOD_S 10U
799 /*
800 
801  Field: SWTCHIGH
802  From..to bits: 14...14
803  DefaultValue: 0x0
804  Access type: read-write
805  Description: At mode which switch iq with din (bit 15) take bits from 127 to 32 when this bit is one otherwise take 97:0.
806 
807 */
808 #define WSOC_OCLA_MODE_SWTCHIGH 0x00004000U
809 #define WSOC_OCLA_MODE_SWTCHIGH_M 0x00004000U
810 #define WSOC_OCLA_MODE_SWTCHIGH_S 14U
811 /*
812 
813  Field: SWTCIQDIN
814  From..to bits: 15...15
815  DefaultValue: 0x0
816  Access type: read-write
817  Description: Switch between IQ_SAVE data in and debug bus in.
818  This enable to do all triggers and save data on iq_in.
819 
820 */
821 #define WSOC_OCLA_MODE_SWTCIQDIN 0x00008000U
822 #define WSOC_OCLA_MODE_SWTCIQDIN_M 0x00008000U
823 #define WSOC_OCLA_MODE_SWTCIQDIN_S 15U
824 /*
825 
826  Field: D2SAVE
827  From..to bits: 16...17
828  DefaultValue: 0x0
829  Access type: read-write
830  Description: This do shift down to the monitor which saved (not the triggers)
831 
832  0: monitor as it is.
833  1: Shift right 16 bits
834  for mode of 32 bits monitor[47:16]
835  for mode of 16 bits monitor[31:16]
836  for mode of 8 bits monitor[24:16].
837  2: Shift right 32 bits
838  for mode of 32 bits monitor[63:32]
839  for mode of 16 bits monitor[47:32]
840  for mode of 8 bits monitor[39:32].
841  3: Shift right 64 bits
842  Don't use in 64bits mode
843  for mode of 32 bits monitor[95:64]
844  for mode of 16 bits monitor[79:64]
845  for mode of 8 bits monitor[71:64].
846 
847 
848  for IQ save mode 14
849  0 : output is iq_save_in[63:0]
850  1: output is iq_save_in[127:64]
851  2: output is iq_save_in[127:0]
852 
853 */
854 #define WSOC_OCLA_MODE_D2SAVE_W 2U
855 #define WSOC_OCLA_MODE_D2SAVE_M 0x00030000U
856 #define WSOC_OCLA_MODE_D2SAVE_S 16U
857 /*
858 
859  Field: ADDRSW2D
860  From..to bits: 22...22
861  DefaultValue: 0x0
862  Access type: read-write
863  Description: Save the mem_sw on the bits [31:24]
864 
865 */
866 #define WSOC_OCLA_MODE_ADDRSW2D 0x00400000U
867 #define WSOC_OCLA_MODE_ADDRSW2D_M 0x00400000U
868 #define WSOC_OCLA_MODE_ADDRSW2D_S 22U
869 /*
870 
871  Field: MAXMIN
872  From..to bits: 23...23
873  DefaultValue: 0x0
874  Access type: read-write
875  Description: For max_time function can change it to min time by:
876  max = 0, min = 1.
877 
878 */
879 #define WSOC_OCLA_MODE_MAXMIN 0x00800000U
880 #define WSOC_OCLA_MODE_MAXMIN_M 0x00800000U
881 #define WSOC_OCLA_MODE_MAXMIN_S 23U
882 
883 
884 /*-----------------------------------REGISTER------------------------------------
885  Register name: MEMSIZE
886  Offset name: WSOC_OCLA_O_MEMSIZE
887  Relative address: 0x50
888  Description: OCLA Memory Size.
889  Default Value: 0x00000000
890 
891  Field: SIZE
892  From..to bits: 0...7
893  DefaultValue: 0x0
894  Access type: read-write
895  Description: The last address in the memory OCLA use.
896  this is the 8 MSB out of 18 bits of 128bit wide lines.
897  (concatenated with 0x3FF to form the last address).
898 
899 */
900 #define WSOC_OCLA_MEMSIZE_SIZE_W 8U
901 #define WSOC_OCLA_MEMSIZE_SIZE_M 0x000000FFU
902 #define WSOC_OCLA_MEMSIZE_SIZE_S 0U
903 
904 
905 /*-----------------------------------REGISTER------------------------------------
906  Register name: MEMSIZEEVT
907  Offset name: WSOC_OCLA_O_MEMSIZEEVT
908  Relative address: 0x54
909  Description: Memory Size After Event.
910  Default Value: 0x00000000
911 
912  Field: SIZE
913  From..to bits: 0...17
914  DefaultValue: 0x0
915  Access type: read-write
916  Description: Number of writes (128bit wide each) to the memory after the event
917 
918 */
919 #define WSOC_OCLA_MEMSIZEEVT_SIZE_W 18U
920 #define WSOC_OCLA_MEMSIZEEVT_SIZE_M 0x0003FFFFU
921 #define WSOC_OCLA_MEMSIZEEVT_SIZE_S 0U
922 
923 
924 /*-----------------------------------REGISTER------------------------------------
925  Register name: MEMSWINF
926  Offset name: WSOC_OCLA_O_MEMSWINF
927  Relative address: 0x58
928  Description: Memory SW Info.
929  Register which write to the memory as part of the data for SW HW alignment.
930  can also trigger an event to start OCLA recording.
931  Default Value: 0x00000000
932 
933  Field: SWINFO
934  From..to bits: 0...15
935  DefaultValue: 0x0
936  Access type: read-write
937  Description: Data save in memory .
938  not in mode : 6 , 10.
939  At mode of 64bits save it as MSB when en is high.
940 
941 */
942 #define WSOC_OCLA_MEMSWINF_SWINFO_W 16U
943 #define WSOC_OCLA_MEMSWINF_SWINFO_M 0x0000FFFFU
944 #define WSOC_OCLA_MEMSWINF_SWINFO_S 0U
945 /*
946 
947  Field: EN
948  From..to bits: 16...16
949  DefaultValue: 0x0
950  Access type: read-write
951  Description: When this bit is one and at ocla mode of not 6, 10 save the data.
952 
953 */
954 #define WSOC_OCLA_MEMSWINF_EN 0x00010000U
955 #define WSOC_OCLA_MEMSWINF_EN_M 0x00010000U
956 #define WSOC_OCLA_MEMSWINF_EN_S 16U
957 /*
958 
959  Field: TRIG
960  From..to bits: 17...17
961  DefaultValue: 0x0
962  Access type: read-write
963  Description: raise bit to issue sw trigger.
964 
965 */
966 #define WSOC_OCLA_MEMSWINF_TRIG 0x00020000U
967 #define WSOC_OCLA_MEMSWINF_TRIG_M 0x00020000U
968 #define WSOC_OCLA_MEMSWINF_TRIG_S 17U
969 /*
970 
971  Field: SAMP
972  From..to bits: 18...18
973  DefaultValue: 0x0
974  Access type: read-write
975  Description: signal to force re-sampling of the sw_info data into the recorded bus,
976 
977 */
978 #define WSOC_OCLA_MEMSWINF_SAMP 0x00040000U
979 #define WSOC_OCLA_MEMSWINF_SAMP_M 0x00040000U
980 #define WSOC_OCLA_MEMSWINF_SAMP_S 18U
981 
982 
983 /*-----------------------------------REGISTER------------------------------------
984  Register name: STATESTA
985  Offset name: WSOC_OCLA_O_STATESTA
986  Relative address: 0x5C
987  Description: Hold the pointer to the place in memory which event happened
988  Default Value: 0x00000008
989 
990  Field: INTRS
991  From..to bits: 0...2
992  DefaultValue: 0x0
993  Access type: read-only
994  Description: To read the OCLA state
995 
996  ocla_mem_phase[1] - before or after the event
997  event_t_reg,
998  event_reg
999 
1000 */
1001 #define WSOC_OCLA_STATESTA_INTRS_W 3U
1002 #define WSOC_OCLA_STATESTA_INTRS_M 0x00000007U
1003 #define WSOC_OCLA_STATESTA_INTRS_S 0U
1004 /*
1005 
1006  Field: FIRSTFILL
1007  From..to bits: 3...3
1008  DefaultValue: 0x1
1009  Access type: read-only
1010  Description: Indicates if this is the first time that the RAM is fill and therefore part of the RAM is unknown.
1011  This value should be read when OCLA is finished working, before disabling the OCLA, because it is reset when OCLA is disabled.
1012 
1013 */
1014 #define WSOC_OCLA_STATESTA_FIRSTFILL 0x00000008U
1015 #define WSOC_OCLA_STATESTA_FIRSTFILL_M 0x00000008U
1016 #define WSOC_OCLA_STATESTA_FIRSTFILL_S 3U
1017 /*
1018 
1019  Field: DATEVT
1020  From..to bits: 4...7
1021  DefaultValue: 0x0
1022  Access type: read-only
1023  Description: This is as LSB of the event_ptr when use mode other then 64bits
1024  0 event happened when the building of the 64bits was full.
1025  1 event happened when the building of the 64 bits was on 8 bits.
1026  2 event happened when the building of the 64 bits was on 16 bits.
1027  ...
1028 
1029 */
1030 #define WSOC_OCLA_STATESTA_DATEVT_W 4U
1031 #define WSOC_OCLA_STATESTA_DATEVT_M 0x000000F0U
1032 #define WSOC_OCLA_STATESTA_DATEVT_S 4U
1033 /*
1034 
1035  Field: EVTPTR
1036  From..to bits: 8...25
1037  DefaultValue: 0x0
1038  Access type: read-only
1039  Description: the address of the memory when event happened.
1040 
1041 */
1042 #define WSOC_OCLA_STATESTA_EVTPTR_W 18U
1043 #define WSOC_OCLA_STATESTA_EVTPTR_M 0x03FFFF00U
1044 #define WSOC_OCLA_STATESTA_EVTPTR_S 8U
1045 /*
1046 
1047  Field: STATE
1048  From..to bits: 26...27
1049  DefaultValue: 0x0
1050  Access type: read-only
1051  Description: State machine:
1052  0: looking for the event.
1053  1: event found.
1054  2: finish.
1055 
1056 */
1057 #define WSOC_OCLA_STATESTA_STATE_W 2U
1058 #define WSOC_OCLA_STATESTA_STATE_M 0x0C000000U
1059 #define WSOC_OCLA_STATESTA_STATE_S 26U
1060 
1061 
1062 /*-----------------------------------REGISTER------------------------------------
1063  Register name: RDDBG0
1064  Offset name: WSOC_OCLA_O_RDDBG0
1065  Relative address: 0x60
1066  Description: Read Debug 0.
1067 
1068  Read the debug bus enter to OCLA 32 LSB
1069  Default Value: 0x00000000
1070 
1071  Field: 31TO0
1072  From..to bits: 0...31
1073  DefaultValue: 0x0
1074  Access type: read-only
1075  Description: 32 LSBs
1076 
1077 */
1078 #define WSOC_OCLA_RDDBG0_31TO0_W 32U
1079 #define WSOC_OCLA_RDDBG0_31TO0_M 0xFFFFFFFFU
1080 #define WSOC_OCLA_RDDBG0_31TO0_S 0U
1081 
1082 
1083 /*-----------------------------------REGISTER------------------------------------
1084  Register name: RDDBG1
1085  Offset name: WSOC_OCLA_O_RDDBG1
1086  Relative address: 0x64
1087  Description: Read Debug 1.
1088 
1089  Read the debug bus enter to OCLA 63-32
1090  Default Value: 0x00000000
1091 
1092  Field: 63TO32
1093  From..to bits: 0...31
1094  DefaultValue: 0x0
1095  Access type: read-only
1096  Description: 63 to 32 Bits.
1097 
1098 */
1099 #define WSOC_OCLA_RDDBG1_63TO32_W 32U
1100 #define WSOC_OCLA_RDDBG1_63TO32_M 0xFFFFFFFFU
1101 #define WSOC_OCLA_RDDBG1_63TO32_S 0U
1102 
1103 
1104 /*-----------------------------------REGISTER------------------------------------
1105  Register name: RDMAXTIME
1106  Offset name: WSOC_OCLA_O_RDMAXTIME
1107  Relative address: 0x6C
1108  Description: Read Max Time.
1109  Default Value: 0x00000000
1110 
1111  Field: MAXTIME
1112  From..to bits: 0...25
1113  DefaultValue: 0x0
1114  Access type: read-only
1115  Description: Value of the counter of max/min read
1116 
1117 */
1118 #define WSOC_OCLA_RDMAXTIME_MAXTIME_W 26U
1119 #define WSOC_OCLA_RDMAXTIME_MAXTIME_M 0x03FFFFFFU
1120 #define WSOC_OCLA_RDMAXTIME_MAXTIME_S 0U
1121 
1122 
1123 /*-----------------------------------REGISTER------------------------------------
1124  Register name: MEMCTL
1125  Offset name: WSOC_OCLA_O_MEMCTL
1126  Relative address: 0x70
1127  Description: Memory Start Address.
1128  Default Value: 0x00000000
1129 
1130  Field: STARTADDR
1131  From..to bits: 0...7
1132  DefaultValue: 0x0
1133  Access type: read-write
1134  Description: Which address the RAM start, change only for the 8 MSB, the 10 LSB is always 0.
1135 
1136 */
1137 #define WSOC_OCLA_MEMCTL_STARTADDR_W 8U
1138 #define WSOC_OCLA_MEMCTL_STARTADDR_M 0x000000FFU
1139 #define WSOC_OCLA_MEMCTL_STARTADDR_S 0U
1140 /*
1141 
1142  Field: SAMPRATE
1143  From..to bits: 8...12
1144  DefaultValue: 0x0
1145  Access type: read-write
1146  Description: Sample to the RAM once each X times
1147 
1148 */
1149 #define WSOC_OCLA_MEMCTL_SAMPRATE_W 5U
1150 #define WSOC_OCLA_MEMCTL_SAMPRATE_M 0x00001F00U
1151 #define WSOC_OCLA_MEMCTL_SAMPRATE_S 8U
1152 
1153 
1154 /*-----------------------------------REGISTER------------------------------------
1155  Register name: INJECTCTL
1156  Offset name: WSOC_OCLA_O_INJECTCTL
1157  Relative address: 0x74
1158  Description: OCLA Inject Control.
1159  Default Value: 0x00000000
1160 
1161  Field: START
1162  From..to bits: 0...0
1163  DefaultValue: 0x0
1164  Access type: write-only
1165  Description: Start INJECT
1166 
1167 */
1168 #define WSOC_OCLA_INJECTCTL_START 0x00000001U
1169 #define WSOC_OCLA_INJECTCTL_START_M 0x00000001U
1170 #define WSOC_OCLA_INJECTCTL_START_S 0U
1171 /*
1172 
1173  Field: STOP
1174  From..to bits: 1...1
1175  DefaultValue: 0x0
1176  Access type: write-only
1177  Description: Which address the RAM start, change only for the 8 MSB, the 10 LSB is always 0.
1178 
1179 */
1180 #define WSOC_OCLA_INJECTCTL_STOP 0x00000002U
1181 #define WSOC_OCLA_INJECTCTL_STOP_M 0x00000002U
1182 #define WSOC_OCLA_INJECTCTL_STOP_S 1U
1183 /*
1184 
1185  Field: MODE
1186  From..to bits: 16...16
1187  DefaultValue: 0x0
1188  Access type: read-write
1189  Description: Inject Mode:
1190 
1191  0. Single INJECT mode (Stop when Address=Max address)
1192  1. Multi INJECT mode (stop when Wr to "stop" field)
1193 
1194 */
1195 #define WSOC_OCLA_INJECTCTL_MODE 0x00010000U
1196 #define WSOC_OCLA_INJECTCTL_MODE_M 0x00010000U
1197 #define WSOC_OCLA_INJECTCTL_MODE_S 16U
1198 
1199 
1200 /*-----------------------------------REGISTER------------------------------------
1201  Register name: PORTCFG0
1202  Offset name: WSOC_OCLA_O_PORTCFG0
1203  Relative address: 0x78
1204  Description: Debug Port CFG 0.
1205  Default Value: 0xAAAAAAAA
1206 
1207  Field: BIT0SEL
1208  From..to bits: 0...31
1209  DefaultValue: 0xAAAAAAAA
1210  Access type: read-write
1211  Description: Bit 0.
1212 
1213 */
1214 #define WSOC_OCLA_PORTCFG0_BIT0SEL_W 32U
1215 #define WSOC_OCLA_PORTCFG0_BIT0SEL_M 0xFFFFFFFFU
1216 #define WSOC_OCLA_PORTCFG0_BIT0SEL_S 0U
1217 
1218 
1219 /*-----------------------------------REGISTER------------------------------------
1220  Register name: PORTCFG1
1221  Offset name: WSOC_OCLA_O_PORTCFG1
1222  Relative address: 0x7C
1223  Description: Debug Port CFG 1.
1224  Default Value: 0xCCCCCCCC
1225 
1226  Field: BIT1SEL
1227  From..to bits: 0...31
1228  DefaultValue: 0xCCCCCCCC
1229  Access type: read-write
1230  Description: Bit 1.
1231 
1232 */
1233 #define WSOC_OCLA_PORTCFG1_BIT1SEL_W 32U
1234 #define WSOC_OCLA_PORTCFG1_BIT1SEL_M 0xFFFFFFFFU
1235 #define WSOC_OCLA_PORTCFG1_BIT1SEL_S 0U
1236 
1237 
1238 /*-----------------------------------REGISTER------------------------------------
1239  Register name: PORTCFG2
1240  Offset name: WSOC_OCLA_O_PORTCFG2
1241  Relative address: 0x80
1242  Description: Debug Port CFG 2.
1243  Default Value: 0xF0F0F0F0
1244 
1245  Field: BIT2SEL
1246  From..to bits: 0...31
1247  DefaultValue: 0xF0F0F0F0
1248  Access type: read-write
1249  Description: Bit 2.
1250 
1251 */
1252 #define WSOC_OCLA_PORTCFG2_BIT2SEL_W 32U
1253 #define WSOC_OCLA_PORTCFG2_BIT2SEL_M 0xFFFFFFFFU
1254 #define WSOC_OCLA_PORTCFG2_BIT2SEL_S 0U
1255 
1256 
1257 /*-----------------------------------REGISTER------------------------------------
1258  Register name: PORTCFG3
1259  Offset name: WSOC_OCLA_O_PORTCFG3
1260  Relative address: 0x84
1261  Description: Debug Port CFG 3.
1262  Default Value: 0xFF00FF00
1263 
1264  Field: BIT3SEL
1265  From..to bits: 0...31
1266  DefaultValue: 0xFF00FF00
1267  Access type: read-write
1268  Description: Bit 3.
1269 
1270 */
1271 #define WSOC_OCLA_PORTCFG3_BIT3SEL_W 32U
1272 #define WSOC_OCLA_PORTCFG3_BIT3SEL_M 0xFFFFFFFFU
1273 #define WSOC_OCLA_PORTCFG3_BIT3SEL_S 0U
1274 
1275 
1276 /*-----------------------------------REGISTER------------------------------------
1277  Register name: PORTCFG4
1278  Offset name: WSOC_OCLA_O_PORTCFG4
1279  Relative address: 0x88
1280  Description: Debug Port CFG 4.
1281  Default Value: 0xFFFF0000
1282 
1283  Field: BIT4SEL
1284  From..to bits: 0...31
1285  DefaultValue: 0xFFFF0000
1286  Access type: read-write
1287  Description: Bit 4.
1288 
1289 */
1290 #define WSOC_OCLA_PORTCFG4_BIT4SEL_W 32U
1291 #define WSOC_OCLA_PORTCFG4_BIT4SEL_M 0xFFFFFFFFU
1292 #define WSOC_OCLA_PORTCFG4_BIT4SEL_S 0U
1293 
1294 
1295 /*-----------------------------------REGISTER------------------------------------
1296  Register name: TPSEL
1297  Offset name: WSOC_OCLA_O_TPSEL
1298  Relative address: 0x8C
1299  Description: Debug Port TP1 or TP2.
1300  Default Value: 0x00000000
1301 
1302  Field: SEL
1303  From..to bits: 0...31
1304  DefaultValue: 0x0
1305  Access type: read-write
1306  Description: Each bit select which TP1 or TP2 would connect to OCLA bus bits[63:32]
1307 
1308  0. select TP2
1309  1. select TP1
1310 
1311  Note: OCLA bus [31:0] is TP1
1312 
1313 */
1314 #define WSOC_OCLA_TPSEL_SEL_W 32U
1315 #define WSOC_OCLA_TPSEL_SEL_M 0xFFFFFFFFU
1316 #define WSOC_OCLA_TPSEL_SEL_S 0U
1317 
1318 
1319 /*-----------------------------------REGISTER------------------------------------
1320  Register name: PORTSEL
1321  Offset name: WSOC_OCLA_O_PORTSEL
1322  Relative address: 0x90
1323  Description: Debug Port Selector.
1324  Default Value: 0x00000000
1325 
1326  Field: TP1SEL
1327  From..to bits: 0...2
1328  DefaultValue: 0x0
1329  Access type: read-write
1330  Description: Select which debug port used by OCLA for TP1 --> [31:0]
1331 
1332  0x0. select PHY Debug Port
1333  0x1. select WSOC Debug Port
1334  0x2. select TOP Debug Port
1335  0x3. select BLE Debug Port
1336  0x4. select Peripheral Debug Port
1337 
1338 */
1339 #define WSOC_OCLA_PORTSEL_TP1SEL_W 3U
1340 #define WSOC_OCLA_PORTSEL_TP1SEL_M 0x00000007U
1341 #define WSOC_OCLA_PORTSEL_TP1SEL_S 0U
1342 /*
1343 
1344  Field: TP2SEL
1345  From..to bits: 8...10
1346  DefaultValue: 0x0
1347  Access type: read-write
1348  Description: Select which debug port used by OCLA for TP2 --> [63:32]
1349 
1350  0x0. select PHY Debug Port
1351  0x1. select WSOC Debug Port
1352  0x2. select TOP Debug Port
1353  0x3. select BLE Debug Port
1354  0x4. select Peripheral Debug Port
1355 
1356 */
1357 #define WSOC_OCLA_PORTSEL_TP2SEL_W 3U
1358 #define WSOC_OCLA_PORTSEL_TP2SEL_M 0x00000700U
1359 #define WSOC_OCLA_PORTSEL_TP2SEL_S 8U
1360 
1361 
1362 /*-----------------------------------REGISTER------------------------------------
1363  Register name: OUTSEL
1364  Offset name: WSOC_OCLA_O_OUTSEL
1365  Relative address: 0x94
1366  Description: Debug Out Selector.
1367 
1368  select if debug port output is connected to GPIO values (OCP mapped register) or to debug port.
1369  Default Value: NA
1370 
1371  Field: SEL
1372  From..to bits: 0...31
1373  DefaultValue: NA
1374  Access type: read-write
1375  Description: per bit selection
1376 
1377  0. GPIO
1378  1. debug port
1379 
1380 */
1381 #define WSOC_OCLA_OUTSEL_SEL_W 32U
1382 #define WSOC_OCLA_OUTSEL_SEL_M 0xFFFFFFFFU
1383 #define WSOC_OCLA_OUTSEL_SEL_S 0U
1384 
1385 
1386 /*-----------------------------------REGISTER------------------------------------
1387  Register name: OUTVAL
1388  Offset name: WSOC_OCLA_O_OUTVAL
1389  Relative address: 0x98
1390  Description: GPIO Out Value.
1391  Default Value: NA
1392 
1393  Field: VAL
1394  From..to bits: 0...31
1395  DefaultValue: NA
1396  Access type: read-write
1397  Description: GPIO out read/write value.
1398 
1399 */
1400 #define WSOC_OCLA_OUTVAL_VAL_W 32U
1401 #define WSOC_OCLA_OUTVAL_VAL_M 0xFFFFFFFFU
1402 #define WSOC_OCLA_OUTVAL_VAL_S 0U
1403 
1404 
1405 /*-----------------------------------REGISTER------------------------------------
1406  Register name: OUTVALSET
1407  Offset name: WSOC_OCLA_O_OUTVALSET
1408  Relative address: 0x9C
1409  Description: GPIO Out Value Set.
1410  Default Value: NA
1411 
1412  Field: SET
1413  From..to bits: 0...31
1414  DefaultValue: NA
1415  Access type: read-write
1416  Description: writing 1 to a bit will set the [OUTVAL.VAL]. writing 0 is ignored
1417 
1418 */
1419 #define WSOC_OCLA_OUTVALSET_SET_W 32U
1420 #define WSOC_OCLA_OUTVALSET_SET_M 0xFFFFFFFFU
1421 #define WSOC_OCLA_OUTVALSET_SET_S 0U
1422 
1423 
1424 /*-----------------------------------REGISTER------------------------------------
1425  Register name: OUTVALCLR
1426  Offset name: WSOC_OCLA_O_OUTVALCLR
1427  Relative address: 0xA0
1428  Description: GPIO Out Value Clear.
1429  Default Value: NA
1430 
1431  Field: CLR
1432  From..to bits: 0...31
1433  DefaultValue: NA
1434  Access type: read-write
1435  Description: writing 1 to a bit will clr a bit [OUTVAL.VAL]
1436 
1437 */
1438 #define WSOC_OCLA_OUTVALCLR_CLR_W 32U
1439 #define WSOC_OCLA_OUTVALCLR_CLR_M 0xFFFFFFFFU
1440 #define WSOC_OCLA_OUTVALCLR_CLR_S 0U
1441 
1442 
1443 /*-----------------------------------REGISTER------------------------------------
1444  Register name: OUTVALTGL
1445  Offset name: WSOC_OCLA_O_OUTVALTGL
1446  Relative address: 0xA4
1447  Description: GPIO Out Value Toggle.
1448  Default Value: NA
1449 
1450  Field: TOGGLE
1451  From..to bits: 0...31
1452  DefaultValue: NA
1453  Access type: read-write
1454  Description: writing 1 to a bit will toggle a bit at [OUTVAL.VAL].
1455 
1456 */
1457 #define WSOC_OCLA_OUTVALTGL_TOGGLE_W 32U
1458 #define WSOC_OCLA_OUTVALTGL_TOGGLE_M 0xFFFFFFFFU
1459 #define WSOC_OCLA_OUTVALTGL_TOGGLE_S 0U
1460 
1461 
1462 /*-----------------------------------REGISTER------------------------------------
1463  Register name: OUTVALPLS
1464  Offset name: WSOC_OCLA_O_OUTVALPLS
1465  Relative address: 0xA8
1466  Description: GPIO Out Value Pulse.
1467  Default Value: NA
1468 
1469  Field: PULSE
1470  From..to bits: 0...31
1471  DefaultValue: NA
1472  Access type: read-write
1473  Description: writing 1 to a bit will create a pulse for the same bit at [OUTVAL.VAL]
1474  ( Pulse is equal to toggle twice )
1475 
1476 */
1477 #define WSOC_OCLA_OUTVALPLS_PULSE_W 32U
1478 #define WSOC_OCLA_OUTVALPLS_PULSE_M 0xFFFFFFFFU
1479 #define WSOC_OCLA_OUTVALPLS_PULSE_S 0U
1480 
1481 
1482 /*-----------------------------------REGISTER------------------------------------
1483  Register name: TFSONTRG
1484  Offset name: WSOC_OCLA_O_TFSONTRG
1485  Relative address: 0xB0
1486  Description: TSF on Trigger.
1487 
1488  this is the 32 lower bits of the tsf latched on final trigger event
1489  Default Value: 0x00000000
1490 
1491  Field: TIMESTAMP
1492  From..to bits: 0...31
1493  DefaultValue: 0x0
1494  Access type: read-only
1495  Description: TSF time stamp samled on trigger.
1496 
1497 */
1498 #define WSOC_OCLA_TFSONTRG_TIMESTAMP_W 32U
1499 #define WSOC_OCLA_TFSONTRG_TIMESTAMP_M 0xFFFFFFFFU
1500 #define WSOC_OCLA_TFSONTRG_TIMESTAMP_S 0U
1501 
1502 #endif /* __HW_WSOC_OCLA_H__*/