CC35xxDriverLibrary
hw_uartlin.h
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1 /******************************************************************************
2 * Filename: hw_uartlin.h
3 *
4 * Description: Defines and prototypes for the UARTLIN peripheral.
5 *
6 * Copyright (c) 2023, Texas Instruments Incorporated
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35 ******************************************************************************/
36 #ifndef __HW_UARTLIN_H__
37 #define __HW_UARTLIN_H__
38 /*-------------------------------------------------------------------------------
39 
40 This section defines the register offsets of the UARTLIN component
41 
42 --------------------------------------------------------------------------------- */
43 
44 //Data
45 #define UARTLIN_O_DR 0x00000000U
46 
47 //Status
48 #define UARTLIN_O_RSRECR 0x00000004U
49 
50 //Flag
51 #define UARTLIN_O_FR 0x00000018U
52 
53 //IrDA <Low-Power Counter Register
54 #define UARTLIN_O_UARTILPR 0x00000020U
55 
56 //Integer Baud-Rate Divisor
57 #define UARTLIN_O_IBRD 0x00000024U
58 
59 //Fractional Baud-Rate Divisor
60 #define UARTLIN_O_FBRD 0x00000028U
61 
62 //Line Control
63 #define UARTLIN_O_LCRH 0x0000002CU
64 
65 //Control
66 #define UARTLIN_O_CTL 0x00000030U
67 
68 //Interrupt **FIFO** Level Select
69 #define UARTLIN_O_IFLS 0x00000034U
70 
71 //Interrupt Mask Set/Clear
72 #define UARTLIN_O_IMSC 0x00000038U
73 
74 //Raw Interrupt Status
75 #define UARTLIN_O_RIS 0x0000003CU
76 
77 //Masked Interrupt Status
78 #define UARTLIN_O_MIS 0x00000040U
79 
80 //Interrupt Clear
81 #define UARTLIN_O_ICR 0x00000044U
82 
83 //DMA Control
84 #define UARTLIN_O_DMACTL 0x00000048U
85 
86 //Test Control
87 #define UARTLIN_O_TCR 0x00000080U
88 
89 //Integration Test Input
90 #define UARTLIN_O_ITIP 0x00000084U
91 
92 //Integration Test Output
93 #define UARTLIN_O_ITOP 0x00000088U
94 
95 //Test Data
96 #define UARTLIN_O_TDR 0x0000008CU
97 
98 //Peripheral Identification 0
99 #define UARTLIN_O_PERIPHID0 0x00000FE0U
100 
101 //Peripheral Identification 1
102 #define UARTLIN_O_PERIPHID1 0x00000FE4U
103 
104 //Peripheral Identification 2
105 #define UARTLIN_O_PERIPHID2 0x00000FE8U
106 
107 //Peripheral Identification 3
108 #define UARTLIN_O_PERIPHID3 0x00000FECU
109 
110 //PrimeCell Identification 0
111 #define UARTLIN_O_PCELLID0 0x00000FF0U
112 
113 //PrimeCell Identification 1
114 #define UARTLIN_O_PCELLID1 0x00000FF4U
115 
116 //PrimeCell Identification 2
117 #define UARTLIN_O_PCELLID2 0x00000FF8U
118 
119 //PrimeCell Identification 3
120 #define UARTLIN_O_PCELLID3 0x00000FFCU
121 
122 //This register enable or disables the bus clock *uartlin*
123 #define UARTLIN_O_CLKCFG 0x00001000U
124 
125 
126 
127 /*-----------------------------------REGISTER------------------------------------
128  Register name: DR
129  Offset name: UARTLIN_O_DR
130  Relative address: 0x0
131  Description: Data
132  For words to be transmitted:
133  - if the **FIFO**s are enabled ([LCRH.FEN] = 1), data written to this location is pushed onto the transmit **FIFO**
134  - if the **FIFO**s are not enabled ([LCRH.FEN] = 0), data is stored in the transmitter holding register (the bottom word of the transmit **FIFO**).
135  The write operation initiates transmission from the **UART**. The data is prefixed with a start bit, appended with the appropriate parity bit (if parity is enabled), and a stop bit.
136  The resultant word is then transmitted.
137  For received words:
138  - if the **FIFO**s are enabled ([LCRH.FEN] = 1), the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive **FIFO**
139  - if the **FIFO**s are not enabled ([LCRH.FEN] = 0), the data byte and status are stored in the receiving holding register (the bottom word of the receive **FIFO**).
140  The received data byte is read by performing reads from this register along with the corresponding status information. The status information can also be read by a read of the [RSR.*] register.
141  Default Value: 0x00000000
142 
143  Field: DATA
144  From..to bits: 0...7
145  DefaultValue: 0x0
146  Access type: read-write
147  Description: Data transmitted or received:
148  On writes, the transmit data character is pushed into the **FIFO**.
149  On reads, the oldest received data character since the last read is returned.
150 
151 */
152 #define UARTLIN_DR_DATA_W 8U
153 #define UARTLIN_DR_DATA_M 0x000000FFU
154 #define UARTLIN_DR_DATA_S 0U
155 /*
156 
157  Field: FE
158  From..to bits: 8...8
159  DefaultValue: 0x0
160  Access type: read-only
161  Description: UART Framing Error:
162  When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1).
163  In **FIFO** mode, this error is associated with the character at the top of the **FIFO** (i.e., the oldest received data character since last read).
164 
165 */
166 #define UARTLIN_DR_FE 0x00000100U
167 #define UARTLIN_DR_FE_M 0x00000100U
168 #define UARTLIN_DR_FE_S 8U
169 /*
170 
171  Field: PE
172  From..to bits: 9...9
173  DefaultValue: 0x0
174  Access type: read-only
175  Description: UART Parity Error:
176  When set to 1, it indicates that the parity of the received data character does not match the parity that the [LCRH.EPS] and [LCRH.SPS] select.
177  In **FIFO** mode, this error is associated with the character at the top of the **FIFO** (i.e., the oldest received data character since last read).
178 
179 */
180 #define UARTLIN_DR_PE 0x00000200U
181 #define UARTLIN_DR_PE_M 0x00000200U
182 #define UARTLIN_DR_PE_S 9U
183 /*
184 
185  Field: BE
186  From..to bits: 10...10
187  DefaultValue: 0x0
188  Access type: read-only
189  Description: UART Break Error:
190  This bit is set to 1 if a break condition was detected, indicating that the received data input (**UARTRXD** input pin) was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits).
191  In **FIFO** mode, this error is associated with the character at the top of the **FIFO** (i.e., the oldest received data character since last read). When a break occurs, a 0 character is loaded into the **FIFO**. The next character is enabled after the receive data input (**UARTRXD** input pin) goes to a 1 (marking state), and the next valid start bit is received.
192 
193 */
194 #define UARTLIN_DR_BE 0x00000400U
195 #define UARTLIN_DR_BE_M 0x00000400U
196 #define UARTLIN_DR_BE_S 10U
197 /*
198 
199  Field: OE
200  From..to bits: 11...11
201  DefaultValue: 0x0
202  Access type: read-only
203  Description: UART Overrun Error:
204  This bit is set to 1 if data is received and the receive **FIFO** is already full. The **FIFO** contents remain valid because no more data is written when the **FIFO** is full, , only the contents of the shift register are overwritten.
205  This is cleared to 0 once there is an empty space in the **FIFO** and a new character can be written to it.
206 
207 */
208 #define UARTLIN_DR_OE 0x00000800U
209 #define UARTLIN_DR_OE_M 0x00000800U
210 #define UARTLIN_DR_OE_S 11U
211 
212 
213 /*-----------------------------------REGISTER------------------------------------
214  Register name: RSRECR
215  Offset name: UARTLIN_O_RSRECR
216  Relative address: 0x4
217  Description: Status
218  This register is mapped to the same address as [ECR.*] register. Reads from this address are associated with [RSR_ECR.*] register and return the receive status. Writes to this address are associated with [ECR.*] register and clear the receive status flags (framing, parity, break, and overrun errors).
219  If the status is read from this register, then the status information for break, framing and parity corresponds to the data character read from the Data Register, [DR.*] prior to reading the [RSR_ECR.*]. The status information for overrun is set immediately when an overrun condition occurs.
220  Default Value: 0x00000000
221 
222  Field: FE
223  From..to bits: 0...0
224  DefaultValue: 0x0
225  Access type: read-write
226  Description: UART Framing Error:
227  When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1).
228 
229  ENUMs:
230  ERROR_SET: Error flag is set
231  CLEAR_ERROR_0: Clears error flag if error is set. Write value is not important.
232  CLEAR_ERROR_1: Clears error flag if error is set. Write value is not important.
233  ERROR_NOTSET: Error flag is not set
234 */
235 #define UARTLIN_RSRECR_FE 0x00000001U
236 #define UARTLIN_RSRECR_FE_M 0x00000001U
237 #define UARTLIN_RSRECR_FE_S 0U
238 #define UARTLIN_RSRECR_FE_ERROR_SET 0x00000001U
239 #define UARTLIN_RSRECR_FE_CLEAR_ERROR_0 0x00000000U
240 #define UARTLIN_RSRECR_FE_CLEAR_ERROR_1 0x00000001U
241 #define UARTLIN_RSRECR_FE_ERROR_NOTSET 0x00000000U
242 /*
243 
244  Field: PE
245  From..to bits: 1...1
246  DefaultValue: 0x0
247  Access type: read-write
248  Description: UART Parity Error:
249  When set to 1, it indicates that the parity of the received data character does not match the parity that the [LCRH.EPS] and [LCRH.SPS] select.
250 
251  ENUMs:
252  CLEAR_ERROR_0: Clears error flag if error is set. Write value is not important.
253  ERROR_NOTSET: Error flag is not set
254  ERROR_SET: Error flag is set
255  CLEAR_ERROR_1: Clears error flag if error is set. Write value is not important.
256 */
257 #define UARTLIN_RSRECR_PE 0x00000002U
258 #define UARTLIN_RSRECR_PE_M 0x00000002U
259 #define UARTLIN_RSRECR_PE_S 1U
260 #define UARTLIN_RSRECR_PE_CLEAR_ERROR_0 0x00000000U
261 #define UARTLIN_RSRECR_PE_ERROR_NOTSET 0x00000000U
262 #define UARTLIN_RSRECR_PE_ERROR_SET 0x00000002U
263 #define UARTLIN_RSRECR_PE_CLEAR_ERROR_1 0x00000002U
264 /*
265 
266  Field: BE
267  From..to bits: 2...2
268  DefaultValue: 0x0
269  Access type: read-write
270  Description: UART Break Error:
271  This bit is set to 1 if a break condition was detected, indicating that the received data input (**UARTRXD** input pin) was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits).
272  When a break occurs, a 0 character is loaded into the **FIFO**. The next character is enabled after the receive data input (**UARTRXD** input pin) goes to a 1 (marking state), and the next valid start bit is received.
273 
274  ENUMs:
275  CLEAR_ERROR_0: Clears error flag if error is set. Write value is not important.
276  ERROR_NOTSET: Error flag is not set
277  ERROR_SET: Error flag is set
278  CLEAR_ERROR_1: Clears error flag if error is set. Write value is not important.
279 */
280 #define UARTLIN_RSRECR_BE 0x00000004U
281 #define UARTLIN_RSRECR_BE_M 0x00000004U
282 #define UARTLIN_RSRECR_BE_S 2U
283 #define UARTLIN_RSRECR_BE_CLEAR_ERROR_0 0x00000000U
284 #define UARTLIN_RSRECR_BE_ERROR_NOTSET 0x00000000U
285 #define UARTLIN_RSRECR_BE_ERROR_SET 0x00000004U
286 #define UARTLIN_RSRECR_BE_CLEAR_ERROR_1 0x00000004U
287 /*
288 
289  Field: OE
290  From..to bits: 3...3
291  DefaultValue: 0x0
292  Access type: read-write
293  Description: UART Overrun Error:
294  This bit is set to 1 if data is received and the receive **FIFO** is already full. The **FIFO** contents remain valid because no more data is written when the **FIFO** is full, , only the contents of the shift register are overwritten.
295  This is cleared to 0 once there is an empty space in the **FIFO** and a new character can be written to it.
296 
297  ENUMs:
298  CLEAR_ERROR_0: Clears error flag if error is set. Write value is not important.
299  ERROR_NOTSET: Error flag is not set
300  ERROR_SET: Error flag is set
301  CLEAR_ERROR_1: Clears error flag if error is set. Write value is not important.
302 */
303 #define UARTLIN_RSRECR_OE 0x00000008U
304 #define UARTLIN_RSRECR_OE_M 0x00000008U
305 #define UARTLIN_RSRECR_OE_S 3U
306 #define UARTLIN_RSRECR_OE_CLEAR_ERROR_0 0x00000000U
307 #define UARTLIN_RSRECR_OE_ERROR_NOTSET 0x00000000U
308 #define UARTLIN_RSRECR_OE_ERROR_SET 0x00000008U
309 #define UARTLIN_RSRECR_OE_CLEAR_ERROR_1 0x00000008U
310 
311 
312 /*-----------------------------------REGISTER------------------------------------
313  Register name: FR
314  Offset name: UARTLIN_O_FR
315  Relative address: 0x18
316  Description: Flag
317  Reads from this register return the **UART** flags.
318  Default Value: 0x00000000
319 
320  Field: CTS
321  From..to bits: 0...0
322  DefaultValue: 0x0
323  Access type: read-only
324  Description: Clear To Send:
325  This bit is the complement of the active-low **UART** **CTS** input pin.
326  That is, the bit is 1 when **CTS** input pin is LOW.
327 
328 */
329 #define UARTLIN_FR_CTS 0x00000001U
330 #define UARTLIN_FR_CTS_M 0x00000001U
331 #define UARTLIN_FR_CTS_S 0U
332 /*
333 
334  Field: BUSY
335  From..to bits: 3...3
336  DefaultValue: 0x0
337  Access type: read-only
338  Description: UART Busy:
339  If this bit is set to 1, the **UART** is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register.
340  This bit is set as soon as the transmit **FIFO** becomes non-empty, regardless of whether the **UART** is enabled or not.
341 
342 */
343 #define UARTLIN_FR_BUSY 0x00000008U
344 #define UARTLIN_FR_BUSY_M 0x00000008U
345 #define UARTLIN_FR_BUSY_S 3U
346 /*
347 
348  Field: RXFE
349  From..to bits: 4...4
350  DefaultValue: 0x0
351  Access type: read-only
352  Description: UART Receive **FIFO** Empty:
353  Receive **FIFO** empty. The meaning of this bit depends on the state of [LCRH.FEN].
354  - If the **FIFO** is disabled, this bit is set when the receive holding register is empty.
355  - If the **FIFO** is enabled, this bit is set when the receive **FIFO** is empty.
356 
357 */
358 #define UARTLIN_FR_RXFE 0x00000010U
359 #define UARTLIN_FR_RXFE_M 0x00000010U
360 #define UARTLIN_FR_RXFE_S 4U
361 /*
362 
363  Field: TXFF
364  From..to bits: 5...5
365  DefaultValue: 0x0
366  Access type: read-only
367  Description: UART Transmit **FIFO** Full:
368  Transmit **FIFO** full. The meaning of this bit depends on the state of [LCRH.FEN].
369  - If the **FIFO** is disabled, this bit is set when the transmit holding register is full.
370  - If the **FIFO** is enabled, this bit is set when the transmit **FIFO** is full.
371 
372 */
373 #define UARTLIN_FR_TXFF 0x00000020U
374 #define UARTLIN_FR_TXFF_M 0x00000020U
375 #define UARTLIN_FR_TXFF_S 5U
376 /*
377 
378  Field: RXFF
379  From..to bits: 6...6
380  DefaultValue: 0x0
381  Access type: read-only
382  Description: UART Receive **FIFO** Full:
383  The meaning of this bit depends on the state of [LCRH.FEN].
384  - If the **FIFO** is disabled, this bit is set when the receive holding register is full.
385  - If the **FIFO** is enabled, this bit is set when the receive **FIFO** is full.
386 
387 */
388 #define UARTLIN_FR_RXFF 0x00000040U
389 #define UARTLIN_FR_RXFF_M 0x00000040U
390 #define UARTLIN_FR_RXFF_S 6U
391 /*
392 
393  Field: TXFE
394  From..to bits: 7...7
395  DefaultValue: 0x0
396  Access type: read-only
397  Description: UART Transmit **FIFO** Empty:
398  The meaning of this bit depends on the state of [LCRH.FEN] .
399  - If the **FIFO** is disabled, this bit is set when the transmit holding register is empty.
400  - If the **FIFO** is enabled, this bit is set when the transmit **FIFO** is empty.
401  This bit does not indicate if there is data in the transmit shift register.
402 
403 */
404 #define UARTLIN_FR_TXFE 0x00000080U
405 #define UARTLIN_FR_TXFE_M 0x00000080U
406 #define UARTLIN_FR_TXFE_S 7U
407 
408 
409 /*-----------------------------------REGISTER------------------------------------
410  Register name: UARTILPR
411  Offset name: UARTLIN_O_UARTILPR
412  Relative address: 0x20
413  Description: IrDA <Low-Power Counter Register
414  Default Value: 0x00000000
415 
416  Field: ILPDVSR
417  From..to bits: 0...7
418  DefaultValue: 0x0
419  Access type: read-write
420  Description: 8 bit low-power divisor value
421 
422 */
423 #define UARTLIN_UARTILPR_ILPDVSR_W 8U
424 #define UARTLIN_UARTILPR_ILPDVSR_M 0x000000FFU
425 #define UARTLIN_UARTILPR_ILPDVSR_S 0U
426 
427 
428 /*-----------------------------------REGISTER------------------------------------
429  Register name: IBRD
430  Offset name: UARTLIN_O_IBRD
431  Relative address: 0x24
432  Description: Integer Baud-Rate Divisor
433  If this register is modified while transmission or reception is on-going, the baudrate will not be updated until transmission or reception of the current character is complete.
434  Default Value: 0x00000000
435 
436  Field: DIVINT
437  From..to bits: 0...15
438  DefaultValue: 0x0
439  Access type: read-write
440  Description: The integer baud rate divisor:
441  The baud rate divisor is calculated using the formula below:
442  Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate)
443  Baud rate divisor must be minimum 1 and maximum 65535.
444  That is, [DIVINT]=0 does not give a valid baud rate.
445  Similarly, if [DIVINT]=0xFFFF, any non-zero values in [FBRD.DIVFRAC] will be illegal.
446  A valid value must be written to this field before the **UART** can be used for **RX** or **TX** operations.
447  INTERNAL_NOTE
448  The calculator below can be used to find the register values:
449  [Baud-rate calculator](https://spsemea.itg.ti.com/sites/lpw/proj/CC26xx/Modules/UART/UART_baudrate_calculator.xlsx)
450 
451 */
452 #define UARTLIN_IBRD_DIVINT_W 16U
453 #define UARTLIN_IBRD_DIVINT_M 0x0000FFFFU
454 #define UARTLIN_IBRD_DIVINT_S 0U
455 
456 
457 /*-----------------------------------REGISTER------------------------------------
458  Register name: FBRD
459  Offset name: UARTLIN_O_FBRD
460  Relative address: 0x28
461  Description: Fractional Baud-Rate Divisor
462  If this register is modified while transmission or reception is on-going, the baudrate will not be updated until transmission or reception of the current character is complete.
463  Default Value: 0x00000000
464 
465  Field: DIVFRAC
466  From..to bits: 0...5
467  DefaultValue: 0x0
468  Access type: read-write
469  Description: Fractional Baud-Rate Divisor:
470  The baud rate divisor is calculated using the formula below:
471  Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate)
472  Baud rate divisor must be minimum 1 and maximum 65535.
473  That is, [IBRD.DIVINT]=0 does not give a valid baud rate.
474  Similarly, if [IBRD.DIVINT]=0xFFFF, any non-zero values in [DIVFRAC] will be illegal.
475  A valid value must be written to this field before the **UART** can be used for **RX** or **TX** operations.
476  INTERNAL_NOTE
477  The calculator below can be used to find the register values:
478  [Baud-rate calculator](https://spsemea.itg.ti.com/sites/lpw/proj/CC26xx/Modules/UART/UART_baudrate_calculator.xlsx)
479 
480 */
481 #define UARTLIN_FBRD_DIVFRAC_W 6U
482 #define UARTLIN_FBRD_DIVFRAC_M 0x0000003FU
483 #define UARTLIN_FBRD_DIVFRAC_S 0U
484 
485 
486 /*-----------------------------------REGISTER------------------------------------
487  Register name: LCRH
488  Offset name: UARTLIN_O_LCRH
489  Relative address: 0x2C
490  Description: Line Control
491  Default Value: 0x00000000
492 
493  Field: BRK
494  From..to bits: 0...0
495  DefaultValue: 0x0
496  Access type: read-write
497  Description: UART Send Break
498  If this bit is set to 1, a low-level is continually output on the **UARTTXD** output pin, after completing transmission of the current character. For the proper execution of the break command, the
499  software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0.
500 
501 */
502 #define UARTLIN_LCRH_BRK 0x00000001U
503 #define UARTLIN_LCRH_BRK_M 0x00000001U
504 #define UARTLIN_LCRH_BRK_S 0U
505 /*
506 
507  Field: PEN
508  From..to bits: 1...1
509  DefaultValue: 0x0
510  Access type: read-write
511  Description: UART Parity Enable
512  This bit controls generation and checking of parity bit.
513  INTERNAL_NOTE
514  See [Parity truth table](https://spsemea.itg.ti.com/sites/lpw/proj/CC26xx/Modules/UART/parity.png) for details.
515 
516  ENUMs:
517  DIS: Parity is disabled and no parity bit is added to the data frame
518  EN: Parity checking and generation is enabled.
519 */
520 #define UARTLIN_LCRH_PEN 0x00000002U
521 #define UARTLIN_LCRH_PEN_M 0x00000002U
522 #define UARTLIN_LCRH_PEN_S 1U
523 #define UARTLIN_LCRH_PEN_DIS 0x00000000U
524 #define UARTLIN_LCRH_PEN_EN 0x00000002U
525 /*
526 
527  Field: EPS
528  From..to bits: 2...2
529  DefaultValue: 0x0
530  Access type: read-write
531  Description: UART Even Parity Select
532 
533  ENUMs:
534  ODD: Odd parity: The **UART** generates or checks for an odd number of 1s in the data and parity bits.
535  EVEN: Even parity: The **UART** generates or checks for an even number of 1s in the data and parity bits.
536 */
537 #define UARTLIN_LCRH_EPS 0x00000004U
538 #define UARTLIN_LCRH_EPS_M 0x00000004U
539 #define UARTLIN_LCRH_EPS_S 2U
540 #define UARTLIN_LCRH_EPS_ODD 0x00000000U
541 #define UARTLIN_LCRH_EPS_EVEN 0x00000004U
542 /*
543 
544  Field: STP2
545  From..to bits: 3...3
546  DefaultValue: 0x0
547  Access type: read-write
548  Description: UART Two Stop Bits Select:
549  If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received.
550 
551 */
552 #define UARTLIN_LCRH_STP2 0x00000008U
553 #define UARTLIN_LCRH_STP2_M 0x00000008U
554 #define UARTLIN_LCRH_STP2_S 3U
555 /*
556 
557  Field: FEN
558  From..to bits: 4...4
559  DefaultValue: 0x0
560  Access type: read-write
561  Description: UART Enable **FIFO**s
562 
563  ENUMs:
564  DIS: **FIFO**s are disabled (character mode) that is, the **FIFO**s become 1-byte-deep holding registers.
565  EN: Transmit and receive **FIFO** buffers are enabled (**FIFO** mode)
566 */
567 #define UARTLIN_LCRH_FEN 0x00000010U
568 #define UARTLIN_LCRH_FEN_M 0x00000010U
569 #define UARTLIN_LCRH_FEN_S 4U
570 #define UARTLIN_LCRH_FEN_DIS 0x00000000U
571 #define UARTLIN_LCRH_FEN_EN 0x00000010U
572 /*
573 
574  Field: WLEN
575  From..to bits: 5...6
576  DefaultValue: 0x0
577  Access type: read-write
578  Description: UART Word Length:
579  These bits indicate the number of data bits transmitted or received in a frame.
580 
581  ENUMs:
582  BITL5: Word Length 5 bits
583  BITL6: Word Length 6 bits
584  BITL7: Word Length 7 bits
585  BITL8: Word Length 8 bits
586 */
587 #define UARTLIN_LCRH_WLEN_W 2U
588 #define UARTLIN_LCRH_WLEN_M 0x00000060U
589 #define UARTLIN_LCRH_WLEN_S 5U
590 #define UARTLIN_LCRH_WLEN_BITL5 0x00000000U
591 #define UARTLIN_LCRH_WLEN_BITL6 0x00000020U
592 #define UARTLIN_LCRH_WLEN_BITL7 0x00000040U
593 #define UARTLIN_LCRH_WLEN_BITL8 0x00000060U
594 /*
595 
596  Field: SPS
597  From..to bits: 7...7
598  DefaultValue: 0x0
599  Access type: read-write
600  Description: UART Stick Parity Select:
601 
602  0: Stick parity is disabled
603  1: The parity bit is transmitted and checked as invert of [EPS] field (i.e. the parity bit is transmitted and checked as 1 when [EPS] = 0).
604 
605  This bit has no effect when [PEN] disables parity checking and generation.
606 
607 */
608 #define UARTLIN_LCRH_SPS 0x00000080U
609 #define UARTLIN_LCRH_SPS_M 0x00000080U
610 #define UARTLIN_LCRH_SPS_S 7U
611 /*
612 
613  Field: TXBRKSYNC
614  From..to bits: 8...8
615  DefaultValue: 0x0
616  Access type: read-write
617  Description: UART LIN mode TXBRKSYNC:
618 
619  0: In LIN mode TXBRKSYNC will not be sent.
620  1: In LIN mode send TXBRKSYNC field and reset the LCRH.TXBRKSYNC bit.
621 
622  This bit has no effect when [PEN] disables parity checking and generation.
623 
624 */
625 #define UARTLIN_LCRH_TXBRKSYNC 0x00000100U
626 #define UARTLIN_LCRH_TXBRKSYNC_M 0x00000100U
627 #define UARTLIN_LCRH_TXBRKSYNC_S 8U
628 /*
629 
630  Field: DELIM
631  From..to bits: 9...10
632  DefaultValue: 0x0
633  Access type: read-write
634  Description: In UART LIN defines the length of DELIM field that has to be sent
635 
636  ENUMs:
637  LEN_1:
638  LEN_2:
639  LEN_3:
640  LEN_4:
641 */
642 #define UARTLIN_LCRH_DELIM_W 2U
643 #define UARTLIN_LCRH_DELIM_M 0x00000600U
644 #define UARTLIN_LCRH_DELIM_S 9U
645 #define UARTLIN_LCRH_DELIM_LEN_1 0x00000000U
646 #define UARTLIN_LCRH_DELIM_LEN_2 0x00000200U
647 #define UARTLIN_LCRH_DELIM_LEN_3 0x00000400U
648 #define UARTLIN_LCRH_DELIM_LEN_4 0x00000600U
649 
650 
651 /*-----------------------------------REGISTER------------------------------------
652  Register name: CTL
653  Offset name: UARTLIN_O_CTL
654  Relative address: 0x30
655  Description: Control
656  Default Value: 0x00000000
657 
658  Field: UARTEN
659  From..to bits: 0...0
660  DefaultValue: 0x0
661  Access type: read-write
662  Description: UART Enable
663 
664  ENUMs:
665  DIS: UART disabled
666  EN: UART enabled
667 */
668 #define UARTLIN_CTL_UARTEN 0x00000001U
669 #define UARTLIN_CTL_UARTEN_M 0x00000001U
670 #define UARTLIN_CTL_UARTEN_S 0U
671 #define UARTLIN_CTL_UARTEN_DIS 0x00000000U
672 #define UARTLIN_CTL_UARTEN_EN 0x00000001U
673 /*
674 
675  Field: SIREN
676  From..to bits: 1...1
677  DefaultValue: 0x0
678  Access type: read-write
679  Description: SIR Enable
680  This bit has no effect if UARTEN bit disables the UART.
681 
682  ENUMs:
683  DIS: IrDA SIR ENDEC is disabled
684  EN: IrDA SIR ENDEC is enabled. Data is transmitted and received via nSIROUT and SIRIN.
685 */
686 #define UARTLIN_CTL_SIREN 0x00000002U
687 #define UARTLIN_CTL_SIREN_M 0x00000002U
688 #define UARTLIN_CTL_SIREN_S 1U
689 #define UARTLIN_CTL_SIREN_DIS 0x00000000U
690 #define UARTLIN_CTL_SIREN_EN 0x00000002U
691 /*
692 
693  Field: SIRLP
694  From..to bits: 2...2
695  DefaultValue: 0x0
696  Access type: read-write
697  Description: SIR low power IrDA mode
698  This bit selects the IrDA encoding mode
699 
700  ENUMs:
701  DIS: Low-level bits are transmitted as active high with a 3/16th period width,
702  EN: Low-level bits are transmitted with a pulse width of 3 times the period of IrLPBaud16, regardless of the selected bit rate.
703 */
704 #define UARTLIN_CTL_SIRLP 0x00000004U
705 #define UARTLIN_CTL_SIRLP_M 0x00000004U
706 #define UARTLIN_CTL_SIRLP_S 2U
707 #define UARTLIN_CTL_SIRLP_DIS 0x00000000U
708 #define UARTLIN_CTL_SIRLP_EN 0x00000004U
709 /*
710 
711  Field: LINEN
712  From..to bits: 3...3
713  DefaultValue: 0x0
714  Access type: read-write
715  Description: This is the LIN Mode of operation configuration bit.
716 
717  ENUMs:
718  DIS:
719  EN:
720 */
721 #define UARTLIN_CTL_LINEN 0x00000008U
722 #define UARTLIN_CTL_LINEN_M 0x00000008U
723 #define UARTLIN_CTL_LINEN_S 3U
724 #define UARTLIN_CTL_LINEN_DIS 0x00000000U
725 #define UARTLIN_CTL_LINEN_EN 0x00000008U
726 /*
727 
728  Field: ABDEN
729  From..to bits: 4...4
730  DefaultValue: 0x0
731  Access type: read-write
732  Description: This configuration bit defines whether we want automatic baud rate detection enabled or not in the LIN mode of operation.
733 
734  ENUMs:
735  DIS:
736  EN:
737 */
738 #define UARTLIN_CTL_ABDEN 0x00000010U
739 #define UARTLIN_CTL_ABDEN_M 0x00000010U
740 #define UARTLIN_CTL_ABDEN_S 4U
741 #define UARTLIN_CTL_ABDEN_DIS 0x00000000U
742 #define UARTLIN_CTL_ABDEN_EN 0x00000010U
743 /*
744 
745  Field: DORMEN
746  From..to bits: 5...5
747  DefaultValue: 0x0
748  Access type: read-write
749  Description: DORMEN bit is only functionally makes sense for LIN mode of operation.
750  When dormant mode is disabled, break and sync data shall be loaded to RX FIFO and associated interrupt flags shall be set as in normal UART operation.
751  When dormant mode is enabled, break and sync data shall not be loaded to RX FIFO and RX FIFO shall be updated with actual data (PID) only after successful reception of break/sync fields.
752 
753  ENUMs:
754  DIS:
755  EN:
756 */
757 #define UARTLIN_CTL_DORMEN 0x00000020U
758 #define UARTLIN_CTL_DORMEN_M 0x00000020U
759 #define UARTLIN_CTL_DORMEN_S 5U
760 #define UARTLIN_CTL_DORMEN_DIS 0x00000000U
761 #define UARTLIN_CTL_DORMEN_EN 0x00000020U
762 /*
763 
764  Field: FCEN
765  From..to bits: 6...6
766  DefaultValue: 0x0
767  Access type: read-write
768  Description: UART FIFO Concatenation Enable
769  Enabling the lFIFO concatenation in TX moderesulting in 16 TX buffers.
770 
771  ENUMs:
772  DIS: UART FIFO Concatenation disabled
773  EN: UART FIFO Concatenation enabled
774 */
775 #define UARTLIN_CTL_FCEN 0x00000040U
776 #define UARTLIN_CTL_FCEN_M 0x00000040U
777 #define UARTLIN_CTL_FCEN_S 6U
778 #define UARTLIN_CTL_FCEN_DIS 0x00000000U
779 #define UARTLIN_CTL_FCEN_EN 0x00000040U
780 /*
781 
782  Field: LBE
783  From..to bits: 7...7
784  DefaultValue: 0x0
785  Access type: read-write
786  Description: UART Loop Back Enable
787  Enabling the loop-back mode connects the **UARTTXD** output from the **UART** to **UARTRXD** input of the **UART**.
788 
789  ENUMs:
790  DIS: Loop Back disabled
791  EN: Loop Back enabled
792 */
793 #define UARTLIN_CTL_LBE 0x00000080U
794 #define UARTLIN_CTL_LBE_M 0x00000080U
795 #define UARTLIN_CTL_LBE_S 7U
796 #define UARTLIN_CTL_LBE_DIS 0x00000000U
797 #define UARTLIN_CTL_LBE_EN 0x00000080U
798 /*
799 
800  Field: TXE
801  From..to bits: 8...8
802  DefaultValue: 0x0
803  Access type: read-write
804  Description: UART Transmit Enable
805  If the **UART** is disabled in the middle of transmission, it completes the current character before stopping.
806 
807  ENUMs:
808  DIS: UART Transmit disabled
809  EN: UART Transmit enabled
810 */
811 #define UARTLIN_CTL_TXE 0x00000100U
812 #define UARTLIN_CTL_TXE_M 0x00000100U
813 #define UARTLIN_CTL_TXE_S 8U
814 #define UARTLIN_CTL_TXE_DIS 0x00000000U
815 #define UARTLIN_CTL_TXE_EN 0x00000100U
816 /*
817 
818  Field: RXE
819  From..to bits: 9...9
820  DefaultValue: 0x0
821  Access type: read-write
822  Description: UART Receive Enable
823  If the **UART** is disabled in the middle of reception, it completes the current character before stopping.
824 
825  ENUMs:
826  DIS: UART Receive disabled
827  EN: UART Receive enabled
828 */
829 #define UARTLIN_CTL_RXE 0x00000200U
830 #define UARTLIN_CTL_RXE_M 0x00000200U
831 #define UARTLIN_CTL_RXE_S 9U
832 #define UARTLIN_CTL_RXE_DIS 0x00000000U
833 #define UARTLIN_CTL_RXE_EN 0x00000200U
834 /*
835 
836  Field: RTS
837  From..to bits: 11...11
838  DefaultValue: 0x0
839  Access type: read-write
840  Description: Request to Send
841  This bit is the complement of the active-low **UART** **RTS** output. That is, when the bit is programmed to a 1 then **RTS** output on the pins is LOW.
842 
843 */
844 #define UARTLIN_CTL_RTS 0x00000800U
845 #define UARTLIN_CTL_RTS_M 0x00000800U
846 #define UARTLIN_CTL_RTS_S 11U
847 /*
848 
849  Field: RTSEN
850  From..to bits: 14...14
851  DefaultValue: 0x0
852  Access type: read-write
853  Description: **RTS** hardware flow control enable
854 
855  ENUMs:
856  DIS: **RTS** hardware flow control disabled
857  EN: **RTS** hardware flow control enabled
858 */
859 #define UARTLIN_CTL_RTSEN 0x00004000U
860 #define UARTLIN_CTL_RTSEN_M 0x00004000U
861 #define UARTLIN_CTL_RTSEN_S 14U
862 #define UARTLIN_CTL_RTSEN_DIS 0x00000000U
863 #define UARTLIN_CTL_RTSEN_EN 0x00004000U
864 /*
865 
866  Field: CTSEN
867  From..to bits: 15...15
868  DefaultValue: 0x0
869  Access type: read-write
870  Description: **CTS** hardware flow control enable
871 
872  ENUMs:
873  DIS: **CTS** hardware flow control disabled
874  EN: **CTS** hardware flow control enabled
875 */
876 #define UARTLIN_CTL_CTSEN 0x00008000U
877 #define UARTLIN_CTL_CTSEN_M 0x00008000U
878 #define UARTLIN_CTL_CTSEN_S 15U
879 #define UARTLIN_CTL_CTSEN_DIS 0x00000000U
880 #define UARTLIN_CTL_CTSEN_EN 0x00008000U
881 
882 
883 /*-----------------------------------REGISTER------------------------------------
884  Register name: IFLS
885  Offset name: UARTLIN_O_IFLS
886  Relative address: 0x34
887  Description: Interrupt **FIFO** Level Select
888  Default Value: 0x00000002
889 
890  Field: TXSEL
891  From..to bits: 0...2
892  DefaultValue: 0x2
893  Access type: read-write
894  Description: Transmit interrupt **FIFO** level select:
895  This field sets the trigger points for the transmit interrupt. Values 0b101-0b111 are reserved.
896 
897  ENUMs:
898  QUARTER: Transmit **FIFO** becomes <= 1/4 full
899  HALF: Transmit **FIFO** becomes <= 1/2 full
900  THREEQU: Transmit **FIFO** becomes <= 3/4 full
901 */
902 #define UARTLIN_IFLS_TXSEL_W 3U
903 #define UARTLIN_IFLS_TXSEL_M 0x00000007U
904 #define UARTLIN_IFLS_TXSEL_S 0U
905 #define UARTLIN_IFLS_TXSEL_QUARTER 0x00000001U
906 #define UARTLIN_IFLS_TXSEL_HALF 0x00000002U
907 #define UARTLIN_IFLS_TXSEL_THREEQU 0x00000003U
908 /*
909 
910  Field: RXSEL
911  From..to bits: 3...5
912  DefaultValue: 0x0
913  Access type: read-write
914  Description: Receive interrupt **FIFO** level select:
915  This field sets the trigger points for the receive interrupt. Values 0b101-0b111 are reserved.
916 
917  ENUMs:
918  QUARTER: Receive **FIFO** becomes >= 1/4 full
919  HALF: Receive **FIFO** becomes >= 1/2 full
920  THREEQU: Receive **FIFO** becomes >= 3/4 full
921 */
922 #define UARTLIN_IFLS_RXSEL_W 3U
923 #define UARTLIN_IFLS_RXSEL_M 0x00000038U
924 #define UARTLIN_IFLS_RXSEL_S 3U
925 #define UARTLIN_IFLS_RXSEL_QUARTER 0x00000008U
926 #define UARTLIN_IFLS_RXSEL_HALF 0x00000010U
927 #define UARTLIN_IFLS_RXSEL_THREEQU 0x00000018U
928 
929 
930 /*-----------------------------------REGISTER------------------------------------
931  Register name: IMSC
932  Offset name: UARTLIN_O_IMSC
933  Relative address: 0x38
934  Description: Interrupt Mask Set/Clear
935  Default Value: 0x00000000
936 
937  Field: CTSM
938  From..to bits: 1...1
939  DefaultValue: 0x0
940  Access type: read-write
941  Description: Clear to Send (CTS) modem interrupt mask. A read returns the current mask for **UART**'s clear to send interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in [MIS.CTSMMIS]. A write of 0 clears the mask which means [MIS.CTSMMIS] will not reflect the interrupt.
942 
943 */
944 #define UARTLIN_IMSC_CTSM 0x00000002U
945 #define UARTLIN_IMSC_CTSM_M 0x00000002U
946 #define UARTLIN_IMSC_CTSM_S 1U
947 /*
948 
949  Field: RX
950  From..to bits: 4...4
951  DefaultValue: 0x0
952  Access type: read-write
953  Description: Receive interrupt mask. A read returns the current mask for **UART**'s receive interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in [MIS.RXMIS]. A write of 0 clears the mask which means [MIS.RXMIS] will not reflect the interrupt.
954 
955 */
956 #define UARTLIN_IMSC_RX 0x00000010U
957 #define UARTLIN_IMSC_RX_M 0x00000010U
958 #define UARTLIN_IMSC_RX_S 4U
959 /*
960 
961  Field: TX
962  From..to bits: 5...5
963  DefaultValue: 0x0
964  Access type: read-write
965  Description: Transmit interrupt mask. A read returns the current mask for **UART**'s transmit interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in [MIS.TXMIS]. A write of 0 clears the mask which means [MIS.TXMIS] will not reflect the interrupt.
966 
967 */
968 #define UARTLIN_IMSC_TX 0x00000020U
969 #define UARTLIN_IMSC_TX_M 0x00000020U
970 #define UARTLIN_IMSC_TX_S 5U
971 /*
972 
973  Field: RT
974  From..to bits: 6...6
975  DefaultValue: 0x0
976  Access type: read-write
977  Description: Receive timeout interrupt mask. A read returns the current mask for **UART**'s receive timeout interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in [MIS.RTMIS]. A write of 0 clears the mask which means this bitfield will not reflect the interrupt.
978  The raw interrupt for receive timeout [RIS.RTRIS] cannot be set unless the mask is set ([RTIM] = 1). This is because the mask acts as an enable for power saving. That is, the same status can be read from [MIS.RTMIS] and [RIS.RTRIS].
979 
980 */
981 #define UARTLIN_IMSC_RT 0x00000040U
982 #define UARTLIN_IMSC_RT_M 0x00000040U
983 #define UARTLIN_IMSC_RT_S 6U
984 /*
985 
986  Field: FE
987  From..to bits: 7...7
988  DefaultValue: 0x0
989  Access type: read-write
990  Description: Framing error interrupt mask. A read returns the current mask for **UART**'s framing error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in [MIS.FEMIS]. A write of 0 clears the mask which means [MIS.FEMIS] will not reflect the interrupt.
991 
992 */
993 #define UARTLIN_IMSC_FE 0x00000080U
994 #define UARTLIN_IMSC_FE_M 0x00000080U
995 #define UARTLIN_IMSC_FE_S 7U
996 /*
997 
998  Field: PE
999  From..to bits: 8...8
1000  DefaultValue: 0x0
1001  Access type: read-write
1002  Description: Parity error interrupt mask. A read returns the current mask for **UART**'s parity error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in [MIS.PEMIS]. A write of 0 clears the mask which means [MIS.PEMIS] will not reflect the interrupt.
1003 
1004 */
1005 #define UARTLIN_IMSC_PE 0x00000100U
1006 #define UARTLIN_IMSC_PE_M 0x00000100U
1007 #define UARTLIN_IMSC_PE_S 8U
1008 /*
1009 
1010  Field: BE
1011  From..to bits: 9...9
1012  DefaultValue: 0x0
1013  Access type: read-write
1014  Description: Break error interrupt mask. A read returns the current mask for **UART**'s break error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in [MIS.BEMIS]. A write of 0 clears the mask which means [MIS.BEMIS] will not reflect the interrupt.
1015 
1016 */
1017 #define UARTLIN_IMSC_BE 0x00000200U
1018 #define UARTLIN_IMSC_BE_M 0x00000200U
1019 #define UARTLIN_IMSC_BE_S 9U
1020 /*
1021 
1022  Field: OE
1023  From..to bits: 10...10
1024  DefaultValue: 0x0
1025  Access type: read-write
1026  Description: Overrun error interrupt mask. A read returns the current mask for **UART**'s overrun error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in [MIS.OEMIS]. A write of 0 clears the mask which means [MIS.OEMIS] will not reflect the interrupt.
1027 
1028 */
1029 #define UARTLIN_IMSC_OE 0x00000400U
1030 #define UARTLIN_IMSC_OE_M 0x00000400U
1031 #define UARTLIN_IMSC_OE_S 10U
1032 /*
1033 
1034  Field: EOT
1035  From..to bits: 11...11
1036  DefaultValue: 0x0
1037  Access type: read-write
1038  Description: End of Transmission interrupt mask. A read returns the current mask for UART's EoT interrupt. On a write of 1, the mask of the EoT interrupt is set which means the interrupt state will be reflected in MIS.EOTMIS. A write of 0 clears the mask which means MIS.EOTMIS will not reflect the interrupt.
1039 
1040 */
1041 #define UARTLIN_IMSC_EOT 0x00000800U
1042 #define UARTLIN_IMSC_EOT_M 0x00000800U
1043 #define UARTLIN_IMSC_EOT_S 11U
1044 /*
1045 
1046  Field: TXDMADONE
1047  From..to bits: 12...12
1048  DefaultValue: 0x0
1049  Access type: read-write
1050  Description: Tx DMA done interrupt mask. A read returns the current mask for UART's TXDMADONE interrupt. On a write of 1, the mask of the TXDMADONE interrupt is set which means the interrupt state will be reflected in MIS.TXDMADONEMIS. A write of 0 clears the mask which means MIS.TXDMADONEMIS will not reflect the interrupt.
1051 
1052 */
1053 #define UARTLIN_IMSC_TXDMADONE 0x00001000U
1054 #define UARTLIN_IMSC_TXDMADONE_M 0x00001000U
1055 #define UARTLIN_IMSC_TXDMADONE_S 12U
1056 /*
1057 
1058  Field: RXDMADONE
1059  From..to bits: 13...13
1060  DefaultValue: 0x0
1061  Access type: read-write
1062  Description: Rx DMA done interrupt mask. A read returns the current mask for UART's RXDMADONE interrupt. On a write of 1, the mask of the RXDMADONE interrupt is set which means the interrupt state will be reflected in MIS.RXDMADONEMIS. A write of 0 clears the mask which means MIS.RXDMADONEMIS will not reflect the interrupt.
1063 
1064 */
1065 #define UARTLIN_IMSC_RXDMADONE 0x00002000U
1066 #define UARTLIN_IMSC_RXDMADONE_M 0x00002000U
1067 #define UARTLIN_IMSC_RXDMADONE_S 13U
1068 /*
1069 
1070  Field: LINBRK
1071  From..to bits: 14...14
1072  DefaultValue: 0x0
1073  Access type: read-write
1074  Description: LIN Break field received/detected interrupt mask. A read returns the current mask for UART's LINBRK interrupt. On a write of 1, the mask of the LINBRK interrupt is set which means the interrupt state will be reflected in MIS.LINBRK. A write of 0 clears the mask which means MIS.LINBRK will not reflect the interrupt.
1075 
1076 */
1077 #define UARTLIN_IMSC_LINBRK 0x00004000U
1078 #define UARTLIN_IMSC_LINBRK_M 0x00004000U
1079 #define UARTLIN_IMSC_LINBRK_S 14U
1080 /*
1081 
1082  Field: LINBRKTOE
1083  From..to bits: 15...15
1084  DefaultValue: 0x0
1085  Access type: read-write
1086  Description: LIN Break field Time out error interrupt mask. A read returns the current mask for UART's LINBRKTOE interrupt. On a write of 1, the mask of the LINBRKTOE interrupt is set which means the interrupt state will be reflected in MIS.LINBRKTOE. A write of 0 clears the mask which means MIS.LINBRKTOE will not reflect the interrupt.
1087 
1088 */
1089 #define UARTLIN_IMSC_LINBRKTOE 0x00008000U
1090 #define UARTLIN_IMSC_LINBRKTOE_M 0x00008000U
1091 #define UARTLIN_IMSC_LINBRKTOE_S 15U
1092 /*
1093 
1094  Field: LINSYNCTOE
1095  From..to bits: 16...16
1096  DefaultValue: 0x0
1097  Access type: read-write
1098  Description: LIN Sync Time out error interrupt mask. A read returns the current mask for UART's LINSYNCTOE interrupt. On a write of 1, the mask of the LINSYNCTOE interrupt is set which means the interrupt state will be reflected in MIS.LINSYNCTOE. A write of 0 clears the mask which means MIS.LINSYNCTOE will not reflect the interrupt.
1099 
1100 */
1101 #define UARTLIN_IMSC_LINSYNCTOE 0x00010000U
1102 #define UARTLIN_IMSC_LINSYNCTOE_M 0x00010000U
1103 #define UARTLIN_IMSC_LINSYNCTOE_S 16U
1104 
1105 
1106 /*-----------------------------------REGISTER------------------------------------
1107  Register name: RIS
1108  Offset name: UARTLIN_O_RIS
1109  Relative address: 0x3C
1110  Description: Raw Interrupt Status
1111  Default Value: 0x00000001
1112 
1113  Field: CTSM
1114  From..to bits: 1...1
1115  DefaultValue: 0x0
1116  Access type: read-only
1117  Description: Clear to Send (CTS) modem interrupt status:
1118  This field returns the raw interrupt state of **UART**'s clear to send interrupt.
1119 
1120 */
1121 #define UARTLIN_RIS_CTSM 0x00000002U
1122 #define UARTLIN_RIS_CTSM_M 0x00000002U
1123 #define UARTLIN_RIS_CTSM_S 1U
1124 /*
1125 
1126  Field: RX
1127  From..to bits: 4...4
1128  DefaultValue: 0x0
1129  Access type: read-only
1130  Description: Receive interrupt status:
1131  This field returns the raw interrupt state of **UART**'s receive interrupt.
1132  When **FIFO**s are enabled ([LCRH.FEN] = 1), the receive interrupt is asserted if the receive **FIFO** reaches the programmed trigger
1133  level ([IFLS.RXSEL]). The receive interrupt is cleared by reading data from the receive **FIFO** until it becomes less than the trigger level, or by clearing the interrupt through [ICR.RXIC].
1134  When **FIFO**s are disabled ([LCRH.FEN] = 0), that is they have a depth of one location, the receive interrupt is asserted if data is received
1135  thereby filling the location. The receive interrupt is cleared by performing a single read of the receive **FIFO**, or by clearing the interrupt through [ICR.RXIC].
1136 
1137 */
1138 #define UARTLIN_RIS_RX 0x00000010U
1139 #define UARTLIN_RIS_RX_M 0x00000010U
1140 #define UARTLIN_RIS_RX_S 4U
1141 /*
1142 
1143  Field: TX
1144  From..to bits: 5...5
1145  DefaultValue: 0x0
1146  Access type: read-only
1147  Description: Transmit interrupt status:
1148  This field returns the raw interrupt state of **UART**'s transmit interrupt.
1149  When **FIFO**s are enabled ([LCRH.FEN] = 1), the transmit interrupt is asserted if the number of bytes in transmit **FIFO** is equal to or lower than the programmed trigger level ([IFLS.TXSEL]). The transmit interrupt is cleared by writing data to the transmit **FIFO** until it becomes greater than the trigger level, or by clearing the interrupt through [ICR.TXIC].
1150  When **FIFO**s are disabled ([LCRH.FEN] = 0), that is they have a depth of one location, the transmit interrupt is asserted if there is no data present in the transmitters single location. It is cleared by performing a single write to the transmit **FIFO**, or by clearing the interrupt through [ICR.TXIC].
1151 
1152 */
1153 #define UARTLIN_RIS_TX 0x00000020U
1154 #define UARTLIN_RIS_TX_M 0x00000020U
1155 #define UARTLIN_RIS_TX_S 5U
1156 /*
1157 
1158  Field: RT
1159  From..to bits: 6...6
1160  DefaultValue: 0x0
1161  Access type: read-only
1162  Description: Receive timeout interrupt status:
1163  This field returns the raw interrupt state of **UART**'s receive timeout interrupt. The receive timeout interrupt is asserted when the receive **FIFO** is not empty, and no more data is received during a 32-bit period. The receive timeout interrupt is cleared either when the **FIFO** becomes empty through reading all the data, or when a 1 is written to [ICR.RTIC].
1164  The raw interrupt for receive timeout cannot be set unless the mask is set ([IMSC.RTIM] = 1). This is because the mask acts as an enable for power saving. That is, the same status can be read from [MIS.RTMIS] and [RTRIS].
1165 
1166 */
1167 #define UARTLIN_RIS_RT 0x00000040U
1168 #define UARTLIN_RIS_RT_M 0x00000040U
1169 #define UARTLIN_RIS_RT_S 6U
1170 /*
1171 
1172  Field: FE
1173  From..to bits: 7...7
1174  DefaultValue: 0x0
1175  Access type: read-only
1176  Description: Framing error interrupt status:
1177  This field returns the raw interrupt state of **UART**'s framing error interrupt. Framing error is set if the received character does not have a valid stop bit (a valid stop bit is 1).
1178 
1179 */
1180 #define UARTLIN_RIS_FE 0x00000080U
1181 #define UARTLIN_RIS_FE_M 0x00000080U
1182 #define UARTLIN_RIS_FE_S 7U
1183 /*
1184 
1185  Field: PE
1186  From..to bits: 8...8
1187  DefaultValue: 0x0
1188  Access type: read-only
1189  Description: Parity error interrupt status:
1190  This field returns the raw interrupt state of **UART**'s parity error interrupt. Parity error is set if the parity of the received data character does not match the parity that the [LCRH.EPS] and [LCRH.SPS] select.
1191 
1192 */
1193 #define UARTLIN_RIS_PE 0x00000100U
1194 #define UARTLIN_RIS_PE_M 0x00000100U
1195 #define UARTLIN_RIS_PE_S 8U
1196 /*
1197 
1198  Field: BE
1199  From..to bits: 9...9
1200  DefaultValue: 0x0
1201  Access type: read-only
1202  Description: Break error interrupt status:
1203  This field returns the raw interrupt state of **UART**'s break error interrupt. Break error is set when a break condition is detected, indicating that the received data input (**UARTRXD** input pin) was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits).
1204 
1205 */
1206 #define UARTLIN_RIS_BE 0x00000200U
1207 #define UARTLIN_RIS_BE_M 0x00000200U
1208 #define UARTLIN_RIS_BE_S 9U
1209 /*
1210 
1211  Field: OE
1212  From..to bits: 10...10
1213  DefaultValue: 0x0
1214  Access type: read-only
1215  Description: Overrun error interrupt status:
1216  This field returns the raw interrupt state of **UART**'s overrun error interrupt. Overrun error occurs if data is received and the receive **FIFO** is full.
1217 
1218 */
1219 #define UARTLIN_RIS_OE 0x00000400U
1220 #define UARTLIN_RIS_OE_M 0x00000400U
1221 #define UARTLIN_RIS_OE_S 10U
1222 /*
1223 
1224  Field: EOT
1225  From..to bits: 11...11
1226  DefaultValue: 0x0
1227  Access type: read-only
1228  Description: End of Transmission interrupt status:
1229  This field returns the raw interrupt state of UART's end of transmission interrupt. End of transmission flag is set when all the Transmit data in the FIFO and on the TX Line is transmitted.
1230 
1231 */
1232 #define UARTLIN_RIS_EOT 0x00000800U
1233 #define UARTLIN_RIS_EOT_M 0x00000800U
1234 #define UARTLIN_RIS_EOT_S 11U
1235 /*
1236 
1237  Field: TXDMADONE
1238  From..to bits: 12...12
1239  DefaultValue: 0x0
1240  Access type: read-only
1241  Description: Tx DMA done interrupt status:
1242  This field returns the raw interrupt state of UART's tx dma done interrupt. TX DMA done flag is set when you receive tx dma done status from dma module.
1243 
1244 */
1245 #define UARTLIN_RIS_TXDMADONE 0x00001000U
1246 #define UARTLIN_RIS_TXDMADONE_M 0x00001000U
1247 #define UARTLIN_RIS_TXDMADONE_S 12U
1248 /*
1249 
1250  Field: RXDMADONE
1251  From..to bits: 13...13
1252  DefaultValue: 0x0
1253  Access type: read-only
1254  Description: Rx DMA done interrupt status:
1255  This field returns the raw interrupt state of UART's rx dma done interrupt. RX DMA done flag is set when you receive rx dma done status from dma module.
1256 
1257 */
1258 #define UARTLIN_RIS_RXDMADONE 0x00002000U
1259 #define UARTLIN_RIS_RXDMADONE_M 0x00002000U
1260 #define UARTLIN_RIS_RXDMADONE_S 13U
1261 /*
1262 
1263  Field: LINBRK
1264  From..to bits: 14...14
1265  DefaultValue: 0x0
1266  Access type: read-only
1267  Description: LIN BRK detected interrupt status:
1268  This field returns the raw interrupt state of whether break field is received/detected in UART's LIN mode of operation.
1269 
1270 */
1271 #define UARTLIN_RIS_LINBRK 0x00004000U
1272 #define UARTLIN_RIS_LINBRK_M 0x00004000U
1273 #define UARTLIN_RIS_LINBRK_S 14U
1274 /*
1275 
1276  Field: LINBRKTOE
1277  From..to bits: 15...15
1278  DefaultValue: 0x0
1279  Access type: read-only
1280  Description: LIN BRK field time out interrupt status:
1281  This field returns the raw interrupt state of whether break field is measurable in UART's LIN mode of operation. This is set when the timer measuring the Break field overflows.
1282 
1283 */
1284 #define UARTLIN_RIS_LINBRKTOE 0x00008000U
1285 #define UARTLIN_RIS_LINBRKTOE_M 0x00008000U
1286 #define UARTLIN_RIS_LINBRKTOE_S 15U
1287 /*
1288 
1289  Field: LINSYNCTOE
1290  From..to bits: 16...16
1291  DefaultValue: 0x0
1292  Access type: read-only
1293  Description: LIN SYNC field time out interrupt status:
1294  This field returns the raw interrupt state of whether sync field is measurable in UART's LIN mode of operation. This is set when the timer measuring the SYNC field overflows.
1295 
1296 */
1297 #define UARTLIN_RIS_LINSYNCTOE 0x00010000U
1298 #define UARTLIN_RIS_LINSYNCTOE_M 0x00010000U
1299 #define UARTLIN_RIS_LINSYNCTOE_S 16U
1300 
1301 
1302 /*-----------------------------------REGISTER------------------------------------
1303  Register name: MIS
1304  Offset name: UARTLIN_O_MIS
1305  Relative address: 0x40
1306  Description: Masked Interrupt Status
1307  Default Value: 0x00000000
1308 
1309  Field: CTSM
1310  From..to bits: 1...1
1311  DefaultValue: 0x0
1312  Access type: read-only
1313  Description: Clear to Send (CTS) modem masked interrupt status:
1314  This field returns the masked interrupt state of the clear to send interrupt which is the AND product of raw interrupt state [RIS.CTSRMIS] and the mask setting [IMSC.CTSMIM].
1315 
1316 */
1317 #define UARTLIN_MIS_CTSM 0x00000002U
1318 #define UARTLIN_MIS_CTSM_M 0x00000002U
1319 #define UARTLIN_MIS_CTSM_S 1U
1320 /*
1321 
1322  Field: RX
1323  From..to bits: 4...4
1324  DefaultValue: 0x0
1325  Access type: read-only
1326  Description: Receive masked interrupt status:
1327  This field returns the masked interrupt state of the receive interrupt which is the AND product of raw interrupt state [RIS.RXRIS] and the mask setting [IMSC.RXIM].
1328 
1329 */
1330 #define UARTLIN_MIS_RX 0x00000010U
1331 #define UARTLIN_MIS_RX_M 0x00000010U
1332 #define UARTLIN_MIS_RX_S 4U
1333 /*
1334 
1335  Field: TX
1336  From..to bits: 5...5
1337  DefaultValue: 0x0
1338  Access type: read-only
1339  Description: Transmit masked interrupt status:
1340  This field returns the masked interrupt state of the transmit interrupt which is the AND product of raw interrupt state [RIS.TXRIS] and the mask setting [IMSC.TXIM].
1341 
1342 */
1343 #define UARTLIN_MIS_TX 0x00000020U
1344 #define UARTLIN_MIS_TX_M 0x00000020U
1345 #define UARTLIN_MIS_TX_S 5U
1346 /*
1347 
1348  Field: RT
1349  From..to bits: 6...6
1350  DefaultValue: 0x0
1351  Access type: read-only
1352  Description: Receive timeout masked interrupt status:
1353  Returns the masked interrupt state of the receive timeout interrupt.
1354  The raw interrupt for receive timeout cannot be set unless the mask is set ([IMSC.RTIM] = 1). This is because the mask acts as an enable for power saving. That is, the same status can be read from [RTMIS] and [RIS.RTRIS].
1355 
1356 */
1357 #define UARTLIN_MIS_RT 0x00000040U
1358 #define UARTLIN_MIS_RT_M 0x00000040U
1359 #define UARTLIN_MIS_RT_S 6U
1360 /*
1361 
1362  Field: FE
1363  From..to bits: 7...7
1364  DefaultValue: 0x0
1365  Access type: read-only
1366  Description: Framing error masked interrupt status: Returns the masked interrupt state of the framing error interrupt which is the AND product of raw interrupt state [RIS.FERIS] and the mask setting [IMSC.FEIM].
1367 
1368 */
1369 #define UARTLIN_MIS_FE 0x00000080U
1370 #define UARTLIN_MIS_FE_M 0x00000080U
1371 #define UARTLIN_MIS_FE_S 7U
1372 /*
1373 
1374  Field: PE
1375  From..to bits: 8...8
1376  DefaultValue: 0x0
1377  Access type: read-only
1378  Description: Parity error masked interrupt status:
1379  This field returns the masked interrupt state of the parity error interrupt which is the AND product of raw interrupt state [RIS.PERIS] and the mask setting [IMSC.PEIM].
1380 
1381 */
1382 #define UARTLIN_MIS_PE 0x00000100U
1383 #define UARTLIN_MIS_PE_M 0x00000100U
1384 #define UARTLIN_MIS_PE_S 8U
1385 /*
1386 
1387  Field: BE
1388  From..to bits: 9...9
1389  DefaultValue: 0x0
1390  Access type: read-only
1391  Description: Break error masked interrupt status:
1392  This field returns the masked interrupt state of the break error interrupt which is the AND product of raw interrupt state [RIS.BERIS] and the mask setting [IMSC.BEIM].
1393 
1394 */
1395 #define UARTLIN_MIS_BE 0x00000200U
1396 #define UARTLIN_MIS_BE_M 0x00000200U
1397 #define UARTLIN_MIS_BE_S 9U
1398 /*
1399 
1400  Field: OE
1401  From..to bits: 10...10
1402  DefaultValue: 0x0
1403  Access type: read-only
1404  Description: Overrun error masked interrupt status:
1405  This field returns the masked interrupt state of the overrun interrupt which is the AND product of raw interrupt state [RIS.OERIS] and the mask setting [IMSC.OEIM].
1406 
1407 */
1408 #define UARTLIN_MIS_OE 0x00000400U
1409 #define UARTLIN_MIS_OE_M 0x00000400U
1410 #define UARTLIN_MIS_OE_S 10U
1411 /*
1412 
1413  Field: EOT
1414  From..to bits: 11...11
1415  DefaultValue: 0x0
1416  Access type: read-only
1417  Description: End of Transmission interrupt status:
1418  This field returns the masked interrupt state of the End of transmission interrupt which is the AND product of raw interrupt state RIS.EOTRIS and the mask setting IMSC.EOTIM.
1419 
1420 */
1421 #define UARTLIN_MIS_EOT 0x00000800U
1422 #define UARTLIN_MIS_EOT_M 0x00000800U
1423 #define UARTLIN_MIS_EOT_S 11U
1424 /*
1425 
1426  Field: TXDMADONE
1427  From..to bits: 12...12
1428  DefaultValue: 0x0
1429  Access type: read-only
1430  Description: Tx DMA done interrupt status:
1431  This field returns the masked interrupt state of the tx dma done interrupt which is the AND product of raw interrupt state RIS.TXDMADONERIS and the mask setting IMSC.TXDMADONEIM.
1432 
1433 */
1434 #define UARTLIN_MIS_TXDMADONE 0x00001000U
1435 #define UARTLIN_MIS_TXDMADONE_M 0x00001000U
1436 #define UARTLIN_MIS_TXDMADONE_S 12U
1437 /*
1438 
1439  Field: RXDMADONE
1440  From..to bits: 13...13
1441  DefaultValue: 0x0
1442  Access type: read-only
1443  Description: Rx DMA done interrupt status:
1444  This field returns the masked interrupt state of the rx dma done interrupt which is the AND product of raw interrupt state RIS.RXDMADONERIS and the mask setting IMSC.RXDMADONEIM.
1445 
1446 */
1447 #define UARTLIN_MIS_RXDMADONE 0x00002000U
1448 #define UARTLIN_MIS_RXDMADONE_M 0x00002000U
1449 #define UARTLIN_MIS_RXDMADONE_S 13U
1450 /*
1451 
1452  Field: LINBRK
1453  From..to bits: 14...14
1454  DefaultValue: 0x0
1455  Access type: read-only
1456  Description: LIN BRK field detected interrupt status:
1457  This field returns the masked interrupt state of the LIN BRK detected interrupt which is the AND product of raw interrupt state RIS.LINBRKRIS and the mask setting IMSC.LINBRKIM.
1458 
1459 */
1460 #define UARTLIN_MIS_LINBRK 0x00004000U
1461 #define UARTLIN_MIS_LINBRK_M 0x00004000U
1462 #define UARTLIN_MIS_LINBRK_S 14U
1463 /*
1464 
1465  Field: LINBRKTOE
1466  From..to bits: 15...15
1467  DefaultValue: 0x0
1468  Access type: read-only
1469  Description: LIN BRK field time out error interrupt status:
1470  This field returns the masked interrupt state of the LIN BRK timeout error interrupt which is the AND product of raw interrupt state RIS.LINBRKTOERIS and the mask setting IMSC.LINBRKTOEIM.
1471 
1472 */
1473 #define UARTLIN_MIS_LINBRKTOE 0x00008000U
1474 #define UARTLIN_MIS_LINBRKTOE_M 0x00008000U
1475 #define UARTLIN_MIS_LINBRKTOE_S 15U
1476 /*
1477 
1478  Field: LINSYNCTOE
1479  From..to bits: 16...16
1480  DefaultValue: 0x0
1481  Access type: read-only
1482  Description: LIN sync field time out error interrupt status:
1483  This field returns the masked interrupt state of the LIN sync timeout error interrupt which is the AND product of raw interrupt state RIS.LINSYNCTOERIS and the mask setting IMSC.LINSYNCTOEIM.
1484 
1485 */
1486 #define UARTLIN_MIS_LINSYNCTOE 0x00010000U
1487 #define UARTLIN_MIS_LINSYNCTOE_M 0x00010000U
1488 #define UARTLIN_MIS_LINSYNCTOE_S 16U
1489 
1490 
1491 /*-----------------------------------REGISTER------------------------------------
1492  Register name: ICR
1493  Offset name: UARTLIN_O_ICR
1494  Relative address: 0x44
1495  Description: Interrupt Clear
1496  On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.
1497  Default Value: 0x00000000
1498 
1499  Field: CTSM
1500  From..to bits: 1...1
1501  DefaultValue: 0x0
1502  Access type: write-only
1503  Description: Clear to Send (CTS) modem interrupt clear:
1504  Writing 1 to this field clears the clear to send interrupt ([RIS.CTSRMIS]). Writing 0 has no effect.
1505 
1506 */
1507 #define UARTLIN_ICR_CTSM 0x00000002U
1508 #define UARTLIN_ICR_CTSM_M 0x00000002U
1509 #define UARTLIN_ICR_CTSM_S 1U
1510 /*
1511 
1512  Field: RX
1513  From..to bits: 4...4
1514  DefaultValue: 0x0
1515  Access type: write-only
1516  Description: Receive interrupt clear:
1517  Writing 1 to this field clears the receive interrupt ([RIS.RXRIS]). Writing 0 has no effect.
1518 
1519 */
1520 #define UARTLIN_ICR_RX 0x00000010U
1521 #define UARTLIN_ICR_RX_M 0x00000010U
1522 #define UARTLIN_ICR_RX_S 4U
1523 /*
1524 
1525  Field: TX
1526  From..to bits: 5...5
1527  DefaultValue: 0x0
1528  Access type: write-only
1529  Description: Transmit interrupt clear:
1530  Writing 1 to this field clears the transmit interrupt ([RIS.TXRIS]). Writing 0 has no effect.
1531 
1532 */
1533 #define UARTLIN_ICR_TX 0x00000020U
1534 #define UARTLIN_ICR_TX_M 0x00000020U
1535 #define UARTLIN_ICR_TX_S 5U
1536 /*
1537 
1538  Field: RT
1539  From..to bits: 6...6
1540  DefaultValue: 0x0
1541  Access type: write-only
1542  Description: Receive timeout interrupt clear:
1543  Writing 1 to this field clears the receive timeout interrupt ([RIS.RTRIS]). Writing 0 has no effect.
1544 
1545 */
1546 #define UARTLIN_ICR_RT 0x00000040U
1547 #define UARTLIN_ICR_RT_M 0x00000040U
1548 #define UARTLIN_ICR_RT_S 6U
1549 /*
1550 
1551  Field: FE
1552  From..to bits: 7...7
1553  DefaultValue: 0x0
1554  Access type: write-only
1555  Description: Framing error interrupt clear:
1556  Writing 1 to this field clears the framing error interrupt ([RIS.FERIS]). Writing 0 has no effect.
1557 
1558 */
1559 #define UARTLIN_ICR_FE 0x00000080U
1560 #define UARTLIN_ICR_FE_M 0x00000080U
1561 #define UARTLIN_ICR_FE_S 7U
1562 /*
1563 
1564  Field: PE
1565  From..to bits: 8...8
1566  DefaultValue: 0x0
1567  Access type: write-only
1568  Description: Parity error interrupt clear:
1569  Writing 1 to this field clears the parity error interrupt ([RIS.PERIS]). Writing 0 has no effect.
1570 
1571 */
1572 #define UARTLIN_ICR_PE 0x00000100U
1573 #define UARTLIN_ICR_PE_M 0x00000100U
1574 #define UARTLIN_ICR_PE_S 8U
1575 /*
1576 
1577  Field: BE
1578  From..to bits: 9...9
1579  DefaultValue: 0x0
1580  Access type: write-only
1581  Description: Break error interrupt clear:
1582  Writing 1 to this field clears the break error interrupt ([RIS.BERIS]). Writing 0 has no effect.
1583 
1584 */
1585 #define UARTLIN_ICR_BE 0x00000200U
1586 #define UARTLIN_ICR_BE_M 0x00000200U
1587 #define UARTLIN_ICR_BE_S 9U
1588 /*
1589 
1590  Field: OE
1591  From..to bits: 10...10
1592  DefaultValue: 0x0
1593  Access type: write-only
1594  Description: Overrun error interrupt clear:
1595  Writing 1 to this field clears the overrun error interrupt ([RIS.OERIS]). Writing 0 has no effect.
1596 
1597 */
1598 #define UARTLIN_ICR_OE 0x00000400U
1599 #define UARTLIN_ICR_OE_M 0x00000400U
1600 #define UARTLIN_ICR_OE_S 10U
1601 /*
1602 
1603  Field: EOT
1604  From..to bits: 11...11
1605  DefaultValue: 0x0
1606  Access type: write-only
1607  Description: End of Transmission interrupt clear:
1608  Writing 1 to this field clears the End of Transmission interrupt (RIS.EOTRIS). Writing 0 has no effect.
1609 
1610 */
1611 #define UARTLIN_ICR_EOT 0x00000800U
1612 #define UARTLIN_ICR_EOT_M 0x00000800U
1613 #define UARTLIN_ICR_EOT_S 11U
1614 /*
1615 
1616  Field: TXDMADONE
1617  From..to bits: 12...12
1618  DefaultValue: 0x0
1619  Access type: write-only
1620  Description: Tx DMA Done interrupt clear:
1621  Writing 1 to this field clears the txdma done interrupt (RIS.TXDMADONERIS). Writing 0 has no effect.
1622 
1623 */
1624 #define UARTLIN_ICR_TXDMADONE 0x00001000U
1625 #define UARTLIN_ICR_TXDMADONE_M 0x00001000U
1626 #define UARTLIN_ICR_TXDMADONE_S 12U
1627 /*
1628 
1629  Field: RXDMADONE
1630  From..to bits: 13...13
1631  DefaultValue: 0x0
1632  Access type: write-only
1633  Description: Rx DMA Done interrupt clear:
1634  Writing 1 to this field clears the rxdma done interrupt (RIS.RXDMADONERIS). Writing 0 has no effect.
1635 
1636 */
1637 #define UARTLIN_ICR_RXDMADONE 0x00002000U
1638 #define UARTLIN_ICR_RXDMADONE_M 0x00002000U
1639 #define UARTLIN_ICR_RXDMADONE_S 13U
1640 /*
1641 
1642  Field: LINBRK
1643  From..to bits: 14...14
1644  DefaultValue: 0x0
1645  Access type: write-only
1646  Description: LIN BRK field detected interrupt clear:
1647  Writing 1 to this field clears the rxdma done interrupt (RIS.LINBRKRIS). Writing 0 has no effect.
1648 
1649 */
1650 #define UARTLIN_ICR_LINBRK 0x00004000U
1651 #define UARTLIN_ICR_LINBRK_M 0x00004000U
1652 #define UARTLIN_ICR_LINBRK_S 14U
1653 /*
1654 
1655  Field: LINBRKTOE
1656  From..to bits: 15...15
1657  DefaultValue: 0x0
1658  Access type: write-only
1659  Description: LIN BRK field timeout interrupt clear:
1660  Writing 1 to this field clears the rxdma done interrupt (RIS.LINBRKTOERIS). Writing 0 has no effect.
1661 
1662 */
1663 #define UARTLIN_ICR_LINBRKTOE 0x00008000U
1664 #define UARTLIN_ICR_LINBRKTOE_M 0x00008000U
1665 #define UARTLIN_ICR_LINBRKTOE_S 15U
1666 /*
1667 
1668  Field: LINSYNCTOE
1669  From..to bits: 16...16
1670  DefaultValue: 0x0
1671  Access type: write-only
1672  Description: LIN SYNC timeout interrupt clear:
1673  Writing 1 to this field clears the rxdma done interrupt (RIS.LINSYNCTOERIS). Writing 0 has no effect.
1674 
1675 */
1676 #define UARTLIN_ICR_LINSYNCTOE 0x00010000U
1677 #define UARTLIN_ICR_LINSYNCTOE_M 0x00010000U
1678 #define UARTLIN_ICR_LINSYNCTOE_S 16U
1679 
1680 
1681 /*-----------------------------------REGISTER------------------------------------
1682  Register name: DMACTL
1683  Offset name: UARTLIN_O_DMACTL
1684  Relative address: 0x48
1685  Description: DMA Control
1686  Default Value: 0x00000000
1687 
1688  Field: RXDMAE
1689  From..to bits: 0...0
1690  DefaultValue: 0x0
1691  Access type: read-write
1692  Description: Receive **DMA** enable. If this bit is set to 1, **DMA** for the receive **FIFO** is enabled.
1693 
1694 */
1695 #define UARTLIN_DMACTL_RXDMAE 0x00000001U
1696 #define UARTLIN_DMACTL_RXDMAE_M 0x00000001U
1697 #define UARTLIN_DMACTL_RXDMAE_S 0U
1698 /*
1699 
1700  Field: TXDMAE
1701  From..to bits: 1...1
1702  DefaultValue: 0x0
1703  Access type: read-write
1704  Description: Transmit **DMA** enable. If this bit is set to 1, **DMA** for the transmit **FIFO** is enabled.
1705 
1706 */
1707 #define UARTLIN_DMACTL_TXDMAE 0x00000002U
1708 #define UARTLIN_DMACTL_TXDMAE_M 0x00000002U
1709 #define UARTLIN_DMACTL_TXDMAE_S 1U
1710 /*
1711 
1712  Field: DMAONERR
1713  From..to bits: 2...2
1714  DefaultValue: 0x0
1715  Access type: read-write
1716  Description: DMA on error. If this bit is set to 1, the **DMA** receive request outputs (for single and burst requests) are disabled when the **UART** error interrupt is asserted (more specifically if any of the error interrupts [RIS.PERIS], [RIS.BERIS], [RIS.FERIS] or [RIS.OERIS] are asserted).
1717 
1718 */
1719 #define UARTLIN_DMACTL_DMAONERR 0x00000004U
1720 #define UARTLIN_DMACTL_DMAONERR_M 0x00000004U
1721 #define UARTLIN_DMACTL_DMAONERR_S 2U
1722 
1723 
1724 /*-----------------------------------REGISTER------------------------------------
1725  Register name: TCR
1726  Offset name: UARTLIN_O_TCR
1727  Relative address: 0x80
1728  Description: Test Control
1729  NOTE: This register is intended for integration testing and debugging only. In normal usecases, this register should not be used.
1730  Default Value: 0x00000000
1731 
1732  Field: ITEN
1733  From..to bits: 0...0
1734  DefaultValue: 0x0
1735  Access type: read-write
1736  Description: Integration test enable. When this bit is 1, the **UART** is placed in integration test mode, otherwise it is in normal operation.
1737 
1738 */
1739 #define UARTLIN_TCR_ITEN 0x00000001U
1740 #define UARTLIN_TCR_ITEN_M 0x00000001U
1741 #define UARTLIN_TCR_ITEN_S 0U
1742 /*
1743 
1744  Field: TESTFIFO
1745  From..to bits: 1...1
1746  DefaultValue: 0x0
1747  Access type: read-write
1748  Description: Test **FIFO** enable. When this bit it 1, a write to the Test Data Register, [TDR.DATA] writes data into the receive **FIFO**, and a read from the [TDR.DATA] reads data out of the transmit **FIFO**. When this bit is 0, data cannot be read directly from the transmit **FIFO** or written directly to the receive **FIFO** (normal operation).
1749 
1750 */
1751 #define UARTLIN_TCR_TESTFIFO 0x00000002U
1752 #define UARTLIN_TCR_TESTFIFO_M 0x00000002U
1753 #define UARTLIN_TCR_TESTFIFO_S 1U
1754 /*
1755 
1756  Field: SIRTEST
1757  From..to bits: 2...2
1758  DefaultValue: 0x0
1759  Access type: read-write
1760  Description: SIR test enable. Setting this bit to 1 enables the receive data path during IrDA transmission (SIR
1761  full-duplex operation is only available when testing). This bit must be set to 1 to enable SIR system
1762  loopback testing, and you must also set the LBE bit to 1 in the Control Register, CTL
1763 
1764 */
1765 #define UARTLIN_TCR_SIRTEST 0x00000004U
1766 #define UARTLIN_TCR_SIRTEST_M 0x00000004U
1767 #define UARTLIN_TCR_SIRTEST_S 2U
1768 
1769 
1770 /*-----------------------------------REGISTER------------------------------------
1771  Register name: ITIP
1772  Offset name: UARTLIN_O_ITIP
1773  Relative address: 0x84
1774  Description: Integration Test Input
1775  NOTE: This register is intended for integration testing and debugging only. In normal usecases, this register should not be used.
1776  Default Value: 0x00000000
1777 
1778  Field: UARTRXD
1779  From..to bits: 0...0
1780  DefaultValue: 0x0
1781  Access type: read-only
1782  Description: Reads return the value of the **UARTRXD** primary input at PrimeCell PL011 level.
1783 
1784 */
1785 #define UARTLIN_ITIP_UARTRXD 0x00000001U
1786 #define UARTLIN_ITIP_UARTRXD_M 0x00000001U
1787 #define UARTLIN_ITIP_UARTRXD_S 0U
1788 /*
1789 
1790  Field: NUARTCTS
1791  From..to bits: 3...3
1792  DefaultValue: 0x0
1793  Access type: read-only
1794  Description: Reads return the value of the nUARTCTS primary input at PrimeCell PL011 level.
1795 
1796 */
1797 #define UARTLIN_ITIP_NUARTCTS 0x00000008U
1798 #define UARTLIN_ITIP_NUARTCTS_M 0x00000008U
1799 #define UARTLIN_ITIP_NUARTCTS_S 3U
1800 /*
1801 
1802  Field: RXDMACLR
1803  From..to bits: 6...6
1804  DefaultValue: 0x0
1805  Access type: read-write
1806  Description: Writes to this bit specify the value to be driven on the intra-chip input at PrimeCell PL011 level,
1807  UARTRXDMACLR, in the integration test mode.
1808  Reads return the value of UARTRXDMACLR at the output of the test multiplexor.
1809 
1810 */
1811 #define UARTLIN_ITIP_RXDMACLR 0x00000040U
1812 #define UARTLIN_ITIP_RXDMACLR_M 0x00000040U
1813 #define UARTLIN_ITIP_RXDMACLR_S 6U
1814 /*
1815 
1816  Field: TXDMACLR
1817  From..to bits: 7...7
1818  DefaultValue: 0x0
1819  Access type: read-write
1820  Description: Writes to this bit specify the value to be driven on the intra-chip input at PrimeCell PL011 level,
1821  UARTTXDMACLR, in the integration test mode.
1822  Reads return the value of UARTTXDMACLR at the output of the test multiplexor.
1823 
1824 */
1825 #define UARTLIN_ITIP_TXDMACLR 0x00000080U
1826 #define UARTLIN_ITIP_TXDMACLR_M 0x00000080U
1827 #define UARTLIN_ITIP_TXDMACLR_S 7U
1828 
1829 
1830 /*-----------------------------------REGISTER------------------------------------
1831  Register name: ITOP
1832  Offset name: UARTLIN_O_ITOP
1833  Relative address: 0x88
1834  Description: Integration Test Output
1835  Default Value: 0x00000000
1836 
1837  Field: UARTTXD
1838  From..to bits: 0...0
1839  DefaultValue: 0x0
1840  Access type: read-write
1841  Description: Writes specify the value to be driven on UARTTXD, primary output of PrimeCell PL011 IP.
1842 
1843 */
1844 #define UARTLIN_ITOP_UARTTXD 0x00000001U
1845 #define UARTLIN_ITOP_UARTTXD_M 0x00000001U
1846 #define UARTLIN_ITOP_UARTTXD_S 0U
1847 /*
1848 
1849  Field: NUARTRTS
1850  From..to bits: 3...3
1851  DefaultValue: 0x0
1852  Access type: read-write
1853  Description: Writes specify the value to be driven on nUARTRTS, primary output of PrimeCell PL011 IP.
1854 
1855 */
1856 #define UARTLIN_ITOP_NUARTRTS 0x00000008U
1857 #define UARTLIN_ITOP_NUARTRTS_M 0x00000008U
1858 #define UARTLIN_ITOP_NUARTRTS_S 3U
1859 /*
1860 
1861  Field: UARTINTR
1862  From..to bits: 6...6
1863  DefaultValue: 0x0
1864  Access type: read-write
1865  Description: Intra-chip output of PrimeCell PL011 IP. Writes specify the value to be driven on UARTINTR.
1866  Reads return the value of UARTINTR at the output of the test multiplexor.
1867 
1868 */
1869 #define UARTLIN_ITOP_UARTINTR 0x00000040U
1870 #define UARTLIN_ITOP_UARTINTR_M 0x00000040U
1871 #define UARTLIN_ITOP_UARTINTR_S 6U
1872 /*
1873 
1874  Field: RXDMABREQ
1875  From..to bits: 12...12
1876  DefaultValue: 0x0
1877  Access type: read-write
1878  Description: Intra-chip output of PrimeCell PL011 IP. Writes specify the value to be driven on UARTRXDMABREQ.
1879  Reads return the value of UARTRXDMABREQ at the output of the test multiplexor.
1880 
1881 */
1882 #define UARTLIN_ITOP_RXDMABREQ 0x00001000U
1883 #define UARTLIN_ITOP_RXDMABREQ_M 0x00001000U
1884 #define UARTLIN_ITOP_RXDMABREQ_S 12U
1885 /*
1886 
1887  Field: RXDMASREQ
1888  From..to bits: 13...13
1889  DefaultValue: 0x0
1890  Access type: read-write
1891  Description: Intra-chip output of PrimeCell PL011 IP. Writes specify the value to be driven on UARTRXDMASREQ.
1892  Reads return the value of UARTRXDMASREQ at the output of the test multiplexor.
1893 
1894 */
1895 #define UARTLIN_ITOP_RXDMASREQ 0x00002000U
1896 #define UARTLIN_ITOP_RXDMASREQ_M 0x00002000U
1897 #define UARTLIN_ITOP_RXDMASREQ_S 13U
1898 /*
1899 
1900  Field: TXDMABREQ
1901  From..to bits: 14...14
1902  DefaultValue: 0x0
1903  Access type: read-write
1904  Description: Intra-chip output of PrimeCell PL011 IP. Writes specify the value to be driven on UARTTXDMABREQ.
1905  Reads return the value of UARTTXDMABREQ at the output of the test multiplexor.
1906 
1907 */
1908 #define UARTLIN_ITOP_TXDMABREQ 0x00004000U
1909 #define UARTLIN_ITOP_TXDMABREQ_M 0x00004000U
1910 #define UARTLIN_ITOP_TXDMABREQ_S 14U
1911 /*
1912 
1913  Field: TXDMASREQ
1914  From..to bits: 15...15
1915  DefaultValue: 0x0
1916  Access type: read-write
1917  Description: Intra-chip output of PrimeCell PL011 IP. Writes specify the value to be driven on UARTTXDMASREQ.
1918  Reads return the value of UARTTXDMASREQ at the output of the test multiplexor.
1919 
1920 */
1921 #define UARTLIN_ITOP_TXDMASREQ 0x00008000U
1922 #define UARTLIN_ITOP_TXDMASREQ_M 0x00008000U
1923 #define UARTLIN_ITOP_TXDMASREQ_S 15U
1924 
1925 
1926 /*-----------------------------------REGISTER------------------------------------
1927  Register name: TDR
1928  Offset name: UARTLIN_O_TDR
1929  Relative address: 0x8C
1930  Description: Test Data
1931  Default Value: 0x00000000
1932 
1933  Field: DATA
1934  From..to bits: 0...10
1935  DefaultValue: 0x0
1936  Access type: read-write
1937  Description: When the [TCR.TESTFIFO] bit is set to 1, data is written into the receive **FIFO** and read out of the transmit **FIFO**.
1938 
1939 */
1940 #define UARTLIN_TDR_DATA_W 11U
1941 #define UARTLIN_TDR_DATA_M 0x000007FFU
1942 #define UARTLIN_TDR_DATA_S 0U
1943 
1944 
1945 /*-----------------------------------REGISTER------------------------------------
1946  Register name: PERIPHID0
1947  Offset name: UARTLIN_O_PERIPHID0
1948  Relative address: 0xFE0
1949  Description: Peripheral Identification 0
1950  Default Value: 0x00000011
1951 
1952  Field: PARTNUM0
1953  From..to bits: 0...7
1954  DefaultValue: 0x11
1955  Access type: read-only
1956  Description: Identifies the peripheral
1957 
1958 */
1959 #define UARTLIN_PERIPHID0_PARTNUM0_W 8U
1960 #define UARTLIN_PERIPHID0_PARTNUM0_M 0x000000FFU
1961 #define UARTLIN_PERIPHID0_PARTNUM0_S 0U
1962 
1963 
1964 /*-----------------------------------REGISTER------------------------------------
1965  Register name: PERIPHID1
1966  Offset name: UARTLIN_O_PERIPHID1
1967  Relative address: 0xFE4
1968  Description: Peripheral Identification 1
1969  Default Value: 0x00000000
1970 
1971  Field: PARTNUM1
1972  From..to bits: 0...3
1973  DefaultValue: 0x0
1974  Access type: read-only
1975  Description: Identifies the peripheral
1976 
1977 */
1978 #define UARTLIN_PERIPHID1_PARTNUM1_W 4U
1979 #define UARTLIN_PERIPHID1_PARTNUM1_M 0x0000000FU
1980 #define UARTLIN_PERIPHID1_PARTNUM1_S 0U
1981 /*
1982 
1983  Field: DESIGNER0
1984  From..to bits: 4...7
1985  DefaultValue: 0x0
1986  Access type: read-only
1987  Description: Identifies the designer (ARM)
1988 
1989 */
1990 #define UARTLIN_PERIPHID1_DESIGNER0_W 4U
1991 #define UARTLIN_PERIPHID1_DESIGNER0_M 0x000000F0U
1992 #define UARTLIN_PERIPHID1_DESIGNER0_S 4U
1993 
1994 
1995 /*-----------------------------------REGISTER------------------------------------
1996  Register name: PERIPHID2
1997  Offset name: UARTLIN_O_PERIPHID2
1998  Relative address: 0xFE8
1999  Description: Peripheral Identification 2
2000  Default Value: 0x00000004
2001 
2002  Field: DESIGNER1
2003  From..to bits: 0...3
2004  DefaultValue: 0x4
2005  Access type: read-only
2006  Description: Identifies the designer (ARM)
2007 
2008 */
2009 #define UARTLIN_PERIPHID2_DESIGNER1_W 4U
2010 #define UARTLIN_PERIPHID2_DESIGNER1_M 0x0000000FU
2011 #define UARTLIN_PERIPHID2_DESIGNER1_S 0U
2012 /*
2013 
2014  Field: REVISION
2015  From..to bits: 4...7
2016  DefaultValue: 0x0
2017  Access type: read-only
2018  Description: UART revision
2019 
2020 */
2021 #define UARTLIN_PERIPHID2_REVISION_W 4U
2022 #define UARTLIN_PERIPHID2_REVISION_M 0x000000F0U
2023 #define UARTLIN_PERIPHID2_REVISION_S 4U
2024 
2025 
2026 /*-----------------------------------REGISTER------------------------------------
2027  Register name: PERIPHID3
2028  Offset name: UARTLIN_O_PERIPHID3
2029  Relative address: 0xFEC
2030  Description: Peripheral Identification 3
2031  Default Value: 0x00000000
2032 
2033  Field: CNF
2034  From..to bits: 0...7
2035  DefaultValue: 0x0
2036  Access type: read-only
2037  Description: The configuration option of the UART.
2038 
2039 */
2040 #define UARTLIN_PERIPHID3_CNF_W 8U
2041 #define UARTLIN_PERIPHID3_CNF_M 0x000000FFU
2042 #define UARTLIN_PERIPHID3_CNF_S 0U
2043 
2044 
2045 /*-----------------------------------REGISTER------------------------------------
2046  Register name: PCELLID0
2047  Offset name: UARTLIN_O_PCELLID0
2048  Relative address: 0xFF0
2049  Description: PrimeCell Identification 0
2050  Default Value: 0x0000000D
2051 
2052  Field: PCELLID0
2053  From..to bits: 0...7
2054  DefaultValue: 0xD
2055  Access type: read-only
2056  Description: This field is hard coded and reads back as 0x0D
2057 
2058 */
2059 #define UARTLIN_PCELLID0_PCELLID0_W 8U
2060 #define UARTLIN_PCELLID0_PCELLID0_M 0x000000FFU
2061 #define UARTLIN_PCELLID0_PCELLID0_S 0U
2062 
2063 
2064 /*-----------------------------------REGISTER------------------------------------
2065  Register name: PCELLID1
2066  Offset name: UARTLIN_O_PCELLID1
2067  Relative address: 0xFF4
2068  Description: PrimeCell Identification 1
2069  Default Value: 0x000000F0
2070 
2071  Field: PCELLID1
2072  From..to bits: 0...7
2073  DefaultValue: 0xF0
2074  Access type: read-only
2075  Description: This field is hard coded and reads back as 0xF0
2076 
2077 */
2078 #define UARTLIN_PCELLID1_PCELLID1_W 8U
2079 #define UARTLIN_PCELLID1_PCELLID1_M 0x000000FFU
2080 #define UARTLIN_PCELLID1_PCELLID1_S 0U
2081 
2082 
2083 /*-----------------------------------REGISTER------------------------------------
2084  Register name: PCELLID2
2085  Offset name: UARTLIN_O_PCELLID2
2086  Relative address: 0xFF8
2087  Description: PrimeCell Identification 2
2088  Default Value: 0x00000005
2089 
2090  Field: PCELLID2
2091  From..to bits: 0...7
2092  DefaultValue: 0x5
2093  Access type: read-only
2094  Description: This field is hard coded and reads back as 0x05
2095 
2096 */
2097 #define UARTLIN_PCELLID2_PCELLID2_W 8U
2098 #define UARTLIN_PCELLID2_PCELLID2_M 0x000000FFU
2099 #define UARTLIN_PCELLID2_PCELLID2_S 0U
2100 
2101 
2102 /*-----------------------------------REGISTER------------------------------------
2103  Register name: PCELLID3
2104  Offset name: UARTLIN_O_PCELLID3
2105  Relative address: 0xFFC
2106  Description: PrimeCell Identification 3
2107  Default Value: 0x000000B1
2108 
2109  Field: PCELLID3
2110  From..to bits: 0...7
2111  DefaultValue: 0xB1
2112  Access type: read-only
2113  Description: This field is hard coded and reads back as 0xB1
2114 
2115 */
2116 #define UARTLIN_PCELLID3_PCELLID3_W 8U
2117 #define UARTLIN_PCELLID3_PCELLID3_M 0x000000FFU
2118 #define UARTLIN_PCELLID3_PCELLID3_S 0U
2119 
2120 
2121 /*-----------------------------------REGISTER------------------------------------
2122  Register name: CLKCFG
2123  Offset name: UARTLIN_O_CLKCFG
2124  Relative address: 0x1000
2125  Description: This register enable or disables the bus clock *uartlin*
2126  Default Value: NA
2127 
2128  Field: EN
2129  From..to bits: 0...0
2130  DefaultValue: NA
2131  Access type: read-write
2132  Description: This bit enable or disables the bus clock *Uartlin*
2133 
2134  ENUMs:
2135  DIS: Disables the clock to *Uartlin*
2136  EN: Enables the clock to *Uartlin*
2137 */
2138 #define UARTLIN_CLKCFG_EN 0x00000001U
2139 #define UARTLIN_CLKCFG_EN_M 0x00000001U
2140 #define UARTLIN_CLKCFG_EN_S 0U
2141 #define UARTLIN_CLKCFG_EN_DIS 0x00000000U
2142 #define UARTLIN_CLKCFG_EN_EN 0x00000001U
2143 
2144 #endif /* __HW_UARTLIN_H__*/