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CC35xxDriverLibrary
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| #define SYSTIM_O_DESC 0x00000000U |
| #define SYSTIM_O_IBM 0x00000044U |
| #define SYSTIM_O_RIS 0x00000048U |
| #define SYSTIM_O_MIS 0x0000004CU |
| #define SYSTIM_O_ISET 0x00000050U |
| #define SYSTIM_O_ICLR 0x00000054U |
| #define SYSTIM_O_IMSET 0x00000058U |
| #define SYSTIM_O_IMCLR 0x0000005CU |
| #define SYSTIM_O_EMU 0x00000060U |
| #define SYSTIM_O_DTB 0x00000064U |
| #define SYSTIM_O_TIME250N 0x00000100U |
| #define SYSTIM_O_TIME1U 0x00000104U |
| #define SYSTIM_O_OUT 0x00000108U |
| #define SYSTIM_O_CH0CFG 0x0000010CU |
| #define SYSTIM_O_CH1CFG 0x00000110U |
| #define SYSTIM_O_CH0CC 0x00000120U |
| #define SYSTIM_O_CH1CC 0x00000124U |
| #define SYSTIM_O_TIMEBIT 0x00000134U |
| #define SYSTIM_O_KP 0x00000138U |
| #define SYSTIM_O_KI 0x0000013CU |
| #define SYSTIM_O_STA 0x00000140U |
| #define SYSTIM_O_ARMSET 0x00000144U |
| #define SYSTIM_O_ARMCLR 0x00000148U |
| #define SYSTIM_O_CH0CCSR 0x0000014CU |
| #define SYSTIM_O_CH1CCSR 0x00000150U |
| #define SYSTIM_O_CLKCFG 0x00001000U |
| #define SYSTIM_DESC_MINREV_W 4U |
| #define SYSTIM_DESC_MINREV_M 0x0000000FU |
| #define SYSTIM_DESC_MINREV_S 0U |
| #define SYSTIM_DESC_MINREV_MINIMUM 0x00000000U |
| #define SYSTIM_DESC_MINREV_MAXIMUM 0x0000000FU |
| #define SYSTIM_DESC_MAJREV_W 4U |
| #define SYSTIM_DESC_MAJREV_M 0x000000F0U |
| #define SYSTIM_DESC_MAJREV_S 4U |
| #define SYSTIM_DESC_MAJREV_MINIMUM 0x00000000U |
| #define SYSTIM_DESC_MAJREV_MAXIMUM 0x000000F0U |
| #define SYSTIM_DESC_INSTIDX_W 4U |
| #define SYSTIM_DESC_INSTIDX_M 0x00000F00U |
| #define SYSTIM_DESC_INSTIDX_S 8U |
| #define SYSTIM_DESC_INSTIDX_MINIMUM 0x00000000U |
| #define SYSTIM_DESC_INSTIDX_MAXIMUM 0x00000F00U |
| #define SYSTIM_DESC_STDIPOFF_W 4U |
| #define SYSTIM_DESC_STDIPOFF_M 0x0000F000U |
| #define SYSTIM_DESC_STDIPOFF_S 12U |
| #define SYSTIM_DESC_STDIPOFF_MINIMUM 0x00000000U |
| #define SYSTIM_DESC_STDIPOFF_MAXIMUM 0x0000F000U |
| #define SYSTIM_DESC_MODID_W 16U |
| #define SYSTIM_DESC_MODID_M 0xFFFF0000U |
| #define SYSTIM_DESC_MODID_S 16U |
| #define SYSTIM_DESC_MODID_MINIMUM 0x00000000U |
| #define SYSTIM_DESC_MODID_MAXIMUM 0xFFFF0000U |
| #define SYSTIM_IBM_EVT0 0x00000001U |
| #define SYSTIM_IBM_EVT0_M 0x00000001U |
| #define SYSTIM_IBM_EVT0_S 0U |
| #define SYSTIM_IBM_EVT0_CLR 0x00000000U |
| #define SYSTIM_IBM_EVT0_SET 0x00000001U |
| #define SYSTIM_IBM_EVT1 0x00000002U |
| #define SYSTIM_IBM_EVT1_M 0x00000002U |
| #define SYSTIM_IBM_EVT1_S 1U |
| #define SYSTIM_IBM_EVT1_CLR 0x00000000U |
| #define SYSTIM_IBM_EVT1_SET 0x00000002U |
| #define SYSTIM_IBM_OVFL 0x00000040U |
| #define SYSTIM_IBM_OVFL_M 0x00000040U |
| #define SYSTIM_IBM_OVFL_S 6U |
| #define SYSTIM_IBM_OVFL_CLR 0x00000000U |
| #define SYSTIM_IBM_OVFL_SET 0x00000040U |
| #define SYSTIM_RIS_EVT0 0x00000001U |
| #define SYSTIM_RIS_EVT0_M 0x00000001U |
| #define SYSTIM_RIS_EVT0_S 0U |
| #define SYSTIM_RIS_EVT0_CLR 0x00000000U |
| #define SYSTIM_RIS_EVT0_SET 0x00000001U |
| #define SYSTIM_RIS_EVT1 0x00000002U |
| #define SYSTIM_RIS_EVT1_M 0x00000002U |
| #define SYSTIM_RIS_EVT1_S 1U |
| #define SYSTIM_RIS_EVT1_CLR 0x00000000U |
| #define SYSTIM_RIS_EVT1_SET 0x00000002U |
| #define SYSTIM_RIS_OVFL 0x00000040U |
| #define SYSTIM_RIS_OVFL_M 0x00000040U |
| #define SYSTIM_RIS_OVFL_S 6U |
| #define SYSTIM_RIS_OVFL_CLR 0x00000000U |
| #define SYSTIM_RIS_OVFL_SET 0x00000040U |
| #define SYSTIM_MIS_EVT0 0x00000001U |
| #define SYSTIM_MIS_EVT0_M 0x00000001U |
| #define SYSTIM_MIS_EVT0_S 0U |
| #define SYSTIM_MIS_EVT0_CLR 0x00000000U |
| #define SYSTIM_MIS_EVT0_SET 0x00000001U |
| #define SYSTIM_MIS_EVT1 0x00000002U |
| #define SYSTIM_MIS_EVT1_M 0x00000002U |
| #define SYSTIM_MIS_EVT1_S 1U |
| #define SYSTIM_MIS_EVT1_CLR 0x00000000U |
| #define SYSTIM_MIS_EVT1_SET 0x00000002U |
| #define SYSTIM_MIS_OVFL 0x00000040U |
| #define SYSTIM_MIS_OVFL_M 0x00000040U |
| #define SYSTIM_MIS_OVFL_S 6U |
| #define SYSTIM_MIS_OVFL_CLR 0x00000000U |
| #define SYSTIM_MIS_OVFL_SET 0x00000040U |
| #define SYSTIM_ISET_EVT0 0x00000001U |
| #define SYSTIM_ISET_EVT0_M 0x00000001U |
| #define SYSTIM_ISET_EVT0_S 0U |
| #define SYSTIM_ISET_EVT0_NO_EFFECT 0x00000000U |
| #define SYSTIM_ISET_EVT0_SET 0x00000001U |
| #define SYSTIM_ISET_EVT1 0x00000002U |
| #define SYSTIM_ISET_EVT1_M 0x00000002U |
| #define SYSTIM_ISET_EVT1_S 1U |
| #define SYSTIM_ISET_EVT1_NO_EFFECT 0x00000000U |
| #define SYSTIM_ISET_EVT1_SET 0x00000002U |
| #define SYSTIM_ISET_OVFL 0x00000040U |
| #define SYSTIM_ISET_OVFL_M 0x00000040U |
| #define SYSTIM_ISET_OVFL_S 6U |
| #define SYSTIM_ISET_OVFL_NO_EFFECT 0x00000000U |
| #define SYSTIM_ISET_OVFL_SET 0x00000040U |
| #define SYSTIM_ICLR_EVT0 0x00000001U |
| #define SYSTIM_ICLR_EVT0_M 0x00000001U |
| #define SYSTIM_ICLR_EVT0_S 0U |
| #define SYSTIM_ICLR_EVT0_NO_EFFECT 0x00000000U |
| #define SYSTIM_ICLR_EVT0_CLR 0x00000001U |
| #define SYSTIM_ICLR_EVT1 0x00000002U |
| #define SYSTIM_ICLR_EVT1_M 0x00000002U |
| #define SYSTIM_ICLR_EVT1_S 1U |
| #define SYSTIM_ICLR_EVT1_NO_EFFECT 0x00000000U |
| #define SYSTIM_ICLR_EVT1_CLR 0x00000002U |
| #define SYSTIM_ICLR_OVFL 0x00000040U |
| #define SYSTIM_ICLR_OVFL_M 0x00000040U |
| #define SYSTIM_ICLR_OVFL_S 6U |
| #define SYSTIM_ICLR_OVFL_NO_EFFECT 0x00000000U |
| #define SYSTIM_ICLR_OVFL_CLR 0x00000040U |
| #define SYSTIM_IMSET_EVT0 0x00000001U |
| #define SYSTIM_IMSET_EVT0_M 0x00000001U |
| #define SYSTIM_IMSET_EVT0_S 0U |
| #define SYSTIM_IMSET_EVT0_NO_EFFECT 0x00000000U |
| #define SYSTIM_IMSET_EVT0_SET 0x00000001U |
| #define SYSTIM_IMSET_EVT1 0x00000002U |
| #define SYSTIM_IMSET_EVT1_M 0x00000002U |
| #define SYSTIM_IMSET_EVT1_S 1U |
| #define SYSTIM_IMSET_EVT1_NO_EFFECT 0x00000000U |
| #define SYSTIM_IMSET_EVT1_SET 0x00000002U |
| #define SYSTIM_IMSET_OVFL 0x00000040U |
| #define SYSTIM_IMSET_OVFL_M 0x00000040U |
| #define SYSTIM_IMSET_OVFL_S 6U |
| #define SYSTIM_IMSET_OVFL_NO_EFFECT 0x00000000U |
| #define SYSTIM_IMSET_OVFL_SET 0x00000040U |
| #define SYSTIM_IMCLR_EVT0 0x00000001U |
| #define SYSTIM_IMCLR_EVT0_M 0x00000001U |
| #define SYSTIM_IMCLR_EVT0_S 0U |
| #define SYSTIM_IMCLR_EVT0_NO_EFFECT 0x00000000U |
| #define SYSTIM_IMCLR_EVT0_CLR 0x00000001U |
| #define SYSTIM_IMCLR_EVT1 0x00000002U |
| #define SYSTIM_IMCLR_EVT1_M 0x00000002U |
| #define SYSTIM_IMCLR_EVT1_S 1U |
| #define SYSTIM_IMCLR_EVT1_NO_EFFECT 0x00000000U |
| #define SYSTIM_IMCLR_EVT1_CLR 0x00000002U |
| #define SYSTIM_IMCLR_OVFL 0x00000040U |
| #define SYSTIM_IMCLR_OVFL_M 0x00000040U |
| #define SYSTIM_IMCLR_OVFL_S 6U |
| #define SYSTIM_IMCLR_OVFL_NO_EFFECT 0x00000000U |
| #define SYSTIM_IMCLR_OVFL_CLR 0x00000040U |
| #define SYSTIM_EMU_HALT 0x00000001U |
| #define SYSTIM_EMU_HALT_M 0x00000001U |
| #define SYSTIM_EMU_HALT_S 0U |
| #define SYSTIM_EMU_HALT_RUN 0x00000000U |
| #define SYSTIM_EMU_HALT_STOP 0x00000001U |
| #define SYSTIM_DTB_SEL_W 4U |
| #define SYSTIM_DTB_SEL_M 0x0000000FU |
| #define SYSTIM_DTB_SEL_S 0U |
| #define SYSTIM_DTB_SEL_DISABLE 0x00000000U |
| #define SYSTIM_DTB_SEL_GRP1 0x00000001U |
| #define SYSTIM_DTB_SEL_GRP2 0x00000002U |
| #define SYSTIM_DTB_SEL_GRP3 0x00000003U |
| #define SYSTIM_DTB_SEL_GRP4 0x00000004U |
| #define SYSTIM_DTB_SEL_GRP5 0x00000005U |
| #define SYSTIM_DTB_SEL_GRP6 0x00000006U |
| #define SYSTIM_DTB_SEL_GRP7 0x00000007U |
| #define SYSTIM_DTB_SEL_GRP8 0x00000008U |
| #define SYSTIM_DTB_SEL_GRP9 0x00000009U |
| #define SYSTIM_DTB_SEL_GRP10 0x0000000AU |
| #define SYSTIM_DTB_SEL_GRP11 0x0000000BU |
| #define SYSTIM_DTB_SEL_GRP12 0x0000000CU |
| #define SYSTIM_DTB_SEL_GRP13 0x0000000DU |
| #define SYSTIM_DTB_SEL_GRP14 0x0000000EU |
| #define SYSTIM_DTB_SEL_GRP15 0x0000000FU |
| #define SYSTIM_TIME250N_VAL_W 32U |
| #define SYSTIM_TIME250N_VAL_M 0xFFFFFFFFU |
| #define SYSTIM_TIME250N_VAL_S 0U |
| #define SYSTIM_TIME250N_VAL_MINIMUM 0x00000000U |
| #define SYSTIM_TIME250N_VAL_MAXIMUM 0xFFFFFFFFU |
| #define SYSTIM_TIME1U_VAL_W 32U |
| #define SYSTIM_TIME1U_VAL_M 0xFFFFFFFFU |
| #define SYSTIM_TIME1U_VAL_S 0U |
| #define SYSTIM_TIME1U_VAL_MINIMUM 0x00000000U |
| #define SYSTIM_TIME1U_VAL_MAXIMUM 0xFFFFFFFFU |
| #define SYSTIM_OUT_OUT0 0x00000001U |
| #define SYSTIM_OUT_OUT0_M 0x00000001U |
| #define SYSTIM_OUT_OUT0_S 0U |
| #define SYSTIM_OUT_OUT0_CLR 0x00000000U |
| #define SYSTIM_OUT_OUT0_SET 0x00000001U |
| #define SYSTIM_OUT_OUT1 0x00000002U |
| #define SYSTIM_OUT_OUT1_M 0x00000002U |
| #define SYSTIM_OUT_OUT1_S 1U |
| #define SYSTIM_OUT_OUT1_CLR 0x00000000U |
| #define SYSTIM_OUT_OUT1_SET 0x00000002U |
| #define SYSTIM_CH0CFG_MODE 0x00000001U |
| #define SYSTIM_CH0CFG_MODE_M 0x00000001U |
| #define SYSTIM_CH0CFG_MODE_S 0U |
| #define SYSTIM_CH0CFG_MODE_DIS 0x00000000U |
| #define SYSTIM_CH0CFG_MODE_CAPT 0x00000001U |
| #define SYSTIM_CH0CFG_INP_W 2U |
| #define SYSTIM_CH0CFG_INP_M 0x00000006U |
| #define SYSTIM_CH0CFG_INP_S 1U |
| #define SYSTIM_CH0CFG_INP_RISE 0x00000000U |
| #define SYSTIM_CH0CFG_INP_FALL 0x00000002U |
| #define SYSTIM_CH0CFG_INP_BOTH 0x00000004U |
| #define SYSTIM_CH0CFG_REARM 0x00000008U |
| #define SYSTIM_CH0CFG_REARM_M 0x00000008U |
| #define SYSTIM_CH0CFG_REARM_S 3U |
| #define SYSTIM_CH0CFG_REARM_EN 0x00000008U |
| #define SYSTIM_CH0CFG_REARM_NS 0x00000000U |
| #define SYSTIM_CH0CFG_RES 0x00000010U |
| #define SYSTIM_CH0CFG_RES_M 0x00000010U |
| #define SYSTIM_CH0CFG_RES_S 4U |
| #define SYSTIM_CH0CFG_RES_US 0x00000000U |
| #define SYSTIM_CH0CFG_RES_NS 0x00000010U |
| #define SYSTIM_CH1CFG_MODE 0x00000001U |
| #define SYSTIM_CH1CFG_MODE_M 0x00000001U |
| #define SYSTIM_CH1CFG_MODE_S 0U |
| #define SYSTIM_CH1CFG_MODE_DIS 0x00000000U |
| #define SYSTIM_CH1CFG_MODE_CAPT 0x00000001U |
| #define SYSTIM_CH1CFG_INP_W 2U |
| #define SYSTIM_CH1CFG_INP_M 0x00000006U |
| #define SYSTIM_CH1CFG_INP_S 1U |
| #define SYSTIM_CH1CFG_INP_RISE 0x00000000U |
| #define SYSTIM_CH1CFG_INP_FALL 0x00000002U |
| #define SYSTIM_CH1CFG_INP_BOTH 0x00000004U |
| #define SYSTIM_CH1CFG_REARM 0x00000008U |
| #define SYSTIM_CH1CFG_REARM_M 0x00000008U |
| #define SYSTIM_CH1CFG_REARM_S 3U |
| #define SYSTIM_CH1CFG_REARM_EN 0x00000008U |
| #define SYSTIM_CH1CFG_REARM_NS 0x00000000U |
| #define SYSTIM_CH0CC_VAL_W 32U |
| #define SYSTIM_CH0CC_VAL_M 0xFFFFFFFFU |
| #define SYSTIM_CH0CC_VAL_S 0U |
| #define SYSTIM_CH0CC_VAL_MINIMUM 0x00000000U |
| #define SYSTIM_CH0CC_VAL_MAXIMUM 0xFFFFFFFFU |
| #define SYSTIM_CH1CC_VAL_W 32U |
| #define SYSTIM_CH1CC_VAL_M 0xFFFFFFFFU |
| #define SYSTIM_CH1CC_VAL_S 0U |
| #define SYSTIM_CH1CC_VAL_MINIMUM 0x00000000U |
| #define SYSTIM_CH1CC_VAL_MAXIMUM 0xFFFFFFFFU |
| #define SYSTIM_TIMEBIT_VAL_W 16U |
| #define SYSTIM_TIMEBIT_VAL_M 0x0000FFFFU |
| #define SYSTIM_TIMEBIT_VAL_S 0U |
| #define SYSTIM_TIMEBIT_VAL_NOBIT 0x00000000U |
| #define SYSTIM_TIMEBIT_VAL_BIT3 0x00000002U |
| #define SYSTIM_TIMEBIT_VAL_BIT4 0x00000004U |
| #define SYSTIM_TIMEBIT_VAL_BIT5 0x00000008U |
| #define SYSTIM_TIMEBIT_VAL_BIT6 0x00000010U |
| #define SYSTIM_TIMEBIT_VAL_BIT7 0x00000020U |
| #define SYSTIM_TIMEBIT_VAL_BIT8 0x00000040U |
| #define SYSTIM_TIMEBIT_VAL_BIT9 0x00000080U |
| #define SYSTIM_TIMEBIT_VAL_BIT10 0x00000100U |
| #define SYSTIM_TIMEBIT_VAL_BIT11 0x00000200U |
| #define SYSTIM_TIMEBIT_VAL_BIT12 0x00000400U |
| #define SYSTIM_TIMEBIT_VAL_BIT13 0x00000800U |
| #define SYSTIM_TIMEBIT_VAL_BIT14 0x00001000U |
| #define SYSTIM_TIMEBIT_VAL_BIT15 0x00002000U |
| #define SYSTIM_TIMEBIT_VAL_BIT16 0x00004000U |
| #define SYSTIM_TIMEBIT_VAL_BIT17 0x00008000U |
| #define SYSTIM_TIMEBIT_VAL_BIT2 0x00000001U |
| #define SYSTIM_KP_VAL_W 4U |
| #define SYSTIM_KP_VAL_M 0x0000000FU |
| #define SYSTIM_KP_VAL_S 0U |
| #define SYSTIM_KP_VAL_MINIMUM 0x00000000U |
| #define SYSTIM_KP_VAL_MAXIMUM 0x0000000FU |
| #define SYSTIM_KI_VAL_W 4U |
| #define SYSTIM_KI_VAL_M 0x0000000FU |
| #define SYSTIM_KI_VAL_S 0U |
| #define SYSTIM_KI_VAL_MINIMUM 0x00000000U |
| #define SYSTIM_KI_VAL_MAXIMUM 0x0000000FU |
| #define SYSTIM_STA_VAL 0x00000001U |
| #define SYSTIM_STA_VAL_M 0x00000001U |
| #define SYSTIM_STA_VAL_S 0U |
| #define SYSTIM_STA_VAL_STOP 0x00000000U |
| #define SYSTIM_STA_VAL_RUN 0x00000001U |
| #define SYSTIM_STA_SYNCUP 0x00000010U |
| #define SYSTIM_STA_SYNCUP_M 0x00000010U |
| #define SYSTIM_STA_SYNCUP_S 4U |
| #define SYSTIM_STA_SYNCUP_CLR 0x00000000U |
| #define SYSTIM_STA_SYNCUP_SET 0x00000010U |
| #define SYSTIM_ARMSET_CH0 0x00000001U |
| #define SYSTIM_ARMSET_CH0_M 0x00000001U |
| #define SYSTIM_ARMSET_CH0_S 0U |
| #define SYSTIM_ARMSET_CH0_NOEFFECT 0x00000000U |
| #define SYSTIM_ARMSET_CH0_SET 0x00000001U |
| #define SYSTIM_ARMSET_CH1 0x00000002U |
| #define SYSTIM_ARMSET_CH1_M 0x00000002U |
| #define SYSTIM_ARMSET_CH1_S 1U |
| #define SYSTIM_ARMSET_CH1_NOEFFECT 0x00000000U |
| #define SYSTIM_ARMSET_CH1_SET 0x00000002U |
| #define SYSTIM_ARMCLR_CH0 0x00000001U |
| #define SYSTIM_ARMCLR_CH0_M 0x00000001U |
| #define SYSTIM_ARMCLR_CH0_S 0U |
| #define SYSTIM_ARMCLR_CH0_NOEFFECT 0x00000000U |
| #define SYSTIM_ARMCLR_CH0_CLR 0x00000001U |
| #define SYSTIM_ARMCLR_CH1 0x00000002U |
| #define SYSTIM_ARMCLR_CH1_M 0x00000002U |
| #define SYSTIM_ARMCLR_CH1_S 1U |
| #define SYSTIM_ARMCLR_CH1_NOEFFECT 0x00000000U |
| #define SYSTIM_ARMCLR_CH1_CLR 0x00000002U |
| #define SYSTIM_CH0CCSR_VAL_W 32U |
| #define SYSTIM_CH0CCSR_VAL_M 0xFFFFFFFFU |
| #define SYSTIM_CH0CCSR_VAL_S 0U |
| #define SYSTIM_CH0CCSR_VAL_MINIMUM 0x00000000U |
| #define SYSTIM_CH0CCSR_VAL_MAXIMUM 0xFFFFFFFFU |
| #define SYSTIM_CH1CCSR_VAL_W 32U |
| #define SYSTIM_CH1CCSR_VAL_M 0xFFFFFFFFU |
| #define SYSTIM_CH1CCSR_VAL_S 0U |
| #define SYSTIM_CH1CCSR_VAL_MINIMUM 0x00000000U |
| #define SYSTIM_CH1CCSR_VAL_MAXIMUM 0xFFFFFFFFU |
| #define SYSTIM_CLKCFG_EN 0x00000001U |
| #define SYSTIM_CLKCFG_EN_M 0x00000001U |
| #define SYSTIM_CLKCFG_EN_S 0U |
| #define SYSTIM_CLKCFG_EN_MINIMUM 0x00000000U |
| #define SYSTIM_CLKCFG_EN_MAXIMUM 0xFFFFFFFFU |