CC35xxDriverLibrary
hw_sysresources.h
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1 /******************************************************************************
2 * Filename: hw_sysresources.h
3 *
4 * Description: Defines and prototypes for the SYSRESOURCES peripheral.
5 *
6 * Copyright (c) 2023, Texas Instruments Incorporated
7 * All rights reserved.
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13 * this list of conditions and the following disclaimer.
14 *
15 * 2) Redistributions in binary form must reproduce the above copyright notice,
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23  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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35 ******************************************************************************/
36 #ifndef __HW_SYSRESOURCES_H__
37 #define __HW_SYSRESOURCES_H__
38 /*-------------------------------------------------------------------------------
39 
40 This section defines the register offsets of the SYSRESOURCES component
41 
42 --------------------------------------------------------------------------------- */
43 
44 //SYSTIM_CTRL
45 #define SYSRESOURCES_O_SYSTIM_CTRL 0x00000008U
46 
47 //MEMSS_GENERAL
48 #define SYSRESOURCES_O_MEMSS_GENERAL 0x00000400U
49 
50 //MEMSS_BUS_FAULT_RAW_STATUS
51 #define SYSRESOURCES_O_MEMSS_BUS_FAULT_RAW_STATUS 0x00000404U
52 
53 
54 
55 /*-----------------------------------REGISTER------------------------------------
56  Register name: SYSTIM_CTRL
57  Offset name: SYSRESOURCES_O_SYSTIM_CTRL
58  Relative address: 0x8
59  Description:
60  Default Value: 0x00000000
61 
62  Field: MEM_SYSTIM_ENCLK
63  From..to bits: 0...0
64  DefaultValue: 0x0
65  Access type: read-write
66  Description: '1' - enable the reqeusets for the systim clk
67 
68 */
69 #define SYSRESOURCES_SYSTIM_CTRL_MEM_SYSTIM_ENCLK 0x00000001U
70 #define SYSRESOURCES_SYSTIM_CTRL_MEM_SYSTIM_ENCLK_M 0x00000001U
71 #define SYSRESOURCES_SYSTIM_CTRL_MEM_SYSTIM_ENCLK_S 0U
72 
73 
74 /*-----------------------------------REGISTER------------------------------------
75  Register name: MEMSS_GENERAL
76  Offset name: SYSRESOURCES_O_MEMSS_GENERAL
77  Relative address: 0x400
78  Description:
79  Default Value: 0x00000000
80 
81  Field: MEM_STRV_CNTR_VAL
82  From..to bits: 0...2
83  DefaultValue: 0x0
84  Access type: read-write
85  Description: HOST to config how long writing to mailbox can be delayed
86 
87 */
88 #define SYSRESOURCES_MEMSS_GENERAL_MEM_STRV_CNTR_VAL_W 3U
89 #define SYSRESOURCES_MEMSS_GENERAL_MEM_STRV_CNTR_VAL_M 0x00000007U
90 #define SYSRESOURCES_MEMSS_GENERAL_MEM_STRV_CNTR_VAL_S 0U
91 /*
92 
93  Field: MEM_MEMSS_BUS_FAULT_MASK
94  From..to bits: 3...3
95  DefaultValue: 0x0
96  Access type: read-write
97  Description: '1' - Mask
98  '0' - Do not mask
99 
100 */
101 #define SYSRESOURCES_MEMSS_GENERAL_MEM_MEMSS_BUS_FAULT_MASK 0x00000008U
102 #define SYSRESOURCES_MEMSS_GENERAL_MEM_MEMSS_BUS_FAULT_MASK_M 0x00000008U
103 #define SYSRESOURCES_MEMSS_GENERAL_MEM_MEMSS_BUS_FAULT_MASK_S 3U
104 /*
105 
106  Field: MEMSS_BUS_FAULT_STATUS_MASKED
107  From..to bits: 4...6
108  DefaultValue: 0x0
109  Access type: read-only
110  Description: '1' - Mask
111  '0' - Do not mask
112 
113 */
114 #define SYSRESOURCES_MEMSS_GENERAL_MEMSS_BUS_FAULT_STATUS_MASKED_W 3U
115 #define SYSRESOURCES_MEMSS_GENERAL_MEMSS_BUS_FAULT_STATUS_MASKED_M 0x00000070U
116 #define SYSRESOURCES_MEMSS_GENERAL_MEMSS_BUS_FAULT_STATUS_MASKED_S 4U
117 
118 
119 /*-----------------------------------REGISTER------------------------------------
120  Register name: MEMSS_BUS_FAULT_RAW_STATUS
121  Offset name: SYSRESOURCES_O_MEMSS_BUS_FAULT_RAW_STATUS
122  Relative address: 0x404
123  Description:
124  Default Value: 0x00000000
125 
126  Field: MEMSS_BUS_FAULT_STATUS_RAW_RDCL
127  From..to bits: 0...2
128  DefaultValue: 0x0
129  Access type: read-only
130  Description: HOST to config how long writing to mailbox can be delayed
131 
132 */
133 #define SYSRESOURCES_MEMSS_BUS_FAULT_RAW_STATUS_MEMSS_BUS_FAULT_STATUS_RAW_RDCL_W 3U
134 #define SYSRESOURCES_MEMSS_BUS_FAULT_RAW_STATUS_MEMSS_BUS_FAULT_STATUS_RAW_RDCL_M 0x00000007U
135 #define SYSRESOURCES_MEMSS_BUS_FAULT_RAW_STATUS_MEMSS_BUS_FAULT_STATUS_RAW_RDCL_S 0U
136 
137 #endif /* __HW_SYSRESOURCES_H__*/