CC35xxDriverLibrary
hw_soc_debugss_dssm.h
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1 /******************************************************************************
2 * Filename: hw_soc_debugss_dssm.h
3 *
4 * Description: Defines and prototypes for the SOC_DEBUGSS_DSSM peripheral.
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6 * Copyright (c) 2023-2025, Texas Instruments Incorporated
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36 #ifndef __HW_SOC_DEBUGSS_DSSM_H__
37 #define __HW_SOC_DEBUGSS_DSSM_H__
38 /*-------------------------------------------------------------------------------
39 
40 This section defines the register offsets of the SOC_DEBUGSS_DSSM component
41 
42 --------------------------------------------------------------------------------- */
43 
44 //This register provides the highest priority enabled interrupt index
45 #define SOC_DEBUGSS_DSSM_O_IIDX 0x00000020U
46 
47 //Interrupt Mask
48 #define SOC_DEBUGSS_DSSM_O_IMASK 0x00000028U
49 
50 //Raw Interrupt Status
51 #define SOC_DEBUGSS_DSSM_O_RIS 0x00000030U
52 
53 //Masked Interrupt Status
54 #define SOC_DEBUGSS_DSSM_O_MIS 0x00000038U
55 
56 //Interrupt Clear
57 #define SOC_DEBUGSS_DSSM_O_ICLR 0x00000040U
58 
59 //Interrupt Set
60 #define SOC_DEBUGSS_DSSM_O_TRIG 0x00000048U
61 
62 //This register is to select the primary debug domain
63 #define SOC_DEBUGSS_DSSM_O_PRIDBGDMN 0x000000E0U
64 
65 //This register is used for data transfers from external debug tools to the DSSM module
66 #define SOC_DEBUGSS_DSSM_O_TXD 0x00000060U
67 
68 //Transmit control register
69 #define SOC_DEBUGSS_DSSM_O_TXCTL 0x00000064U
70 
71 //Receive data register
72 #define SOC_DEBUGSS_DSSM_O_RXD 0x00000068U
73 
74 //Receive control register
75 #define SOC_DEBUGSS_DSSM_O_RXCTL 0x0000006CU
76 
77 //This register is used to control SEC_DBG, NONSEC_DBG, SPIDEN, and SPNONSEC_DBG of Application APPCPU
78 #define SOC_DEBUGSS_DSSM_O_AUTHAPPCPU 0x00000090U
79 
80 //This register is used to control SEC_DBG, NONSEC_DBG, SPIDEN, and SPNONSEC_DBG of Application CORE
81 #define SOC_DEBUGSS_DSSM_O_AUTHCORE 0x000000A0U
82 
83 
84 
85 /*-----------------------------------REGISTER------------------------------------
86  Register name: IIDX
87  Offset name: SOC_DEBUGSS_DSSM_O_IIDX
88  Relative address: 0x20
89  Description: This register provides the highest priority enabled interrupt index. FFh means no event pending. Interrupt 0h is the highest priority, 1h next highest, and FEh is the least priority. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
90 
91  On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt, if none are pending, then it displays FFh.
92  Default Value: 0x00000000
93 
94  Field: STAT
95  From..to bits: 0...1
96  DefaultValue: 0x0
97  Access type: read-only
98  Description: Interrupt index status
99 
100  ENUMs:
101  NO_INTR: No pending interrupt request
102  MSG_PEND: TX interrupt
103  MSG_TAKEN: RX interrupt
104 */
105 #define SOC_DEBUGSS_DSSM_IIDX_STAT_W 2U
106 #define SOC_DEBUGSS_DSSM_IIDX_STAT_M 0x00000003U
107 #define SOC_DEBUGSS_DSSM_IIDX_STAT_S 0U
108 #define SOC_DEBUGSS_DSSM_IIDX_STAT_NO_INTR 0x00000000U
109 #define SOC_DEBUGSS_DSSM_IIDX_STAT_MSG_PEND 0x00000001U
110 #define SOC_DEBUGSS_DSSM_IIDX_STAT_MSG_TAKEN 0x00000002U
111 
112 
113 /*-----------------------------------REGISTER------------------------------------
114  Register name: IMASK
115  Offset name: SOC_DEBUGSS_DSSM_O_IMASK
116  Relative address: 0x28
117  Description: Interrupt Mask.
118 
119  If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.
120  Default Value: 0x00000000
121 
122  Field: MSGPEND
123  From..to bits: 0...0
124  DefaultValue: 0x0
125  Access type: read-write
126  Description: Masks MSG_PEND in MIS register
127 
128  ENUMs:
129  CLR: Interrupt is masked out
130  SET: Interrupt will request an interrupt service routine and corresponding bit in MIS will be set
131 */
132 #define SOC_DEBUGSS_DSSM_IMASK_MSGPEND 0x00000001U
133 #define SOC_DEBUGSS_DSSM_IMASK_MSGPEND_M 0x00000001U
134 #define SOC_DEBUGSS_DSSM_IMASK_MSGPEND_S 0U
135 #define SOC_DEBUGSS_DSSM_IMASK_MSGPEND_CLR 0x00000000U
136 #define SOC_DEBUGSS_DSSM_IMASK_MSGPEND_SET 0x00000001U
137 /*
138 
139  Field: MSGTAKEN
140  From..to bits: 1...1
141  DefaultValue: 0x0
142  Access type: read-write
143  Description: Masks MSG_TAKEN in MIS register
144 
145  ENUMs:
146  CLR: Interrupt is masked out
147  SET: Interrupt will request an interrupt service routine and corresponding bit in MIS will be set
148 */
149 #define SOC_DEBUGSS_DSSM_IMASK_MSGTAKEN 0x00000002U
150 #define SOC_DEBUGSS_DSSM_IMASK_MSGTAKEN_M 0x00000002U
151 #define SOC_DEBUGSS_DSSM_IMASK_MSGTAKEN_S 1U
152 #define SOC_DEBUGSS_DSSM_IMASK_MSGTAKEN_CLR 0x00000000U
153 #define SOC_DEBUGSS_DSSM_IMASK_MSGTAKEN_SET 0x00000002U
154 
155 
156 /*-----------------------------------REGISTER------------------------------------
157  Register name: RIS
158  Offset name: SOC_DEBUGSS_DSSM_O_RIS
159  Relative address: 0x30
160  Description: Raw Interrupt Status.
161 
162  Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
163  Default Value: 0x00000000
164 
165  Field: MSGPEND
166  From..to bits: 0...0
167  DefaultValue: 0x0
168  Access type: read-only
169  Description: Raw interrupt status for MSG_PEND
170 
171  ENUMs:
172  SET: MSG_PEND occurred
173  CLR: MSG_PEND did not occur
174 */
175 #define SOC_DEBUGSS_DSSM_RIS_MSGPEND 0x00000001U
176 #define SOC_DEBUGSS_DSSM_RIS_MSGPEND_M 0x00000001U
177 #define SOC_DEBUGSS_DSSM_RIS_MSGPEND_S 0U
178 #define SOC_DEBUGSS_DSSM_RIS_MSGPEND_SET 0x00000001U
179 #define SOC_DEBUGSS_DSSM_RIS_MSGPEND_CLR 0x00000000U
180 /*
181 
182  Field: MSGTAKEN
183  From..to bits: 1...1
184  DefaultValue: 0x0
185  Access type: read-only
186  Description: Raw interrupt status for MSG_TAKEN
187 
188  ENUMs:
189  SET: MSG_TAKEN occurred
190  CLR: MSG_TAKEN did not occur
191 */
192 #define SOC_DEBUGSS_DSSM_RIS_MSGTAKEN 0x00000002U
193 #define SOC_DEBUGSS_DSSM_RIS_MSGTAKEN_M 0x00000002U
194 #define SOC_DEBUGSS_DSSM_RIS_MSGTAKEN_S 1U
195 #define SOC_DEBUGSS_DSSM_RIS_MSGTAKEN_SET 0x00000002U
196 #define SOC_DEBUGSS_DSSM_RIS_MSGTAKEN_CLR 0x00000000U
197 
198 
199 /*-----------------------------------REGISTER------------------------------------
200  Register name: MIS
201  Offset name: SOC_DEBUGSS_DSSM_O_MIS
202  Relative address: 0x38
203  Description: Masked Interrupt Status.
204 
205  This is an AND of the IMASK and RIS registers.
206  Default Value: 0x00000000
207 
208  Field: MSGPEND
209  From..to bits: 0...0
210  DefaultValue: 0x0
211  Access type: read-only
212  Description: Masked interrupt status for MSG_PEND
213 
214  ENUMs:
215  SET: MSG_PEND requests an interrupt service routine
216  CLR: MSG_PEND did not request an interrupt service routine
217 */
218 #define SOC_DEBUGSS_DSSM_MIS_MSGPEND 0x00000001U
219 #define SOC_DEBUGSS_DSSM_MIS_MSGPEND_M 0x00000001U
220 #define SOC_DEBUGSS_DSSM_MIS_MSGPEND_S 0U
221 #define SOC_DEBUGSS_DSSM_MIS_MSGPEND_SET 0x00000001U
222 #define SOC_DEBUGSS_DSSM_MIS_MSGPEND_CLR 0x00000000U
223 /*
224 
225  Field: MSGTAKEN
226  From..to bits: 1...1
227  DefaultValue: 0x0
228  Access type: read-only
229  Description: Masked interrupt status for MSG_TAKEN
230 
231  ENUMs:
232  SET: MSG_TAKEN requests an interrupt service routine
233  CLR: MSG_TAKEN did not request an interrupt service routine
234 */
235 #define SOC_DEBUGSS_DSSM_MIS_MSGTAKEN 0x00000002U
236 #define SOC_DEBUGSS_DSSM_MIS_MSGTAKEN_M 0x00000002U
237 #define SOC_DEBUGSS_DSSM_MIS_MSGTAKEN_S 1U
238 #define SOC_DEBUGSS_DSSM_MIS_MSGTAKEN_SET 0x00000002U
239 #define SOC_DEBUGSS_DSSM_MIS_MSGTAKEN_CLR 0x00000000U
240 
241 
242 /*-----------------------------------REGISTER------------------------------------
243  Register name: ICLR
244  Offset name: SOC_DEBUGSS_DSSM_O_ICLR
245  Relative address: 0x40
246  Description: Interrupt Clear.
247 
248  Write a 1 to clear corresponding Interrupt.
249  Default Value: 0x00000000
250 
251  Field: MSGPEND
252  From..to bits: 0...0
253  DefaultValue: 0x0
254  Access type: write-only
255  Description: Clears MSG_PEND_WROPT in RIS register
256 
257  ENUMs:
258  CLR: RIS bit corresponding to MSG_PEND is cleared
259  NO_EFFECT: Writing a 0 has no effect
260 */
261 #define SOC_DEBUGSS_DSSM_ICLR_MSGPEND 0x00000001U
262 #define SOC_DEBUGSS_DSSM_ICLR_MSGPEND_M 0x00000001U
263 #define SOC_DEBUGSS_DSSM_ICLR_MSGPEND_S 0U
264 #define SOC_DEBUGSS_DSSM_ICLR_MSGPEND_CLR 0x00000001U
265 #define SOC_DEBUGSS_DSSM_ICLR_MSGPEND_NO_EFFECT 0x00000000U
266 /*
267 
268  Field: MSGTAKEN
269  From..to bits: 1...1
270  DefaultValue: 0x0
271  Access type: write-only
272  Description: Clears MSG_TAKEN_WROPT in RIS register
273 
274  ENUMs:
275  CLR: RIS bit corresponding to MSG_TAKEN is cleared
276  NO_EFFECT: Writing a 0 has no effect
277 */
278 #define SOC_DEBUGSS_DSSM_ICLR_MSGTAKEN 0x00000002U
279 #define SOC_DEBUGSS_DSSM_ICLR_MSGTAKEN_M 0x00000002U
280 #define SOC_DEBUGSS_DSSM_ICLR_MSGTAKEN_S 1U
281 #define SOC_DEBUGSS_DSSM_ICLR_MSGTAKEN_CLR 0x00000002U
282 #define SOC_DEBUGSS_DSSM_ICLR_MSGTAKEN_NO_EFFECT 0x00000000U
283 
284 
285 /*-----------------------------------REGISTER------------------------------------
286  Register name: TRIG
287  Offset name: SOC_DEBUGSS_DSSM_O_TRIG
288  Relative address: 0x48
289  Description: Interrupt Set.
290 
291  Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
292  Default Value: 0x00000000
293 
294  Field: MSGPEND
295  From..to bits: 0...0
296  DefaultValue: 0x0
297  Access type: write-only
298  Description: Sets MSG_PEND_WROPT in RIS register
299 
300  ENUMs:
301  SET: RIS bit corresponding to MSG_PEND is set
302  NO_EFFECT: Writing a 0 has no effect
303 */
304 #define SOC_DEBUGSS_DSSM_TRIG_MSGPEND 0x00000001U
305 #define SOC_DEBUGSS_DSSM_TRIG_MSGPEND_M 0x00000001U
306 #define SOC_DEBUGSS_DSSM_TRIG_MSGPEND_S 0U
307 #define SOC_DEBUGSS_DSSM_TRIG_MSGPEND_SET 0x00000001U
308 #define SOC_DEBUGSS_DSSM_TRIG_MSGPEND_NO_EFFECT 0x00000000U
309 /*
310 
311  Field: MSGTAKEN
312  From..to bits: 1...1
313  DefaultValue: 0x0
314  Access type: write-only
315  Description: Sets MSG_TAKEN_WROPT in RIS register
316 
317  ENUMs:
318  SET: RIS bit corresponding to MSG_TAKEN is set
319  NO_EFFECT: Writing a 0 has no effect
320 */
321 #define SOC_DEBUGSS_DSSM_TRIG_MSGTAKEN 0x00000002U
322 #define SOC_DEBUGSS_DSSM_TRIG_MSGTAKEN_M 0x00000002U
323 #define SOC_DEBUGSS_DSSM_TRIG_MSGTAKEN_S 1U
324 #define SOC_DEBUGSS_DSSM_TRIG_MSGTAKEN_SET 0x00000002U
325 #define SOC_DEBUGSS_DSSM_TRIG_MSGTAKEN_NO_EFFECT 0x00000000U
326 
327 
328 /*-----------------------------------REGISTER------------------------------------
329  Register name: PRIDBGDMN
330  Offset name: SOC_DEBUGSS_DSSM_O_PRIDBGDMN
331  Relative address: 0xE0
332  Description: This register is to select the primary debug domain. Whichever domain is selected as primary gets powered up by writing onto csyspwrupreq bit
333  Default Value: 0x00000001
334 
335  Field: HOST
336  From..to bits: 0...0
337  DefaultValue: 0x1
338  Access type: read-write
339  Description: Set this bit to 1 if host is to be selected as primary debug domain
340 
341 */
342 #define SOC_DEBUGSS_DSSM_PRIDBGDMN_HOST 0x00000001U
343 #define SOC_DEBUGSS_DSSM_PRIDBGDMN_HOST_M 0x00000001U
344 #define SOC_DEBUGSS_DSSM_PRIDBGDMN_HOST_S 0U
345 /*
346 
347  Field: CORE
348  From..to bits: 1...1
349  DefaultValue: 0x0
350  Access type: read-write
351  Description: Set this bit to 1 if core is to be selected as primary debug domain
352 
353 */
354 #define SOC_DEBUGSS_DSSM_PRIDBGDMN_CORE 0x00000002U
355 #define SOC_DEBUGSS_DSSM_PRIDBGDMN_CORE_M 0x00000002U
356 #define SOC_DEBUGSS_DSSM_PRIDBGDMN_CORE_S 1U
357 
358 
359 /*-----------------------------------REGISTER------------------------------------
360  Register name: TXD
361  Offset name: SOC_DEBUGSS_DSSM_O_TXD
362  Relative address: 0x60
363  Description: This register is used for data transfers from external debug tools to the DSSM module. With the first write access to this register after power cycle a system reset request is issued.
364 
365  The first write to this register after RESET_ALL will trigger a SYSRST request being asserted for one (or as many as required by the system) clock cycle.
366  Default Value: 0x00000000
367 
368  Field: TXDATA
369  From..to bits: 0...31
370  DefaultValue: 0x0
371  Access type: read-only
372  Description: Contains data written by an external debug tool to the SEC-AP TXDATA register
373 
374 */
375 #define SOC_DEBUGSS_DSSM_TXD_TXDATA_W 32U
376 #define SOC_DEBUGSS_DSSM_TXD_TXDATA_M 0xFFFFFFFFU
377 #define SOC_DEBUGSS_DSSM_TXD_TXDATA_S 0U
378 
379 
380 /*-----------------------------------REGISTER------------------------------------
381  Register name: TXCTL
382  Offset name: SOC_DEBUGSS_DSSM_O_TXCTL
383  Relative address: 0x64
384  Description: Transmit control register
385  Default Value: 0x00000000
386 
387  Field: TX
388  From..to bits: 0...0
389  DefaultValue: 0x0
390  Access type: read-only
391  Description: Indicates data request in DSSM.TXD, set on write via Debug AP to DSSM.TXD.
392 
393  A read of the DSSM.TXD register by SM/OW will clear the TX field. The tool can check that TXD is empty by reading this field.
394  When this flag is 1, a debug request to the SM/OW controller is asserted. If the command starts with 0xAA,
395  the interrupt goes to the SM (or the OW if there is no SM) and if starts with 0x55, it always goes to the OW (going to AT-TEST authentication).
396 
397  ENUMs:
398  EMPTY: TXD is empty
399  FULL: TXD is full
400 */
401 #define SOC_DEBUGSS_DSSM_TXCTL_TX 0x00000001U
402 #define SOC_DEBUGSS_DSSM_TXCTL_TX_M 0x00000001U
403 #define SOC_DEBUGSS_DSSM_TXCTL_TX_S 0U
404 #define SOC_DEBUGSS_DSSM_TXCTL_TX_EMPTY 0x00000000U
405 #define SOC_DEBUGSS_DSSM_TXCTL_TX_FULL 0x00000001U
406 /*
407 
408  Field: TXFLAG
409  From..to bits: 1...31
410  DefaultValue: 0x0
411  Access type: read-only
412  Description: Generic TX flags that can be set by external debug tool. Functionality is defined by SW.
413 
414 */
415 #define SOC_DEBUGSS_DSSM_TXCTL_TXFLAG_W 31U
416 #define SOC_DEBUGSS_DSSM_TXCTL_TXFLAG_M 0xFFFFFFFEU
417 #define SOC_DEBUGSS_DSSM_TXCTL_TXFLAG_S 1U
418 
419 
420 /*-----------------------------------REGISTER------------------------------------
421  Register name: RXD
422  Offset name: SOC_DEBUGSS_DSSM_O_RXD
423  Relative address: 0x68
424  Description: Receive data register. This register contains the data received from SM/OW.
425  This data is read by external debug tool.
426  Default Value: 0x00000000
427 
428  Field: RXDATA
429  From..to bits: 0...31
430  DefaultValue: 0x0
431  Access type: read-write
432  Description: Contains data written by SM/OW.
433 
434 */
435 #define SOC_DEBUGSS_DSSM_RXD_RXDATA_W 32U
436 #define SOC_DEBUGSS_DSSM_RXD_RXDATA_M 0xFFFFFFFFU
437 #define SOC_DEBUGSS_DSSM_RXD_RXDATA_S 0U
438 
439 
440 /*-----------------------------------REGISTER------------------------------------
441  Register name: RXCTL
442  Offset name: SOC_DEBUGSS_DSSM_O_RXCTL
443  Relative address: 0x6C
444  Description: Receive control register
445  Default Value: 0x00000000
446 
447  Field: RCV
448  From..to bits: 0...0
449  DefaultValue: 0x0
450  Access type: read-only
451  Description: Indicates SM/OW write to the DSSM.RXD register.
452  A read of the DSSM.RXD register by SWD (JTAG) Access Port will clear the RX field.
453 
454  ENUMs:
455  EMPTY: RXD empty
456  FULL: RXD full
457 */
458 #define SOC_DEBUGSS_DSSM_RXCTL_RCV 0x00000001U
459 #define SOC_DEBUGSS_DSSM_RXCTL_RCV_M 0x00000001U
460 #define SOC_DEBUGSS_DSSM_RXCTL_RCV_S 0U
461 #define SOC_DEBUGSS_DSSM_RXCTL_RCV_EMPTY 0x00000000U
462 #define SOC_DEBUGSS_DSSM_RXCTL_RCV_FULL 0x00000001U
463 /*
464 
465  Field: RCVFLAGS
466  From..to bits: 1...31
467  DefaultValue: 0x0
468  Access type: read-write
469  Description: Generic RX flags that can be set by SW and read by external debug tool. Functionality is defined by SW.
470 
471 */
472 #define SOC_DEBUGSS_DSSM_RXCTL_RCVFLAGS_W 31U
473 #define SOC_DEBUGSS_DSSM_RXCTL_RCVFLAGS_M 0xFFFFFFFEU
474 #define SOC_DEBUGSS_DSSM_RXCTL_RCVFLAGS_S 1U
475 
476 
477 /*-----------------------------------REGISTER------------------------------------
478  Register name: AUTHAPPCPU
479  Offset name: SOC_DEBUGSS_DSSM_O_AUTHAPPCPU
480  Relative address: 0x90
481  Description: This register is used to control SEC_DBG, NONSEC_DBG, SPIDEN, and SPNONSEC_DBG of Application APPCPU.
482  SEC_DBG, NONSEC_DBG are further processed by DSW based on Active and Debug IPF ID.
483  Default Value: 0x00000000
484 
485  Field: SECDBG
486  From..to bits: 0...0
487  DefaultValue: 0x0
488  Access type: read-only
489  Description: Controls invasive debug enable.
490  SEC_DBG is further processed by DSW based on Active and Debug IPF ID.
491 
492  ENUMs:
493  DISABLE: Invasive debug disabled
494  ENABLE: Invasive debug enabled
495 */
496 #define SOC_DEBUGSS_DSSM_AUTHAPPCPU_SECDBG 0x00000001U
497 #define SOC_DEBUGSS_DSSM_AUTHAPPCPU_SECDBG_M 0x00000001U
498 #define SOC_DEBUGSS_DSSM_AUTHAPPCPU_SECDBG_S 0U
499 #define SOC_DEBUGSS_DSSM_AUTHAPPCPU_SECDBG_DISABLE 0x00000000U
500 #define SOC_DEBUGSS_DSSM_AUTHAPPCPU_SECDBG_ENABLE 0x00000001U
501 /*
502 
503  Field: NONSECDBG
504  From..to bits: 1...1
505  DefaultValue: 0x0
506  Access type: read-only
507  Description: Controls non-invasive debug enable.
508  NONSEC_DBG is further processed by DSW based on Active and Debug IPF ID.
509 
510  ENUMs:
511  DISABLE: Non-invasive debug disabled
512  ENABLE: Non-invasive debug enabled
513 */
514 #define SOC_DEBUGSS_DSSM_AUTHAPPCPU_NONSECDBG 0x00000002U
515 #define SOC_DEBUGSS_DSSM_AUTHAPPCPU_NONSECDBG_M 0x00000002U
516 #define SOC_DEBUGSS_DSSM_AUTHAPPCPU_NONSECDBG_S 1U
517 #define SOC_DEBUGSS_DSSM_AUTHAPPCPU_NONSECDBG_DISABLE 0x00000000U
518 #define SOC_DEBUGSS_DSSM_AUTHAPPCPU_NONSECDBG_ENABLE 0x00000002U
519 
520 
521 /*-----------------------------------REGISTER------------------------------------
522  Register name: AUTHCORE
523  Offset name: SOC_DEBUGSS_DSSM_O_AUTHCORE
524  Relative address: 0xA0
525  Description: This register is used to control SEC_DBG, NONSEC_DBG, SPIDEN, and SPNONSEC_DBG of Application CORE.
526  SEC_DBG, NONSEC_DBG are further processed by DSW based on Active and Debug IPF ID.
527  Default Value: 0x00000000
528 
529  Field: DBG
530  From..to bits: 0...0
531  DefaultValue: 0x0
532  Access type: read-only
533  Description: Controls invasive debug enable.
534  DBG is further processed by DSW based on Active and Debug IPF ID.
535 
536  ENUMs:
537  DISABLE: Invasive debug disabled
538  ENABLE: Invasive debug enabled
539 */
540 #define SOC_DEBUGSS_DSSM_AUTHCORE_DBG 0x00000001U
541 #define SOC_DEBUGSS_DSSM_AUTHCORE_DBG_M 0x00000001U
542 #define SOC_DEBUGSS_DSSM_AUTHCORE_DBG_S 0U
543 #define SOC_DEBUGSS_DSSM_AUTHCORE_DBG_DISABLE 0x00000000U
544 #define SOC_DEBUGSS_DSSM_AUTHCORE_DBG_ENABLE 0x00000001U
545 
546 #endif /* __HW_SOC_DEBUGSS_DSSM_H__*/