CC35xxDriverLibrary
hw_soc_aaon.h
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1 /******************************************************************************
2 * Filename: hw_soc_aaon.h
3 *
4 * Description: Defines and prototypes for the SOC_AAON peripheral.
5 *
6 * Copyright (c) 2023-2025, Texas Instruments Incorporated
7 * All rights reserved.
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13 * this list of conditions and the following disclaimer.
14 *
15 * 2) Redistributions in binary form must reproduce the above copyright notice,
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18 *
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23  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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35 ******************************************************************************/
36 #ifndef __HW_SOC_AAON_H__
37 #define __HW_SOC_AAON_H__
38 /*-------------------------------------------------------------------------------
39 
40 This section defines the register offsets of the SOC_AAON component
41 
42 --------------------------------------------------------------------------------- */
43 
44 //DMA M33 Secure Event IMASK
45 #define SOC_AAON_O_DMASIMASK 0x00000000U
46 
47 //DMA M33 Secure Event ISET
48 #define SOC_AAON_O_DMASISET 0x00000004U
49 
50 //DMA M33 Secure Event ICLR
51 #define SOC_AAON_O_DMASICLR 0x00000008U
52 
53 //DMA M33 Secure Event IMSET
54 #define SOC_AAON_O_DMASIMSET 0x0000000CU
55 
56 //DMA M33 Secure Event IMCLR
57 #define SOC_AAON_O_DMASIMCLR 0x00000010U
58 
59 //DMA M33 Secure Event RIS
60 #define SOC_AAON_O_DMASRIS 0x00000014U
61 
62 //DMA M33 Secure Event MIS
63 #define SOC_AAON_O_DMASMIS 0x00000018U
64 
65 //DMA M33 Non-Secured IMASK
66 #define SOC_AAON_O_DMANSIMASK 0x00001000U
67 
68 //DMA M33 Non-Secured ISET
69 #define SOC_AAON_O_DMANSISET 0x00001004U
70 
71 //DMA M33 Non-Secured ICLR
72 #define SOC_AAON_O_DMANSICLR 0x00001008U
73 
74 //DMA M33 Non-Secured IMSET
75 #define SOC_AAON_O_DMANSIMSET 0x0000100CU
76 
77 //DMA M33 Non-Secured IMCLR
78 #define SOC_AAON_O_DMANSIMCLR 0x00001010U
79 
80 //DMA M33 Non-Secured RIS
81 #define SOC_AAON_O_DMANSRIS 0x00001014U
82 
83 //DMA M33 Non-Secured MIS
84 #define SOC_AAON_O_DMANSMIS 0x00001018U
85 
86 //DMA M3 Event IMASK
87 #define SOC_AAON_O_DMAM3IMASK 0x00002000U
88 
89 //DMA M3 Event ISET
90 #define SOC_AAON_O_DMAM3ISET 0x00002004U
91 
92 //DMA M3 Event ICLR
93 #define SOC_AAON_O_DMAM3ICLR 0x00002008U
94 
95 //DMA M3 Event IMSET
96 #define SOC_AAON_O_DMAM3IMSET 0x0000200CU
97 
98 //DMA M3 Event IMCLR
99 #define SOC_AAON_O_DMAM3IMCLR 0x00002010U
100 
101 //DMA M3 Event RIS
102 #define SOC_AAON_O_DMAM3RIS 0x00002014U
103 
104 //DMA M3 Event MIS
105 #define SOC_AAON_O_DMAM3MIS 0x00002018U
106 
107 
108 
109 /*-----------------------------------REGISTER------------------------------------
110  Register name: DMASIMASK
111  Offset name: SOC_AAON_O_DMASIMASK
112  Relative address: 0x0
113  Description: DMA M33 Secure Event IMASK.
114  Mask Event.
115  '0' - CLR - Clear Interrupt Mask
116  '1' - SET - Set Interrupt Mask
117  Default Value: 0x00000000
118 
119  Field: IMASK
120  From..to bits: 0...11
121  DefaultValue: 0x0
122  Access type: read-write
123  Description: '0' - CLR - Clear Interrupt Mask
124  '1' - SET - Set Interrupt Mask
125 
126 */
127 #define SOC_AAON_DMASIMASK_IMASK_W 12U
128 #define SOC_AAON_DMASIMASK_IMASK_M 0x00000FFFU
129 #define SOC_AAON_DMASIMASK_IMASK_S 0U
130 
131 
132 /*-----------------------------------REGISTER------------------------------------
133  Register name: DMASISET
134  Offset name: SOC_AAON_O_DMASISET
135  Relative address: 0x4
136  Description: DMA M33 Secure Event ISET.
137  Sets event in RIS
138  Write 0 - NO_EFFECT - Writing 0 has no effect
139  Write 1 - SET - Sets interrupt
140  Default Value: 0x00000000
141 
142  Field: ISET
143  From..to bits: 0...11
144  DefaultValue: 0x0
145  Access type: write-only
146  Description: Write 0 - NO_EFFECT - Writing 0 has no effect
147  Write 1 - SET - Sets interrupt
148  Type: Write-Clear.
149 
150 */
151 #define SOC_AAON_DMASISET_ISET_W 12U
152 #define SOC_AAON_DMASISET_ISET_M 0x00000FFFU
153 #define SOC_AAON_DMASISET_ISET_S 0U
154 
155 
156 /*-----------------------------------REGISTER------------------------------------
157  Register name: DMASICLR
158  Offset name: SOC_AAON_O_DMASICLR
159  Relative address: 0x8
160  Description: DMA M33 Secure Event ICLR.
161  Clears event in RIS
162  Write 0 - NO_EFFECT - Writing 0 has no effect
163  Write 1 - CLR - Clears the Event
164  Default Value: 0x00000000
165 
166  Field: ICLR
167  From..to bits: 0...11
168  DefaultValue: 0x0
169  Access type: write-only
170  Description: Write 0 - NO_EFFECT - Writing 0 has no effect
171  Write 1 - CLR - Clears the Event
172  Type: Write-Clear.
173 
174 */
175 #define SOC_AAON_DMASICLR_ICLR_W 12U
176 #define SOC_AAON_DMASICLR_ICLR_M 0x00000FFFU
177 #define SOC_AAON_DMASICLR_ICLR_S 0U
178 
179 
180 /*-----------------------------------REGISTER------------------------------------
181  Register name: DMASIMSET
182  Offset name: SOC_AAON_O_DMASIMSET
183  Relative address: 0xC
184  Description: DMA M33 Secure Event IMSET.
185  Sets Event
186  Write 0 - NO_EFFECT - Writing 0 has no effect
187  Write 1 - SET - Set interrupt mask
188  Default Value: 0x00000000
189 
190  Field: IMSET
191  From..to bits: 0...11
192  DefaultValue: 0x0
193  Access type: write-only
194  Description: Write 0 - NO_EFFECT - Writing 0 has no effect
195  Write 1 - SET - Set interrupt mask
196  Type: Write-Clear
197 
198 */
199 #define SOC_AAON_DMASIMSET_IMSET_W 12U
200 #define SOC_AAON_DMASIMSET_IMSET_M 0x00000FFFU
201 #define SOC_AAON_DMASIMSET_IMSET_S 0U
202 
203 
204 /*-----------------------------------REGISTER------------------------------------
205  Register name: DMASIMCLR
206  Offset name: SOC_AAON_O_DMASIMCLR
207  Relative address: 0x10
208  Description: DMA M33 Secure Event IMCLR.
209  Clears Event
210  Write 0 - NO_EFFECT - Writing 0 has no effect
211  Write 1 - CLR - Clear interrupt mask
212  Default Value: 0x00000000
213 
214  Field: IMCLR
215  From..to bits: 0...11
216  DefaultValue: 0x0
217  Access type: write-only
218  Description: Write 0 - NO_EFFECT - Writing 0 has no effect
219  Write 1 - CLR - Clear interrupt mask
220  Type: Write-Clear.
221 
222 */
223 #define SOC_AAON_DMASIMCLR_IMCLR_W 12U
224 #define SOC_AAON_DMASIMCLR_IMCLR_M 0x00000FFFU
225 #define SOC_AAON_DMASIMCLR_IMCLR_S 0U
226 
227 
228 /*-----------------------------------REGISTER------------------------------------
229  Register name: DMASRIS
230  Offset name: SOC_AAON_O_DMASRIS
231  Relative address: 0x14
232  Description: DMA M33 Secure Event RIS.
233  Raw interrupt status for event.
234  This bit is set to 1 when an event is received. when the corresponding bit in ICLR is set to 1, this bit will be cleared.
235  Read 0 - CLR - Interrupt did not occur
236  Read 1 - SET - Interrupt occurred
237  Default Value: 0x00000000
238 
239  Field: RIS
240  From..to bits: 0...11
241  DefaultValue: 0x0
242  Access type: read-only
243  Description: Read 0 - CLR - Interrupt did not occur
244  Read 1 - SET - Interrupt occurred
245 
246 */
247 #define SOC_AAON_DMASRIS_RIS_W 12U
248 #define SOC_AAON_DMASRIS_RIS_M 0x00000FFFU
249 #define SOC_AAON_DMASRIS_RIS_S 0U
250 
251 
252 /*-----------------------------------REGISTER------------------------------------
253  Register name: DMASMIS
254  Offset name: SOC_AAON_O_DMASMIS
255  Relative address: 0x18
256  Description: DMA M33 Secure Event MIS.
257  Mask interrupt status for event
258  Read 0 - CLR - Interrupt did not occur
259  Read 1 - SET - Interrupt occurred
260  Default Value: 0x00000000
261 
262  Field: MIS
263  From..to bits: 0...11
264  DefaultValue: 0x0
265  Access type: read-only
266  Description: Read 0 - CLR - Interrupt did not occur
267  Read 1 - SET - Interrupt occurred
268 
269 */
270 #define SOC_AAON_DMASMIS_MIS_W 12U
271 #define SOC_AAON_DMASMIS_MIS_M 0x00000FFFU
272 #define SOC_AAON_DMASMIS_MIS_S 0U
273 
274 
275 /*-----------------------------------REGISTER------------------------------------
276  Register name: DMANSIMASK
277  Offset name: SOC_AAON_O_DMANSIMASK
278  Relative address: 0x1000
279  Description: DMA M33 Non-Secured IMASK.
280  Mask Event.
281  '0' - CLR - Clear Interrupt Mask
282  '1' - SET - Set Interrupt Mask
283  Default Value: 0x00000000
284 
285  Field: IMASK
286  From..to bits: 0...11
287  DefaultValue: 0x0
288  Access type: read-write
289  Description: '0' - CLR - Clear Interrupt Mask
290  '1' - SET - Set Interrupt Mask
291 
292 */
293 #define SOC_AAON_DMANSIMASK_IMASK_W 12U
294 #define SOC_AAON_DMANSIMASK_IMASK_M 0x00000FFFU
295 #define SOC_AAON_DMANSIMASK_IMASK_S 0U
296 
297 
298 /*-----------------------------------REGISTER------------------------------------
299  Register name: DMANSISET
300  Offset name: SOC_AAON_O_DMANSISET
301  Relative address: 0x1004
302  Description: DMA M33 Non-Secured ISET.
303  Sets event in RIS
304  Write 0 - NO_EFFECT - Writing 0 has no effect
305  Write 1 - SET - Sets interrupt
306  Default Value: 0x00000000
307 
308  Field: ISET
309  From..to bits: 0...11
310  DefaultValue: 0x0
311  Access type: write-only
312  Description: Write 0 - NO_EFFECT - Writing 0 has no effect
313  Write 1 - SET - Sets interrupt
314  Type: Write-Clear.
315 
316 */
317 #define SOC_AAON_DMANSISET_ISET_W 12U
318 #define SOC_AAON_DMANSISET_ISET_M 0x00000FFFU
319 #define SOC_AAON_DMANSISET_ISET_S 0U
320 
321 
322 /*-----------------------------------REGISTER------------------------------------
323  Register name: DMANSICLR
324  Offset name: SOC_AAON_O_DMANSICLR
325  Relative address: 0x1008
326  Description: DMA M33 Non-Secured ICLR.
327  Clears event in RIS
328  Write 0 - NO_EFFECT - Writing 0 has no effect
329  Write 1 - CLR - Clears the Event
330  Default Value: 0x00000000
331 
332  Field: ICLR
333  From..to bits: 0...11
334  DefaultValue: 0x0
335  Access type: write-only
336  Description: Write 0 - NO_EFFECT - Writing 0 has no effect
337  Write 1 - CLR - Clears the Event
338  Type: Write-Clear.
339 
340 */
341 #define SOC_AAON_DMANSICLR_ICLR_W 12U
342 #define SOC_AAON_DMANSICLR_ICLR_M 0x00000FFFU
343 #define SOC_AAON_DMANSICLR_ICLR_S 0U
344 
345 
346 /*-----------------------------------REGISTER------------------------------------
347  Register name: DMANSIMSET
348  Offset name: SOC_AAON_O_DMANSIMSET
349  Relative address: 0x100C
350  Description: DMA M33 Non-Secured IMSET.
351  Sets Event
352  Write 0 - NO_EFFECT - Writing 0 has no effect
353  Write 1 - SET - Set interrupt mask
354  Default Value: 0x00000000
355 
356  Field: IMSET
357  From..to bits: 0...11
358  DefaultValue: 0x0
359  Access type: write-only
360  Description: Write 0 - NO_EFFECT - Writing 0 has no effect
361  Write 1 - SET - Set interrupt mask
362  Type: Write-Clear
363 
364 */
365 #define SOC_AAON_DMANSIMSET_IMSET_W 12U
366 #define SOC_AAON_DMANSIMSET_IMSET_M 0x00000FFFU
367 #define SOC_AAON_DMANSIMSET_IMSET_S 0U
368 
369 
370 /*-----------------------------------REGISTER------------------------------------
371  Register name: DMANSIMCLR
372  Offset name: SOC_AAON_O_DMANSIMCLR
373  Relative address: 0x1010
374  Description: DMA M33 Non-Secured IMCLR.
375  Clears Event
376  Write 0 - NO_EFFECT - Writing 0 has no effect
377  Write 1 - CLR - Clear interrupt mask
378  Default Value: 0x00000000
379 
380  Field: IMCLR
381  From..to bits: 0...11
382  DefaultValue: 0x0
383  Access type: write-only
384  Description: Write 0 - NO_EFFECT - Writing 0 has no effect
385  Write 1 - CLR - Clear interrupt mask
386  Type: Write-Clear.
387 
388 */
389 #define SOC_AAON_DMANSIMCLR_IMCLR_W 12U
390 #define SOC_AAON_DMANSIMCLR_IMCLR_M 0x00000FFFU
391 #define SOC_AAON_DMANSIMCLR_IMCLR_S 0U
392 
393 
394 /*-----------------------------------REGISTER------------------------------------
395  Register name: DMANSRIS
396  Offset name: SOC_AAON_O_DMANSRIS
397  Relative address: 0x1014
398  Description: DMA M33 Non-Secured RIS.
399  Raw interrupt status for event.
400  This bit is set to 1 when an event is received. when the corresponding bit in ICLR is set to 1, this bit will be cleared.
401  Read 0 - CLR - Interrupt did not occur
402  Read 1 - SET - Interrupt occurred
403  Default Value: 0x00000000
404 
405  Field: RIS
406  From..to bits: 0...11
407  DefaultValue: 0x0
408  Access type: read-only
409  Description: Read 0 - CLR - Interrupt did not occur
410  Read 1 - SET - Interrupt occurred
411 
412 */
413 #define SOC_AAON_DMANSRIS_RIS_W 12U
414 #define SOC_AAON_DMANSRIS_RIS_M 0x00000FFFU
415 #define SOC_AAON_DMANSRIS_RIS_S 0U
416 
417 
418 /*-----------------------------------REGISTER------------------------------------
419  Register name: DMANSMIS
420  Offset name: SOC_AAON_O_DMANSMIS
421  Relative address: 0x1018
422  Description: DMA M33 Non-Secured MIS.
423  Mask interrupt status for event
424  Read 0 - CLR - Interrupt did not occur
425  Read 1 - SET - Interrupt occurred
426  Default Value: 0x00000000
427 
428  Field: MIS
429  From..to bits: 0...11
430  DefaultValue: 0x0
431  Access type: read-only
432  Description: Read 0 - CLR - Interrupt did not occur
433  Read 1 - SET - Interrupt occurred
434 
435 */
436 #define SOC_AAON_DMANSMIS_MIS_W 12U
437 #define SOC_AAON_DMANSMIS_MIS_M 0x00000FFFU
438 #define SOC_AAON_DMANSMIS_MIS_S 0U
439 
440 
441 /*-----------------------------------REGISTER------------------------------------
442  Register name: DMAM3IMASK
443  Offset name: SOC_AAON_O_DMAM3IMASK
444  Relative address: 0x2000
445  Description: DMA M3 Event IMASK.
446  Mask Event.
447  '0' - CLR - Clear Interrupt Mask
448  '1' - SET - Set Interrupt Mask
449  Default Value: 0x00000000
450 
451  Field: IMASK
452  From..to bits: 0...11
453  DefaultValue: 0x0
454  Access type: read-write
455  Description: '0' - CLR - Clear Interrupt Mask
456  '1' - SET - Set Interrupt Mask
457 
458 */
459 #define SOC_AAON_DMAM3IMASK_IMASK_W 12U
460 #define SOC_AAON_DMAM3IMASK_IMASK_M 0x00000FFFU
461 #define SOC_AAON_DMAM3IMASK_IMASK_S 0U
462 
463 
464 /*-----------------------------------REGISTER------------------------------------
465  Register name: DMAM3ISET
466  Offset name: SOC_AAON_O_DMAM3ISET
467  Relative address: 0x2004
468  Description: DMA M3 Event ISET.
469  Sets event in RIS
470  Write 0 - NO_EFFECT - Writing 0 has no effect
471  Write 1 - SET - Sets interrupt
472  Default Value: 0x00000000
473 
474  Field: ISET
475  From..to bits: 0...11
476  DefaultValue: 0x0
477  Access type: write-only
478  Description: Write 0 - NO_EFFECT - Writing 0 has no effect
479  Write 1 - SET - Sets interrupt
480  Type: Write-Clear.
481 
482 */
483 #define SOC_AAON_DMAM3ISET_ISET_W 12U
484 #define SOC_AAON_DMAM3ISET_ISET_M 0x00000FFFU
485 #define SOC_AAON_DMAM3ISET_ISET_S 0U
486 
487 
488 /*-----------------------------------REGISTER------------------------------------
489  Register name: DMAM3ICLR
490  Offset name: SOC_AAON_O_DMAM3ICLR
491  Relative address: 0x2008
492  Description: DMA M3 Event ICLR.
493  Clears event in RIS
494  Write 0 - NO_EFFECT - Writing 0 has no effect
495  Write 1 - CLR - Clears the Event
496  Default Value: 0x00000000
497 
498  Field: ICLR
499  From..to bits: 0...11
500  DefaultValue: 0x0
501  Access type: write-only
502  Description: Write 0 - NO_EFFECT - Writing 0 has no effect
503  Write 1 - CLR - Clears the Event
504  Type: Write-Clear.
505 
506 */
507 #define SOC_AAON_DMAM3ICLR_ICLR_W 12U
508 #define SOC_AAON_DMAM3ICLR_ICLR_M 0x00000FFFU
509 #define SOC_AAON_DMAM3ICLR_ICLR_S 0U
510 
511 
512 /*-----------------------------------REGISTER------------------------------------
513  Register name: DMAM3IMSET
514  Offset name: SOC_AAON_O_DMAM3IMSET
515  Relative address: 0x200C
516  Description: DMA M3 Event IMSET.
517  Sets Event
518  Write 0 - NO_EFFECT - Writing 0 has no effect
519  Write 1 - SET - Set interrupt mask
520  Default Value: 0x00000000
521 
522  Field: IMSET
523  From..to bits: 0...11
524  DefaultValue: 0x0
525  Access type: write-only
526  Description: Write 0 - NO_EFFECT - Writing 0 has no effect
527  Write 1 - SET - Set interrupt mask
528  Type: Write-Clear
529 
530 */
531 #define SOC_AAON_DMAM3IMSET_IMSET_W 12U
532 #define SOC_AAON_DMAM3IMSET_IMSET_M 0x00000FFFU
533 #define SOC_AAON_DMAM3IMSET_IMSET_S 0U
534 
535 
536 /*-----------------------------------REGISTER------------------------------------
537  Register name: DMAM3IMCLR
538  Offset name: SOC_AAON_O_DMAM3IMCLR
539  Relative address: 0x2010
540  Description: DMA M3 Event IMCLR.
541  Clears Event
542  Write 0 - NO_EFFECT - Writing 0 has no effect
543  Write 1 - CLR - Clear interrupt mask
544  Default Value: 0x00000000
545 
546  Field: IMCLR
547  From..to bits: 0...11
548  DefaultValue: 0x0
549  Access type: write-only
550  Description: Write 0 - NO_EFFECT - Writing 0 has no effect
551  Write 1 - CLR - Clear interrupt mask
552  Type: Write-Clear.
553 
554 */
555 #define SOC_AAON_DMAM3IMCLR_IMCLR_W 12U
556 #define SOC_AAON_DMAM3IMCLR_IMCLR_M 0x00000FFFU
557 #define SOC_AAON_DMAM3IMCLR_IMCLR_S 0U
558 
559 
560 /*-----------------------------------REGISTER------------------------------------
561  Register name: DMAM3RIS
562  Offset name: SOC_AAON_O_DMAM3RIS
563  Relative address: 0x2014
564  Description: DMA M3 Event RIS.
565  This bit is set to 1 when an event is received. when the corresponding bit in ICLR is set to 1, this bit will be cleared.
566  Read 0 - CLR - Interrupt did not occur
567  Read 1 - SET - Interrupt occurred
568  Default Value: 0x00000000
569 
570  Field: RIS
571  From..to bits: 0...11
572  DefaultValue: 0x0
573  Access type: read-only
574  Description: Read 0 - CLR - Interrupt did not occur
575  Read 1 - SET - Interrupt occurred
576 
577 */
578 #define SOC_AAON_DMAM3RIS_RIS_W 12U
579 #define SOC_AAON_DMAM3RIS_RIS_M 0x00000FFFU
580 #define SOC_AAON_DMAM3RIS_RIS_S 0U
581 
582 
583 /*-----------------------------------REGISTER------------------------------------
584  Register name: DMAM3MIS
585  Offset name: SOC_AAON_O_DMAM3MIS
586  Relative address: 0x2018
587  Description: DMA M3 Event MIS.
588  Mask interrupt status for event
589  Read 0 - CLR - Interrupt did not occur
590  Read 1 - SET - Interrupt occurred
591  Default Value: 0x00000000
592 
593  Field: MIS
594  From..to bits: 0...11
595  DefaultValue: 0x0
596  Access type: read-only
597  Description: Read 0 - CLR - Interrupt did not occur
598  Read 1 - SET - Interrupt occured
599 
600 */
601 #define SOC_AAON_DMAM3MIS_MIS_W 12U
602 #define SOC_AAON_DMAM3MIS_MIS_M 0x00000FFFU
603 #define SOC_AAON_DMAM3MIS_MIS_S 0U
604 
605 #endif /* __HW_SOC_AAON_H__*/