CC35xxDriverLibrary
hw_rtc.h
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1 /******************************************************************************
2 * Filename: hw_rtc.h
3 *
4 * Description: Defines and prototypes for the RTC peripheral.
5 *
6 * Copyright (c) 2023, Texas Instruments Incorporated
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36 #ifndef __HW_RTC_H__
37 #define __HW_RTC_H__
38 /*-------------------------------------------------------------------------------
39 
40 This section defines the register offsets of the RTC component
41 
42 --------------------------------------------------------------------------------- */
43 
44 //Description Register
45 #define RTC_O_DESC 0x00000000U
46 
47 //RTC Control register
48 #define RTC_O_CTL 0x00000004U
49 
50 //RTC channel mode set register
51 #define RTC_O_ARMSET 0x00000008U
52 
53 //RTC channel mode clear register
54 #define RTC_O_ARMCLR 0x0000000CU
55 
56 //RTC Time value register
57 #define RTC_O_TIME250N 0x00000010U
58 
59 //RTC Time value register
60 #define RTC_O_TIME1U 0x00000014U
61 
62 //RTC Time value register
63 #define RTC_O_TIME8U 0x00000018U
64 
65 //RTC time value register
66 #define RTC_O_TIME524M 0x0000001CU
67 
68 //Channel 0 compare value with 250ns resolution
69 #define RTC_O_CH0CC250N 0x00000020U
70 
71 //Channel 0 compare value with 1us resolution
72 #define RTC_O_CH0CC1U 0x00000024U
73 
74 //Channel 0 compare value
75 #define RTC_O_CH0CC8U 0x00000028U
76 
77 //Channel 1 capture value
78 #define RTC_O_CH1CC8U 0x00000038U
79 
80 //Channel 1 configuration register
81 #define RTC_O_CH1CFG 0x0000003CU
82 
83 //Interrupt Mask
84 #define RTC_O_IMASK 0x00000044U
85 
86 //Interrupt mask
87 #define RTC_O_RIS 0x00000048U
88 
89 //Masked interrupt status
90 #define RTC_O_MIS 0x0000004CU
91 
92 //Interrupt set register
93 #define RTC_O_ISET 0x00000050U
94 
95 //Interrupt clear register
96 #define RTC_O_ICLR 0x00000054U
97 
98 //Interrupt mask set register
99 #define RTC_O_IMSET 0x00000058U
100 
101 //Interrupt mask clear register
102 #define RTC_O_IMCLR 0x0000005CU
103 
104 //Emulation control register
105 #define RTC_O_EMU 0x00000060U
106 
107 //Digital test bus control register
108 #define RTC_O_DTB 0x00000064U
109 
110 //A delta time mechanism is implemented for RTC that allows the TIME value to be adjusted under software control
111 #define RTC_O_DTIME 0x00000068U
112 
113 
114 
115 /*-----------------------------------REGISTER------------------------------------
116  Register name: DESC
117  Offset name: RTC_O_DESC
118  Relative address: 0x0
119  Description: Description Register. This register provides IP module ID, revision information, instance index and standard MMR registers offset.
120  Default Value: 0x64421010
121 
122  Field: MINREV
123  From..to bits: 0...3
124  DefaultValue: 0x0
125  Access type: read-only
126  Description: Minor revision of IP (0-15).
127 
128 */
129 #define RTC_DESC_MINREV_W 4U
130 #define RTC_DESC_MINREV_M 0x0000000FU
131 #define RTC_DESC_MINREV_S 0U
132 /*
133 
134  Field: MAJREV
135  From..to bits: 4...7
136  DefaultValue: 0x1
137  Access type: read-only
138  Description: Major revision of IP (0-15).
139 
140 */
141 #define RTC_DESC_MAJREV_W 4U
142 #define RTC_DESC_MAJREV_M 0x000000F0U
143 #define RTC_DESC_MAJREV_S 4U
144 /*
145 
146  Field: INSTIDX
147  From..to bits: 8...11
148  DefaultValue: 0x0
149  Access type: read-only
150  Description: IP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15).
151 
152 */
153 #define RTC_DESC_INSTIDX_W 4U
154 #define RTC_DESC_INSTIDX_M 0x00000F00U
155 #define RTC_DESC_INSTIDX_S 8U
156 /*
157 
158  Field: STDIPOFF
159  From..to bits: 12...15
160  DefaultValue: 0x1
161  Access type: read-only
162  Description: Standard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB.
163 
164  0: Standard IP MMRs do not exist
165 
166  0x1-0xF: Standard IP MMRs begin at offset of (64*[STDIPOFF] from the base IP address)
167 
168 */
169 #define RTC_DESC_STDIPOFF_W 4U
170 #define RTC_DESC_STDIPOFF_M 0x0000F000U
171 #define RTC_DESC_STDIPOFF_S 12U
172 /*
173 
174  Field: MODID
175  From..to bits: 16...31
176  DefaultValue: 0x6442
177  Access type: read-only
178  Description: Module identifier used to uniquely identify this IP.
179 
180 */
181 #define RTC_DESC_MODID_W 16U
182 #define RTC_DESC_MODID_M 0xFFFF0000U
183 #define RTC_DESC_MODID_S 16U
184 
185 
186 /*-----------------------------------REGISTER------------------------------------
187  Register name: CTL
188  Offset name: RTC_O_CTL
189  Relative address: 0x4
190  Description: RTC Control register. This register controls resetting the of RTC counter
191  Default Value: 0x00000000
192 
193  Field: RST
194  From..to bits: 0...0
195  DefaultValue: 0x0
196  Access type: write-only
197  Description: RTC counter reset. Writing 1 to this bit will reset the RTC counter, and cause it to resume counting from 0x0
198 
199  ENUMs:
200  NOEFF: No effect
201  CLR: Reset the timer.
202 */
203 #define RTC_CTL_RST 0x00000001U
204 #define RTC_CTL_RST_M 0x00000001U
205 #define RTC_CTL_RST_S 0U
206 #define RTC_CTL_RST_NOEFF 0x00000000U
207 #define RTC_CTL_RST_CLR 0x00000001U
208 
209 
210 /*-----------------------------------REGISTER------------------------------------
211  Register name: ARMSET
212  Offset name: RTC_O_ARMSET
213  Relative address: 0x8
214  Description: RTC channel mode set register. Read to each bit field of this register provides the current channel mode.
215  - Read of 1'b0 indicates the channel is unarmed.
216  - Read of 1'b1 indicates the channel is either in capture or compare mode.
217 
218  A write to each bitfield of this register the following effect:
219  - Write of 1'b0 has no effect on channel mode.
220  - Write of 1'b1 has no effect on the compare channel. While write of 1'b1 for capture channel will arm it in capture mode if it is disabled.
221  Default Value: 0x00000000
222 
223  Field: CH0
224  From..to bits: 0...0
225  DefaultValue: 0x0
226  Access type: read-write
227  Description: No effect on arming the channel. Read will give the status of the Channel 0.
228 
229  ENUMs:
230  NOEFF: No effect on the channel
231  SET: No effect on the compare channel
232 */
233 #define RTC_ARMSET_CH0 0x00000001U
234 #define RTC_ARMSET_CH0_M 0x00000001U
235 #define RTC_ARMSET_CH0_S 0U
236 #define RTC_ARMSET_CH0_NOEFF 0x00000000U
237 #define RTC_ARMSET_CH0_SET 0x00000001U
238 /*
239 
240  Field: CH1
241  From..to bits: 1...1
242  DefaultValue: 0x0
243  Access type: read-write
244  Description: Arming Channel 1 for capture operation.
245 
246  ENUMs:
247  NOEFF: No effect on the channel
248  SET: Enable the Channel 1 for capture operation
249 */
250 #define RTC_ARMSET_CH1 0x00000002U
251 #define RTC_ARMSET_CH1_M 0x00000002U
252 #define RTC_ARMSET_CH1_S 1U
253 #define RTC_ARMSET_CH1_NOEFF 0x00000000U
254 #define RTC_ARMSET_CH1_SET 0x00000002U
255 
256 
257 /*-----------------------------------REGISTER------------------------------------
258  Register name: ARMCLR
259  Offset name: RTC_O_ARMCLR
260  Relative address: 0xC
261  Description: RTC channel mode clear register. Read to each bit field of this register provides the current channel mode.
262  - Read of 1'b0 indicates the channel is unarmed.
263  - Read of 1'b1 indicates the channel is either in capture or compare mode.
264 
265  A write to each bitfield of this register the following effect:
266  - Write of 1'b0 has no effect on channel mode.
267  - Write of 1'b1 for capture/compare channel will disarm it without triggering event unless a compare/capture event happens in the same cycle.
268  Default Value: 0x00000000
269 
270  Field: CH0
271  From..to bits: 0...0
272  DefaultValue: 0x0
273  Access type: read-write
274  Description: Disarming Channel 0
275 
276  ENUMs:
277  NOEFF: No effect on the channel
278  CLR: Set channel in UNARMED state without triggering event unless a compare event happens in the same cycle
279 */
280 #define RTC_ARMCLR_CH0 0x00000001U
281 #define RTC_ARMCLR_CH0_M 0x00000001U
282 #define RTC_ARMCLR_CH0_S 0U
283 #define RTC_ARMCLR_CH0_NOEFF 0x00000000U
284 #define RTC_ARMCLR_CH0_CLR 0x00000001U
285 /*
286 
287  Field: CH1
288  From..to bits: 1...1
289  DefaultValue: 0x0
290  Access type: read-write
291  Description: Disarming Channel 1
292 
293  ENUMs:
294  NOEFF: No effect on the channel
295  CLR: Set channel in UNARMED state without triggering event unless a capture event happens in the same cycle
296 */
297 #define RTC_ARMCLR_CH1 0x00000002U
298 #define RTC_ARMCLR_CH1_M 0x00000002U
299 #define RTC_ARMCLR_CH1_S 1U
300 #define RTC_ARMCLR_CH1_NOEFF 0x00000000U
301 #define RTC_ARMCLR_CH1_CLR 0x00000002U
302 
303 
304 /*-----------------------------------REGISTER------------------------------------
305  Register name: TIME250N
306  Offset name: RTC_O_TIME250N
307  Relative address: 0x10
308  Description: RTC Time value register. 32-bit unsigned integer representing [29:-2] time slice of the real time clock counter. The counter runs on **LFCLK**. This field has a resolution of 250ns, and range of about 17.8 minutes.
309  Default Value: 0x00000000
310 
311  Field: VAL
312  From..to bits: 0...31
313  DefaultValue: 0x0
314  Access type: read-only
315  Description: Unsigned integer representing [34:3]slice of real time counter.
316 
317 */
318 #define RTC_TIME250N_VAL_W 32U
319 #define RTC_TIME250N_VAL_M 0xFFFFFFFFU
320 #define RTC_TIME250N_VAL_S 0U
321 
322 
323 /*-----------------------------------REGISTER------------------------------------
324  Register name: TIME1U
325  Offset name: RTC_O_TIME1U
326  Relative address: 0x14
327  Description: RTC Time value register. 32-bit unsigned integer representing [31:0] time slice of the real time clock counter. The counter runs on **LFCLK**. This field has a resolution of 1us, and range of about 1.19 hours.
328  Default Value: 0x00000000
329 
330  Field: VAL
331  From..to bits: 0...31
332  DefaultValue: 0x0
333  Access type: read-only
334  Description: Unsigned integer representing [34:3]slice of real time counter.
335 
336 
337 */
338 #define RTC_TIME1U_VAL_W 32U
339 #define RTC_TIME1U_VAL_M 0xFFFFFFFFU
340 #define RTC_TIME1U_VAL_S 0U
341 
342 
343 /*-----------------------------------REGISTER------------------------------------
344  Register name: TIME8U
345  Offset name: RTC_O_TIME8U
346  Relative address: 0x18
347  Description: RTC Time value register. 32-bit unsigned integer representing [34:3] time slice of the real time clock counter. The counter runs on **LFCLK**. This field has a resolution of 8us, and range of about 9.5 hours.
348  Default Value: 0x00000000
349 
350  Field: VAL
351  From..to bits: 0...31
352  DefaultValue: 0x0
353  Access type: read-only
354  Description: Unsigned integer representing [34:3]slice of real time counter.
355 
356 
357 */
358 #define RTC_TIME8U_VAL_W 32U
359 #define RTC_TIME8U_VAL_M 0xFFFFFFFFU
360 #define RTC_TIME8U_VAL_S 0U
361 
362 
363 /*-----------------------------------REGISTER------------------------------------
364  Register name: TIME524M
365  Offset name: RTC_O_TIME524M
366  Relative address: 0x1C
367  Description: RTC time value register. 32-bit unsigned integer representing [50:19] time slice of the real time clock counter. This field has a resolution of about 0.5s and a range of about 71.4 years.
368  Default Value: 0x00000000
369 
370  Field: VAL
371  From..to bits: 0...31
372  DefaultValue: 0x0
373  Access type: read-only
374  Description: Unsigned integer representing. [50:19]slice of real time counter.
375 
376 */
377 #define RTC_TIME524M_VAL_W 32U
378 #define RTC_TIME524M_VAL_M 0xFFFFFFFFU
379 #define RTC_TIME524M_VAL_S 0U
380 
381 
382 /*-----------------------------------REGISTER------------------------------------
383  Register name: CH0CC250N
384  Offset name: RTC_O_CH0CC250N
385  Relative address: 0x20
386  Description: Channel 0 compare value with 250ns resolution. A read to this register returns the value {CH0CC8U[29:3], 5b'0}
387  A write to this register arms the channel in compare mode. Event would occur at the same time +/ Tlfclk/2 on the RTC as if it was written to SYSTIM.
388  Default Value: 0x00000000
389 
390  Field: VAL
391  From..to bits: 0...31
392  DefaultValue: 0x0
393  Access type: read-write
394  Description: RTC Channel 0 compare value. This value is compared against [TIME8U.VAL]. A Channel 0 event is generated when [TIME8U.VAL] value reaches or exceeds this compare value.
395 
396 */
397 #define RTC_CH0CC250N_VAL_W 32U
398 #define RTC_CH0CC250N_VAL_M 0xFFFFFFFFU
399 #define RTC_CH0CC250N_VAL_S 0U
400 
401 
402 /*-----------------------------------REGISTER------------------------------------
403  Register name: CH0CC1U
404  Offset name: RTC_O_CH0CC1U
405  Relative address: 0x24
406  Description: Channel 0 compare value with 1us resolution. A read to this register returns the value {CH0CC8U[31:3], 3b'0}
407  A write to this register arms the channel in compare mode. Event would occur at the same time +/ Tlfclk/2 on the RTC as if it was written to SYSTIM.
408  Default Value: 0x00000000
409 
410  Field: VAL
411  From..to bits: 0...31
412  DefaultValue: 0x0
413  Access type: read-write
414  Description: RTC Channel 0 compare value. This value is compared against [TIME8U.VAL]. A Channel 0 event is generated when [TIME8U.VAL] value reaches or exceeds this compare value.
415 
416 */
417 #define RTC_CH0CC1U_VAL_W 32U
418 #define RTC_CH0CC1U_VAL_M 0xFFFFFFFFU
419 #define RTC_CH0CC1U_VAL_S 0U
420 
421 
422 /*-----------------------------------REGISTER------------------------------------
423  Register name: CH0CC8U
424  Offset name: RTC_O_CH0CC8U
425  Relative address: 0x28
426  Description: Channel 0 compare value. A write to this register automatically enables the channel to trigger an event when RTC timer reaches the programmed value or if the programmed value is 1 sec in the past.
427  Default Value: 0x00000000
428 
429  Field: VAL
430  From..to bits: 0...31
431  DefaultValue: 0x0
432  Access type: read-write
433  Description: RTC Channel 0 compare value. This value is compared against [TIME8U.VAL]. A Channel 0 event is generated when [TIME8U.VAL] value reaches or exceeds this compare value.
434 
435 */
436 #define RTC_CH0CC8U_VAL_W 32U
437 #define RTC_CH0CC8U_VAL_M 0xFFFFFFFFU
438 #define RTC_CH0CC8U_VAL_S 0U
439 
440 
441 /*-----------------------------------REGISTER------------------------------------
442  Register name: CH1CC8U
443  Offset name: RTC_O_CH1CC8U
444  Relative address: 0x38
445  Description: Channel 1 capture value. This register captures the RTC time slice [34:3] on each selected edge of the capture event when the [ARMSET.CH1] = 1.
446  Default Value: 0x00000000
447 
448  Field: VAL
449  From..to bits: 0...20
450  DefaultValue: 0x0
451  Access type: read-only
452  Description: [TIME8U.VAL] captured value at the last selected edge of capture event.
453 
454 */
455 #define RTC_CH1CC8U_VAL_W 21U
456 #define RTC_CH1CC8U_VAL_M 0x001FFFFFU
457 #define RTC_CH1CC8U_VAL_S 0U
458 
459 
460 /*-----------------------------------REGISTER------------------------------------
461  Register name: CH1CFG
462  Offset name: RTC_O_CH1CFG
463  Relative address: 0x3C
464  Description: Channel 1 configuration register. This register can be used to select the capture edge for generating the capture event.
465  Default Value: 0x00000000
466 
467  Field: EDGE
468  From..to bits: 0...0
469  DefaultValue: 0x0
470  Access type: read-write
471  Description: Edge detect configuration for capture source
472 
473  ENUMs:
474  RISE: Rising Edge.
475  FALL: Falling Edge.
476 */
477 #define RTC_CH1CFG_EDGE 0x00000001U
478 #define RTC_CH1CFG_EDGE_M 0x00000001U
479 #define RTC_CH1CFG_EDGE_S 0U
480 #define RTC_CH1CFG_EDGE_RISE 0x00000000U
481 #define RTC_CH1CFG_EDGE_FALL 0x00000001U
482 
483 
484 /*-----------------------------------REGISTER------------------------------------
485  Register name: IMASK
486  Offset name: RTC_O_IMASK
487  Relative address: 0x44
488  Description: Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.
489  Default Value: 0x00000000
490 
491  Field: EV0
492  From..to bits: 0...0
493  DefaultValue: 0x0
494  Access type: read-write
495  Description: Channel 0 Event Interrupt Mask.
496 
497  ENUMs:
498  DIS: Disable Interrupt Mask
499  EN: Enable Interrupt Mask
500 */
501 #define RTC_IMASK_EV0 0x00000001U
502 #define RTC_IMASK_EV0_M 0x00000001U
503 #define RTC_IMASK_EV0_S 0U
504 #define RTC_IMASK_EV0_DIS 0x00000000U
505 #define RTC_IMASK_EV0_EN 0x00000001U
506 /*
507 
508  Field: EV1
509  From..to bits: 1...1
510  DefaultValue: 0x0
511  Access type: read-write
512  Description: Channel 1 Event Interrupt Mask.
513 
514  ENUMs:
515  DIS: Clear Interrupt Mask
516  EN: Enable Interrrupt Mask
517 */
518 #define RTC_IMASK_EV1 0x00000002U
519 #define RTC_IMASK_EV1_M 0x00000002U
520 #define RTC_IMASK_EV1_S 1U
521 #define RTC_IMASK_EV1_DIS 0x00000000U
522 #define RTC_IMASK_EV1_EN 0x00000002U
523 
524 
525 /*-----------------------------------REGISTER------------------------------------
526  Register name: RIS
527  Offset name: RTC_O_RIS
528  Relative address: 0x48
529  Description: Interrupt mask. This register selects interrupt sources which are allowed to pass from [RIS.*] to [MIS.*] when the corresponding bit-fields are set to 1.
530  Default Value: 0x00000000
531 
532  Field: EV0
533  From..to bits: 0...0
534  DefaultValue: 0x0
535  Access type: read-only
536  Description: Raw interrupt status for Channel 0 event.
537 
538  This bit is set to 1 when a compare event occurs on Channel 0.
539  This bit will be cleared. When the corresponding bit in [ICLR.EV0] is set to 1. Or when a new compare value is written in [CH0CC8U.*] register
540 
541  ENUMs:
542  CLR: Interrupt did not occur
543  SET: Interrupt occured
544 */
545 #define RTC_RIS_EV0 0x00000001U
546 #define RTC_RIS_EV0_M 0x00000001U
547 #define RTC_RIS_EV0_S 0U
548 #define RTC_RIS_EV0_CLR 0x00000000U
549 #define RTC_RIS_EV0_SET 0x00000001U
550 /*
551 
552  Field: EV1
553  From..to bits: 1...1
554  DefaultValue: 0x0
555  Access type: read-only
556  Description: Raw interrupt status for Channel 1 event.
557 
558  This bit is set to 1 when a capture event is received on Channel 1.
559  This bit will be cleared when the bit in [ICLR.EV1] is set to 1 or when the captured time value is read from the [CH1CC8U.*] register.
560 
561  ENUMs:
562  CLR: Interrupt did not occur
563  SET: Interrupt occured
564 */
565 #define RTC_RIS_EV1 0x00000002U
566 #define RTC_RIS_EV1_M 0x00000002U
567 #define RTC_RIS_EV1_S 1U
568 #define RTC_RIS_EV1_CLR 0x00000000U
569 #define RTC_RIS_EV1_SET 0x00000002U
570 
571 
572 /*-----------------------------------REGISTER------------------------------------
573  Register name: MIS
574  Offset name: RTC_O_MIS
575  Relative address: 0x4C
576  Description: Masked interrupt status. This register is simply a bitwise AND of the contents of [IMASK.*] and RIS.*] registers. A flag set in this register can be cleared by writing 1 to the corresponding [ICLR.*] register bit.
577  Default Value: 0x00000000
578 
579  Field: EV0
580  From..to bits: 0...0
581  DefaultValue: 0x0
582  Access type: read-only
583  Description: Masked interrupt status for channel 0 event.
584 
585  ENUMs:
586  CLR: Interrupt did not occur
587  SET: Interrupt occured
588 */
589 #define RTC_MIS_EV0 0x00000001U
590 #define RTC_MIS_EV0_M 0x00000001U
591 #define RTC_MIS_EV0_S 0U
592 #define RTC_MIS_EV0_CLR 0x00000000U
593 #define RTC_MIS_EV0_SET 0x00000001U
594 /*
595 
596  Field: EV1
597  From..to bits: 1...1
598  DefaultValue: 0x0
599  Access type: read-only
600  Description: Masked interrupt status for channel 1 event.
601 
602  ENUMs:
603  CLR: Interrupt did not occur
604  SET: Interrupt occured
605 */
606 #define RTC_MIS_EV1 0x00000002U
607 #define RTC_MIS_EV1_M 0x00000002U
608 #define RTC_MIS_EV1_S 1U
609 #define RTC_MIS_EV1_CLR 0x00000000U
610 #define RTC_MIS_EV1_SET 0x00000002U
611 
612 
613 /*-----------------------------------REGISTER------------------------------------
614  Register name: ISET
615  Offset name: RTC_O_ISET
616  Relative address: 0x50
617  Description: Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding [RIS.*] bit also gets set. If the corresponding [IMASK.*] bit is set, then the corresponding [MIS.*] register bit also gets set.
618  Default Value: 0x00000000
619 
620  Field: EV0
621  From..to bits: 0...0
622  DefaultValue: 0x0
623  Access type: write-only
624  Description: Set Channel 0 event Interrupt.
625 
626  ENUMs:
627  NO_EFFECT: Writing 0 has no effect
628  SET: Set interrupt
629 */
630 #define RTC_ISET_EV0 0x00000001U
631 #define RTC_ISET_EV0_M 0x00000001U
632 #define RTC_ISET_EV0_S 0U
633 #define RTC_ISET_EV0_NO_EFFECT 0x00000000U
634 #define RTC_ISET_EV0_SET 0x00000001U
635 /*
636 
637  Field: EV1
638  From..to bits: 1...1
639  DefaultValue: 0x0
640  Access type: write-only
641  Description: Set Channel 1 event Interrupt.
642 
643  ENUMs:
644  NO_EFFECT: Writing 0 has no effect
645  SET: Set interrupt
646 */
647 #define RTC_ISET_EV1 0x00000002U
648 #define RTC_ISET_EV1_M 0x00000002U
649 #define RTC_ISET_EV1_S 1U
650 #define RTC_ISET_EV1_NO_EFFECT 0x00000000U
651 #define RTC_ISET_EV1_SET 0x00000002U
652 
653 
654 /*-----------------------------------REGISTER------------------------------------
655  Register name: ICLR
656  Offset name: RTC_O_ICLR
657  Relative address: 0x54
658  Description: Interrupt clear register. This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding [RIS.*] bit also gets cleared. If the corresponding [IMASK.*] bit is set, then the corresponding [MIS.*] register bit also gets cleared.
659  Default Value: 0x00000000
660 
661  Field: EV0
662  From..to bits: 0...0
663  DefaultValue: 0x0
664  Access type: write-only
665  Description: Clears channel 0 event interrupt.
666 
667  ENUMs:
668  NO_EFF: Writing 0 has no effect
669  CLR: Clear Interrupt.
670 */
671 #define RTC_ICLR_EV0 0x00000001U
672 #define RTC_ICLR_EV0_M 0x00000001U
673 #define RTC_ICLR_EV0_S 0U
674 #define RTC_ICLR_EV0_NO_EFF 0x00000000U
675 #define RTC_ICLR_EV0_CLR 0x00000001U
676 /*
677 
678  Field: EV1
679  From..to bits: 1...1
680  DefaultValue: 0x0
681  Access type: write-only
682  Description: Clears channel 1 event interrupt.
683 
684  ENUMs:
685  NO_EFF: Writing 0 has no effect
686  CLR: Clear Interrupt
687 */
688 #define RTC_ICLR_EV1 0x00000002U
689 #define RTC_ICLR_EV1_M 0x00000002U
690 #define RTC_ICLR_EV1_S 1U
691 #define RTC_ICLR_EV1_NO_EFF 0x00000000U
692 #define RTC_ICLR_EV1_CLR 0x00000002U
693 
694 
695 /*-----------------------------------REGISTER------------------------------------
696  Register name: IMSET
697  Offset name: RTC_O_IMSET
698  Relative address: 0x58
699  Description: Interrupt mask set register. Writing a 1 to a bit in this register will set the corresponding [IMASK.*] bit.
700  Default Value: 0x00000000
701 
702  Field: EV0
703  From..to bits: 0...0
704  DefaultValue: 0x0
705  Access type: write-only
706  Description: Set channel 0 event interrupt mask.
707 
708  ENUMs:
709  NO_EFF: Writing 0 has no effect
710  SET: Set interrupt mask
711 */
712 #define RTC_IMSET_EV0 0x00000001U
713 #define RTC_IMSET_EV0_M 0x00000001U
714 #define RTC_IMSET_EV0_S 0U
715 #define RTC_IMSET_EV0_NO_EFF 0x00000000U
716 #define RTC_IMSET_EV0_SET 0x00000001U
717 /*
718 
719  Field: EV1
720  From..to bits: 1...1
721  DefaultValue: 0x0
722  Access type: write-only
723  Description: Set channel 1 event interrupt mask.
724 
725  ENUMs:
726  NO_EFF: Writing 0 has no effect
727  SET: Set interrupt mask
728 */
729 #define RTC_IMSET_EV1 0x00000002U
730 #define RTC_IMSET_EV1_M 0x00000002U
731 #define RTC_IMSET_EV1_S 1U
732 #define RTC_IMSET_EV1_NO_EFF 0x00000000U
733 #define RTC_IMSET_EV1_SET 0x00000002U
734 
735 
736 /*-----------------------------------REGISTER------------------------------------
737  Register name: IMCLR
738  Offset name: RTC_O_IMCLR
739  Relative address: 0x5C
740  Description: Interrupt mask clear register. Writing a 1 to a bit in this register will clear the corresponding [IMASK.*] bit.
741  Default Value: 0x00000000
742 
743  Field: EV0
744  From..to bits: 0...0
745  DefaultValue: 0x0
746  Access type: write-only
747  Description: Clears Channel 0 event interrupt mask.
748 
749  ENUMs:
750  NO_EFF: Writing 0 has no effect
751  CLR: Clear Interrupt Mask
752 */
753 #define RTC_IMCLR_EV0 0x00000001U
754 #define RTC_IMCLR_EV0_M 0x00000001U
755 #define RTC_IMCLR_EV0_S 0U
756 #define RTC_IMCLR_EV0_NO_EFF 0x00000000U
757 #define RTC_IMCLR_EV0_CLR 0x00000001U
758 /*
759 
760  Field: EV1
761  From..to bits: 1...1
762  DefaultValue: 0x0
763  Access type: write-only
764  Description: Clears Channel 1 event interrupt mask.
765 
766  ENUMs:
767  NO_EFF: Writing 0 has no effect
768  CLR: Clear Interrupt Mask
769 */
770 #define RTC_IMCLR_EV1 0x00000002U
771 #define RTC_IMCLR_EV1_M 0x00000002U
772 #define RTC_IMCLR_EV1_S 1U
773 #define RTC_IMCLR_EV1_NO_EFF 0x00000000U
774 #define RTC_IMCLR_EV1_CLR 0x00000002U
775 
776 
777 /*-----------------------------------REGISTER------------------------------------
778  Register name: EMU
779  Offset name: RTC_O_EMU
780  Relative address: 0x60
781  Description: Emulation control register. This register controls the behavior of the IP related to core halted input.
782  Default Value: 0x00000000
783 
784  Field: HALT
785  From..to bits: 0...0
786  DefaultValue: 0x0
787  Access type: read-write
788  Description: Halt control.
789 
790  ENUMs:
791  STOP: Freeze option. The IP freezes functionality when the core halted input is asserted, and resumes when it is deasserted. The freeze can either be immediate or after the IP has reached a boundary from where it can resume without corruption.
792  RUN: Free run option. The IP ignores the state of the core halted input.
793 */
794 #define RTC_EMU_HALT 0x00000001U
795 #define RTC_EMU_HALT_M 0x00000001U
796 #define RTC_EMU_HALT_S 0U
797 #define RTC_EMU_HALT_STOP 0x00000001U
798 #define RTC_EMU_HALT_RUN 0x00000000U
799 
800 
801 /*-----------------------------------REGISTER------------------------------------
802  Register name: DTB
803  Offset name: RTC_O_DTB
804  Relative address: 0x64
805  Description: Digital test bus control register. This register can be used to bring out IP internal signals to the pads for observation. 16 signals can be observed per select value.
806  Default Value: 0x00000000
807 
808  Field: SEL
809  From..to bits: 0...3
810  DefaultValue: 0x0
811  Access type: read-write
812  Description: Digital test bus selection mux control.
813 
814  Non-zero select values output a 16 bit selected group of signals per value.
815 
816  ENUMs:
817  DIS: All 16 observation signals are set to zero.
818 */
819 #define RTC_DTB_SEL_W 4U
820 #define RTC_DTB_SEL_M 0x0000000FU
821 #define RTC_DTB_SEL_S 0U
822 #define RTC_DTB_SEL_DIS 0x00000000U
823 
824 
825 /*-----------------------------------REGISTER------------------------------------
826  Register name: DTIME
827  Offset name: RTC_O_DTIME
828  Relative address: 0x68
829  Description: A delta time mechanism is implemented for RTC that allows the TIME value to be adjusted under software control. This is used by boot code to perform the compensation for reset duration (accomplished by adding MMR write to FCFG.generalTrims copylist to avoid ROM changes)
830  DTIME format is:
831  [31]: E (exponent)
832  [30:0] M (mantissa)
833  TIME[50:-2] is adjusted by TIME += sxt(M[30:0], 53) * 2^(22*E). In other words:
834  (E==0): TIME is adjusted by M * 250 ns (range +/-134 s)
835  (E==1): TIME is adjusted by M * 1.049 s (range +/- 35.7 yr)
836  Default Value: 0x00000000
837 
838 */
839 #endif /* __HW_RTC_H__*/