CC35xxDriverLibrary
hw_prcm_scratchpad.h
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1 /******************************************************************************
2 * Filename: hw_prcm_scratchpad.h
3 *
4 * Description: Defines and prototypes for the PRCM_SCRATCHPAD peripheral.
5 *
6 * Copyright (c) 2023, Texas Instruments Incorporated
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35 ******************************************************************************/
36 #ifndef __HW_PRCM_SCRATCHPAD_H__
37 #define __HW_PRCM_SCRATCHPAD_H__
38 /*-------------------------------------------------------------------------------
39 
40 This section defines the register offsets of the PRCM_SCRATCHPAD component
41 
42 --------------------------------------------------------------------------------- */
43 
44 //PRCM SCRATCHPAD
45 #define PRCM_SCRATCHPAD_O_LINE1 0x00000000U
46 
47 //RESET CAUSE
48 #define PRCM_SCRATCHPAD_O_RSTCAUS 0x00000004U
49 
50 //OSPREY PRCM AON scratch pad, this register bank is not deleted in SOC AON RESET and kept through reset/low power and brownout events
51 #define PRCM_SCRATCHPAD_O_LINE0 0x00000008U
52 
53 //OSPREY PRCM AON scratch pad, this register bank is not deleted in SOC AON RESET and kept through reset/low power and brownout events
54 #define PRCM_SCRATCHPAD_O_LOCK 0x0000000CU
55 
56 //PRCM SCRATCHPAD 2
57 #define PRCM_SCRATCHPAD_O_LINE2 0x00001000U
58 
59 
60 
61 /*-----------------------------------REGISTER------------------------------------
62  Register name: LINE1
63  Offset name: PRCM_SCRATCHPAD_O_LINE1
64  Relative address: 0x0
65  Description: PRCM SCRATCHPAD
66 
67  m3 messages which should survive AON Reset and provide additional info on reset cause:
68 
69  Critical error types + indication if reset applied for this error- number of bits?
70  Max number of failures for reset apply - one common value for all errors with reset apply set
71  Counter
72  Default Value: NA
73 
74  Field: VAL
75  From..to bits: 0...31
76  DefaultValue: NA
77  Access type: read-write
78  Description: VALUE LINE 1
79 
80  Scratch pad line 1
81 
82 */
83 #define PRCM_SCRATCHPAD_LINE1_VAL_W 32U
84 #define PRCM_SCRATCHPAD_LINE1_VAL_M 0xFFFFFFFFU
85 #define PRCM_SCRATCHPAD_LINE1_VAL_S 0U
86 
87 
88 /*-----------------------------------REGISTER------------------------------------
89  Register name: RSTCAUS
90  Offset name: PRCM_SCRATCHPAD_O_RSTCAUS
91  Relative address: 0x4
92  Description: RESET CAUSE
93 
94  OSPREY PRCM AON scratch pad, this register bank is not deleted in SOC AON RESET and kept through reset/low power and brownout events
95  Default Value: NA
96 
97  Field: RSTLINE
98  From..to bits: 0...0
99  DefaultValue: NA
100  Access type: read-only
101  Description: Reset line
102 
103 */
104 #define PRCM_SCRATCHPAD_RSTCAUS_RSTLINE 0x00000001U
105 #define PRCM_SCRATCHPAD_RSTCAUS_RSTLINE_M 0x00000001U
106 #define PRCM_SCRATCHPAD_RSTCAUS_RSTLINE_S 0U
107 /*
108 
109  Field: POR
110  From..to bits: 1...1
111  DefaultValue: NA
112  Access type: read-only
113  Description: POR
114 
115 */
116 #define PRCM_SCRATCHPAD_RSTCAUS_POR 0x00000002U
117 #define PRCM_SCRATCHPAD_RSTCAUS_POR_M 0x00000002U
118 #define PRCM_SCRATCHPAD_RSTCAUS_POR_S 1U
119 /*
120 
121  Field: RVML
122  From..to bits: 2...2
123  DefaultValue: NA
124  Access type: read-only
125  Description: RVM low detect of fault injection ; applicable only when protection RVML is disabled
126 
127 */
128 #define PRCM_SCRATCHPAD_RSTCAUS_RVML 0x00000004U
129 #define PRCM_SCRATCHPAD_RSTCAUS_RVML_M 0x00000004U
130 #define PRCM_SCRATCHPAD_RSTCAUS_RVML_S 2U
131 /*
132 
133  Field: RVMH
134  From..to bits: 3...3
135  DefaultValue: NA
136  Access type: read-only
137  Description: RVM high detect of fault injection ; applicable only when protection RVMH is disabled
138 
139 */
140 #define PRCM_SCRATCHPAD_RSTCAUS_RVMH 0x00000008U
141 #define PRCM_SCRATCHPAD_RSTCAUS_RVMH_M 0x00000008U
142 #define PRCM_SCRATCHPAD_RSTCAUS_RVMH_S 3U
143 /*
144 
145  Field: BOD
146  From..to bits: 4...4
147  DefaultValue: NA
148  Access type: read-only
149  Description: BOD; applicable only when protection BOD is disabled
150 
151 */
152 #define PRCM_SCRATCHPAD_RSTCAUS_BOD 0x00000010U
153 #define PRCM_SCRATCHPAD_RSTCAUS_BOD_M 0x00000010U
154 #define PRCM_SCRATCHPAD_RSTCAUS_BOD_S 4U
155 /*
156 
157  Field: SOCAON
158  From..to bits: 5...5
159  DefaultValue: NA
160  Access type: read-only
161  Description: SOC AON
162 
163  Device self reset (SOC AON by CORE )
164 
165 */
166 #define PRCM_SCRATCHPAD_RSTCAUS_SOCAON 0x00000020U
167 #define PRCM_SCRATCHPAD_RSTCAUS_SOCAON_M 0x00000020U
168 #define PRCM_SCRATCHPAD_RSTCAUS_SOCAON_S 5U
169 /*
170 
171  Field: DBGSS
172  From..to bits: 6...6
173  DefaultValue: NA
174  Access type: read-only
175  Description: DEBUGSS REQUEST
176 
177  Debug req reset
178 
179 */
180 #define PRCM_SCRATCHPAD_RSTCAUS_DBGSS 0x00000040U
181 #define PRCM_SCRATCHPAD_RSTCAUS_DBGSS_M 0x00000040U
182 #define PRCM_SCRATCHPAD_RSTCAUS_DBGSS_S 6U
183 /*
184 
185  Field: M33WD
186  From..to bits: 7...7
187  DefaultValue: NA
188  Access type: read-only
189  Description: M33 WATCH DOG
190 
191 */
192 #define PRCM_SCRATCHPAD_RSTCAUS_M33WD 0x00000080U
193 #define PRCM_SCRATCHPAD_RSTCAUS_M33WD_M 0x00000080U
194 #define PRCM_SCRATCHPAD_RSTCAUS_M33WD_S 7U
195 /*
196 
197  Field: SOCAONH
198  From..to bits: 8...8
199  DefaultValue: NA
200  Access type: read-only
201  Description: SOC AON by HOST
202 
203 */
204 #define PRCM_SCRATCHPAD_RSTCAUS_SOCAONH 0x00000100U
205 #define PRCM_SCRATCHPAD_RSTCAUS_SOCAONH_M 0x00000100U
206 #define PRCM_SCRATCHPAD_RSTCAUS_SOCAONH_S 8U
207 /*
208 
209  Field: OOFSLP
210  From..to bits: 9...9
211  DefaultValue: NA
212  Access type: read-only
213  Description: OUT OF SLEEP
214 
215  Exit sleep on wakeup event only
216 
217 */
218 #define PRCM_SCRATCHPAD_RSTCAUS_OOFSLP 0x00000200U
219 #define PRCM_SCRATCHPAD_RSTCAUS_OOFSLP_M 0x00000200U
220 #define PRCM_SCRATCHPAD_RSTCAUS_OOFSLP_S 9U
221 /*
222 
223  Field: M33CRSLSTA
224  From..to bits: 10...10
225  DefaultValue: NA
226  Access type: read-only
227  Description: M33 CORE SL START
228 
229  Core CONN STOP (M33 driven)
230 
231 */
232 #define PRCM_SCRATCHPAD_RSTCAUS_M33CRSLSTA 0x00000400U
233 #define PRCM_SCRATCHPAD_RSTCAUS_M33CRSLSTA_M 0x00000400U
234 #define PRCM_SCRATCHPAD_RSTCAUS_M33CRSLSTA_S 10U
235 /*
236 
237  Field: M3WD
238  From..to bits: 11...11
239  DefaultValue: NA
240  Access type: read-only
241  Description: M3 Watch Dog
242 
243 */
244 #define PRCM_SCRATCHPAD_RSTCAUS_M3WD 0x00000800U
245 #define PRCM_SCRATCHPAD_RSTCAUS_M3WD_M 0x00000800U
246 #define PRCM_SCRATCHPAD_RSTCAUS_M3WD_S 11U
247 /*
248 
249  Field: CLR
250  From..to bits: 16...16
251  DefaultValue: NA
252  Access type: write-only
253  Description: CLEAR
254 
255  write clear
256 
257  Reset cause clear on write - first initiate relevant source reset clear
258  RVM - RVMTRIMCTL.RVMRSTCAUSCLR
259  BOD - BODCTL.RSTCAUSECLR
260  DEBUGSS - PMURSTCLR.DBGSSCAUS
261  WDT - PMURSTCLR.WDTCAUS
262 
263 */
264 #define PRCM_SCRATCHPAD_RSTCAUS_CLR 0x00010000U
265 #define PRCM_SCRATCHPAD_RSTCAUS_CLR_M 0x00010000U
266 #define PRCM_SCRATCHPAD_RSTCAUS_CLR_S 16U
267 
268 
269 /*-----------------------------------REGISTER------------------------------------
270  Register name: LINE0
271  Offset name: PRCM_SCRATCHPAD_O_LINE0
272  Relative address: 0x8
273  Description: OSPREY PRCM AON scratch pad, this register bank is not deleted in SOC AON RESET and kept through reset/low power and brownout events
274 
275  keep approved authenticated debug requests locked to allow OTA debug
276 
277  allow write only during M3 boot - M3 Privilege mode (before soc_boot_done)
278 
279  Allow read by M3/M33 according to configuration/firewall
280  Default Value: NA
281 
282  Field: VAL
283  From..to bits: 0...31
284  DefaultValue: NA
285  Access type: read-write
286  Description: VALUE LINE 0
287 
288  Scratch pad line 0
289 
290 */
291 #define PRCM_SCRATCHPAD_LINE0_VAL_W 32U
292 #define PRCM_SCRATCHPAD_LINE0_VAL_M 0xFFFFFFFFU
293 #define PRCM_SCRATCHPAD_LINE0_VAL_S 0U
294 
295 
296 /*-----------------------------------REGISTER------------------------------------
297  Register name: LOCK
298  Offset name: PRCM_SCRATCHPAD_O_LOCK
299  Relative address: 0xC
300  Description: OSPREY PRCM AON scratch pad, this register bank is not deleted in SOC AON RESET and kept through reset/low power and brownout events
301  Lock is released on power on reset
302 
303  allow write only during M3 boot - M3 Privilege mode (before soc_boot_done)
304  Default Value: NA
305 
306  Field: SPLOCK
307  From..to bits: 0...0
308  DefaultValue: NA
309  Access type: read-write
310  Description: SCRATCHPAD LOCK
311 
312 */
313 #define PRCM_SCRATCHPAD_LOCK_SPLOCK 0x00000001U
314 #define PRCM_SCRATCHPAD_LOCK_SPLOCK_M 0x00000001U
315 #define PRCM_SCRATCHPAD_LOCK_SPLOCK_S 0U
316 
317 
318 /*-----------------------------------REGISTER------------------------------------
319  Register name: LINE2
320  Offset name: PRCM_SCRATCHPAD_O_LINE2
321  Relative address: 0x1000
322  Description: PRCM SCRATCHPAD 2
323 
324  m33 messages which should survive AON Reset:
325 
326  OTA info -number of bits?
327  Critical error types + indication if reset applied for this error- number of bits?
328  Default Value: NA
329 
330  Field: VAL
331  From..to bits: 0...31
332  DefaultValue: NA
333  Access type: read-write
334  Description: VALUE LINE 2
335 
336  Scratch pad line 2
337 
338 
339 */
340 #define PRCM_SCRATCHPAD_LINE2_VAL_W 32U
341 #define PRCM_SCRATCHPAD_LINE2_VAL_M 0xFFFFFFFFU
342 #define PRCM_SCRATCHPAD_LINE2_VAL_S 0U
343 
344 #endif /* __HW_PRCM_SCRATCHPAD_H__*/