CC35xxDriverLibrary
Macros
hw_memmap.h File Reference
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Macros

#define HOSTMCU_TGT_BASE   0x00000000
 
#define TCM_CRAM_BASE   0x00000000
 
#define TCM_CRAM_SEC_BASE   0x04000000
 
#define CRAM_BASE   0x08000000
 
#define CRAM_SEC_BASE   0x0C000000
 
#define EXT_FLASH_BASE   0x10000000
 
#define EXT_FLASH_SEC_BASE   0x14000000
 
#define TCM_DRAM_BASE   0x20000000
 
#define TCM_DRAM_SEC_BASE   0x24000000
 
#define DRAM_BASE   0x28000000
 
#define DRAM_SEC_BASE   0x2C000000
 
#define EXT_PSRAM_BASE   0x60000000
 
#define EXT_PSRAM_SEC_BASE   0x64000000
 
#define HOST_MCU_BASE   0x41900000
 
#define ICACHE_BASE   0x41902000
 
#define DCACHE_BASE   0x41902400
 
#define HOST_MCU_SEC_BASE   0x41903000
 
#define OSPI_REGS_BASE   0x41910000
 
#define OSPI_INDAC_BASE   0x41911000
 
#define HOST_XIP_REGS_BASE   0x41912000
 
#define HIF_BASE   0x408A0000
 
#define COEX_BASE   0x40850000
 
#define IOMUX_BASE   0x41140000
 
#define PRCM_BASE   0x41090000
 
#define PRCM_AON_BASE   0x41090000
 
#define PRCM_SCRATCHPAD_BASE   0x4109F000
 
#define PLL_SHARING_BASE   0x410A0000
 
#define CKM_BASE   0x410a0000
 
#define SOC_DEBUGSS_BASE   0x410d0000
 
#define SOC_DEBUGSS_DSSM_BASE   0x410d0000
 
#define SOC_IC_REGS_BASE   0x410f0000
 
#define SOC_AON_BASE   0x41100000
 
#define SOC_AAON_BASE   0x41104000
 
#define RTC_BASE   0x41108000
 
#define WSOC_OCLA_BASE   0x411C0000
 
#define MEMSS_BASE   0x41C00000
 
#define HOSTMCU_AON_BASE   0x411D0000
 
#define SYSRESOURCES_BASE   0x411E0000
 
#define SYSTIM_BASE   0x411E2000
 
#define HOST_DMA_TGT_BASE   0x41A00000
 
#define HSM_BASE   0x41B00000
 
#define HSM_NON_SEC_BASE   0x41B04000
 
#define HSM_SEC_BASE   0x41B05000
 
#define I2C0_BASE   0x41200000
 
#define I2C1_BASE   0x41210000
 
#define SPI0_BASE   0x41220000
 
#define SPI1_BASE   0x41230000
 
#define UARTLIN0_BASE   0x41240000
 
#define UARTLIN1_BASE   0x41250000
 
#define UARTLIN2_BASE   0x41300000
 
#define GPTIMER0_BASE   0x41260000
 
#define GPTIMER1_BASE   0x41268000
 
#define I2S_BASE   0x41270000
 
#define PDM_BASE   0x41280000
 
#define DCAN_BASE   0x412A0000
 
#define ADC_BASE   0x412B0000
 
#define SDMMC_BASE   0x412C0000
 
#define SDIO_CARD_FN1_BASE   0x412D0000
 
#define SDIO_CORE_BASE   0x412E0000
 
#define CORE_AON_BASE   0x41E00000
 
#define CPU_ITM_BASE   0xE0000000
 
#define CPU_DWT_BASE   0xE0001000
 
#define CPU_ICB_BASE   0xE000E000
 
#define CPU_SYSTICK_BASE   0xE000E010
 
#define CPU_NVIC_BASE   0xE000E100
 
#define CPU_MPU_BASE   0xE000EDC0
 
#define CPU_SAU_BASE   0xE000EDD0
 
#define CPU_FPU_BASE   0xE000EF30
 

Macro Definition Documentation

§ HOSTMCU_TGT_BASE

#define HOSTMCU_TGT_BASE   0x00000000

§ TCM_CRAM_BASE

#define TCM_CRAM_BASE   0x00000000

§ TCM_CRAM_SEC_BASE

#define TCM_CRAM_SEC_BASE   0x04000000

§ CRAM_BASE

#define CRAM_BASE   0x08000000

§ CRAM_SEC_BASE

#define CRAM_SEC_BASE   0x0C000000

§ EXT_FLASH_BASE

#define EXT_FLASH_BASE   0x10000000

§ EXT_FLASH_SEC_BASE

#define EXT_FLASH_SEC_BASE   0x14000000

§ TCM_DRAM_BASE

#define TCM_DRAM_BASE   0x20000000

§ TCM_DRAM_SEC_BASE

#define TCM_DRAM_SEC_BASE   0x24000000

§ DRAM_BASE

#define DRAM_BASE   0x28000000

§ DRAM_SEC_BASE

#define DRAM_SEC_BASE   0x2C000000

§ EXT_PSRAM_BASE

#define EXT_PSRAM_BASE   0x60000000

§ EXT_PSRAM_SEC_BASE

#define EXT_PSRAM_SEC_BASE   0x64000000

§ HOST_MCU_BASE

#define HOST_MCU_BASE   0x41900000

§ ICACHE_BASE

#define ICACHE_BASE   0x41902000

§ DCACHE_BASE

#define DCACHE_BASE   0x41902400

§ HOST_MCU_SEC_BASE

#define HOST_MCU_SEC_BASE   0x41903000

§ OSPI_REGS_BASE

#define OSPI_REGS_BASE   0x41910000

Referenced by __attribute__(), and OSPISetSTIGDataRegister().

§ OSPI_INDAC_BASE

#define OSPI_INDAC_BASE   0x41911000

§ HOST_XIP_REGS_BASE

#define HOST_XIP_REGS_BASE   0x41912000

Referenced by __attribute__(), XIPGetUDMAChannelProgressingStatus(), XIPGetUDMAChannelWordsLeft(), XIPGetUDMAIrqStatus(), and XIPStartUDMATransaction().

§ HIF_BASE

#define HIF_BASE   0x408A0000

§ COEX_BASE

#define COEX_BASE   0x40850000

§ IOMUX_BASE

#define IOMUX_BASE   0x41140000

§ PRCM_BASE

#define PRCM_BASE   0x41090000

§ PRCM_AON_BASE

#define PRCM_AON_BASE   0x41090000

§ PRCM_SCRATCHPAD_BASE

#define PRCM_SCRATCHPAD_BASE   0x4109F000

§ PLL_SHARING_BASE

#define PLL_SHARING_BASE   0x410A0000

§ CKM_BASE

#define CKM_BASE   0x410a0000

§ SOC_DEBUGSS_BASE

#define SOC_DEBUGSS_BASE   0x410d0000

§ SOC_DEBUGSS_DSSM_BASE

#define SOC_DEBUGSS_DSSM_BASE   0x410d0000

§ SOC_IC_REGS_BASE

#define SOC_IC_REGS_BASE   0x410f0000

§ SOC_AON_BASE

#define SOC_AON_BASE   0x41100000

§ SOC_AAON_BASE

#define SOC_AAON_BASE   0x41104000

Referenced by DMAClearInt(), DMADisableInt(), DMAEnableInt(), and DMAIntStatus().

§ RTC_BASE

#define RTC_BASE   0x41108000

§ WSOC_OCLA_BASE

#define WSOC_OCLA_BASE   0x411C0000

§ MEMSS_BASE

#define MEMSS_BASE   0x41C00000

§ HOSTMCU_AON_BASE

#define HOSTMCU_AON_BASE   0x411D0000

Referenced by WatchdogClearWakeUpEvent(), WatchdogDisableResetEvent(), WatchdogDisableWakeUpEvent(), WatchdogEnableResetEvent(), WatchdogEnableWakeUpEvent(), WatchdogReset(), WatchdogSetResetThreshold(), WatchdogSetSwMode(), WatchdogSetWakeUpThreshold(), WatchdogStartSequence(), WatchdogStatus(), and WatchdogStopSequence().

§ SYSRESOURCES_BASE

#define SYSRESOURCES_BASE   0x411E0000

§ SYSTIM_BASE

#define SYSTIM_BASE   0x411E2000

§ HOST_DMA_TGT_BASE

#define HOST_DMA_TGT_BASE   0x41A00000

Referenced by DMAConfigureChannel(), DMAConfigureChannelFlags(), DMADisableDestinationFifoMode(), DMAEnableDestinationFifoMode(), DMAGetChannelDirection(), DMAGetChannelPeripheral(), DMAGetChannelStatus(), DMAInitChannel(), and DMAStartTransaction().

§ HSM_BASE

#define HSM_BASE   0x41B00000

§ HSM_NON_SEC_BASE

#define HSM_NON_SEC_BASE   0x41B04000

§ HSM_SEC_BASE

#define HSM_SEC_BASE   0x41B05000

§ I2C0_BASE

#define I2C0_BASE   0x41200000

§ I2C1_BASE

#define I2C1_BASE   0x41210000

§ SPI0_BASE

#define SPI0_BASE   0x41220000

§ SPI1_BASE

#define SPI1_BASE   0x41230000

Referenced by SPIRegisterInt(), and SPIUnregisterInt().

§ UARTLIN0_BASE

#define UARTLIN0_BASE   0x41240000

Referenced by UARTEnable().

§ UARTLIN1_BASE

#define UARTLIN1_BASE   0x41250000

Referenced by UARTEnable().

§ UARTLIN2_BASE

#define UARTLIN2_BASE   0x41300000

Referenced by UARTEnable().

§ GPTIMER0_BASE

#define GPTIMER0_BASE   0x41260000

§ GPTIMER1_BASE

#define GPTIMER1_BASE   0x41268000

§ I2S_BASE

#define I2S_BASE   0x41270000

Referenced by I2SClearInt(), I2SConfigureAdfs(), I2SConfigureClocks(), I2SConfigureFormat(), I2SConfigureFrame(), I2SConfigureInSampleStampTrigger(), I2SConfigureOutSampleStampTrigger(), I2SConfigureWclkCounter(), I2SConfigureWclkCounterPeriod(), I2SDisableAdfs(), I2SDisableClk(), I2SDisableControllerClocks(), I2SDisableInt(), I2SDisableSampleStamp(), I2SEnableAdfs(), I2SEnableClk(), I2SEnableControllerClocks(), I2SEnableInt(), I2SEnableSampleStamp(), I2SGetInPointer(), I2SGetInPointerNext(), I2SGetOutPointer(), I2SGetOutPointerNext(), I2SGetSampleStamp(), I2SIntStatus(), I2SResetWclkCounter(), I2SSelectAdfsInputClk(), I2SSetInPointer(), I2SSetOutPointer(), I2SStart(), and I2SStop().

§ PDM_BASE

#define PDM_BASE   0x41280000

§ DCAN_BASE

#define DCAN_BASE   0x412A0000

§ ADC_BASE

#define ADC_BASE   0x412B0000

Referenced by ADCClearInterrupt(), ADCDisableConversion(), ADCDisableDmaTrigger(), ADCDisableInterrupt(), ADCEnableConversion(), ADCEnableDmaTrigger(), ADCEnableInterrupt(), ADCIsBusy(), ADCMaskedInterruptStatus(), ADCRawInterruptStatus(), ADCReadResult(), ADCReadResultNonBlocking(), ADCRestoreTrims(), ADCSetInput(), ADCSetMemctlRange(), ADCSetPowerDownPolicy(), ADCSetSampleDuration(), ADCSetSamplingClk(), ADCSetSamplingMode(), ADCSetSequence(), ADCSetTriggerPolicy(), ADCSetTriggerSource(), ADCStartConversion(), and ADCStopConversion().

§ SDMMC_BASE

#define SDMMC_BASE   0x412C0000

§ SDIO_CARD_FN1_BASE

#define SDIO_CARD_FN1_BASE   0x412D0000

§ SDIO_CORE_BASE

#define SDIO_CORE_BASE   0x412E0000

§ CORE_AON_BASE

#define CORE_AON_BASE   0x41E00000

§ CPU_ITM_BASE

#define CPU_ITM_BASE   0xE0000000

§ CPU_DWT_BASE

#define CPU_DWT_BASE   0xE0001000

§ CPU_ICB_BASE

#define CPU_ICB_BASE   0xE000E000

§ CPU_SYSTICK_BASE

#define CPU_SYSTICK_BASE   0xE000E010

§ CPU_NVIC_BASE

#define CPU_NVIC_BASE   0xE000E100

§ CPU_MPU_BASE

#define CPU_MPU_BASE   0xE000EDC0

§ CPU_SAU_BASE

#define CPU_SAU_BASE   0xE000EDD0

§ CPU_FPU_BASE

#define CPU_FPU_BASE   0xE000EF30