CC35xxDriverLibrary
hw_ints.h
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33 
34 #ifndef __HW_INTS_H__
35 #define __HW_INTS_H__
36 
37 //*****************************************************************************
38 //
39 // The following are defines for the interrupt assignments.
40 //
41 //*****************************************************************************
42 #define INT_NMI_FAULT 2 //-14 NMI Fault
43 #define INT_HARD_FAULT 3 //-13 Hard Fault
44 #define INT_MEMMANAGE_FAULT 4 //-12 Memory Management (MemManage) Fault
45 #define INT_BUS_FAULT 5 //-11 Bus Fault
46 #define INT_USAGE_FAULT 6 //-10 Usage Fault
47 #define INT_SVCALL 11 //-5 Supervisor Call (SVCall)
48 #define INT_DEBUG 12 //-4 Debug Monitor
49 #define INT_PENDSV 14 //-2 Pending Service Call (PendSV)
50 #define INT_SYSTICK 15 //-1 SysTick Interrupt from the System Timer
51  // in NVIC.
52 
53 
54 #define INT_SP_UART_0_INT_REQ 16 //0 UART 0 interrupt
55 #define INT_SP_UART_1_INT_REQ 17 //1 UART 2 interrupt
56 #define INT_SP_I2C_0_INTREQ 18 //2 I2C 0 interrupt
57 #define INT_SP_I2C_1_INTREQ 19 //3 I2C 1 interrupt
58 #define INT_SP_SPI_0_EVT_REQ 20 //4 SPI 0 interrupt
59 #define INT_SP_SPI_1_EVT_REQ 21 //5 SPI 1 interrupt
60 #define INT_GPTIMER_0_EVT_CPU_IRQ 22 //6 GPT 0 interrupt
61 #define INT_GPTIMER_1_EVT_CPU_IRQ 23 //7 GPT 1 interrupt
62 #define INT_SP_UART_2_INT_REQ 24 //8 UART 2 interrupt
63 #define INT_I2S_IRQ_REQ 25 //9 I2S interrupt
64 #define INT_EVT_PDM_EVENT_REQ 26 //10 PDM interrupt
65 #define INT_EVT_SWINT0_REQ 27 //11 SWINT 0 interrupt
66 #define INT_EVT_SWINT1_REQ 28 //12 SWINT 1 interrupt
67 #define INT_EVT_SDMMC_PUB_REQ 29 //13 SDMMC interrupt
68 #define INT_SDIO_CARD_IRQ_REQ 30 //14 SDIO interrupt
69 #define INT_ULL_USC_ULPADCHP_PUB_EVT0_REQ 31 //15
70 #define INT_NON_SECURED_GPIO_IRQ_EVT_IND_OUT 32 //16 GPIO_NS interrupt
71 #define INT_SECURED_GPIO_IRQ_EVT_IND_OUT 33 //17 GPIO_S interrupt
72 #define INT_OSPR_HSM_HOST_0_SEC_IRQ 34 //18 HSM_S 0 interrupt
73 #define INT_OSPR_HSM_HOST_0_IRQ 35 //19 HSM_NS 0 interrupt
74 #define INT_OSPR_HSM_HOST_1_IRQ 36 //20 HSM_NS 1 interrupt
75 #define INT_SVT_EVT_COMBINED_SYSTIM_OUT_IRQ 37 //21 SYSTIM_COMB interrupt
76 #define INT_SVT_EVT_SYSTIMER_BIT_OUT_IRQ 38 //22 SYSTIM_BIT interrupt
77 #define INT_SVT_EVT_SYSTIMER_OUT_0_IRQ 39 //23 SYSTIM 0 interrupt
78 #define INT_SVT_EVT_SYSTIMER_OUT_1_IRQ 40 //24 SYSTIM 1 interrupt
79 #define INT_NON_SECURED_DMA_IRQ_EVT_IND_OUT 41 //25 DMA_NS interrupt
80 #define INT_SECURED_DMA_IRQ_EVT_IND_OUT 42 //26 DMA_S interrupt
81 #define INT_NON_SECURED_DOORBELL_IRQ_EVT_IND_OUT 43 //27 DOORBELL_NS interrupt
82 #define INT_SECURED_DOORBELL_IRQ_EVT_IND_OUT 44 //28 DOORBELL_S interrupt
83 #define INT_ICACHE_ERR_IRQ 45 //29 ICACHE_ERR interrupt
84 #define INT_OSPI_IRQ 46 //30 OSPI interrupt
85 #define INT_OTFDE_IRQ 47 //31 OTFDE interrupt
86 #define INT_XIP_ARB_IRQ 48 //32 XIP_ARN interrupt
87 #define INT_XIP_DMA_SEC_IRQ 49 //33 XIP_DMA_S interrupt
88 #define INT_XIP_DMA_NONSEC_IRQ 50 //34 XIP_DMA_NS interrupt
89 #define INT_SW_INTERRUPT_0 51 //35 SW 0 interrupt
90 #define INT_SW_INTERRUPT_1 52 //36 SW 1 interrupt
91 #define INT_SW_INTERRUPT_2 53 //37 SW 2 interrupt
92 #define INT_SW_INTERRUPT_3 54 //38 SW 3 interrupt
93 #define INT_SW_INTERRUPT_4 55 //39 SW 4 interrupt
94 #define INT_SW_INTERRUPT_5 56 //40 SW 5 interrupt
95 #define INT_SW_INTERRUPT_6 57 //41 SW 6 interrupt
96 #define INT_SW_INTERRUPT_7 58 //42 SW 7 interrupt
97 #define INT_PRCM_IRQ 59 //43 PRCM interrupt
98 #define INT_OCLA_IRQ 60 //44 OCLA interrupt
99 #define INT_HIF_FIFO_IRQ 61 //45 HIF interrupt
100 //Wakeup events
101 #define INT_HOST_ELP_TMR_WAKEUP_REQ 62 //46 ELP_TMR interrupt
102 #define INT_NAB_HOST_IRQ 63 //47 NAB_HOST interrupt
103 #define INT_BLE_RFC_GPO_8_IRQ 64 //48 BLE_RFC interrupt
104 #define INT_RTC_EVENT_IRQ 65 //49 RTC interrupt
105 #define INT_DEBUGSS_HOST_CSYSPWRUPREQ 66 //50 DEBUGSS_PWRUP interrupt
106 #define INT_DEBUGSS_HOST_FORCEACTIVE 67 //51 DEBUGSS_FORCEACTIVE interrupt
107 #define INT_SECURED_ERROR_IRQ_EVT_IND_OUT 68 //52
108 
109 
110 #define NUM_INTERRUPTS 69 //Number of interrupts
111 #define NUM_PRIORITY 16 //Number of priority levels
112 #define NUM_PRIORITY_BITS 4 //Number of priority bits
113 
114 #endif // __HW_INTS__