CC35xxDriverLibrary
Macros
hw_i2s.h File Reference
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define I2S_O_AIFWCLKSRC   0x00000000U
 
#define I2S_O_AIFDMACFG   0x00000004U
 
#define I2S_O_AIFDIRCFG   0x00000008U
 
#define I2S_O_AIFFMTCFG   0x0000000CU
 
#define I2S_O_AIFWMASK0   0x00000010U
 
#define I2S_O_AIFWMASK1   0x00000014U
 
#define I2S_O_AIFINPTNXT   0x00000020U
 
#define I2S_O_AIFINPTR   0x00000024U
 
#define I2S_O_AIFOPTNXT   0x00000028U
 
#define I2S_O_AIFOUTPTR   0x0000002CU
 
#define I2S_O_STMPCTL   0x00000034U
 
#define I2S_O_STMPXCPT0   0x00000038U
 
#define I2S_O_STMPXPER   0x0000003CU
 
#define I2S_O_STMPWCPT0   0x00000040U
 
#define I2S_O_STMPWPER   0x00000044U
 
#define I2S_O_STMPINTRIG   0x00000048U
 
#define I2S_O_STMPOTRIG   0x0000004CU
 
#define I2S_O_STMPWSET   0x00000050U
 
#define I2S_O_STMPWADD   0x00000054U
 
#define I2S_O_STMPXPRMIN   0x00000058U
 
#define I2S_O_STMPWCNT   0x0000005CU
 
#define I2S_O_STMPXCNT   0x00000060U
 
#define I2S_O_IRQMASK   0x00000070U
 
#define I2S_O_IRQFLAGS   0x00000074U
 
#define I2S_O_IRQSET   0x00000078U
 
#define I2S_O_IRQCLR   0x0000007CU
 
#define I2S_O_AIFMCLKDIV   0x00000080U
 
#define I2S_O_AIFBCLKDIV   0x00000084U
 
#define I2S_O_AIFWCLKDIV   0x00000088U
 
#define I2S_O_AIFCLKCTL   0x0000008CU
 
#define I2S_O_CLKCFG   0x00001000U
 
#define I2S_O_ADFSCTRL1   0x00001004U
 
#define I2S_O_ADFSCTRL2   0x00001008U
 
#define I2S_AIFWCLKSRC_WBCLKSRC_W   2U
 
#define I2S_AIFWCLKSRC_WBCLKSRC_M   0x00000003U
 
#define I2S_AIFWCLKSRC_WBCLKSRC_S   0U
 
#define I2S_AIFWCLKSRC_WBCLKSRC_NONE   0x00000000U
 
#define I2S_AIFWCLKSRC_WBCLKSRC_EXT   0x00000001U
 
#define I2S_AIFWCLKSRC_WBCLKSRC_INT   0x00000002U
 
#define I2S_AIFWCLKSRC_WBCLKSRC_RESERVED   0x00000003U
 
#define I2S_AIFWCLKSRC_WCLKINV   0x00000004U
 
#define I2S_AIFWCLKSRC_WCLKINV_M   0x00000004U
 
#define I2S_AIFWCLKSRC_WCLKINV_S   2U
 
#define I2S_AIFDMACFG_ENDFRAMIDX_W   8U
 
#define I2S_AIFDMACFG_ENDFRAMIDX_M   0x000000FFU
 
#define I2S_AIFDMACFG_ENDFRAMIDX_S   0U
 
#define I2S_AIFDIRCFG_AD0_W   2U
 
#define I2S_AIFDIRCFG_AD0_M   0x00000003U
 
#define I2S_AIFDIRCFG_AD0_S   0U
 
#define I2S_AIFDIRCFG_AD0_DIS   0x00000000U
 
#define I2S_AIFDIRCFG_AD0_IN   0x00000001U
 
#define I2S_AIFDIRCFG_AD0_OUT   0x00000002U
 
#define I2S_AIFDIRCFG_AD1_W   2U
 
#define I2S_AIFDIRCFG_AD1_M   0x00000030U
 
#define I2S_AIFDIRCFG_AD1_S   4U
 
#define I2S_AIFDIRCFG_AD1_DIS   0x00000000U
 
#define I2S_AIFDIRCFG_AD1_IN   0x00000010U
 
#define I2S_AIFDIRCFG_AD1_OUT   0x00000020U
 
#define I2S_AIFFMTCFG_WORDLEN_W   5U
 
#define I2S_AIFFMTCFG_WORDLEN_M   0x0000001FU
 
#define I2S_AIFFMTCFG_WORDLEN_S   0U
 
#define I2S_AIFFMTCFG_DUALPHASE   0x00000020U
 
#define I2S_AIFFMTCFG_DUALPHASE_M   0x00000020U
 
#define I2S_AIFFMTCFG_DUALPHASE_S   5U
 
#define I2S_AIFFMTCFG_SMPLEDGE   0x00000040U
 
#define I2S_AIFFMTCFG_SMPLEDGE_M   0x00000040U
 
#define I2S_AIFFMTCFG_SMPLEDGE_S   6U
 
#define I2S_AIFFMTCFG_SMPLEDGE_NEG   0x00000000U
 
#define I2S_AIFFMTCFG_SMPLEDGE_POS   0x00000040U
 
#define I2S_AIFFMTCFG_LEN32   0x00000080U
 
#define I2S_AIFFMTCFG_LEN32_M   0x00000080U
 
#define I2S_AIFFMTCFG_LEN32_S   7U
 
#define I2S_AIFFMTCFG_LEN32__16BIT   0x00000000U
 
#define I2S_AIFFMTCFG_LEN32__32BIT   0x00000080U
 
#define I2S_AIFFMTCFG_DATADELAY_W   8U
 
#define I2S_AIFFMTCFG_DATADELAY_M   0x0000FF00U
 
#define I2S_AIFFMTCFG_DATADELAY_S   8U
 
#define I2S_AIFWMASK0_MASK_W   8U
 
#define I2S_AIFWMASK0_MASK_M   0x000000FFU
 
#define I2S_AIFWMASK0_MASK_S   0U
 
#define I2S_AIFWMASK1_MASK_W   8U
 
#define I2S_AIFWMASK1_MASK_M   0x000000FFU
 
#define I2S_AIFWMASK1_MASK_S   0U
 
#define I2S_AIFINPTNXT_PTR_W   32U
 
#define I2S_AIFINPTNXT_PTR_M   0xFFFFFFFFU
 
#define I2S_AIFINPTNXT_PTR_S   0U
 
#define I2S_AIFINPTR_PTR_W   32U
 
#define I2S_AIFINPTR_PTR_M   0xFFFFFFFFU
 
#define I2S_AIFINPTR_PTR_S   0U
 
#define I2S_AIFOPTNXT_PTR_W   32U
 
#define I2S_AIFOPTNXT_PTR_M   0xFFFFFFFFU
 
#define I2S_AIFOPTNXT_PTR_S   0U
 
#define I2S_AIFOUTPTR_PTR_W   32U
 
#define I2S_AIFOUTPTR_PTR_M   0xFFFFFFFFU
 
#define I2S_AIFOUTPTR_PTR_S   0U
 
#define I2S_STMPCTL_STMPEN   0x00000001U
 
#define I2S_STMPCTL_STMPEN_M   0x00000001U
 
#define I2S_STMPCTL_STMPEN_S   0U
 
#define I2S_STMPCTL_INRDY   0x00000002U
 
#define I2S_STMPCTL_INRDY_M   0x00000002U
 
#define I2S_STMPCTL_INRDY_S   1U
 
#define I2S_STMPCTL_OUTRDY   0x00000004U
 
#define I2S_STMPCTL_OUTRDY_M   0x00000004U
 
#define I2S_STMPCTL_OUTRDY_S   2U
 
#define I2S_STMPXCPT0_CAPTVAL_W   16U
 
#define I2S_STMPXCPT0_CAPTVAL_M   0x0000FFFFU
 
#define I2S_STMPXCPT0_CAPTVAL_S   0U
 
#define I2S_STMPXPER_VALUE_W   16U
 
#define I2S_STMPXPER_VALUE_M   0x0000FFFFU
 
#define I2S_STMPXPER_VALUE_S   0U
 
#define I2S_STMPWCPT0_CAPTVAL_W   16U
 
#define I2S_STMPWCPT0_CAPTVAL_M   0x0000FFFFU
 
#define I2S_STMPWCPT0_CAPTVAL_S   0U
 
#define I2S_STMPWPER_VALUE_W   16U
 
#define I2S_STMPWPER_VALUE_M   0x0000FFFFU
 
#define I2S_STMPWPER_VALUE_S   0U
 
#define I2S_STMPINTRIG_INSTRTWCNT_W   16U
 
#define I2S_STMPINTRIG_INSTRTWCNT_M   0x0000FFFFU
 
#define I2S_STMPINTRIG_INSTRTWCNT_S   0U
 
#define I2S_STMPOTRIG_OSTRTWCNT_W   16U
 
#define I2S_STMPOTRIG_OSTRTWCNT_M   0x0000FFFFU
 
#define I2S_STMPOTRIG_OSTRTWCNT_S   0U
 
#define I2S_STMPWSET_VALUE_W   16U
 
#define I2S_STMPWSET_VALUE_M   0x0000FFFFU
 
#define I2S_STMPWSET_VALUE_S   0U
 
#define I2S_STMPWADD_VALINC_W   16U
 
#define I2S_STMPWADD_VALINC_M   0x0000FFFFU
 
#define I2S_STMPWADD_VALINC_S   0U
 
#define I2S_STMPXPRMIN_VALUE_W   16U
 
#define I2S_STMPXPRMIN_VALUE_M   0x0000FFFFU
 
#define I2S_STMPXPRMIN_VALUE_S   0U
 
#define I2S_STMPWCNT_CURRVAL_W   16U
 
#define I2S_STMPWCNT_CURRVAL_M   0x0000FFFFU
 
#define I2S_STMPWCNT_CURRVAL_S   0U
 
#define I2S_STMPXCNT_CURRVAL_W   16U
 
#define I2S_STMPXCNT_CURRVAL_M   0x0000FFFFU
 
#define I2S_STMPXCNT_CURRVAL_S   0U
 
#define I2S_IRQMASK_PTRERR   0x00000001U
 
#define I2S_IRQMASK_PTRERR_M   0x00000001U
 
#define I2S_IRQMASK_PTRERR_S   0U
 
#define I2S_IRQMASK_WCLKERR   0x00000002U
 
#define I2S_IRQMASK_WCLKERR_M   0x00000002U
 
#define I2S_IRQMASK_WCLKERR_S   1U
 
#define I2S_IRQMASK_BUSERR   0x00000004U
 
#define I2S_IRQMASK_BUSERR_M   0x00000004U
 
#define I2S_IRQMASK_BUSERR_S   2U
 
#define I2S_IRQMASK_WCLKTOUT   0x00000008U
 
#define I2S_IRQMASK_WCLKTOUT_M   0x00000008U
 
#define I2S_IRQMASK_WCLKTOUT_S   3U
 
#define I2S_IRQMASK_AIFDMAOUT   0x00000010U
 
#define I2S_IRQMASK_AIFDMAOUT_M   0x00000010U
 
#define I2S_IRQMASK_AIFDMAOUT_S   4U
 
#define I2S_IRQMASK_AIFDMAIN   0x00000020U
 
#define I2S_IRQMASK_AIFDMAIN_M   0x00000020U
 
#define I2S_IRQMASK_AIFDMAIN_S   5U
 
#define I2S_IRQMASK_XCNTCPT   0x00000040U
 
#define I2S_IRQMASK_XCNTCPT_M   0x00000040U
 
#define I2S_IRQMASK_XCNTCPT_S   6U
 
#define I2S_IRQFLAGS_PTRERR   0x00000001U
 
#define I2S_IRQFLAGS_PTRERR_M   0x00000001U
 
#define I2S_IRQFLAGS_PTRERR_S   0U
 
#define I2S_IRQFLAGS_WCLKERR   0x00000002U
 
#define I2S_IRQFLAGS_WCLKERR_M   0x00000002U
 
#define I2S_IRQFLAGS_WCLKERR_S   1U
 
#define I2S_IRQFLAGS_BUSERR   0x00000004U
 
#define I2S_IRQFLAGS_BUSERR_M   0x00000004U
 
#define I2S_IRQFLAGS_BUSERR_S   2U
 
#define I2S_IRQFLAGS_WCLKTOUT   0x00000008U
 
#define I2S_IRQFLAGS_WCLKTOUT_M   0x00000008U
 
#define I2S_IRQFLAGS_WCLKTOUT_S   3U
 
#define I2S_IRQFLAGS_AIFDMAOUT   0x00000010U
 
#define I2S_IRQFLAGS_AIFDMAOUT_M   0x00000010U
 
#define I2S_IRQFLAGS_AIFDMAOUT_S   4U
 
#define I2S_IRQFLAGS_AIFDMAIN   0x00000020U
 
#define I2S_IRQFLAGS_AIFDMAIN_M   0x00000020U
 
#define I2S_IRQFLAGS_AIFDMAIN_S   5U
 
#define I2S_IRQFLAGS_XCNTCPT   0x00000040U
 
#define I2S_IRQFLAGS_XCNTCPT_M   0x00000040U
 
#define I2S_IRQFLAGS_XCNTCPT_S   6U
 
#define I2S_IRQSET_PTRERR   0x00000001U
 
#define I2S_IRQSET_PTRERR_M   0x00000001U
 
#define I2S_IRQSET_PTRERR_S   0U
 
#define I2S_IRQSET_WCLKERR   0x00000002U
 
#define I2S_IRQSET_WCLKERR_M   0x00000002U
 
#define I2S_IRQSET_WCLKERR_S   1U
 
#define I2S_IRQSET_BUSERR   0x00000004U
 
#define I2S_IRQSET_BUSERR_M   0x00000004U
 
#define I2S_IRQSET_BUSERR_S   2U
 
#define I2S_IRQSET_WCLKTOUT   0x00000008U
 
#define I2S_IRQSET_WCLKTOUT_M   0x00000008U
 
#define I2S_IRQSET_WCLKTOUT_S   3U
 
#define I2S_IRQSET_AIFDMAOUT   0x00000010U
 
#define I2S_IRQSET_AIFDMAOUT_M   0x00000010U
 
#define I2S_IRQSET_AIFDMAOUT_S   4U
 
#define I2S_IRQSET_AIFDMAIN   0x00000020U
 
#define I2S_IRQSET_AIFDMAIN_M   0x00000020U
 
#define I2S_IRQSET_AIFDMAIN_S   5U
 
#define I2S_IRQSET_XCNTCPT   0x00000040U
 
#define I2S_IRQSET_XCNTCPT_M   0x00000040U
 
#define I2S_IRQSET_XCNTCPT_S   6U
 
#define I2S_IRQCLR_PTRERR   0x00000001U
 
#define I2S_IRQCLR_PTRERR_M   0x00000001U
 
#define I2S_IRQCLR_PTRERR_S   0U
 
#define I2S_IRQCLR_WCLKERR   0x00000002U
 
#define I2S_IRQCLR_WCLKERR_M   0x00000002U
 
#define I2S_IRQCLR_WCLKERR_S   1U
 
#define I2S_IRQCLR_BUSERR   0x00000004U
 
#define I2S_IRQCLR_BUSERR_M   0x00000004U
 
#define I2S_IRQCLR_BUSERR_S   2U
 
#define I2S_IRQCLR_WCLKTOUT   0x00000008U
 
#define I2S_IRQCLR_WCLKTOUT_M   0x00000008U
 
#define I2S_IRQCLR_WCLKTOUT_S   3U
 
#define I2S_IRQCLR_AIFDMAOUT   0x00000010U
 
#define I2S_IRQCLR_AIFDMAOUT_M   0x00000010U
 
#define I2S_IRQCLR_AIFDMAOUT_S   4U
 
#define I2S_IRQCLR_AIFDMAIN   0x00000020U
 
#define I2S_IRQCLR_AIFDMAIN_M   0x00000020U
 
#define I2S_IRQCLR_AIFDMAIN_S   5U
 
#define I2S_IRQCLR_XCNTCPT   0x00000040U
 
#define I2S_IRQCLR_XCNTCPT_M   0x00000040U
 
#define I2S_IRQCLR_XCNTCPT_S   6U
 
#define I2S_AIFMCLKDIV_MDIV_W   10U
 
#define I2S_AIFMCLKDIV_MDIV_M   0x000003FFU
 
#define I2S_AIFMCLKDIV_MDIV_S   0U
 
#define I2S_AIFBCLKDIV_BDIV_W   10U
 
#define I2S_AIFBCLKDIV_BDIV_M   0x000003FFU
 
#define I2S_AIFBCLKDIV_BDIV_S   0U
 
#define I2S_AIFWCLKDIV_WDIV_W   16U
 
#define I2S_AIFWCLKDIV_WDIV_M   0x0000FFFFU
 
#define I2S_AIFWCLKDIV_WDIV_S   0U
 
#define I2S_AIFCLKCTL_WBEN   0x00000001U
 
#define I2S_AIFCLKCTL_WBEN_M   0x00000001U
 
#define I2S_AIFCLKCTL_WBEN_S   0U
 
#define I2S_AIFCLKCTL_WCLKPHASE_W   2U
 
#define I2S_AIFCLKCTL_WCLKPHASE_M   0x00000006U
 
#define I2S_AIFCLKCTL_WCLKPHASE_S   1U
 
#define I2S_AIFCLKCTL_MEN   0x00000008U
 
#define I2S_AIFCLKCTL_MEN_M   0x00000008U
 
#define I2S_AIFCLKCTL_MEN_S   3U
 
#define I2S_CLKCFG_EN   0x00000001U
 
#define I2S_CLKCFG_EN_M   0x00000001U
 
#define I2S_CLKCFG_EN_S   0U
 
#define I2S_CLKCFG_CLKSEL_W   3U
 
#define I2S_CLKCFG_CLKSEL_M   0x00000070U
 
#define I2S_CLKCFG_CLKSEL_S   4U
 
#define I2S_CLKCFG_CLKSEL_SEL_0   0x00000000U
 
#define I2S_CLKCFG_CLKSEL_SEL_1   0x00000010U
 
#define I2S_CLKCFG_CLKSEL_SEL_2   0x00000020U
 
#define I2S_CLKCFG_CLKSEL_SEL_3   0x00000030U
 
#define I2S_CLKCFG_ADFSEN   0x00000080U
 
#define I2S_CLKCFG_ADFSEN_M   0x00000080U
 
#define I2S_CLKCFG_ADFSEN_S   7U
 
#define I2S_ADFSCTRL1_TREF_W   21U
 
#define I2S_ADFSCTRL1_TREF_M   0x001FFFFFU
 
#define I2S_ADFSCTRL1_TREF_S   0U
 
#define I2S_ADFSCTRL2_DELTA_W   17U
 
#define I2S_ADFSCTRL2_DELTA_M   0x0001FFFFU
 
#define I2S_ADFSCTRL2_DELTA_S   0U
 
#define I2S_ADFSCTRL2_DELTASIGN   0x00020000U
 
#define I2S_ADFSCTRL2_DELTASIGN_M   0x00020000U
 
#define I2S_ADFSCTRL2_DELTASIGN_S   17U
 
#define I2S_ADFSCTRL2_DIV_W   10U
 
#define I2S_ADFSCTRL2_DIV_M   0x3FF00000U
 
#define I2S_ADFSCTRL2_DIV_S   20U
 

Macro Definition Documentation

§ I2S_O_AIFWCLKSRC

#define I2S_O_AIFWCLKSRC   0x00000000U

Referenced by I2SConfigureClocks().

§ I2S_O_AIFDMACFG

#define I2S_O_AIFDMACFG   0x00000004U

Referenced by I2SStart(), and I2SStop().

§ I2S_O_AIFDIRCFG

#define I2S_O_AIFDIRCFG   0x00000008U

Referenced by I2SConfigureFrame().

§ I2S_O_AIFFMTCFG

#define I2S_O_AIFFMTCFG   0x0000000CU

Referenced by I2SConfigureFormat().

§ I2S_O_AIFWMASK0

#define I2S_O_AIFWMASK0   0x00000010U

Referenced by I2SConfigureFrame().

§ I2S_O_AIFWMASK1

#define I2S_O_AIFWMASK1   0x00000014U

Referenced by I2SConfigureFrame().

§ I2S_O_AIFINPTNXT

#define I2S_O_AIFINPTNXT   0x00000020U

Referenced by I2SGetInPointerNext(), and I2SSetInPointer().

§ I2S_O_AIFINPTR

#define I2S_O_AIFINPTR   0x00000024U

Referenced by I2SGetInPointer().

§ I2S_O_AIFOPTNXT

#define I2S_O_AIFOPTNXT   0x00000028U

Referenced by I2SGetOutPointerNext(), and I2SSetOutPointer().

§ I2S_O_AIFOUTPTR

#define I2S_O_AIFOUTPTR   0x0000002CU

Referenced by I2SGetOutPointer().

§ I2S_O_STMPCTL

#define I2S_O_STMPCTL   0x00000034U

Referenced by I2SDisableSampleStamp(), and I2SEnableSampleStamp().

§ I2S_O_STMPXCPT0

#define I2S_O_STMPXCPT0   0x00000038U

Referenced by I2SGetSampleStamp().

§ I2S_O_STMPXPER

#define I2S_O_STMPXPER   0x0000003CU

Referenced by I2SGetSampleStamp().

§ I2S_O_STMPWCPT0

#define I2S_O_STMPWCPT0   0x00000040U

Referenced by I2SGetSampleStamp().

§ I2S_O_STMPWPER

#define I2S_O_STMPWPER   0x00000044U

Referenced by I2SConfigureWclkCounter(), and I2SConfigureWclkCounterPeriod().

§ I2S_O_STMPINTRIG

#define I2S_O_STMPINTRIG   0x00000048U

Referenced by I2SConfigureInSampleStampTrigger().

§ I2S_O_STMPOTRIG

#define I2S_O_STMPOTRIG   0x0000004CU

Referenced by I2SConfigureOutSampleStampTrigger().

§ I2S_O_STMPWSET

#define I2S_O_STMPWSET   0x00000050U

Referenced by I2SResetWclkCounter().

§ I2S_O_STMPWADD

#define I2S_O_STMPWADD   0x00000054U

Referenced by I2SConfigureWclkCounter().

§ I2S_O_STMPXPRMIN

#define I2S_O_STMPXPRMIN   0x00000058U

§ I2S_O_STMPWCNT

#define I2S_O_STMPWCNT   0x0000005CU

§ I2S_O_STMPXCNT

#define I2S_O_STMPXCNT   0x00000060U

§ I2S_O_IRQMASK

#define I2S_O_IRQMASK   0x00000070U

Referenced by I2SDisableInt(), I2SEnableInt(), and I2SIntStatus().

§ I2S_O_IRQFLAGS

#define I2S_O_IRQFLAGS   0x00000074U

Referenced by I2SIntStatus().

§ I2S_O_IRQSET

#define I2S_O_IRQSET   0x00000078U

§ I2S_O_IRQCLR

#define I2S_O_IRQCLR   0x0000007CU

Referenced by I2SClearInt().

§ I2S_O_AIFMCLKDIV

#define I2S_O_AIFMCLKDIV   0x00000080U

Referenced by I2SConfigureClocks().

§ I2S_O_AIFBCLKDIV

#define I2S_O_AIFBCLKDIV   0x00000084U

Referenced by I2SConfigureClocks().

§ I2S_O_AIFWCLKDIV

#define I2S_O_AIFWCLKDIV   0x00000088U

Referenced by I2SConfigureClocks().

§ I2S_O_AIFCLKCTL

#define I2S_O_AIFCLKCTL   0x0000008CU

Referenced by I2SConfigureClocks(), I2SDisableControllerClocks(), and I2SEnableControllerClocks().

§ I2S_O_CLKCFG

#define I2S_O_CLKCFG   0x00001000U

Referenced by I2SDisableAdfs(), I2SDisableClk(), I2SEnableAdfs(), I2SEnableClk(), and I2SSelectAdfsInputClk().

§ I2S_O_ADFSCTRL1

#define I2S_O_ADFSCTRL1   0x00001004U

Referenced by I2SConfigureAdfs().

§ I2S_O_ADFSCTRL2

#define I2S_O_ADFSCTRL2   0x00001008U

Referenced by I2SConfigureAdfs().

§ I2S_AIFWCLKSRC_WBCLKSRC_W

#define I2S_AIFWCLKSRC_WBCLKSRC_W   2U

§ I2S_AIFWCLKSRC_WBCLKSRC_M

#define I2S_AIFWCLKSRC_WBCLKSRC_M   0x00000003U

§ I2S_AIFWCLKSRC_WBCLKSRC_S

#define I2S_AIFWCLKSRC_WBCLKSRC_S   0U

§ I2S_AIFWCLKSRC_WBCLKSRC_NONE

#define I2S_AIFWCLKSRC_WBCLKSRC_NONE   0x00000000U

§ I2S_AIFWCLKSRC_WBCLKSRC_EXT

#define I2S_AIFWCLKSRC_WBCLKSRC_EXT   0x00000001U

Referenced by I2SConfigureClocks().

§ I2S_AIFWCLKSRC_WBCLKSRC_INT

#define I2S_AIFWCLKSRC_WBCLKSRC_INT   0x00000002U

Referenced by I2SConfigureClocks().

§ I2S_AIFWCLKSRC_WBCLKSRC_RESERVED

#define I2S_AIFWCLKSRC_WBCLKSRC_RESERVED   0x00000003U

§ I2S_AIFWCLKSRC_WCLKINV

#define I2S_AIFWCLKSRC_WCLKINV   0x00000004U

Referenced by I2SConfigureClocks().

§ I2S_AIFWCLKSRC_WCLKINV_M

#define I2S_AIFWCLKSRC_WCLKINV_M   0x00000004U

§ I2S_AIFWCLKSRC_WCLKINV_S

#define I2S_AIFWCLKSRC_WCLKINV_S   2U

§ I2S_AIFDMACFG_ENDFRAMIDX_W

#define I2S_AIFDMACFG_ENDFRAMIDX_W   8U

§ I2S_AIFDMACFG_ENDFRAMIDX_M

#define I2S_AIFDMACFG_ENDFRAMIDX_M   0x000000FFU

Referenced by I2SStart().

§ I2S_AIFDMACFG_ENDFRAMIDX_S

#define I2S_AIFDMACFG_ENDFRAMIDX_S   0U

§ I2S_AIFDIRCFG_AD0_W

#define I2S_AIFDIRCFG_AD0_W   2U

§ I2S_AIFDIRCFG_AD0_M

#define I2S_AIFDIRCFG_AD0_M   0x00000003U

§ I2S_AIFDIRCFG_AD0_S

#define I2S_AIFDIRCFG_AD0_S   0U

§ I2S_AIFDIRCFG_AD0_DIS

#define I2S_AIFDIRCFG_AD0_DIS   0x00000000U

§ I2S_AIFDIRCFG_AD0_IN

#define I2S_AIFDIRCFG_AD0_IN   0x00000001U

§ I2S_AIFDIRCFG_AD0_OUT

#define I2S_AIFDIRCFG_AD0_OUT   0x00000002U

§ I2S_AIFDIRCFG_AD1_W

#define I2S_AIFDIRCFG_AD1_W   2U

§ I2S_AIFDIRCFG_AD1_M

#define I2S_AIFDIRCFG_AD1_M   0x00000030U

§ I2S_AIFDIRCFG_AD1_S

#define I2S_AIFDIRCFG_AD1_S   4U

§ I2S_AIFDIRCFG_AD1_DIS

#define I2S_AIFDIRCFG_AD1_DIS   0x00000000U

§ I2S_AIFDIRCFG_AD1_IN

#define I2S_AIFDIRCFG_AD1_IN   0x00000010U

§ I2S_AIFDIRCFG_AD1_OUT

#define I2S_AIFDIRCFG_AD1_OUT   0x00000020U

§ I2S_AIFFMTCFG_WORDLEN_W

#define I2S_AIFFMTCFG_WORDLEN_W   5U

§ I2S_AIFFMTCFG_WORDLEN_M

#define I2S_AIFFMTCFG_WORDLEN_M   0x0000001FU

§ I2S_AIFFMTCFG_WORDLEN_S

#define I2S_AIFFMTCFG_WORDLEN_S   0U

Referenced by I2SConfigureFormat().

§ I2S_AIFFMTCFG_DUALPHASE

#define I2S_AIFFMTCFG_DUALPHASE   0x00000020U

§ I2S_AIFFMTCFG_DUALPHASE_M

#define I2S_AIFFMTCFG_DUALPHASE_M   0x00000020U

§ I2S_AIFFMTCFG_DUALPHASE_S

#define I2S_AIFFMTCFG_DUALPHASE_S   5U

Referenced by I2SConfigureFormat().

§ I2S_AIFFMTCFG_SMPLEDGE

#define I2S_AIFFMTCFG_SMPLEDGE   0x00000040U

§ I2S_AIFFMTCFG_SMPLEDGE_M

#define I2S_AIFFMTCFG_SMPLEDGE_M   0x00000040U

§ I2S_AIFFMTCFG_SMPLEDGE_S

#define I2S_AIFFMTCFG_SMPLEDGE_S   6U

§ I2S_AIFFMTCFG_SMPLEDGE_NEG

#define I2S_AIFFMTCFG_SMPLEDGE_NEG   0x00000000U

§ I2S_AIFFMTCFG_SMPLEDGE_POS

#define I2S_AIFFMTCFG_SMPLEDGE_POS   0x00000040U

§ I2S_AIFFMTCFG_LEN32

#define I2S_AIFFMTCFG_LEN32   0x00000080U

§ I2S_AIFFMTCFG_LEN32_M

#define I2S_AIFFMTCFG_LEN32_M   0x00000080U

§ I2S_AIFFMTCFG_LEN32_S

#define I2S_AIFFMTCFG_LEN32_S   7U

§ I2S_AIFFMTCFG_LEN32__16BIT

#define I2S_AIFFMTCFG_LEN32__16BIT   0x00000000U

§ I2S_AIFFMTCFG_LEN32__32BIT

#define I2S_AIFFMTCFG_LEN32__32BIT   0x00000080U

§ I2S_AIFFMTCFG_DATADELAY_W

#define I2S_AIFFMTCFG_DATADELAY_W   8U

§ I2S_AIFFMTCFG_DATADELAY_M

#define I2S_AIFFMTCFG_DATADELAY_M   0x0000FF00U

§ I2S_AIFFMTCFG_DATADELAY_S

#define I2S_AIFFMTCFG_DATADELAY_S   8U

Referenced by I2SConfigureFormat().

§ I2S_AIFWMASK0_MASK_W

#define I2S_AIFWMASK0_MASK_W   8U

§ I2S_AIFWMASK0_MASK_M

#define I2S_AIFWMASK0_MASK_M   0x000000FFU

§ I2S_AIFWMASK0_MASK_S

#define I2S_AIFWMASK0_MASK_S   0U

§ I2S_AIFWMASK1_MASK_W

#define I2S_AIFWMASK1_MASK_W   8U

§ I2S_AIFWMASK1_MASK_M

#define I2S_AIFWMASK1_MASK_M   0x000000FFU

§ I2S_AIFWMASK1_MASK_S

#define I2S_AIFWMASK1_MASK_S   0U

§ I2S_AIFINPTNXT_PTR_W

#define I2S_AIFINPTNXT_PTR_W   32U

§ I2S_AIFINPTNXT_PTR_M

#define I2S_AIFINPTNXT_PTR_M   0xFFFFFFFFU

§ I2S_AIFINPTNXT_PTR_S

#define I2S_AIFINPTNXT_PTR_S   0U

§ I2S_AIFINPTR_PTR_W

#define I2S_AIFINPTR_PTR_W   32U

§ I2S_AIFINPTR_PTR_M

#define I2S_AIFINPTR_PTR_M   0xFFFFFFFFU

§ I2S_AIFINPTR_PTR_S

#define I2S_AIFINPTR_PTR_S   0U

§ I2S_AIFOPTNXT_PTR_W

#define I2S_AIFOPTNXT_PTR_W   32U

§ I2S_AIFOPTNXT_PTR_M

#define I2S_AIFOPTNXT_PTR_M   0xFFFFFFFFU

§ I2S_AIFOPTNXT_PTR_S

#define I2S_AIFOPTNXT_PTR_S   0U

§ I2S_AIFOUTPTR_PTR_W

#define I2S_AIFOUTPTR_PTR_W   32U

§ I2S_AIFOUTPTR_PTR_M

#define I2S_AIFOUTPTR_PTR_M   0xFFFFFFFFU

§ I2S_AIFOUTPTR_PTR_S

#define I2S_AIFOUTPTR_PTR_S   0U

§ I2S_STMPCTL_STMPEN

#define I2S_STMPCTL_STMPEN   0x00000001U

§ I2S_STMPCTL_STMPEN_M

#define I2S_STMPCTL_STMPEN_M   0x00000001U

Referenced by I2SDisableSampleStamp(), and I2SEnableSampleStamp().

§ I2S_STMPCTL_STMPEN_S

#define I2S_STMPCTL_STMPEN_S   0U

§ I2S_STMPCTL_INRDY

#define I2S_STMPCTL_INRDY   0x00000002U

§ I2S_STMPCTL_INRDY_M

#define I2S_STMPCTL_INRDY_M   0x00000002U

§ I2S_STMPCTL_INRDY_S

#define I2S_STMPCTL_INRDY_S   1U

§ I2S_STMPCTL_OUTRDY

#define I2S_STMPCTL_OUTRDY   0x00000004U

§ I2S_STMPCTL_OUTRDY_M

#define I2S_STMPCTL_OUTRDY_M   0x00000004U

§ I2S_STMPCTL_OUTRDY_S

#define I2S_STMPCTL_OUTRDY_S   2U

§ I2S_STMPXCPT0_CAPTVAL_W

#define I2S_STMPXCPT0_CAPTVAL_W   16U

§ I2S_STMPXCPT0_CAPTVAL_M

#define I2S_STMPXCPT0_CAPTVAL_M   0x0000FFFFU

§ I2S_STMPXCPT0_CAPTVAL_S

#define I2S_STMPXCPT0_CAPTVAL_S   0U

§ I2S_STMPXPER_VALUE_W

#define I2S_STMPXPER_VALUE_W   16U

§ I2S_STMPXPER_VALUE_M

#define I2S_STMPXPER_VALUE_M   0x0000FFFFU

§ I2S_STMPXPER_VALUE_S

#define I2S_STMPXPER_VALUE_S   0U

§ I2S_STMPWCPT0_CAPTVAL_W

#define I2S_STMPWCPT0_CAPTVAL_W   16U

§ I2S_STMPWCPT0_CAPTVAL_M

#define I2S_STMPWCPT0_CAPTVAL_M   0x0000FFFFU

§ I2S_STMPWCPT0_CAPTVAL_S

#define I2S_STMPWCPT0_CAPTVAL_S   0U

§ I2S_STMPWPER_VALUE_W

#define I2S_STMPWPER_VALUE_W   16U

§ I2S_STMPWPER_VALUE_M

#define I2S_STMPWPER_VALUE_M   0x0000FFFFU

§ I2S_STMPWPER_VALUE_S

#define I2S_STMPWPER_VALUE_S   0U

§ I2S_STMPINTRIG_INSTRTWCNT_W

#define I2S_STMPINTRIG_INSTRTWCNT_W   16U

§ I2S_STMPINTRIG_INSTRTWCNT_M

#define I2S_STMPINTRIG_INSTRTWCNT_M   0x0000FFFFU

§ I2S_STMPINTRIG_INSTRTWCNT_S

#define I2S_STMPINTRIG_INSTRTWCNT_S   0U

§ I2S_STMPOTRIG_OSTRTWCNT_W

#define I2S_STMPOTRIG_OSTRTWCNT_W   16U

§ I2S_STMPOTRIG_OSTRTWCNT_M

#define I2S_STMPOTRIG_OSTRTWCNT_M   0x0000FFFFU

§ I2S_STMPOTRIG_OSTRTWCNT_S

#define I2S_STMPOTRIG_OSTRTWCNT_S   0U

§ I2S_STMPWSET_VALUE_W

#define I2S_STMPWSET_VALUE_W   16U

§ I2S_STMPWSET_VALUE_M

#define I2S_STMPWSET_VALUE_M   0x0000FFFFU

§ I2S_STMPWSET_VALUE_S

#define I2S_STMPWSET_VALUE_S   0U

§ I2S_STMPWADD_VALINC_W

#define I2S_STMPWADD_VALINC_W   16U

§ I2S_STMPWADD_VALINC_M

#define I2S_STMPWADD_VALINC_M   0x0000FFFFU

§ I2S_STMPWADD_VALINC_S

#define I2S_STMPWADD_VALINC_S   0U

§ I2S_STMPXPRMIN_VALUE_W

#define I2S_STMPXPRMIN_VALUE_W   16U

§ I2S_STMPXPRMIN_VALUE_M

#define I2S_STMPXPRMIN_VALUE_M   0x0000FFFFU

§ I2S_STMPXPRMIN_VALUE_S

#define I2S_STMPXPRMIN_VALUE_S   0U

§ I2S_STMPWCNT_CURRVAL_W

#define I2S_STMPWCNT_CURRVAL_W   16U

§ I2S_STMPWCNT_CURRVAL_M

#define I2S_STMPWCNT_CURRVAL_M   0x0000FFFFU

§ I2S_STMPWCNT_CURRVAL_S

#define I2S_STMPWCNT_CURRVAL_S   0U

§ I2S_STMPXCNT_CURRVAL_W

#define I2S_STMPXCNT_CURRVAL_W   16U

§ I2S_STMPXCNT_CURRVAL_M

#define I2S_STMPXCNT_CURRVAL_M   0x0000FFFFU

§ I2S_STMPXCNT_CURRVAL_S

#define I2S_STMPXCNT_CURRVAL_S   0U

§ I2S_IRQMASK_PTRERR

#define I2S_IRQMASK_PTRERR   0x00000001U

§ I2S_IRQMASK_PTRERR_M

#define I2S_IRQMASK_PTRERR_M   0x00000001U

§ I2S_IRQMASK_PTRERR_S

#define I2S_IRQMASK_PTRERR_S   0U

§ I2S_IRQMASK_WCLKERR

#define I2S_IRQMASK_WCLKERR   0x00000002U

§ I2S_IRQMASK_WCLKERR_M

#define I2S_IRQMASK_WCLKERR_M   0x00000002U

§ I2S_IRQMASK_WCLKERR_S

#define I2S_IRQMASK_WCLKERR_S   1U

§ I2S_IRQMASK_BUSERR

#define I2S_IRQMASK_BUSERR   0x00000004U

§ I2S_IRQMASK_BUSERR_M

#define I2S_IRQMASK_BUSERR_M   0x00000004U

§ I2S_IRQMASK_BUSERR_S

#define I2S_IRQMASK_BUSERR_S   2U

§ I2S_IRQMASK_WCLKTOUT

#define I2S_IRQMASK_WCLKTOUT   0x00000008U

§ I2S_IRQMASK_WCLKTOUT_M

#define I2S_IRQMASK_WCLKTOUT_M   0x00000008U

§ I2S_IRQMASK_WCLKTOUT_S

#define I2S_IRQMASK_WCLKTOUT_S   3U

§ I2S_IRQMASK_AIFDMAOUT

#define I2S_IRQMASK_AIFDMAOUT   0x00000010U

§ I2S_IRQMASK_AIFDMAOUT_M

#define I2S_IRQMASK_AIFDMAOUT_M   0x00000010U

§ I2S_IRQMASK_AIFDMAOUT_S

#define I2S_IRQMASK_AIFDMAOUT_S   4U

§ I2S_IRQMASK_AIFDMAIN

#define I2S_IRQMASK_AIFDMAIN   0x00000020U

§ I2S_IRQMASK_AIFDMAIN_M

#define I2S_IRQMASK_AIFDMAIN_M   0x00000020U

§ I2S_IRQMASK_AIFDMAIN_S

#define I2S_IRQMASK_AIFDMAIN_S   5U

§ I2S_IRQMASK_XCNTCPT

#define I2S_IRQMASK_XCNTCPT   0x00000040U

§ I2S_IRQMASK_XCNTCPT_M

#define I2S_IRQMASK_XCNTCPT_M   0x00000040U

§ I2S_IRQMASK_XCNTCPT_S

#define I2S_IRQMASK_XCNTCPT_S   6U

§ I2S_IRQFLAGS_PTRERR

#define I2S_IRQFLAGS_PTRERR   0x00000001U

§ I2S_IRQFLAGS_PTRERR_M

#define I2S_IRQFLAGS_PTRERR_M   0x00000001U

§ I2S_IRQFLAGS_PTRERR_S

#define I2S_IRQFLAGS_PTRERR_S   0U

§ I2S_IRQFLAGS_WCLKERR

#define I2S_IRQFLAGS_WCLKERR   0x00000002U

§ I2S_IRQFLAGS_WCLKERR_M

#define I2S_IRQFLAGS_WCLKERR_M   0x00000002U

§ I2S_IRQFLAGS_WCLKERR_S

#define I2S_IRQFLAGS_WCLKERR_S   1U

§ I2S_IRQFLAGS_BUSERR

#define I2S_IRQFLAGS_BUSERR   0x00000004U

§ I2S_IRQFLAGS_BUSERR_M

#define I2S_IRQFLAGS_BUSERR_M   0x00000004U

§ I2S_IRQFLAGS_BUSERR_S

#define I2S_IRQFLAGS_BUSERR_S   2U

§ I2S_IRQFLAGS_WCLKTOUT

#define I2S_IRQFLAGS_WCLKTOUT   0x00000008U

§ I2S_IRQFLAGS_WCLKTOUT_M

#define I2S_IRQFLAGS_WCLKTOUT_M   0x00000008U

§ I2S_IRQFLAGS_WCLKTOUT_S

#define I2S_IRQFLAGS_WCLKTOUT_S   3U

§ I2S_IRQFLAGS_AIFDMAOUT

#define I2S_IRQFLAGS_AIFDMAOUT   0x00000010U

§ I2S_IRQFLAGS_AIFDMAOUT_M

#define I2S_IRQFLAGS_AIFDMAOUT_M   0x00000010U

§ I2S_IRQFLAGS_AIFDMAOUT_S

#define I2S_IRQFLAGS_AIFDMAOUT_S   4U

§ I2S_IRQFLAGS_AIFDMAIN

#define I2S_IRQFLAGS_AIFDMAIN   0x00000020U

§ I2S_IRQFLAGS_AIFDMAIN_M

#define I2S_IRQFLAGS_AIFDMAIN_M   0x00000020U

§ I2S_IRQFLAGS_AIFDMAIN_S

#define I2S_IRQFLAGS_AIFDMAIN_S   5U

§ I2S_IRQFLAGS_XCNTCPT

#define I2S_IRQFLAGS_XCNTCPT   0x00000040U

§ I2S_IRQFLAGS_XCNTCPT_M

#define I2S_IRQFLAGS_XCNTCPT_M   0x00000040U

§ I2S_IRQFLAGS_XCNTCPT_S

#define I2S_IRQFLAGS_XCNTCPT_S   6U

§ I2S_IRQSET_PTRERR

#define I2S_IRQSET_PTRERR   0x00000001U

§ I2S_IRQSET_PTRERR_M

#define I2S_IRQSET_PTRERR_M   0x00000001U

§ I2S_IRQSET_PTRERR_S

#define I2S_IRQSET_PTRERR_S   0U

§ I2S_IRQSET_WCLKERR

#define I2S_IRQSET_WCLKERR   0x00000002U

§ I2S_IRQSET_WCLKERR_M

#define I2S_IRQSET_WCLKERR_M   0x00000002U

§ I2S_IRQSET_WCLKERR_S

#define I2S_IRQSET_WCLKERR_S   1U

§ I2S_IRQSET_BUSERR

#define I2S_IRQSET_BUSERR   0x00000004U

§ I2S_IRQSET_BUSERR_M

#define I2S_IRQSET_BUSERR_M   0x00000004U

§ I2S_IRQSET_BUSERR_S

#define I2S_IRQSET_BUSERR_S   2U

§ I2S_IRQSET_WCLKTOUT

#define I2S_IRQSET_WCLKTOUT   0x00000008U

§ I2S_IRQSET_WCLKTOUT_M

#define I2S_IRQSET_WCLKTOUT_M   0x00000008U

§ I2S_IRQSET_WCLKTOUT_S

#define I2S_IRQSET_WCLKTOUT_S   3U

§ I2S_IRQSET_AIFDMAOUT

#define I2S_IRQSET_AIFDMAOUT   0x00000010U

§ I2S_IRQSET_AIFDMAOUT_M

#define I2S_IRQSET_AIFDMAOUT_M   0x00000010U

§ I2S_IRQSET_AIFDMAOUT_S

#define I2S_IRQSET_AIFDMAOUT_S   4U

§ I2S_IRQSET_AIFDMAIN

#define I2S_IRQSET_AIFDMAIN   0x00000020U

§ I2S_IRQSET_AIFDMAIN_M

#define I2S_IRQSET_AIFDMAIN_M   0x00000020U

§ I2S_IRQSET_AIFDMAIN_S

#define I2S_IRQSET_AIFDMAIN_S   5U

§ I2S_IRQSET_XCNTCPT

#define I2S_IRQSET_XCNTCPT   0x00000040U

§ I2S_IRQSET_XCNTCPT_M

#define I2S_IRQSET_XCNTCPT_M   0x00000040U

§ I2S_IRQSET_XCNTCPT_S

#define I2S_IRQSET_XCNTCPT_S   6U

§ I2S_IRQCLR_PTRERR

#define I2S_IRQCLR_PTRERR   0x00000001U

§ I2S_IRQCLR_PTRERR_M

#define I2S_IRQCLR_PTRERR_M   0x00000001U

§ I2S_IRQCLR_PTRERR_S

#define I2S_IRQCLR_PTRERR_S   0U

§ I2S_IRQCLR_WCLKERR

#define I2S_IRQCLR_WCLKERR   0x00000002U

§ I2S_IRQCLR_WCLKERR_M

#define I2S_IRQCLR_WCLKERR_M   0x00000002U

§ I2S_IRQCLR_WCLKERR_S

#define I2S_IRQCLR_WCLKERR_S   1U

§ I2S_IRQCLR_BUSERR

#define I2S_IRQCLR_BUSERR   0x00000004U

§ I2S_IRQCLR_BUSERR_M

#define I2S_IRQCLR_BUSERR_M   0x00000004U

§ I2S_IRQCLR_BUSERR_S

#define I2S_IRQCLR_BUSERR_S   2U

§ I2S_IRQCLR_WCLKTOUT

#define I2S_IRQCLR_WCLKTOUT   0x00000008U

§ I2S_IRQCLR_WCLKTOUT_M

#define I2S_IRQCLR_WCLKTOUT_M   0x00000008U

§ I2S_IRQCLR_WCLKTOUT_S

#define I2S_IRQCLR_WCLKTOUT_S   3U

§ I2S_IRQCLR_AIFDMAOUT

#define I2S_IRQCLR_AIFDMAOUT   0x00000010U

§ I2S_IRQCLR_AIFDMAOUT_M

#define I2S_IRQCLR_AIFDMAOUT_M   0x00000010U

§ I2S_IRQCLR_AIFDMAOUT_S

#define I2S_IRQCLR_AIFDMAOUT_S   4U

§ I2S_IRQCLR_AIFDMAIN

#define I2S_IRQCLR_AIFDMAIN   0x00000020U

§ I2S_IRQCLR_AIFDMAIN_M

#define I2S_IRQCLR_AIFDMAIN_M   0x00000020U

§ I2S_IRQCLR_AIFDMAIN_S

#define I2S_IRQCLR_AIFDMAIN_S   5U

§ I2S_IRQCLR_XCNTCPT

#define I2S_IRQCLR_XCNTCPT   0x00000040U

§ I2S_IRQCLR_XCNTCPT_M

#define I2S_IRQCLR_XCNTCPT_M   0x00000040U

§ I2S_IRQCLR_XCNTCPT_S

#define I2S_IRQCLR_XCNTCPT_S   6U

§ I2S_AIFMCLKDIV_MDIV_W

#define I2S_AIFMCLKDIV_MDIV_W   10U

§ I2S_AIFMCLKDIV_MDIV_M

#define I2S_AIFMCLKDIV_MDIV_M   0x000003FFU

§ I2S_AIFMCLKDIV_MDIV_S

#define I2S_AIFMCLKDIV_MDIV_S   0U

§ I2S_AIFBCLKDIV_BDIV_W

#define I2S_AIFBCLKDIV_BDIV_W   10U

§ I2S_AIFBCLKDIV_BDIV_M

#define I2S_AIFBCLKDIV_BDIV_M   0x000003FFU

§ I2S_AIFBCLKDIV_BDIV_S

#define I2S_AIFBCLKDIV_BDIV_S   0U

§ I2S_AIFWCLKDIV_WDIV_W

#define I2S_AIFWCLKDIV_WDIV_W   16U

§ I2S_AIFWCLKDIV_WDIV_M

#define I2S_AIFWCLKDIV_WDIV_M   0x0000FFFFU

§ I2S_AIFWCLKDIV_WDIV_S

#define I2S_AIFWCLKDIV_WDIV_S   0U

§ I2S_AIFCLKCTL_WBEN

#define I2S_AIFCLKCTL_WBEN   0x00000001U

Referenced by I2SDisableControllerClocks(), and I2SEnableControllerClocks().

§ I2S_AIFCLKCTL_WBEN_M

#define I2S_AIFCLKCTL_WBEN_M   0x00000001U

§ I2S_AIFCLKCTL_WBEN_S

#define I2S_AIFCLKCTL_WBEN_S   0U

§ I2S_AIFCLKCTL_WCLKPHASE_W

#define I2S_AIFCLKCTL_WCLKPHASE_W   2U

§ I2S_AIFCLKCTL_WCLKPHASE_M

#define I2S_AIFCLKCTL_WCLKPHASE_M   0x00000006U

§ I2S_AIFCLKCTL_WCLKPHASE_S

#define I2S_AIFCLKCTL_WCLKPHASE_S   1U

Referenced by I2SConfigureClocks().

§ I2S_AIFCLKCTL_MEN

#define I2S_AIFCLKCTL_MEN   0x00000008U

Referenced by I2SDisableControllerClocks(), and I2SEnableControllerClocks().

§ I2S_AIFCLKCTL_MEN_M

#define I2S_AIFCLKCTL_MEN_M   0x00000008U

§ I2S_AIFCLKCTL_MEN_S

#define I2S_AIFCLKCTL_MEN_S   3U

§ I2S_CLKCFG_EN

#define I2S_CLKCFG_EN   0x00000001U

§ I2S_CLKCFG_EN_M

#define I2S_CLKCFG_EN_M   0x00000001U

Referenced by I2SDisableClk(), and I2SEnableClk().

§ I2S_CLKCFG_EN_S

#define I2S_CLKCFG_EN_S   0U

§ I2S_CLKCFG_CLKSEL_W

#define I2S_CLKCFG_CLKSEL_W   3U

§ I2S_CLKCFG_CLKSEL_M

#define I2S_CLKCFG_CLKSEL_M   0x00000070U

Referenced by I2SSelectAdfsInputClk().

§ I2S_CLKCFG_CLKSEL_S

#define I2S_CLKCFG_CLKSEL_S   4U

§ I2S_CLKCFG_CLKSEL_SEL_0

#define I2S_CLKCFG_CLKSEL_SEL_0   0x00000000U

§ I2S_CLKCFG_CLKSEL_SEL_1

#define I2S_CLKCFG_CLKSEL_SEL_1   0x00000010U

§ I2S_CLKCFG_CLKSEL_SEL_2

#define I2S_CLKCFG_CLKSEL_SEL_2   0x00000020U

§ I2S_CLKCFG_CLKSEL_SEL_3

#define I2S_CLKCFG_CLKSEL_SEL_3   0x00000030U

§ I2S_CLKCFG_ADFSEN

#define I2S_CLKCFG_ADFSEN   0x00000080U

§ I2S_CLKCFG_ADFSEN_M

#define I2S_CLKCFG_ADFSEN_M   0x00000080U

Referenced by I2SDisableAdfs(), and I2SEnableAdfs().

§ I2S_CLKCFG_ADFSEN_S

#define I2S_CLKCFG_ADFSEN_S   7U

§ I2S_ADFSCTRL1_TREF_W

#define I2S_ADFSCTRL1_TREF_W   21U

§ I2S_ADFSCTRL1_TREF_M

#define I2S_ADFSCTRL1_TREF_M   0x001FFFFFU

Referenced by I2SConfigureAdfs().

§ I2S_ADFSCTRL1_TREF_S

#define I2S_ADFSCTRL1_TREF_S   0U

§ I2S_ADFSCTRL2_DELTA_W

#define I2S_ADFSCTRL2_DELTA_W   17U

§ I2S_ADFSCTRL2_DELTA_M

#define I2S_ADFSCTRL2_DELTA_M   0x0001FFFFU

Referenced by I2SConfigureAdfs().

§ I2S_ADFSCTRL2_DELTA_S

#define I2S_ADFSCTRL2_DELTA_S   0U

§ I2S_ADFSCTRL2_DELTASIGN

#define I2S_ADFSCTRL2_DELTASIGN   0x00020000U

§ I2S_ADFSCTRL2_DELTASIGN_M

#define I2S_ADFSCTRL2_DELTASIGN_M   0x00020000U

Referenced by I2SConfigureAdfs().

§ I2S_ADFSCTRL2_DELTASIGN_S

#define I2S_ADFSCTRL2_DELTASIGN_S   17U

Referenced by I2SConfigureAdfs().

§ I2S_ADFSCTRL2_DIV_W

#define I2S_ADFSCTRL2_DIV_W   10U

§ I2S_ADFSCTRL2_DIV_M

#define I2S_ADFSCTRL2_DIV_M   0x3FF00000U

Referenced by I2SConfigureAdfs().

§ I2S_ADFSCTRL2_DIV_S

#define I2S_ADFSCTRL2_DIV_S   20U

Referenced by I2SConfigureAdfs().