CC35xxDriverLibrary
hw_i2c.h
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1 /******************************************************************************
2 * Filename: hw_i2c.h
3 *
4 * Description: Defines and prototypes for the I2C peripheral.
5 *
6 * Copyright (c) 2023, Texas Instruments Incorporated
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36 #ifndef __HW_I2C_H__
37 #define __HW_I2C_H__
38 /*-------------------------------------------------------------------------------
39 
40 This section defines the register offsets of the I2C component
41 
42 --------------------------------------------------------------------------------- */
43 
44 //This register controls the glitch filter on the SCL and SDA lines
45 #define I2C_O_GFCTL 0x00000100U
46 
47 //Controller target address register
48 #define I2C_O_CSA 0x00000104U
49 
50 //This control register configures the *I2C* controller operation
51 #define I2C_O_CCTR 0x00000108U
52 
53 //The status register indicates the state of the bus controller
54 #define I2C_O_CSR 0x0000010CU
55 
56 //This register is programmed to set the timer period for the SCL clock and assign the SCL clock to standard mode
57 #define I2C_O_CTPR 0x00000110U
58 
59 //Controller configuration register
60 #define I2C_O_CCR 0x00000114U
61 
62 //This register is used to determine the SCL and SDA signal status
63 #define I2C_O_CBMON 0x00000118U
64 
65 //This register consists of seven address bits that identify the I2C device on the I2C bus
66 #define I2C_O_TOAR 0x0000011CU
67 
68 //This register consists of seven address bits that identify the alternate address for the *I2C* device on the *I2C* bus
69 #define I2C_O_TOAR2 0x00000120U
70 
71 //Target control register
72 #define I2C_O_TCTR 0x00000124U
73 
74 //Target status register
75 #define I2C_O_TSR 0x00000128U
76 
77 //RX FIFO read data byte
78 #define I2C_O_RXDATA 0x0000012CU
79 
80 //Transmit data register
81 #define I2C_O_TXDATA 0x00000130U
82 
83 //This register enables the target to not acknowledge (NACK) for invalid data or command or acknowledge (ACK) for valid data or command
84 #define I2C_O_TACKCTL 0x00000134U
85 
86 //Target FIFO control
87 #define I2C_O_FIFOCTL 0x00000138U
88 
89 //FIFO status register
90 #define I2C_O_FIFOSR 0x0000013CU
91 
92 //Register for the selection of divider value to generate functional clock from SVT clock
93 #define I2C_O_FCLKDIV 0x00000140U
94 
95 //This register can be used by the software developer to control the behavior of the peripheral relative to the 'Core Halted' input
96 #define I2C_O_PDBGCTL 0x00000000U
97 
98 //Interrupt Mask
99 #define I2C_O_EVENT0_IMASK 0x00000004U
100 
101 //Raw interrupt status
102 #define I2C_O_EVENT0_RIS 0x00000008U
103 
104 //Masked interrupt status
105 #define I2C_O_EVENT0_MIS 0x0000000CU
106 
107 //Interrupt set
108 #define I2C_O_EVENT0_IEN 0x00000010U
109 
110 //Interrupt clear
111 #define I2C_O_EVENT0_IDIS 0x00000014U
112 
113 //Interrupt mask set
114 #define I2C_O_EVENT0_IMEN 0x00000018U
115 
116 //Interrupt clear
117 #define I2C_O_EVENT0_IMDIS 0x0000001CU
118 
119 //Event mode register
120 #define I2C_O_EVT_MODE 0x00000020U
121 
122 //This register identifies the peripheral and its exact version
123 #define I2C_O_DESC 0x00000024U
124 
125 //This register controls the bus clock to *I2C*
126 #define I2C_O_CLKCFG 0x00001000U
127 
128 
129 
130 /*-----------------------------------REGISTER------------------------------------
131  Register name: GFCTL
132  Offset name: I2C_O_GFCTL
133  Relative address: 0x100
134  Description: This register controls the glitch filter on the SCL and SDA lines
135  Default Value: 0x00000000
136 
137  Field: GFSEL
138  From..to bits: 0...3
139  DefaultValue: 0x0
140  Access type: read-write
141  Description: Glitch suppression pulse width
142 
143  This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks.
144 
145  ENUMs:
146  DIS: Bypass
147  CLK_1: 1 clock
148  CLK_2: 2 clocks
149  CLK_3: 3 clocks
150  CLK_4: 4 clocks
151  CLK_5: 5 clocks
152  CLK_6: 6 clocks
153  CLK_7: 7 clocks
154  CLK_8: 8 clocks
155  CLK_9: 10 clocks
156  CLK_A: 12 clocks
157  CLK_B: 14 clocks
158  CLK_C: 16 clocks
159  CLK_D: 20 clocks
160  CLK_E: 24 clocks
161  CLK_F: 31 clocks
162 */
163 #define I2C_GFCTL_GFSEL_W 4U
164 #define I2C_GFCTL_GFSEL_M 0x0000000FU
165 #define I2C_GFCTL_GFSEL_S 0U
166 #define I2C_GFCTL_GFSEL_DIS 0x00000000U
167 #define I2C_GFCTL_GFSEL_CLK_1 0x00000001U
168 #define I2C_GFCTL_GFSEL_CLK_2 0x00000002U
169 #define I2C_GFCTL_GFSEL_CLK_3 0x00000003U
170 #define I2C_GFCTL_GFSEL_CLK_4 0x00000004U
171 #define I2C_GFCTL_GFSEL_CLK_5 0x00000005U
172 #define I2C_GFCTL_GFSEL_CLK_6 0x00000006U
173 #define I2C_GFCTL_GFSEL_CLK_7 0x00000007U
174 #define I2C_GFCTL_GFSEL_CLK_8 0x00000008U
175 #define I2C_GFCTL_GFSEL_CLK_9 0x00000009U
176 #define I2C_GFCTL_GFSEL_CLK_A 0x0000000AU
177 #define I2C_GFCTL_GFSEL_CLK_B 0x0000000BU
178 #define I2C_GFCTL_GFSEL_CLK_C 0x0000000CU
179 #define I2C_GFCTL_GFSEL_CLK_D 0x0000000DU
180 #define I2C_GFCTL_GFSEL_CLK_E 0x0000000EU
181 #define I2C_GFCTL_GFSEL_CLK_F 0x0000000FU
182 
183 
184 /*-----------------------------------REGISTER------------------------------------
185  Register name: CSA
186  Offset name: I2C_O_CSA
187  Relative address: 0x104
188  Description: Controller target address register
189  Default Value: 0x00000000
190 
191  Field: DIR
192  From..to bits: 0...0
193  DefaultValue: 0x0
194  Access type: read-write
195  Description: This field specifies if the next controller operation is a Receive or Transmit
196 
197  ENUMs:
198  TRANSMIT: The controller is in transmit mode.
199  RECEIVE: The controller is in receive mode.
200 */
201 #define I2C_CSA_DIR 0x00000001U
202 #define I2C_CSA_DIR_M 0x00000001U
203 #define I2C_CSA_DIR_S 0U
204 #define I2C_CSA_DIR_TRANSMIT 0x00000000U
205 #define I2C_CSA_DIR_RECEIVE 0x00000001U
206 /*
207 
208  Field: TADDR
209  From..to bits: 1...10
210  DefaultValue: 0x0
211  Access type: read-write
212  Description: *I2C* Target Address This field specifies bits A9 through A0 of the target address.
213  In 7-field addressing mode as selected by MODE field, the top 3 bits are don't care
214 
215  ENUMs:
216  MINIMUM: Smallest value
217  MAXIMUM: Highest possible value
218 */
219 #define I2C_CSA_TADDR_W 10U
220 #define I2C_CSA_TADDR_M 0x000007FEU
221 #define I2C_CSA_TADDR_S 1U
222 #define I2C_CSA_TADDR_MINIMUM 0x00000000U
223 #define I2C_CSA_TADDR_MAXIMUM 0x000007FEU
224 /*
225 
226  Field: CMODE
227  From..to bits: 15...15
228  DefaultValue: 0x0
229  Access type: read-write
230  Description: This field selects the addressing mode(7-field/10-field) to be used in controller mode
231 
232  ENUMs:
233  SEVEN_BIT: 7-field addressing mode
234  TEN_BIT: 10-field addressing mode
235 */
236 #define I2C_CSA_CMODE 0x00008000U
237 #define I2C_CSA_CMODE_M 0x00008000U
238 #define I2C_CSA_CMODE_S 15U
239 #define I2C_CSA_CMODE_SEVEN_BIT 0x00000000U
240 #define I2C_CSA_CMODE_TEN_BIT 0x00008000U
241 
242 
243 /*-----------------------------------REGISTER------------------------------------
244  Register name: CCTR
245  Offset name: I2C_O_CCTR
246  Relative address: 0x108
247  Description: This control register configures the *I2C* controller operation. The START field generates the START or REPEATED START condition. The STOP field determines if the cycle stops at the end of the data cycle or continues to the next transfer cycle, which could be a repeated START. To generate a single transmit cycle, the *I2C* Controller Target Address [CSA] register is written with the desired address, the RS field is cleared, and this register is written with ACK = X (0 or 1), STOP = 1, START = 1, and RUN = 1 to perform the operation and stop. When the operation is completed (or aborted due an error), an byte transaction completed interrupt becomes active and the data may be read from the RXDATA register. When the I2C module operates in Controller receiver mode, a set ACK field causes the I2C bus controller to transmit an acknowledge automatically after each byte. This field must be cleared when the *I2C* bus controller requires no further data to be transmitted from the target transmitter.
248  Default Value: 0x00000000
249 
250  Field: BURSTRUN
251  From..to bits: 0...0
252  DefaultValue: 0x0
253  Access type: read-write
254  Description: Controller enable and start transaction
255 
256  ENUMs:
257  DIS: In standard mode, the controller will be unable to transmit or receive data.
258  EN: The controller will be able to transmit or receive data
259 */
260 #define I2C_CCTR_BURSTRUN 0x00000001U
261 #define I2C_CCTR_BURSTRUN_M 0x00000001U
262 #define I2C_CCTR_BURSTRUN_S 0U
263 #define I2C_CCTR_BURSTRUN_DIS 0x00000000U
264 #define I2C_CCTR_BURSTRUN_EN 0x00000001U
265 /*
266 
267  Field: START
268  From..to bits: 1...1
269  DefaultValue: 0x0
270  Access type: read-write
271  Description: Generate START
272 
273  ENUMs:
274  DIS_START: The controller does not generate the START condition.
275  EN_START: The controller generates the START or repeated START condition
276 */
277 #define I2C_CCTR_START 0x00000002U
278 #define I2C_CCTR_START_M 0x00000002U
279 #define I2C_CCTR_START_S 1U
280 #define I2C_CCTR_START_DIS_START 0x00000000U
281 #define I2C_CCTR_START_EN_START 0x00000002U
282 /*
283 
284  Field: STOP
285  From..to bits: 2...2
286  DefaultValue: 0x0
287  Access type: read-write
288  Description: Generate STOP
289 
290  ENUMs:
291  DIS_STOP: The controller does not generate the STOP condition.
292  EN_STOP: The controller generates the STOP condition
293 */
294 #define I2C_CCTR_STOP 0x00000004U
295 #define I2C_CCTR_STOP_M 0x00000004U
296 #define I2C_CCTR_STOP_S 2U
297 #define I2C_CCTR_STOP_DIS_STOP 0x00000000U
298 #define I2C_CCTR_STOP_EN_STOP 0x00000004U
299 /*
300 
301  Field: ACK
302  From..to bits: 3...3
303  DefaultValue: 0x0
304  Access type: read-write
305  Description: Data Acknowledge Enable. Configure this field to send the ACK or NACK.
306 
307  ENUMs:
308  DIS_ACK: The last received data byte of a transaction is not acknowledged automatically by the controller.
309  EN_ACK: The last received data byte of a transaction is acknowledged automatically by the controller.
310 */
311 #define I2C_CCTR_ACK 0x00000008U
312 #define I2C_CCTR_ACK_M 0x00000008U
313 #define I2C_CCTR_ACK_S 3U
314 #define I2C_CCTR_ACK_DIS_ACK 0x00000000U
315 #define I2C_CCTR_ACK_EN_ACK 0x00000008U
316 /*
317 
318  Field: CACKOEN
319  From..to bits: 4...4
320  DefaultValue: 0x0
321  Access type: read-write
322  Description: Controller ACK overrride enable
323 
324  ENUMs:
325  EN: When 1 and the controller is receiving data and the number of bytes indicated in MBLEN have been received, the state machine will generate an rxdone interrupt and wait at the start of the ACK for FW to indicate if an ACK or NACK should be sent. The ACK or NACK is selected by writing the [CCTR] register and setting ACK accordingly. The other fields in this register can also be written at this time to continue on with the transaction. If a NACK is sent the state machine will automatically send a Stop.
326  DIS: No special behavior
327 */
328 #define I2C_CCTR_CACKOEN 0x00000010U
329 #define I2C_CCTR_CACKOEN_M 0x00000010U
330 #define I2C_CCTR_CACKOEN_S 4U
331 #define I2C_CCTR_CACKOEN_EN 0x00000010U
332 #define I2C_CCTR_CACKOEN_DIS 0x00000000U
333 /*
334 
335  Field: RDONTXEMPTY
336  From..to bits: 5...5
337  DefaultValue: 0x0
338  Access type: read-write
339  Description: Read on TXFIFO empty
340 
341  ENUMs:
342  EN: When 1 the controller will transmit all bytes from the TX FIFO before continuing with the programmed Burst Run Read. If the [CSA.DIR] is not set to read, then this field is ignored. The Start must be set in the [CCTR] for proper *I2C* protocol. The controller will first send the Start Condition, *I2C* Address with R/W field set to write, before sending the bytes in the TX FIFO. When the TX FIFO is empty, the *I2C* transaction will continue as programmed in [CCTR] and [CSA] without sending a Stop Condition.
343  This is intended to be used to perform simple *I2C* command based reads transition that will complete after initiating them without having to get an interrupt to turn the bus around.
344  DIS: No special behaviour
345 */
346 #define I2C_CCTR_RDONTXEMPTY 0x00000020U
347 #define I2C_CCTR_RDONTXEMPTY_M 0x00000020U
348 #define I2C_CCTR_RDONTXEMPTY_S 5U
349 #define I2C_CCTR_RDONTXEMPTY_EN 0x00000020U
350 #define I2C_CCTR_RDONTXEMPTY_DIS 0x00000000U
351 /*
352 
353  Field: MBLEN
354  From..to bits: 16...27
355  DefaultValue: 0x0
356  Access type: read-write
357  Description: Transaction length
358  This field contains the programmed length of bytes of the Transaction.
359 
360  ENUMs:
361  MINIMUM: Smallest value
362  MAXIMUM: Highest possible value
363 */
364 #define I2C_CCTR_MBLEN_W 12U
365 #define I2C_CCTR_MBLEN_M 0x0FFF0000U
366 #define I2C_CCTR_MBLEN_S 16U
367 #define I2C_CCTR_MBLEN_MINIMUM 0x00000000U
368 #define I2C_CCTR_MBLEN_MAXIMUM 0x0FFF0000U
369 
370 
371 /*-----------------------------------REGISTER------------------------------------
372  Register name: CSR
373  Offset name: I2C_O_CSR
374  Relative address: 0x10C
375  Description: The status register indicates the state of the bus controller.
376  Default Value: 0x00000000
377 
378  Field: BUSY
379  From..to bits: 0...0
380  DefaultValue: 0x0
381  Access type: read-only
382  Description: Controller FSM busy
383 
384  The field is set during an ongoing transaction, so is set during the transmit/receive of the amount of data set in [CCTR.MBLEN] including START, RESTART, Address and STOP signal generation when required for the current transaction.
385 
386  ENUMs:
387  CLEAR: The controller is idle.
388  SET: The controller is busy.
389 */
390 #define I2C_CSR_BUSY 0x00000001U
391 #define I2C_CSR_BUSY_M 0x00000001U
392 #define I2C_CSR_BUSY_S 0U
393 #define I2C_CSR_BUSY_CLEAR 0x00000000U
394 #define I2C_CSR_BUSY_SET 0x00000001U
395 /*
396 
397  Field: ERR
398  From..to bits: 1...1
399  DefaultValue: 0x0
400  Access type: read-only
401  Description: Error
402 
403  The error can be from the target address not being acknowledged or the transmit data not being acknowledged.
404 
405  ENUMs:
406  CLEAR: No error was detected on the last operation.
407  SET: An error occurred on the last operation.
408 */
409 #define I2C_CSR_ERR 0x00000002U
410 #define I2C_CSR_ERR_M 0x00000002U
411 #define I2C_CSR_ERR_S 1U
412 #define I2C_CSR_ERR_CLEAR 0x00000000U
413 #define I2C_CSR_ERR_SET 0x00000002U
414 /*
415 
416  Field: ADRACK
417  From..to bits: 2...2
418  DefaultValue: 0x0
419  Access type: read-only
420  Description: Acknowledge address
421 
422  ENUMs:
423  CLEAR: The transmitted address was acknowledged
424  SET: The transmitted address was not acknowledged.
425 */
426 #define I2C_CSR_ADRACK 0x00000004U
427 #define I2C_CSR_ADRACK_M 0x00000004U
428 #define I2C_CSR_ADRACK_S 2U
429 #define I2C_CSR_ADRACK_CLEAR 0x00000000U
430 #define I2C_CSR_ADRACK_SET 0x00000004U
431 /*
432 
433  Field: DATACK
434  From..to bits: 3...3
435  DefaultValue: 0x0
436  Access type: read-only
437  Description: Acknowledge data
438 
439  ENUMs:
440  CLEAR: The transmitted data was acknowledged
441  SET: The transmitted data was not acknowledged.
442 */
443 #define I2C_CSR_DATACK 0x00000008U
444 #define I2C_CSR_DATACK_M 0x00000008U
445 #define I2C_CSR_DATACK_S 3U
446 #define I2C_CSR_DATACK_CLEAR 0x00000000U
447 #define I2C_CSR_DATACK_SET 0x00000008U
448 /*
449 
450  Field: ARBLST
451  From..to bits: 4...4
452  DefaultValue: 0x0
453  Access type: read-only
454  Description: Arbitration lost
455 
456  ENUMs:
457  CLEAR: The controller won arbitration.
458  SET: The controller lost arbitration.
459 */
460 #define I2C_CSR_ARBLST 0x00000010U
461 #define I2C_CSR_ARBLST_M 0x00000010U
462 #define I2C_CSR_ARBLST_S 4U
463 #define I2C_CSR_ARBLST_CLEAR 0x00000000U
464 #define I2C_CSR_ARBLST_SET 0x00000010U
465 /*
466 
467  Field: IDLE
468  From..to bits: 5...5
469  DefaultValue: 0x0
470  Access type: read-only
471  Description: *I2C* Idle
472 
473  ENUMs:
474  CLEAR: The controller is not idle.
475  SET: The controller is idle.
476 */
477 #define I2C_CSR_IDLE 0x00000020U
478 #define I2C_CSR_IDLE_M 0x00000020U
479 #define I2C_CSR_IDLE_S 5U
480 #define I2C_CSR_IDLE_CLEAR 0x00000000U
481 #define I2C_CSR_IDLE_SET 0x00000020U
482 /*
483 
484  Field: BUSBSY
485  From..to bits: 6...6
486  DefaultValue: 0x0
487  Access type: read-only
488  Description: Bus is busy
489  Controller state machine will wait until this field is cleared before starting a transaction. When first enabling the controller in multi controller environments, FW should wait for one I2C clock period after setting ACTIVE high before writing to the [CCTR] register to start the transaction so that if SCL goes low it will trigger the BUSBSY.
490 
491  ENUMs:
492  CLEAR: The bus is idle.
493  SET: This Status field is set on a START or when SCL goes low. It is cleared on a STOP, or when a SCL high bus busy timeout occurs and SCL and SDA are both high. This status is cleared when the ACTIVE field is low.
494 
495  Note that the controller state machine will wait until this field is cleared before starting a transaction. When first enabling the controller in multi controller environments, FW should wait for one I2C clock period after setting ACTIVE high before writing to the [CCTR] register to start the transaction so that if SCL goes low it will trigger the BUSBSY.
496 */
497 #define I2C_CSR_BUSBSY 0x00000040U
498 #define I2C_CSR_BUSBSY_M 0x00000040U
499 #define I2C_CSR_BUSBSY_S 6U
500 #define I2C_CSR_BUSBSY_CLEAR 0x00000000U
501 #define I2C_CSR_BUSBSY_SET 0x00000040U
502 /*
503 
504  Field: CBCNT
505  From..to bits: 16...27
506  DefaultValue: 0x0
507  Access type: read-only
508  Description: Controller Transaction Count
509  This field contains the current count-down value of the transaction.
510 
511  ENUMs:
512  MAXIMUM: Highest possible value
513  MINIMUM: Smallest value
514 */
515 #define I2C_CSR_CBCNT_W 12U
516 #define I2C_CSR_CBCNT_M 0x0FFF0000U
517 #define I2C_CSR_CBCNT_S 16U
518 #define I2C_CSR_CBCNT_MAXIMUM 0x0FFF0000U
519 #define I2C_CSR_CBCNT_MINIMUM 0x00000000U
520 
521 
522 /*-----------------------------------REGISTER------------------------------------
523  Register name: CTPR
524  Offset name: I2C_O_CTPR
525  Relative address: 0x110
526  Description: This register is programmed to set the timer period for the SCL clock and assign the SCL clock to standard mode.
527  Default Value: 0x00000001
528 
529  Field: TPR
530  From..to bits: 0...6
531  DefaultValue: 0x1
532  Access type: read-write
533  Description: Timer Period
534 
535  This field is used in the equation to configure SCL_PERIOD :
536 
537  SCL_PERIOD = (1 + TPR ) x (SCL_LP + SCL_HP ) x INT_CLK_PRD
538  where:
539 
540  SCL_PRD is the SCL line period (I2C clock).
541 
542  TPR is the Timer Period register value (range of 1 to 127).
543 
544  SCL_LP is the SCL Low period (fixed at 6).
545 
546  SCL_HP is the SCL High period (fixed at 4).
547 
548  INT_CLK_PRD is the functional clock period in ns.
549 
550  Note: INT_CLK_PRD is based on divider value selected in [FCLK_DIV:FCLK:DIV]
551 
552  ENUMs:
553  MINIMUM: Smallest value
554  MAXIMUM: Highest possible value
555 */
556 #define I2C_CTPR_TPR_W 7U
557 #define I2C_CTPR_TPR_M 0x0000007FU
558 #define I2C_CTPR_TPR_S 0U
559 #define I2C_CTPR_TPR_MINIMUM 0x00000000U
560 #define I2C_CTPR_TPR_MAXIMUM 0x0000007FU
561 
562 
563 /*-----------------------------------REGISTER------------------------------------
564  Register name: CCR
565  Offset name: I2C_O_CCR
566  Relative address: 0x114
567  Description: Controller configuration register
568  Default Value: 0x00000000
569 
570  Field: ACTIVE
571  From..to bits: 0...0
572  DefaultValue: 0x0
573  Access type: read-write
574  Description: Device Active After this field has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur.
575 
576  ENUMs:
577  DIS: Disables the *I2C* controller operation.
578  EN: Enables the *I2C* controller operation.
579 */
580 #define I2C_CCR_ACTIVE 0x00000001U
581 #define I2C_CCR_ACTIVE_M 0x00000001U
582 #define I2C_CCR_ACTIVE_S 0U
583 #define I2C_CCR_ACTIVE_DIS 0x00000000U
584 #define I2C_CCR_ACTIVE_EN 0x00000001U
585 /*
586 
587  Field: MCST
588  From..to bits: 1...1
589  DefaultValue: 0x0
590  Access type: read-write
591  Description: Multicontroller mode. In Multicontroller mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the *I2C* controller.
592 
593  ENUMs:
594  DIS: Disable Multicontroller mode.
595  EN: Enable Multicontroller mode.
596 */
597 #define I2C_CCR_MCST 0x00000002U
598 #define I2C_CCR_MCST_M 0x00000002U
599 #define I2C_CCR_MCST_S 1U
600 #define I2C_CCR_MCST_DIS 0x00000000U
601 #define I2C_CCR_MCST_EN 0x00000002U
602 /*
603 
604  Field: CLKSTRETCH
605  From..to bits: 2...2
606  DefaultValue: 0x0
607  Access type: read-write
608  Description: Clock Stretching. This field controls the support for clock stretching of the *I2C* bus.
609 
610  ENUMs:
611  DIS: Disables the clock stretching detection.
612  This can be disabled if no target on the bus does support clock streching, so that the maximum speed on the bus can be reached.
613  EN: Enables the clock stretching detection.
614  Enabling the clock strechting ensures compliance to the I2C standard but could limit the speed due the clock stretching.
615 */
616 #define I2C_CCR_CLKSTRETCH 0x00000004U
617 #define I2C_CCR_CLKSTRETCH_M 0x00000004U
618 #define I2C_CCR_CLKSTRETCH_S 2U
619 #define I2C_CCR_CLKSTRETCH_DIS 0x00000000U
620 #define I2C_CCR_CLKSTRETCH_EN 0x00000004U
621 /*
622 
623  Field: LPBK
624  From..to bits: 8...8
625  DefaultValue: 0x0
626  Access type: read-write
627  Description: I2C Loopback
628 
629  ENUMs:
630  DIS: Normal operation.
631  EN: The controller in a test mode loopback configuration.
632 */
633 #define I2C_CCR_LPBK 0x00000100U
634 #define I2C_CCR_LPBK_M 0x00000100U
635 #define I2C_CCR_LPBK_S 8U
636 #define I2C_CCR_LPBK_DIS 0x00000000U
637 #define I2C_CCR_LPBK_EN 0x00000100U
638 
639 
640 /*-----------------------------------REGISTER------------------------------------
641  Register name: CBMON
642  Offset name: I2C_O_CBMON
643  Relative address: 0x118
644  Description: This register is used to determine the SCL and SDA signal status.
645  Default Value: 0x00000003
646 
647  Field: SCL
648  From..to bits: 0...0
649  DefaultValue: 0x1
650  Access type: read-only
651  Description: SCL status
652 
653  ENUMs:
654  CLEAR: The SCL signal is low.
655  SET: The SCL signal is high
656  Note: During and right after reset, the SCL pin is in GPIO input mode without the internal pull enabled. For proper *I2C* operation, the user should have the external pull-up resistor in place.
657 */
658 #define I2C_CBMON_SCL 0x00000001U
659 #define I2C_CBMON_SCL_M 0x00000001U
660 #define I2C_CBMON_SCL_S 0U
661 #define I2C_CBMON_SCL_CLEAR 0x00000000U
662 #define I2C_CBMON_SCL_SET 0x00000001U
663 /*
664 
665  Field: SDA
666  From..to bits: 1...1
667  DefaultValue: 0x1
668  Access type: read-only
669  Description: SDA status
670 
671  ENUMs:
672  CLEAR: The SDA signal is low.
673  SET: The SDA signal is high.
674  Note: During and right after reset, the SDA pin is in GPIO input mode without the internal pull enabled. For proper *I2C* operation, the user should have the external pull-up resistor in place.
675 */
676 #define I2C_CBMON_SDA 0x00000002U
677 #define I2C_CBMON_SDA_M 0x00000002U
678 #define I2C_CBMON_SDA_S 1U
679 #define I2C_CBMON_SDA_CLEAR 0x00000000U
680 #define I2C_CBMON_SDA_SET 0x00000002U
681 
682 
683 /*-----------------------------------REGISTER------------------------------------
684  Register name: TOAR
685  Offset name: I2C_O_TOAR
686  Relative address: 0x11C
687  Description: This register consists of seven address bits that identify the I2C device on the I2C bus.
688  Default Value: 0x00004000
689 
690  Field: OAR
691  From..to bits: 0...9
692  DefaultValue: 0x0
693  Access type: read-write
694  Description: Target own address: This field specifies bits A9 through A0 of the target address.
695  In 7-field addressing mode as selected by [TOAR.MODE] field, the top 3 bits are don't care
696 
697  ENUMs:
698  MINIMUM: Smallest value
699  MAXIMUM: Highest possible value
700 */
701 #define I2C_TOAR_OAR_W 10U
702 #define I2C_TOAR_OAR_M 0x000003FFU
703 #define I2C_TOAR_OAR_S 0U
704 #define I2C_TOAR_OAR_MINIMUM 0x00000000U
705 #define I2C_TOAR_OAR_MAXIMUM 0x000003FFU
706 /*
707 
708  Field: OAREN
709  From..to bits: 14...14
710  DefaultValue: 0x1
711  Access type: read-write
712  Description: Target own address enable
713 
714  ENUMs:
715  EN: Enable OAR address
716  DIS: Disable OAR address
717 */
718 #define I2C_TOAR_OAREN 0x00004000U
719 #define I2C_TOAR_OAREN_M 0x00004000U
720 #define I2C_TOAR_OAREN_S 14U
721 #define I2C_TOAR_OAREN_EN 0x00004000U
722 #define I2C_TOAR_OAREN_DIS 0x00000000U
723 /*
724 
725  Field: MODE
726  From..to bits: 15...15
727  DefaultValue: 0x0
728  Access type: read-write
729  Description: This field selects the addressing mode(7-field/10-field) to be used in target mode.
730 
731  ENUMs:
732  SEVEN_BIT: Enable 7-field addressing
733  TEN_BIT: Enable 10-field addressing
734 */
735 #define I2C_TOAR_MODE 0x00008000U
736 #define I2C_TOAR_MODE_M 0x00008000U
737 #define I2C_TOAR_MODE_S 15U
738 #define I2C_TOAR_MODE_SEVEN_BIT 0x00000000U
739 #define I2C_TOAR_MODE_TEN_BIT 0x00008000U
740 
741 
742 /*-----------------------------------REGISTER------------------------------------
743  Register name: TOAR2
744  Offset name: I2C_O_TOAR2
745  Relative address: 0x120
746  Description: This register consists of seven address bits that identify the alternate address for the *I2C* device on the *I2C* bus.
747  Default Value: 0x00000000
748 
749  Field: OAR2
750  From..to bits: 0...6
751  DefaultValue: 0x0
752  Access type: read-write
753  Description: Target own address 2
754  This field specifies the alternate target own address.
755 
756  ENUMs:
757  MINIMUM: Smallest value
758  MAXIMUM: Highest possible value
759 */
760 #define I2C_TOAR2_OAR2_W 7U
761 #define I2C_TOAR2_OAR2_M 0x0000007FU
762 #define I2C_TOAR2_OAR2_S 0U
763 #define I2C_TOAR2_OAR2_MINIMUM 0x00000000U
764 #define I2C_TOAR2_OAR2_MAXIMUM 0x0000007FU
765 /*
766 
767  Field: OAR2EN
768  From..to bits: 7...7
769  DefaultValue: 0x0
770  Access type: read-write
771  Description: Target own address 2 enable
772 
773  ENUMs:
774  DIS: The alternate address is disabled.
775  EN: Enables the use of the alternate address in the OAR2 field.
776 */
777 #define I2C_TOAR2_OAR2EN 0x00000080U
778 #define I2C_TOAR2_OAR2EN_M 0x00000080U
779 #define I2C_TOAR2_OAR2EN_S 7U
780 #define I2C_TOAR2_OAR2EN_DIS 0x00000000U
781 #define I2C_TOAR2_OAR2EN_EN 0x00000080U
782 /*
783 
784  Field: OAR2_MASK
785  From..to bits: 16...22
786  DefaultValue: 0x0
787  Access type: read-write
788  Description: Target own address 2 mask: This field specifies bits A6 through A0 of the target address.
789  The bits with value '1' in this field will make the corresponding incoming address bits to match by default regardless of the value inside this field i.e. corresponding bits of this field are don't care.
790 
791  ENUMs:
792  MINIMUM: Minimum Value
793  MAXIMUM: Maximum Value
794 */
795 #define I2C_TOAR2_OAR2_MASK_W 7U
796 #define I2C_TOAR2_OAR2_MASK_M 0x007F0000U
797 #define I2C_TOAR2_OAR2_MASK_S 16U
798 #define I2C_TOAR2_OAR2_MASK_MINIMUM 0x00000000U
799 #define I2C_TOAR2_OAR2_MASK_MAXIMUM 0x007F0000U
800 
801 
802 /*-----------------------------------REGISTER------------------------------------
803  Register name: TCTR
804  Offset name: I2C_O_TCTR
805  Relative address: 0x124
806  Description: Target control register
807  Default Value: 0x00000004
808 
809  Field: ACTIVE
810  From..to bits: 0...0
811  DefaultValue: 0x0
812  Access type: read-write
813  Description: Device active. Setting this field enables the target functionality.
814 
815  ENUMs:
816  DIS: Disables the target operation.
817  EN: Enables the target operation.
818 */
819 #define I2C_TCTR_ACTIVE 0x00000001U
820 #define I2C_TCTR_ACTIVE_M 0x00000001U
821 #define I2C_TCTR_ACTIVE_S 0U
822 #define I2C_TCTR_ACTIVE_DIS 0x00000000U
823 #define I2C_TCTR_ACTIVE_EN 0x00000001U
824 /*
825 
826  Field: GENCALL
827  From..to bits: 1...1
828  DefaultValue: 0x0
829  Access type: read-write
830  Description: General call response enable.
831 
832  ENUMs:
833  DIS: Do not respond to a general call
834  EN: Respond to a general call
835 */
836 #define I2C_TCTR_GENCALL 0x00000002U
837 #define I2C_TCTR_GENCALL_M 0x00000002U
838 #define I2C_TCTR_GENCALL_S 1U
839 #define I2C_TCTR_GENCALL_DIS 0x00000000U
840 #define I2C_TCTR_GENCALL_EN 0x00000002U
841 /*
842 
843  Field: CLKSTRETCH
844  From..to bits: 2...2
845  DefaultValue: 0x1
846  Access type: read-write
847  Description: Target clock stretch enable
848 
849  ENUMs:
850  EN: Target clock stretching is enabled
851  DIS: Target clock stretching is disabled
852 */
853 #define I2C_TCTR_CLKSTRETCH 0x00000004U
854 #define I2C_TCTR_CLKSTRETCH_M 0x00000004U
855 #define I2C_TCTR_CLKSTRETCH_S 2U
856 #define I2C_TCTR_CLKSTRETCH_EN 0x00000004U
857 #define I2C_TCTR_CLKSTRETCH_DIS 0x00000000U
858 /*
859 
860  Field: TXEMPTYONTREQ
861  From..to bits: 3...3
862  DefaultValue: 0x0
863  Access type: read-write
864  Description: Tx Empty Interrupt on TREQ
865 
866  ENUMs:
867  EN: [RIS.STXEMPTY] will be set when the Target State Machine is in the TX_WAIT state which occurs when the TX FIFO is empty and the transaction is clock stretched waiting for the FIFO to receive data.
868  DIS: [RIS.TTXEMPTY] will be set when only the target TX FIFO is empty.
869  This allows the [RIS.TTXEMPTY] interrupt to be used to indicate that the bus is being clock stretched and that target TX data is required.
870 */
871 #define I2C_TCTR_TXEMPTYONTREQ 0x00000008U
872 #define I2C_TCTR_TXEMPTYONTREQ_M 0x00000008U
873 #define I2C_TCTR_TXEMPTYONTREQ_S 3U
874 #define I2C_TCTR_TXEMPTYONTREQ_EN 0x00000008U
875 #define I2C_TCTR_TXEMPTYONTREQ_DIS 0x00000000U
876 /*
877 
878  Field: TXTRIGXMODE
879  From..to bits: 4...4
880  DefaultValue: 0x0
881  Access type: read-write
882  Description: Tx trigger when target FSM is in TX mode
883 
884  ENUMs:
885  EN: [RIS.TXFIFOTRG] will be set when the Target TX FIFO has reached the trigger level AND the target state machine is in the as defined in the [TSR.TXMODE] field.
886  When cleared [RIS.TXFIFOTRG] will be set when the Target TX FIFO is at or above the trigger level.
887  This setting can be used to hold off the TX DMA until a transaction starts.
888  This allows the DMA to be configured when the *I2C* is idle but have it wait till the transaction starts to load the Target TX FIFO, so it can load from a memory buffer that might be changing over time.
889  DIS: No special behavior
890 */
891 #define I2C_TCTR_TXTRIGXMODE 0x00000010U
892 #define I2C_TCTR_TXTRIGXMODE_M 0x00000010U
893 #define I2C_TCTR_TXTRIGXMODE_S 4U
894 #define I2C_TCTR_TXTRIGXMODE_EN 0x00000010U
895 #define I2C_TCTR_TXTRIGXMODE_DIS 0x00000000U
896 /*
897 
898  Field: TXWAITSTALETXFIFO
899  From..to bits: 5...5
900  DefaultValue: 0x0
901  Access type: read-write
902  Description: Tx transfer waits when stale data in Tx FIFO.
903  This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with [TCTR:TXEMPTY_ON_TREQ] set to prevent the Target State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale.
904 
905  ENUMs:
906  EN: The TX FIFO empty signal to the Target State Machine will indicate that the TX FIFO is empty or that the TX FIFO data is stale. The TX FIFO data is determined to be stale when there is data in the TX FIFO when the target state machine leaves the [TSR.TXMODE] field. This can occur is a stop or timeout occur when there are bytes left in the TX FIFO.
907  DIS: The TX FIFO empty signal to the Target State Machine indicates that the TX FIFO is empty.
908 */
909 #define I2C_TCTR_TXWAITSTALETXFIFO 0x00000020U
910 #define I2C_TCTR_TXWAITSTALETXFIFO_M 0x00000020U
911 #define I2C_TCTR_TXWAITSTALETXFIFO_S 5U
912 #define I2C_TCTR_TXWAITSTALETXFIFO_EN 0x00000020U
913 #define I2C_TCTR_TXWAITSTALETXFIFO_DIS 0x00000000U
914 /*
915 
916  Field: RXFULLONRREQ
917  From..to bits: 6...6
918  DefaultValue: 0x0
919  Access type: read-write
920  Description: Rx full interrupt generated based on [TSR.RREQ] filed.
921 
922  ENUMs:
923  EN: [RIS.SRXFULL] will be set when the target state machine is in the RX_WAIT or RX_ACK_WAIT states which occurs when the transaction is clock stretched because the RX FIFO is full or the ACKOEN has been set and the state machine is waiting for FW to ACK/NACK the current byte.
924  DIS: [RIS.TRXFULL] will be set when only the Target RX FIFO is full.
925  This allows the [RIS.TRXFULL] interrupt to be used to indicate that the I2C bus is being clock stretched and that the FW must either read the RX FIFO or ACK/NACK the current RX byte.
926 */
927 #define I2C_TCTR_RXFULLONRREQ 0x00000040U
928 #define I2C_TCTR_RXFULLONRREQ_M 0x00000040U
929 #define I2C_TCTR_RXFULLONRREQ_S 6U
930 #define I2C_TCTR_RXFULLONRREQ_EN 0x00000040U
931 #define I2C_TCTR_RXFULLONRREQ_DIS 0x00000000U
932 /*
933 
934  Field: ENALRESPADR
935  From..to bits: 8...8
936  DefaultValue: 0x0
937  Access type: read-write
938  Description: Enable alert response address
939 
940  ENUMs:
941  EN: Alert response address of 7'h000_1100 is always matched by the target address match logic.
942  DIS: The alert response address is not matched.
943  NOTE: It may still be matched if programmed inside [TOAR]/[TOAR2]
944 */
945 #define I2C_TCTR_ENALRESPADR 0x00000100U
946 #define I2C_TCTR_ENALRESPADR_M 0x00000100U
947 #define I2C_TCTR_ENALRESPADR_S 8U
948 #define I2C_TCTR_ENALRESPADR_EN 0x00000100U
949 #define I2C_TCTR_ENALRESPADR_DIS 0x00000000U
950 /*
951 
952  Field: ENDEFDEVADR
953  From..to bits: 9...9
954  DefaultValue: 0x0
955  Access type: read-write
956  Description: Enable default device address
957 
958  ENUMs:
959  EN: When this field is 1, default device address of 7'h110_0001 is always matched by the target address match logic.
960  DIS: When this field is 0, the default device address is not matched. NOTE: it may still be matched if programmed inside TOAR/TOAR2.
961 */
962 #define I2C_TCTR_ENDEFDEVADR 0x00000200U
963 #define I2C_TCTR_ENDEFDEVADR_M 0x00000200U
964 #define I2C_TCTR_ENDEFDEVADR_S 9U
965 #define I2C_TCTR_ENDEFDEVADR_EN 0x00000200U
966 #define I2C_TCTR_ENDEFDEVADR_DIS 0x00000000U
967 
968 
969 /*-----------------------------------REGISTER------------------------------------
970  Register name: TSR
971  Offset name: I2C_O_TSR
972  Relative address: 0x128
973  Description: Target status register
974  Default Value: 0x00000000
975 
976  Field: RREQ
977  From..to bits: 0...0
978  DefaultValue: 0x0
979  Access type: read-only
980  Description: Receive Request
981 
982  ENUMs:
983  CLEAR: No outstanding receive data.
984  SET: The controller has outstanding receive data and is using clock stretching to delay the controller until the data has been read from the RXDATA FIFO (target RX FIFO is full).
985 */
986 #define I2C_TSR_RREQ 0x00000001U
987 #define I2C_TSR_RREQ_M 0x00000001U
988 #define I2C_TSR_RREQ_S 0U
989 #define I2C_TSR_RREQ_CLEAR 0x00000000U
990 #define I2C_TSR_RREQ_SET 0x00000001U
991 /*
992 
993  Field: TREQ
994  From..to bits: 1...1
995  DefaultValue: 0x0
996  Access type: read-only
997  Description: Transmit Request
998 
999  ENUMs:
1000  CLEAR: No outstanding transmit request.
1001  SET: The controller has been addressed as a target transmitter and is using clock stretching to delay the controller until data has been written to the TXDATA FIFO (Target TX FIFO is empty).
1002 */
1003 #define I2C_TSR_TREQ 0x00000002U
1004 #define I2C_TSR_TREQ_M 0x00000002U
1005 #define I2C_TSR_TREQ_S 1U
1006 #define I2C_TSR_TREQ_CLEAR 0x00000000U
1007 #define I2C_TSR_TREQ_SET 0x00000002U
1008 /*
1009 
1010  Field: RXMODE
1011  From..to bits: 2...2
1012  DefaultValue: 0x0
1013  Access type: read-only
1014  Description: Target FSM is in RX MODE
1015 
1016  ENUMs:
1017  SET: The target state machine is in the RX_DATA, RX_ACK, RX_WAIT, RX_ACK_WAIT or ADDR_ACK state with the bus direction set to write.
1018  CLEAR: The target state machine is not in the RX_DATA, RX_ACK, RX_WAIT, RX_ACK_WAIT or ADDR_ACK state with the bus direction set to write.
1019 */
1020 #define I2C_TSR_RXMODE 0x00000004U
1021 #define I2C_TSR_RXMODE_M 0x00000004U
1022 #define I2C_TSR_RXMODE_S 2U
1023 #define I2C_TSR_RXMODE_SET 0x00000004U
1024 #define I2C_TSR_RXMODE_CLEAR 0x00000000U
1025 /*
1026 
1027  Field: OAR2SEL
1028  From..to bits: 3...3
1029  DefaultValue: 0x0
1030  Access type: read-only
1031  Description: OAR2 address matched
1032  This field gets re-evaluated after every address comparison.
1033 
1034  ENUMs:
1035  CLEAR: Either the OAR2 address is not matched or the match is in legacy mode.
1036  SET: OAR2 address matched and acknowledged by the target.
1037 */
1038 #define I2C_TSR_OAR2SEL 0x00000008U
1039 #define I2C_TSR_OAR2SEL_M 0x00000008U
1040 #define I2C_TSR_OAR2SEL_S 3U
1041 #define I2C_TSR_OAR2SEL_CLEAR 0x00000000U
1042 #define I2C_TSR_OAR2SEL_SET 0x00000008U
1043 /*
1044 
1045  Field: BUSBSY
1046  From..to bits: 6...6
1047  DefaultValue: 0x0
1048  Access type: read-only
1049  Description: Bus is busy
1050 
1051  ENUMs:
1052  SET: Bus is busy. This is cleared on a timeout.
1053  CLEAR: Bus is not busy
1054 */
1055 #define I2C_TSR_BUSBSY 0x00000040U
1056 #define I2C_TSR_BUSBSY_M 0x00000040U
1057 #define I2C_TSR_BUSBSY_S 6U
1058 #define I2C_TSR_BUSBSY_SET 0x00000040U
1059 #define I2C_TSR_BUSBSY_CLEAR 0x00000000U
1060 /*
1061 
1062  Field: TXMODE
1063  From..to bits: 7...7
1064  DefaultValue: 0x0
1065  Access type: read-only
1066  Description: Target FSM is in TX MODE
1067 
1068  ENUMs:
1069  SET: The target state machine is in TX_DATA, TX_WAIT, TX_ACK or ADDR_ACK state with the bus direction set to read.
1070  CLEAR: The target state machine is not in TX_DATA, TX_WAIT, TX_ACK or ADDR_ACK state with the bus direction set to read.
1071 */
1072 #define I2C_TSR_TXMODE 0x00000080U
1073 #define I2C_TSR_TXMODE_M 0x00000080U
1074 #define I2C_TSR_TXMODE_S 7U
1075 #define I2C_TSR_TXMODE_SET 0x00000080U
1076 #define I2C_TSR_TXMODE_CLEAR 0x00000000U
1077 /*
1078 
1079  Field: STALETXFIFO
1080  From..to bits: 8...8
1081  DefaultValue: 0x0
1082  Access type: read-only
1083  Description: Stale TX FIFO
1084 
1085  ENUMs:
1086  SET: The TX FIFO is stale. This occurs when the TX FIFO was not emptied during the previous transaction.
1087  CLEAR: Tx FIFO is not stale
1088 */
1089 #define I2C_TSR_STALETXFIFO 0x00000100U
1090 #define I2C_TSR_STALETXFIFO_M 0x00000100U
1091 #define I2C_TSR_STALETXFIFO_S 8U
1092 #define I2C_TSR_STALETXFIFO_SET 0x00000100U
1093 #define I2C_TSR_STALETXFIFO_CLEAR 0x00000000U
1094 /*
1095 
1096  Field: ADDRMATCH
1097  From..to bits: 9...18
1098  DefaultValue: 0x0
1099  Access type: read-only
1100  Description: Indicates the address for which target address match happened
1101 
1102  ENUMs:
1103  MINIMUM: Minimum Value
1104  MAXIMUM: Maximum Value
1105 */
1106 #define I2C_TSR_ADDRMATCH_W 10U
1107 #define I2C_TSR_ADDRMATCH_M 0x0007FE00U
1108 #define I2C_TSR_ADDRMATCH_S 9U
1109 #define I2C_TSR_ADDRMATCH_MINIMUM 0x00000000U
1110 #define I2C_TSR_ADDRMATCH_MAXIMUM 0x0007FE00U
1111 
1112 
1113 /*-----------------------------------REGISTER------------------------------------
1114  Register name: RXDATA
1115  Offset name: I2C_O_RXDATA
1116  Relative address: 0x12C
1117  Description: RX FIFO read data byte
1118  This field contains the current byte being read in the RX FIFO stack.
1119  If the FIFO is disabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data can be retrieved by reading this register.
1120  Default Value: 0x00000000
1121 
1122  Field: VALUE
1123  From..to bits: 0...7
1124  DefaultValue: 0x0
1125  Access type: read-only
1126  Description: Received Data.
1127 
1128  This field contains the last received data.
1129 
1130  ENUMs:
1131  MINIMUM: Smallest value
1132  MAXIMUM: Highest possible value
1133 */
1134 #define I2C_RXDATA_VALUE_W 8U
1135 #define I2C_RXDATA_VALUE_M 0x000000FFU
1136 #define I2C_RXDATA_VALUE_S 0U
1137 #define I2C_RXDATA_VALUE_MINIMUM 0x00000000U
1138 #define I2C_RXDATA_VALUE_MAXIMUM 0x000000FFU
1139 
1140 
1141 /*-----------------------------------REGISTER------------------------------------
1142  Register name: TXDATA
1143  Offset name: I2C_O_TXDATA
1144  Relative address: 0x130
1145  Description: Transmit data register.
1146  This register is the transmit data register (the interface to the FIFOs). For transmitted data, if the FIFO is enabled, data written to this location is pushed onto the transmit FIFO. If the FIFO is disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO).
1147  Default Value: 0x00000000
1148 
1149  Field: VALUE
1150  From..to bits: 0...7
1151  DefaultValue: 0x0
1152  Access type: read-write
1153  Description: Transmit data
1154  This byte contains the data to be transferred during the next transaction.
1155 
1156  ENUMs:
1157  MINIMUM: Smallest value
1158  MAXIMUM: Highest possible value
1159 */
1160 #define I2C_TXDATA_VALUE_W 8U
1161 #define I2C_TXDATA_VALUE_M 0x000000FFU
1162 #define I2C_TXDATA_VALUE_S 0U
1163 #define I2C_TXDATA_VALUE_MINIMUM 0x00000000U
1164 #define I2C_TXDATA_VALUE_MAXIMUM 0x000000FFU
1165 
1166 
1167 /*-----------------------------------REGISTER------------------------------------
1168  Register name: TACKCTL
1169  Offset name: I2C_O_TACKCTL
1170  Relative address: 0x134
1171  Description: This register enables the target to not acknowledge (NACK) for invalid data or command or acknowledge (ACK) for valid data or command. The *I2C* clock is pulled low after the last data field until this register is written.
1172  Default Value: 0x00000000
1173 
1174  Field: ACKOEN
1175  From..to bits: 0...0
1176  DefaultValue: 0x0
1177  Access type: read-write
1178  Description: Target ACK override enable
1179 
1180  ENUMs:
1181  DIS: A response in not provided.
1182  EN: An ACK or NACK is sent according to the value written to the ACKOVAL field.
1183 */
1184 #define I2C_TACKCTL_ACKOEN 0x00000001U
1185 #define I2C_TACKCTL_ACKOEN_M 0x00000001U
1186 #define I2C_TACKCTL_ACKOEN_S 0U
1187 #define I2C_TACKCTL_ACKOEN_DIS 0x00000000U
1188 #define I2C_TACKCTL_ACKOEN_EN 0x00000001U
1189 /*
1190 
1191  Field: ACKOVAL
1192  From..to bits: 1...1
1193  DefaultValue: 0x0
1194  Access type: read-write
1195  Description: Target ACK override Value
1196 
1197  Note: For general call this field will be ignored if set to NACK and target continues to receive data.
1198 
1199  ENUMs:
1200  DIS: An ACK is sent indicating valid data or command.
1201  EN: A NACK is sent indicating invalid data or command.
1202 */
1203 #define I2C_TACKCTL_ACKOVAL 0x00000002U
1204 #define I2C_TACKCTL_ACKOVAL_M 0x00000002U
1205 #define I2C_TACKCTL_ACKOVAL_S 1U
1206 #define I2C_TACKCTL_ACKOVAL_DIS 0x00000000U
1207 #define I2C_TACKCTL_ACKOVAL_EN 0x00000002U
1208 /*
1209 
1210  Field: ACKOENONSTART
1211  From..to bits: 2...2
1212  DefaultValue: 0x0
1213  Access type: read-write
1214  Description: When set this field will automatically turn on the target ACKOEN field following a start condition.
1215 
1216  ENUMs:
1217  EN: When set this field will automatically turn on the Target ACKOEN field following a start condition.
1218  DIS: No special behavior
1219 */
1220 #define I2C_TACKCTL_ACKOENONSTART 0x00000004U
1221 #define I2C_TACKCTL_ACKOENONSTART_M 0x00000004U
1222 #define I2C_TACKCTL_ACKOENONSTART_S 2U
1223 #define I2C_TACKCTL_ACKOENONSTART_EN 0x00000004U
1224 #define I2C_TACKCTL_ACKOENONSTART_DIS 0x00000000U
1225 
1226 
1227 /*-----------------------------------REGISTER------------------------------------
1228  Register name: FIFOCTL
1229  Offset name: I2C_O_FIFOCTL
1230  Relative address: 0x138
1231  Description: Target FIFO control
1232  Default Value: 0x00000000
1233 
1234  Field: TXTRIG
1235  From..to bits: 0...2
1236  DefaultValue: 0x0
1237  Access type: read-write
1238  Description: TX FIFO trigger
1239  Indicates at what fill level in the TX FIFO a trigger will be generated.
1240 
1241  ENUMs:
1242  EMPTY: Trigger when the TX FIFO is empty.
1243  LEVEL_1: Trigger when TX FIFO contains bigger or equal to 1 byte
1244  LEVEL_2: Trigger when TX FIFO contains bigger or equal to 2 byte
1245  LEVEL_3: Trigger when TX FIFO contains bigger or equal to 3 byte
1246  LEVEL_6: Trigger when TX FIFO contains bigger or equal to 6 byte
1247  LEVEL_4: Trigger when TX FIFO contains bigger or equal to 4 byte
1248  LEVEL_5: Trigger when TX FIFO contains bigger or equal to 5 byte
1249  LEVEL_7: Trigger when TX FIFO contains bigger or equal to 7 byte
1250 */
1251 #define I2C_FIFOCTL_TXTRIG_W 3U
1252 #define I2C_FIFOCTL_TXTRIG_M 0x00000007U
1253 #define I2C_FIFOCTL_TXTRIG_S 0U
1254 #define I2C_FIFOCTL_TXTRIG_EMPTY 0x00000000U
1255 #define I2C_FIFOCTL_TXTRIG_LEVEL_1 0x00000001U
1256 #define I2C_FIFOCTL_TXTRIG_LEVEL_2 0x00000002U
1257 #define I2C_FIFOCTL_TXTRIG_LEVEL_3 0x00000003U
1258 #define I2C_FIFOCTL_TXTRIG_LEVEL_6 0x00000006U
1259 #define I2C_FIFOCTL_TXTRIG_LEVEL_4 0x00000004U
1260 #define I2C_FIFOCTL_TXTRIG_LEVEL_5 0x00000005U
1261 #define I2C_FIFOCTL_TXTRIG_LEVEL_7 0x00000007U
1262 /*
1263 
1264  Field: TXFLUSH
1265  From..to bits: 7...7
1266  DefaultValue: 0x0
1267  Access type: read-write
1268  Description: TX FIFO flush
1269  Setting this field will flush the TX FIFO.
1270  Before resetting this field to stop flush the TXFIFOCNT should be checked to be 8 and indicating that the flush has completed.
1271 
1272  ENUMs:
1273  DIS: Do not flush FIFO
1274  EN: flush FIFO
1275 */
1276 #define I2C_FIFOCTL_TXFLUSH 0x00000080U
1277 #define I2C_FIFOCTL_TXFLUSH_M 0x00000080U
1278 #define I2C_FIFOCTL_TXFLUSH_S 7U
1279 #define I2C_FIFOCTL_TXFLUSH_DIS 0x00000000U
1280 #define I2C_FIFOCTL_TXFLUSH_EN 0x00000080U
1281 /*
1282 
1283  Field: RXTRIG
1284  From..to bits: 8...10
1285  DefaultValue: 0x0
1286  Access type: read-write
1287  Description: RX FIFO trigger
1288  Indicates at what fill level in the RX FIFO a trigger will be generated.
1289  Note: Programming this field to 0x0 has no effect since no data is
1290  present to transfer out of RX FIFO.
1291 
1292  ENUMs:
1293  LEVEL_1: Trigger when RX FIFO contains >= 1 byte
1294  LEVEL_2: Trigger when RX FIFO contains >= 2 byte
1295  LEVEL_3: Trigger when RX FIFO contains >= 3 byte
1296  LEVEL_4: Trigger when RX FIFO contains >= 4 byte
1297  LEVEL_5: Trigger when RX FIFO contains >= 5 byte
1298  LEVEL_6: Trigger when RX FIFO contains >= 6 byte
1299  LEVEL_7: Trigger when RX FIFO contains >= 7 byte
1300  LEVEL_8: Trigger when RX FIFO contains >= 8 byte
1301 */
1302 #define I2C_FIFOCTL_RXTRIG_W 3U
1303 #define I2C_FIFOCTL_RXTRIG_M 0x00000700U
1304 #define I2C_FIFOCTL_RXTRIG_S 8U
1305 #define I2C_FIFOCTL_RXTRIG_LEVEL_1 0x00000000U
1306 #define I2C_FIFOCTL_RXTRIG_LEVEL_2 0x00000100U
1307 #define I2C_FIFOCTL_RXTRIG_LEVEL_3 0x00000200U
1308 #define I2C_FIFOCTL_RXTRIG_LEVEL_4 0x00000300U
1309 #define I2C_FIFOCTL_RXTRIG_LEVEL_5 0x00000400U
1310 #define I2C_FIFOCTL_RXTRIG_LEVEL_6 0x00000500U
1311 #define I2C_FIFOCTL_RXTRIG_LEVEL_7 0x00000600U
1312 #define I2C_FIFOCTL_RXTRIG_LEVEL_8 0x00000700U
1313 /*
1314 
1315  Field: RXFLUSH
1316  From..to bits: 15...15
1317  DefaultValue: 0x0
1318  Access type: read-write
1319  Description: RX FIFO flush
1320  Setting this field will flush the RX FIFO.
1321  Before resetting this field to stop flush the [FIFOSR.RXFIFOCNT] should be checked to be 0 and indicating that the flush has completed.
1322 
1323  ENUMs:
1324  DIS: Do not flush FIFO
1325  EN: Flush FIFO
1326 */
1327 #define I2C_FIFOCTL_RXFLUSH 0x00008000U
1328 #define I2C_FIFOCTL_RXFLUSH_M 0x00008000U
1329 #define I2C_FIFOCTL_RXFLUSH_S 15U
1330 #define I2C_FIFOCTL_RXFLUSH_DIS 0x00000000U
1331 #define I2C_FIFOCTL_RXFLUSH_EN 0x00008000U
1332 
1333 
1334 /*-----------------------------------REGISTER------------------------------------
1335  Register name: FIFOSR
1336  Offset name: I2C_O_FIFOSR
1337  Relative address: 0x13C
1338  Description: FIFO status register
1339  Note: This register should only be read when BUSY is 0
1340  Default Value: 0x00000800
1341 
1342  Field: RXFIFOCNT
1343  From..to bits: 0...3
1344  DefaultValue: 0x0
1345  Access type: read-only
1346  Description: Number of bytes which could be read from the RX FIFO
1347 
1348  ENUMs:
1349  MINIMUM: Smallest value
1350  MAXIMUM: Highest possible value
1351 */
1352 #define I2C_FIFOSR_RXFIFOCNT_W 4U
1353 #define I2C_FIFOSR_RXFIFOCNT_M 0x0000000FU
1354 #define I2C_FIFOSR_RXFIFOCNT_S 0U
1355 #define I2C_FIFOSR_RXFIFOCNT_MINIMUM 0x00000000U
1356 #define I2C_FIFOSR_RXFIFOCNT_MAXIMUM 0x00000008U
1357 /*
1358 
1359  Field: RXFLUSH
1360  From..to bits: 7...7
1361  DefaultValue: 0x0
1362  Access type: read-only
1363  Description: RX FIFO flush
1364  When this field is set a flush operation for the RX FIFO is active. Clear the [FIFOCTL.RXFLUSH] field to stop.
1365 
1366  ENUMs:
1367  CLEAR: FIFO flush not active
1368  SET: FIFO flush active
1369 */
1370 #define I2C_FIFOSR_RXFLUSH 0x00000080U
1371 #define I2C_FIFOSR_RXFLUSH_M 0x00000080U
1372 #define I2C_FIFOSR_RXFLUSH_S 7U
1373 #define I2C_FIFOSR_RXFLUSH_CLEAR 0x00000000U
1374 #define I2C_FIFOSR_RXFLUSH_SET 0x00000080U
1375 /*
1376 
1377  Field: TXFIFOCNT
1378  From..to bits: 8...11
1379  DefaultValue: 0x8
1380  Access type: read-only
1381  Description: Number of bytes which could be put into the TX FIFO
1382 
1383  ENUMs:
1384  MINIMUM: Smallest value
1385  MAXIMUM: Highest possible value
1386 */
1387 #define I2C_FIFOSR_TXFIFOCNT_W 4U
1388 #define I2C_FIFOSR_TXFIFOCNT_M 0x00000F00U
1389 #define I2C_FIFOSR_TXFIFOCNT_S 8U
1390 #define I2C_FIFOSR_TXFIFOCNT_MINIMUM 0x00000000U
1391 #define I2C_FIFOSR_TXFIFOCNT_MAXIMUM 0x00000800U
1392 /*
1393 
1394  Field: TXFLUSH
1395  From..to bits: 15...15
1396  DefaultValue: 0x0
1397  Access type: read-only
1398  Description: TX FIFO flush
1399  When this field is set a flush operation for the TX FIFO is active. Clear [FIFOCTL.TXFLUSH] to stop.
1400 
1401  ENUMs:
1402  CLEAR: FIFO flush not active
1403  SET: FIFO flush active
1404 */
1405 #define I2C_FIFOSR_TXFLUSH 0x00008000U
1406 #define I2C_FIFOSR_TXFLUSH_M 0x00008000U
1407 #define I2C_FIFOSR_TXFLUSH_S 15U
1408 #define I2C_FIFOSR_TXFLUSH_CLEAR 0x00000000U
1409 #define I2C_FIFOSR_TXFLUSH_SET 0x00008000U
1410 
1411 
1412 /*-----------------------------------REGISTER------------------------------------
1413  Register name: FCLKDIV
1414  Offset name: I2C_O_FCLKDIV
1415  Relative address: 0x140
1416  Description: Register for the selection of divider value to generate functional clock from SVT clock
1417  Default Value: NA
1418 
1419  Field: FCLKDIV
1420  From..to bits: 0...3
1421  DefaultValue: NA
1422  Access type: read-write
1423  Description: Divider value selection
1424 
1425  ENUMs:
1426  BY_1: Divide by 1 = 80MHz
1427  BY_2: Divide by 2 = 40MHz
1428  BY_4: Divide by 4 = 20MHz
1429  BY_5: Divide by 5 = 16MHz
1430  BY_8: Divide by 8 = 10MHz
1431  BY_10: Divide by 10 = 8MHz
1432  BY_16: Divide by 16 = 5MHz
1433  BY_20: Divide by 20 = 4MHz
1434  BY_25: Divide by 25 = 3.2MHz
1435  BY_32: Divide by 32 = 2.5MHz
1436  BY_40: Divide by 40 = 2MHz
1437  BY_80: Divide by 80 = 1MHz
1438 */
1439 #define I2C_FCLKDIV_FCLKDIV_W 4U
1440 #define I2C_FCLKDIV_FCLKDIV_M 0x0000000FU
1441 #define I2C_FCLKDIV_FCLKDIV_S 0U
1442 #define I2C_FCLKDIV_FCLKDIV_BY_1 0x00000000U
1443 #define I2C_FCLKDIV_FCLKDIV_BY_2 0x00000001U
1444 #define I2C_FCLKDIV_FCLKDIV_BY_4 0x00000002U
1445 #define I2C_FCLKDIV_FCLKDIV_BY_5 0x00000003U
1446 #define I2C_FCLKDIV_FCLKDIV_BY_8 0x00000004U
1447 #define I2C_FCLKDIV_FCLKDIV_BY_10 0x00000005U
1448 #define I2C_FCLKDIV_FCLKDIV_BY_16 0x00000006U
1449 #define I2C_FCLKDIV_FCLKDIV_BY_20 0x00000007U
1450 #define I2C_FCLKDIV_FCLKDIV_BY_25 0x00000008U
1451 #define I2C_FCLKDIV_FCLKDIV_BY_32 0x00000009U
1452 #define I2C_FCLKDIV_FCLKDIV_BY_40 0x0000000AU
1453 #define I2C_FCLKDIV_FCLKDIV_BY_80 0x0000000BU
1454 
1455 
1456 /*-----------------------------------REGISTER------------------------------------
1457  Register name: PDBGCTL
1458  Offset name: I2C_O_PDBGCTL
1459  Relative address: 0x0
1460  Description: This register can be used by the software developer to control the behavior of the peripheral relative to the 'Core Halted' input
1461  Default Value: 0x00000001
1462 
1463  Field: FREE
1464  From..to bits: 0...0
1465  DefaultValue: 0x1
1466  Access type: read-write
1467  Description: Free run control
1468 
1469  ENUMs:
1470  DIS: The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted.
1471  EN: The peripheral ignores the state of the Core Halted input
1472 */
1473 #define I2C_PDBGCTL_FREE 0x00000001U
1474 #define I2C_PDBGCTL_FREE_M 0x00000001U
1475 #define I2C_PDBGCTL_FREE_S 0U
1476 #define I2C_PDBGCTL_FREE_DIS 0x00000000U
1477 #define I2C_PDBGCTL_FREE_EN 0x00000001U
1478 /*
1479 
1480  Field: SOFT
1481  From..to bits: 1...1
1482  DefaultValue: 0x0
1483  Access type: read-write
1484  Description: Soft halt boundary control. This function is only available, if FREE is set to 'STOP'
1485 
1486  ENUMs:
1487  DIS: The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted
1488  EN: The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption
1489 */
1490 #define I2C_PDBGCTL_SOFT 0x00000002U
1491 #define I2C_PDBGCTL_SOFT_M 0x00000002U
1492 #define I2C_PDBGCTL_SOFT_S 1U
1493 #define I2C_PDBGCTL_SOFT_DIS 0x00000000U
1494 #define I2C_PDBGCTL_SOFT_EN 0x00000002U
1495 
1496 
1497 /*-----------------------------------REGISTER------------------------------------
1498  Register name: EVENT0_IMASK
1499  Offset name: I2C_O_EVENT0_IMASK
1500  Relative address: 0x4
1501  Description: Interrupt Mask. If a field is set, then corresponding interrupt is masked. Un-masking the interrupt causes the raw interrupt to be visible in [RIS], as well as [MIS].
1502  Default Value: 0x00000000
1503 
1504  Field: CRXDONE
1505  From..to bits: 0...0
1506  DefaultValue: 0x0
1507  Access type: read-write
1508  Description: Controller receive transaction completed Interrupt
1509 
1510  ENUMs:
1511  EN: Set Interrrupt Mask
1512  DIS: Clear Interrupt Mask
1513 */
1514 #define I2C_EVENT0_IMASK_CRXDONE 0x00000001U
1515 #define I2C_EVENT0_IMASK_CRXDONE_M 0x00000001U
1516 #define I2C_EVENT0_IMASK_CRXDONE_S 0U
1517 #define I2C_EVENT0_IMASK_CRXDONE_EN 0x00000001U
1518 #define I2C_EVENT0_IMASK_CRXDONE_DIS 0x00000000U
1519 /*
1520 
1521  Field: CTXDONE
1522  From..to bits: 1...1
1523  DefaultValue: 0x0
1524  Access type: read-write
1525  Description: Controller transmit transaction completed Interrupt
1526 
1527  ENUMs:
1528  EN: Set Interrrupt Mask
1529  DIS: Clear Interrupt Mask
1530 */
1531 #define I2C_EVENT0_IMASK_CTXDONE 0x00000002U
1532 #define I2C_EVENT0_IMASK_CTXDONE_M 0x00000002U
1533 #define I2C_EVENT0_IMASK_CTXDONE_S 1U
1534 #define I2C_EVENT0_IMASK_CTXDONE_EN 0x00000002U
1535 #define I2C_EVENT0_IMASK_CTXDONE_DIS 0x00000000U
1536 /*
1537 
1538  Field: RXFIFOTRGC
1539  From..to bits: 2...2
1540  DefaultValue: 0x0
1541  Access type: read-write
1542  Description: Receive FIFO trigger in controller code
1543  Trigger when RX FIFO contains >= defined bytes
1544 
1545  ENUMs:
1546  EN: Set Interrrupt Mask
1547  DIS: Clear Interrupt Mask
1548 */
1549 #define I2C_EVENT0_IMASK_RXFIFOTRGC 0x00000004U
1550 #define I2C_EVENT0_IMASK_RXFIFOTRGC_M 0x00000004U
1551 #define I2C_EVENT0_IMASK_RXFIFOTRGC_S 2U
1552 #define I2C_EVENT0_IMASK_RXFIFOTRGC_EN 0x00000004U
1553 #define I2C_EVENT0_IMASK_RXFIFOTRGC_DIS 0x00000000U
1554 /*
1555 
1556  Field: TXFIFOTRGC
1557  From..to bits: 3...3
1558  DefaultValue: 0x0
1559  Access type: read-write
1560  Description: Transmit FIFO trigger in controller mode
1561  Trigger when TX FIFO contains <= defined bytes
1562 
1563  ENUMs:
1564  EN: Set Interrrupt Mask
1565  DIS: Clear Interrupt Mask
1566 */
1567 #define I2C_EVENT0_IMASK_TXFIFOTRGC 0x00000008U
1568 #define I2C_EVENT0_IMASK_TXFIFOTRGC_M 0x00000008U
1569 #define I2C_EVENT0_IMASK_TXFIFOTRGC_S 3U
1570 #define I2C_EVENT0_IMASK_TXFIFOTRGC_EN 0x00000008U
1571 #define I2C_EVENT0_IMASK_TXFIFOTRGC_DIS 0x00000000U
1572 /*
1573 
1574  Field: RXFIFOFULLC
1575  From..to bits: 4...4
1576  DefaultValue: 0x0
1577  Access type: read-write
1578  Description: RXFIFO full event in controller mode. This interrupt is set if an RX FIFO is full in controller mode.
1579 
1580  ENUMs:
1581  EN: Set Interrrupt Mask
1582  DIS: Clear Interrupt Mask
1583 */
1584 #define I2C_EVENT0_IMASK_RXFIFOFULLC 0x00000010U
1585 #define I2C_EVENT0_IMASK_RXFIFOFULLC_M 0x00000010U
1586 #define I2C_EVENT0_IMASK_RXFIFOFULLC_S 4U
1587 #define I2C_EVENT0_IMASK_RXFIFOFULLC_EN 0x00000010U
1588 #define I2C_EVENT0_IMASK_RXFIFOFULLC_DIS 0x00000000U
1589 /*
1590 
1591  Field: TXEMPTYC
1592  From..to bits: 5...5
1593  DefaultValue: 0x0
1594  Access type: read-write
1595  Description: TXFIFO empty interrupt in controller mode. This interrupt is set if all data in the TX FIFO in controller mode have been shifted out and the transmit goes into idle mode.
1596 
1597  ENUMs:
1598  EN: Set Interrrupt Mask
1599  DIS: Clear Interrupt Mask
1600 */
1601 #define I2C_EVENT0_IMASK_TXEMPTYC 0x00000020U
1602 #define I2C_EVENT0_IMASK_TXEMPTYC_M 0x00000020U
1603 #define I2C_EVENT0_IMASK_TXEMPTYC_S 5U
1604 #define I2C_EVENT0_IMASK_TXEMPTYC_EN 0x00000020U
1605 #define I2C_EVENT0_IMASK_TXEMPTYC_DIS 0x00000000U
1606 /*
1607 
1608  Field: CNACK
1609  From..to bits: 6...6
1610  DefaultValue: 0x0
1611  Access type: read-write
1612  Description: Address/Data NACK interrupt
1613 
1614  ENUMs:
1615  EN: Set Interrrupt Mask
1616  DIS: Clear Interrupt Mask
1617 */
1618 #define I2C_EVENT0_IMASK_CNACK 0x00000040U
1619 #define I2C_EVENT0_IMASK_CNACK_M 0x00000040U
1620 #define I2C_EVENT0_IMASK_CNACK_S 6U
1621 #define I2C_EVENT0_IMASK_CNACK_EN 0x00000040U
1622 #define I2C_EVENT0_IMASK_CNACK_DIS 0x00000000U
1623 /*
1624 
1625  Field: CSTART
1626  From..to bits: 7...7
1627  DefaultValue: 0x0
1628  Access type: read-write
1629  Description: START detection interrupt
1630 
1631  ENUMs:
1632  EN: Set Interrrupt Mask
1633  DIS: Clear Interrupt Mask
1634 */
1635 #define I2C_EVENT0_IMASK_CSTART 0x00000080U
1636 #define I2C_EVENT0_IMASK_CSTART_M 0x00000080U
1637 #define I2C_EVENT0_IMASK_CSTART_S 7U
1638 #define I2C_EVENT0_IMASK_CSTART_EN 0x00000080U
1639 #define I2C_EVENT0_IMASK_CSTART_DIS 0x00000000U
1640 /*
1641 
1642  Field: CSTOP
1643  From..to bits: 8...8
1644  DefaultValue: 0x0
1645  Access type: read-write
1646  Description: STOP detection interrupt
1647 
1648  ENUMs:
1649  EN: Set Interrrupt Mask
1650  DIS: Clear Interrupt Mask
1651 */
1652 #define I2C_EVENT0_IMASK_CSTOP 0x00000100U
1653 #define I2C_EVENT0_IMASK_CSTOP_M 0x00000100U
1654 #define I2C_EVENT0_IMASK_CSTOP_S 8U
1655 #define I2C_EVENT0_IMASK_CSTOP_EN 0x00000100U
1656 #define I2C_EVENT0_IMASK_CSTOP_DIS 0x00000000U
1657 /*
1658 
1659  Field: CARBLOST
1660  From..to bits: 9...9
1661  DefaultValue: 0x0
1662  Access type: read-write
1663  Description: Arbitration lost interrupt
1664 
1665  ENUMs:
1666  EN: Set Interrrupt Mask
1667  DIS: Clear Interrupt Mask
1668 */
1669 #define I2C_EVENT0_IMASK_CARBLOST 0x00000200U
1670 #define I2C_EVENT0_IMASK_CARBLOST_M 0x00000200U
1671 #define I2C_EVENT0_IMASK_CARBLOST_S 9U
1672 #define I2C_EVENT0_IMASK_CARBLOST_EN 0x00000200U
1673 #define I2C_EVENT0_IMASK_CARBLOST_DIS 0x00000000U
1674 /*
1675 
1676  Field: TRXDONE
1677  From..to bits: 16...16
1678  DefaultValue: 0x0
1679  Access type: read-write
1680  Description: Target receive data interrupt. Signals that a byte has been received
1681 
1682  ENUMs:
1683  EN: Set Interrrupt Mask
1684  DIS: Clear Interrupt Mask
1685 */
1686 #define I2C_EVENT0_IMASK_TRXDONE 0x00010000U
1687 #define I2C_EVENT0_IMASK_TRXDONE_M 0x00010000U
1688 #define I2C_EVENT0_IMASK_TRXDONE_S 16U
1689 #define I2C_EVENT0_IMASK_TRXDONE_EN 0x00010000U
1690 #define I2C_EVENT0_IMASK_TRXDONE_DIS 0x00000000U
1691 /*
1692 
1693  Field: TTXDONE
1694  From..to bits: 17...17
1695  DefaultValue: 0x0
1696  Access type: read-write
1697  Description: Target transmit transaction completed interrupt
1698 
1699  ENUMs:
1700  EN: Set Interrrupt Mask
1701  DIS: Clear Interrupt Mask
1702 */
1703 #define I2C_EVENT0_IMASK_TTXDONE 0x00020000U
1704 #define I2C_EVENT0_IMASK_TTXDONE_M 0x00020000U
1705 #define I2C_EVENT0_IMASK_TTXDONE_S 17U
1706 #define I2C_EVENT0_IMASK_TTXDONE_EN 0x00020000U
1707 #define I2C_EVENT0_IMASK_TTXDONE_DIS 0x00000000U
1708 /*
1709 
1710  Field: RXFIFOTRGMT
1711  From..to bits: 18...18
1712  DefaultValue: 0x0
1713  Access type: read-write
1714  Description: RX FIFO trigger in target mode
1715 
1716  ENUMs:
1717  EN: Set Interrrupt Mask
1718  DIS: Clear Interrupt Mask
1719 */
1720 #define I2C_EVENT0_IMASK_RXFIFOTRGMT 0x00040000U
1721 #define I2C_EVENT0_IMASK_RXFIFOTRGMT_M 0x00040000U
1722 #define I2C_EVENT0_IMASK_RXFIFOTRGMT_S 18U
1723 #define I2C_EVENT0_IMASK_RXFIFOTRGMT_EN 0x00040000U
1724 #define I2C_EVENT0_IMASK_RXFIFOTRGMT_DIS 0x00000000U
1725 /*
1726 
1727  Field: TXFIFOTRGT
1728  From..to bits: 19...19
1729  DefaultValue: 0x0
1730  Access type: read-write
1731  Description: TX FIFO trigger in target mode
1732 
1733  ENUMs:
1734  EN: Set Interrrupt Mask
1735  DIS: Clear Interrupt Mask
1736 */
1737 #define I2C_EVENT0_IMASK_TXFIFOTRGT 0x00080000U
1738 #define I2C_EVENT0_IMASK_TXFIFOTRGT_M 0x00080000U
1739 #define I2C_EVENT0_IMASK_TXFIFOTRGT_S 19U
1740 #define I2C_EVENT0_IMASK_TXFIFOTRGT_EN 0x00080000U
1741 #define I2C_EVENT0_IMASK_TXFIFOTRGT_DIS 0x00000000U
1742 /*
1743 
1744  Field: RXFIFOFULLT
1745  From..to bits: 20...20
1746  DefaultValue: 0x0
1747  Access type: read-write
1748  Description: RX FIFO full event. This interrupt is set if an target RX FIFO is full in target mode.
1749 
1750  ENUMs:
1751  EN: Set Interrrupt Mask
1752  DIS: Clear Interrupt Mask
1753 */
1754 #define I2C_EVENT0_IMASK_RXFIFOFULLT 0x00100000U
1755 #define I2C_EVENT0_IMASK_RXFIFOFULLT_M 0x00100000U
1756 #define I2C_EVENT0_IMASK_RXFIFOFULLT_S 20U
1757 #define I2C_EVENT0_IMASK_RXFIFOFULLT_EN 0x00100000U
1758 #define I2C_EVENT0_IMASK_RXFIFOFULLT_DIS 0x00000000U
1759 /*
1760 
1761  Field: TXEMPTYT
1762  From..to bits: 21...21
1763  DefaultValue: 0x0
1764  Access type: read-write
1765  Description: TX FIFO empty interrupt mask in target mode. This interrupt is set if all data in the Transmit FIFO in target mode have been shifted out and the transmit goes into idle mode.
1766 
1767  ENUMs:
1768  EN: Set Interrrupt Mask
1769  DIS: Clear Interrupt Mask
1770 */
1771 #define I2C_EVENT0_IMASK_TXEMPTYT 0x00200000U
1772 #define I2C_EVENT0_IMASK_TXEMPTYT_M 0x00200000U
1773 #define I2C_EVENT0_IMASK_TXEMPTYT_S 21U
1774 #define I2C_EVENT0_IMASK_TXEMPTYT_EN 0x00200000U
1775 #define I2C_EVENT0_IMASK_TXEMPTYT_DIS 0x00000000U
1776 /*
1777 
1778  Field: TSTART
1779  From..to bits: 22...22
1780  DefaultValue: 0x0
1781  Access type: read-write
1782  Description: Target start condition interrupt. Asserted when the received address matches the target address
1783 
1784  ENUMs:
1785  EN: Set Interrrupt Mask
1786  DIS: Clear Interrupt Mask
1787 */
1788 #define I2C_EVENT0_IMASK_TSTART 0x00400000U
1789 #define I2C_EVENT0_IMASK_TSTART_M 0x00400000U
1790 #define I2C_EVENT0_IMASK_TSTART_S 22U
1791 #define I2C_EVENT0_IMASK_TSTART_EN 0x00400000U
1792 #define I2C_EVENT0_IMASK_TSTART_DIS 0x00000000U
1793 /*
1794 
1795  Field: TSTOP
1796  From..to bits: 23...23
1797  DefaultValue: 0x0
1798  Access type: read-write
1799  Description: Stop condition interrupt
1800 
1801  ENUMs:
1802  EN: Set Interrrupt Mask
1803  DIS: Clear Interrupt Mask
1804 */
1805 #define I2C_EVENT0_IMASK_TSTOP 0x00800000U
1806 #define I2C_EVENT0_IMASK_TSTOP_M 0x00800000U
1807 #define I2C_EVENT0_IMASK_TSTOP_S 23U
1808 #define I2C_EVENT0_IMASK_TSTOP_EN 0x00800000U
1809 #define I2C_EVENT0_IMASK_TSTOP_DIS 0x00000000U
1810 /*
1811 
1812  Field: TGENCALL
1813  From..to bits: 24...24
1814  DefaultValue: 0x0
1815  Access type: read-write
1816  Description: General call interrupt
1817 
1818  ENUMs:
1819  EN: Set Interrrupt Mask
1820  DIS: Clear Interrupt Mask
1821 */
1822 #define I2C_EVENT0_IMASK_TGENCALL 0x01000000U
1823 #define I2C_EVENT0_IMASK_TGENCALL_M 0x01000000U
1824 #define I2C_EVENT0_IMASK_TGENCALL_S 24U
1825 #define I2C_EVENT0_IMASK_TGENCALL_EN 0x01000000U
1826 #define I2C_EVENT0_IMASK_TGENCALL_DIS 0x00000000U
1827 /*
1828 
1829  Field: TX_UNFL_T
1830  From..to bits: 25...25
1831  DefaultValue: 0x0
1832  Access type: read-write
1833  Description: TX FIFO underflow in target mode
1834 
1835  ENUMs:
1836  EN: Set Interrupt Mask
1837  DIS: Clear Interrupt Mask
1838 */
1839 #define I2C_EVENT0_IMASK_TX_UNFL_T 0x02000000U
1840 #define I2C_EVENT0_IMASK_TX_UNFL_T_M 0x02000000U
1841 #define I2C_EVENT0_IMASK_TX_UNFL_T_S 25U
1842 #define I2C_EVENT0_IMASK_TX_UNFL_T_EN 0x02000000U
1843 #define I2C_EVENT0_IMASK_TX_UNFL_T_DIS 0x00000000U
1844 /*
1845 
1846  Field: RX_OVFL_T
1847  From..to bits: 26...26
1848  DefaultValue: 0x0
1849  Access type: read-write
1850  Description: RX FIFO overflow in target mode
1851 
1852  ENUMs:
1853  EN: Set Interrupt Mask
1854  DIS: Clear Interrupt Mask
1855 */
1856 #define I2C_EVENT0_IMASK_RX_OVFL_T 0x04000000U
1857 #define I2C_EVENT0_IMASK_RX_OVFL_T_M 0x04000000U
1858 #define I2C_EVENT0_IMASK_RX_OVFL_T_S 26U
1859 #define I2C_EVENT0_IMASK_RX_OVFL_T_EN 0x04000000U
1860 #define I2C_EVENT0_IMASK_RX_OVFL_T_DIS 0x00000000U
1861 /*
1862 
1863  Field: TARBLOST
1864  From..to bits: 27...27
1865  DefaultValue: 0x0
1866  Access type: read-write
1867  Description: Target arbitration lost
1868 
1869  ENUMs:
1870  EN: Set Interrupt Mask
1871  DIS: Clear Interrupt Mask
1872 */
1873 #define I2C_EVENT0_IMASK_TARBLOST 0x08000000U
1874 #define I2C_EVENT0_IMASK_TARBLOST_M 0x08000000U
1875 #define I2C_EVENT0_IMASK_TARBLOST_S 27U
1876 #define I2C_EVENT0_IMASK_TARBLOST_EN 0x08000000U
1877 #define I2C_EVENT0_IMASK_TARBLOST_DIS 0x00000000U
1878 
1879 
1880 /*-----------------------------------REGISTER------------------------------------
1881  Register name: EVENT0_RIS
1882  Offset name: I2C_O_EVENT0_RIS
1883  Relative address: 0x8
1884  Description: Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the [ICLR] register field even if the corresponding [IMASK] field is not enabled.
1885  Default Value: 0x00000000
1886 
1887  Field: CRXDONE
1888  From..to bits: 0...0
1889  DefaultValue: 0x0
1890  Access type: read-only
1891  Description: Controller receive transaction completed interrupt
1892 
1893  ENUMs:
1894  SET: Interrupt occured
1895  CLR: Interrupt did not occur
1896 */
1897 #define I2C_EVENT0_RIS_CRXDONE 0x00000001U
1898 #define I2C_EVENT0_RIS_CRXDONE_M 0x00000001U
1899 #define I2C_EVENT0_RIS_CRXDONE_S 0U
1900 #define I2C_EVENT0_RIS_CRXDONE_SET 0x00000001U
1901 #define I2C_EVENT0_RIS_CRXDONE_CLR 0x00000000U
1902 /*
1903 
1904  Field: CTXDONE
1905  From..to bits: 1...1
1906  DefaultValue: 0x0
1907  Access type: read-only
1908  Description: Controller transmit transaction completed interrupt
1909 
1910  ENUMs:
1911  SET: Interrupt occured
1912  CLR: Interrupt did not occur
1913 */
1914 #define I2C_EVENT0_RIS_CTXDONE 0x00000002U
1915 #define I2C_EVENT0_RIS_CTXDONE_M 0x00000002U
1916 #define I2C_EVENT0_RIS_CTXDONE_S 1U
1917 #define I2C_EVENT0_RIS_CTXDONE_SET 0x00000002U
1918 #define I2C_EVENT0_RIS_CTXDONE_CLR 0x00000000U
1919 /*
1920 
1921  Field: RXFIFOTRGC
1922  From..to bits: 2...2
1923  DefaultValue: 0x0
1924  Access type: read-only
1925  Description: RX FIFO trigger in controller mode
1926  Trigger when RX FIFO contains >= defined bytes
1927 
1928  ENUMs:
1929  SET: Interrupt occured
1930  CLR: Interrupt did not occur
1931 */
1932 #define I2C_EVENT0_RIS_RXFIFOTRGC 0x00000004U
1933 #define I2C_EVENT0_RIS_RXFIFOTRGC_M 0x00000004U
1934 #define I2C_EVENT0_RIS_RXFIFOTRGC_S 2U
1935 #define I2C_EVENT0_RIS_RXFIFOTRGC_SET 0x00000004U
1936 #define I2C_EVENT0_RIS_RXFIFOTRGC_CLR 0x00000000U
1937 /*
1938 
1939  Field: TXFIFOTRGC
1940  From..to bits: 3...3
1941  DefaultValue: 0x0
1942  Access type: read-only
1943  Description: TX FIFO Trigger in Transmit Mode
1944  Trigger when TX FIFO contains <= defined bytes
1945 
1946  ENUMs:
1947  SET: Interrupt occured
1948  CLR: Interrupt did not occur
1949 */
1950 #define I2C_EVENT0_RIS_TXFIFOTRGC 0x00000008U
1951 #define I2C_EVENT0_RIS_TXFIFOTRGC_M 0x00000008U
1952 #define I2C_EVENT0_RIS_TXFIFOTRGC_S 3U
1953 #define I2C_EVENT0_RIS_TXFIFOTRGC_SET 0x00000008U
1954 #define I2C_EVENT0_RIS_TXFIFOTRGC_CLR 0x00000000U
1955 /*
1956 
1957  Field: RXFIFOFULLC
1958  From..to bits: 4...4
1959  DefaultValue: 0x0
1960  Access type: read-only
1961  Description: RX FIFO full event in controller mode. This interrupt is set if an RX FIFO is full in controller mode.
1962 
1963  ENUMs:
1964  SET: Interrupt occured
1965  CLR: Interrupt did not occur
1966 */
1967 #define I2C_EVENT0_RIS_RXFIFOFULLC 0x00000010U
1968 #define I2C_EVENT0_RIS_RXFIFOFULLC_M 0x00000010U
1969 #define I2C_EVENT0_RIS_RXFIFOFULLC_S 4U
1970 #define I2C_EVENT0_RIS_RXFIFOFULLC_SET 0x00000010U
1971 #define I2C_EVENT0_RIS_RXFIFOFULLC_CLR 0x00000000U
1972 /*
1973 
1974  Field: TXEMPTYC
1975  From..to bits: 5...5
1976  DefaultValue: 0x0
1977  Access type: read-only
1978  Description: TX FIFO empty interrupt mask in controller mode. This interrupt is set if all data in the TX FIFO in controller mode have been shifted out and the transmit goes into idle mode.
1979 
1980  ENUMs:
1981  SET: Interrupt occured
1982  CLR: Interrupt did not occur
1983 */
1984 #define I2C_EVENT0_RIS_TXEMPTYC 0x00000020U
1985 #define I2C_EVENT0_RIS_TXEMPTYC_M 0x00000020U
1986 #define I2C_EVENT0_RIS_TXEMPTYC_S 5U
1987 #define I2C_EVENT0_RIS_TXEMPTYC_SET 0x00000020U
1988 #define I2C_EVENT0_RIS_TXEMPTYC_CLR 0x00000000U
1989 /*
1990 
1991  Field: CNACK
1992  From..to bits: 6...6
1993  DefaultValue: 0x0
1994  Access type: read-only
1995  Description: Address/Data NACK interrupt
1996 
1997  ENUMs:
1998  SET: Interrupt occured
1999  CLR: Interrupt did not occur
2000 */
2001 #define I2C_EVENT0_RIS_CNACK 0x00000040U
2002 #define I2C_EVENT0_RIS_CNACK_M 0x00000040U
2003 #define I2C_EVENT0_RIS_CNACK_S 6U
2004 #define I2C_EVENT0_RIS_CNACK_SET 0x00000040U
2005 #define I2C_EVENT0_RIS_CNACK_CLR 0x00000000U
2006 /*
2007 
2008  Field: CSTART
2009  From..to bits: 7...7
2010  DefaultValue: 0x0
2011  Access type: read-only
2012  Description: START detection interrupt
2013 
2014  ENUMs:
2015  SET: Interrupt occured
2016  CLR: Interrupt did not occur
2017 */
2018 #define I2C_EVENT0_RIS_CSTART 0x00000080U
2019 #define I2C_EVENT0_RIS_CSTART_M 0x00000080U
2020 #define I2C_EVENT0_RIS_CSTART_S 7U
2021 #define I2C_EVENT0_RIS_CSTART_SET 0x00000080U
2022 #define I2C_EVENT0_RIS_CSTART_CLR 0x00000000U
2023 /*
2024 
2025  Field: CSTOP
2026  From..to bits: 8...8
2027  DefaultValue: 0x0
2028  Access type: read-only
2029  Description: STOP detection interrupt
2030 
2031  ENUMs:
2032  SET: Interrupt occured
2033  CLR: Interrupt did not occur
2034 */
2035 #define I2C_EVENT0_RIS_CSTOP 0x00000100U
2036 #define I2C_EVENT0_RIS_CSTOP_M 0x00000100U
2037 #define I2C_EVENT0_RIS_CSTOP_S 8U
2038 #define I2C_EVENT0_RIS_CSTOP_SET 0x00000100U
2039 #define I2C_EVENT0_RIS_CSTOP_CLR 0x00000000U
2040 /*
2041 
2042  Field: CARBLOST
2043  From..to bits: 9...9
2044  DefaultValue: 0x0
2045  Access type: read-only
2046  Description: Arbitration lost interrupt
2047 
2048  ENUMs:
2049  SET: Interrupt occured
2050  CLR: Interrupt did not occur
2051 */
2052 #define I2C_EVENT0_RIS_CARBLOST 0x00000200U
2053 #define I2C_EVENT0_RIS_CARBLOST_M 0x00000200U
2054 #define I2C_EVENT0_RIS_CARBLOST_S 9U
2055 #define I2C_EVENT0_RIS_CARBLOST_SET 0x00000200U
2056 #define I2C_EVENT0_RIS_CARBLOST_CLR 0x00000000U
2057 /*
2058 
2059  Field: TRXDONE
2060  From..to bits: 16...16
2061  DefaultValue: 0x0
2062  Access type: read-only
2063  Description: Target receive data interrupt. Signals that a byte has been received
2064 
2065  ENUMs:
2066  SET: Interrupt occured
2067  CLR: Interrupt did not occur
2068 */
2069 #define I2C_EVENT0_RIS_TRXDONE 0x00010000U
2070 #define I2C_EVENT0_RIS_TRXDONE_M 0x00010000U
2071 #define I2C_EVENT0_RIS_TRXDONE_S 16U
2072 #define I2C_EVENT0_RIS_TRXDONE_SET 0x00010000U
2073 #define I2C_EVENT0_RIS_TRXDONE_CLR 0x00000000U
2074 /*
2075 
2076  Field: TTXDONE
2077  From..to bits: 17...17
2078  DefaultValue: 0x0
2079  Access type: read-only
2080  Description: Target transmit transaction completed interrupt
2081 
2082  ENUMs:
2083  SET: Interrupt occured
2084  CLR: Interrupt did not occur
2085 */
2086 #define I2C_EVENT0_RIS_TTXDONE 0x00020000U
2087 #define I2C_EVENT0_RIS_TTXDONE_M 0x00020000U
2088 #define I2C_EVENT0_RIS_TTXDONE_S 17U
2089 #define I2C_EVENT0_RIS_TTXDONE_SET 0x00020000U
2090 #define I2C_EVENT0_RIS_TTXDONE_CLR 0x00000000U
2091 /*
2092 
2093  Field: RXFIFOTRGT
2094  From..to bits: 18...18
2095  DefaultValue: 0x0
2096  Access type: read-only
2097  Description: RX FIFO trigger in target mode
2098 
2099  ENUMs:
2100  SET: Interrupt occured
2101  CLR: Interrupt did not occur
2102 */
2103 #define I2C_EVENT0_RIS_RXFIFOTRGT 0x00040000U
2104 #define I2C_EVENT0_RIS_RXFIFOTRGT_M 0x00040000U
2105 #define I2C_EVENT0_RIS_RXFIFOTRGT_S 18U
2106 #define I2C_EVENT0_RIS_RXFIFOTRGT_SET 0x00040000U
2107 #define I2C_EVENT0_RIS_RXFIFOTRGT_CLR 0x00000000U
2108 /*
2109 
2110  Field: TXFIFOTRGT
2111  From..to bits: 19...19
2112  DefaultValue: 0x0
2113  Access type: read-only
2114  Description: TX FIFO trigger in target mode
2115 
2116  ENUMs:
2117  SET: Interrupt occured
2118  CLR: Interrupt did not occur
2119 */
2120 #define I2C_EVENT0_RIS_TXFIFOTRGT 0x00080000U
2121 #define I2C_EVENT0_RIS_TXFIFOTRGT_M 0x00080000U
2122 #define I2C_EVENT0_RIS_TXFIFOTRGT_S 19U
2123 #define I2C_EVENT0_RIS_TXFIFOTRGT_SET 0x00080000U
2124 #define I2C_EVENT0_RIS_TXFIFOTRGT_CLR 0x00000000U
2125 /*
2126 
2127  Field: RXFIFOFULLT
2128  From..to bits: 20...20
2129  DefaultValue: 0x0
2130  Access type: read-only
2131  Description: RX FIFO full event in target mode. This interrupt is set if an RX FIFO is full in target mode.
2132 
2133  ENUMs:
2134  SET: Interrupt occured
2135  CLR: Interrupt did not occur
2136 */
2137 #define I2C_EVENT0_RIS_RXFIFOFULLT 0x00100000U
2138 #define I2C_EVENT0_RIS_RXFIFOFULLT_M 0x00100000U
2139 #define I2C_EVENT0_RIS_RXFIFOFULLT_S 20U
2140 #define I2C_EVENT0_RIS_RXFIFOFULLT_SET 0x00100000U
2141 #define I2C_EVENT0_RIS_RXFIFOFULLT_CLR 0x00000000U
2142 /*
2143 
2144  Field: TXEMPTYT
2145  From..to bits: 21...21
2146  DefaultValue: 0x0
2147  Access type: read-only
2148  Description: TX FIFO empty interrupt mask in target mode. This interrupt is set if all data in the TX FIFO in target mode have been shifted out and the transmit goes into idle mode.
2149 
2150  ENUMs:
2151  SET: Interrupt occured
2152  CLR: Interrupt did not occur
2153 */
2154 #define I2C_EVENT0_RIS_TXEMPTYT 0x00200000U
2155 #define I2C_EVENT0_RIS_TXEMPTYT_M 0x00200000U
2156 #define I2C_EVENT0_RIS_TXEMPTYT_S 21U
2157 #define I2C_EVENT0_RIS_TXEMPTYT_SET 0x00200000U
2158 #define I2C_EVENT0_RIS_TXEMPTYT_CLR 0x00000000U
2159 /*
2160 
2161  Field: TSTART
2162  From..to bits: 22...22
2163  DefaultValue: 0x0
2164  Access type: read-only
2165  Description: Target start condition interrupt.When the received address matches the target address, this interrupt asserted.
2166 
2167  ENUMs:
2168  SET: Interrupt occured
2169  CLR: Interrupt did not occur
2170 */
2171 #define I2C_EVENT0_RIS_TSTART 0x00400000U
2172 #define I2C_EVENT0_RIS_TSTART_M 0x00400000U
2173 #define I2C_EVENT0_RIS_TSTART_S 22U
2174 #define I2C_EVENT0_RIS_TSTART_SET 0x00400000U
2175 #define I2C_EVENT0_RIS_TSTART_CLR 0x00000000U
2176 /*
2177 
2178  Field: TSTOP
2179  From..to bits: 23...23
2180  DefaultValue: 0x0
2181  Access type: read-only
2182  Description: Stop condition interrupt
2183 
2184  ENUMs:
2185  SET: Interrupt occured
2186  CLR: Interrupt did not occur
2187 */
2188 #define I2C_EVENT0_RIS_TSTOP 0x00800000U
2189 #define I2C_EVENT0_RIS_TSTOP_M 0x00800000U
2190 #define I2C_EVENT0_RIS_TSTOP_S 23U
2191 #define I2C_EVENT0_RIS_TSTOP_SET 0x00800000U
2192 #define I2C_EVENT0_RIS_TSTOP_CLR 0x00000000U
2193 /*
2194 
2195  Field: TGENCALL
2196  From..to bits: 24...24
2197  DefaultValue: 0x0
2198  Access type: read-only
2199  Description: General call interrupt
2200 
2201  ENUMs:
2202  SET: Interrupt occured
2203  CLR: Interrupt did not occur
2204 */
2205 #define I2C_EVENT0_RIS_TGENCALL 0x01000000U
2206 #define I2C_EVENT0_RIS_TGENCALL_M 0x01000000U
2207 #define I2C_EVENT0_RIS_TGENCALL_S 24U
2208 #define I2C_EVENT0_RIS_TGENCALL_SET 0x01000000U
2209 #define I2C_EVENT0_RIS_TGENCALL_CLR 0x00000000U
2210 /*
2211 
2212  Field: TX_UNFL_T
2213  From..to bits: 25...25
2214  DefaultValue: 0x0
2215  Access type: read-only
2216  Description: TX FIFO underflow in target mode
2217 
2218  ENUMs:
2219  SET: Interrupt occured
2220  CLR: Interrupt did not occur
2221 */
2222 #define I2C_EVENT0_RIS_TX_UNFL_T 0x02000000U
2223 #define I2C_EVENT0_RIS_TX_UNFL_T_M 0x02000000U
2224 #define I2C_EVENT0_RIS_TX_UNFL_T_S 25U
2225 #define I2C_EVENT0_RIS_TX_UNFL_T_SET 0x02000000U
2226 #define I2C_EVENT0_RIS_TX_UNFL_T_CLR 0x00000000U
2227 /*
2228 
2229  Field: RX_OVFL_T
2230  From..to bits: 26...26
2231  DefaultValue: 0x0
2232  Access type: read-only
2233  Description: RX FIFO overflow in target mode
2234 
2235  ENUMs:
2236  SET: Interrupt Occured
2237  CLR: Interrupt did not occur
2238 */
2239 #define I2C_EVENT0_RIS_RX_OVFL_T 0x04000000U
2240 #define I2C_EVENT0_RIS_RX_OVFL_T_M 0x04000000U
2241 #define I2C_EVENT0_RIS_RX_OVFL_T_S 26U
2242 #define I2C_EVENT0_RIS_RX_OVFL_T_SET 0x04000000U
2243 #define I2C_EVENT0_RIS_RX_OVFL_T_CLR 0x00000000U
2244 /*
2245 
2246  Field: TARBLOST
2247  From..to bits: 27...27
2248  DefaultValue: 0x0
2249  Access type: read-only
2250  Description: Target arbitration lost
2251 
2252  ENUMs:
2253  SET: Interrupt occured
2254  CLR: Interrupt did not occur
2255 */
2256 #define I2C_EVENT0_RIS_TARBLOST 0x08000000U
2257 #define I2C_EVENT0_RIS_TARBLOST_M 0x08000000U
2258 #define I2C_EVENT0_RIS_TARBLOST_S 27U
2259 #define I2C_EVENT0_RIS_TARBLOST_SET 0x08000000U
2260 #define I2C_EVENT0_RIS_TARBLOST_CLR 0x00000000U
2261 
2262 
2263 /*-----------------------------------REGISTER------------------------------------
2264  Register name: EVENT0_MIS
2265  Offset name: I2C_O_EVENT0_MIS
2266  Relative address: 0xC
2267  Description: Masked interrupt status. This is an AND of the [IMASK] and [RIS] registers.
2268  Default Value: 0x00000000
2269 
2270  Field: CRXDONE
2271  From..to bits: 0...0
2272  DefaultValue: 0x0
2273  Access type: read-only
2274  Description: Controller receive data interrupt
2275 
2276  ENUMs:
2277  SET: Masked interrupt occured
2278  CLR: Masked Interrupt did not occur
2279 */
2280 #define I2C_EVENT0_MIS_CRXDONE 0x00000001U
2281 #define I2C_EVENT0_MIS_CRXDONE_M 0x00000001U
2282 #define I2C_EVENT0_MIS_CRXDONE_S 0U
2283 #define I2C_EVENT0_MIS_CRXDONE_SET 0x00000001U
2284 #define I2C_EVENT0_MIS_CRXDONE_CLR 0x00000000U
2285 /*
2286 
2287  Field: CTXDONE
2288  From..to bits: 1...1
2289  DefaultValue: 0x0
2290  Access type: read-only
2291  Description: Controller transmit transaction completed interrupt
2292 
2293  ENUMs:
2294  SET: Masked interrupt occured
2295  CLR: Masked Interrupt did not occur
2296 */
2297 #define I2C_EVENT0_MIS_CTXDONE 0x00000002U
2298 #define I2C_EVENT0_MIS_CTXDONE_M 0x00000002U
2299 #define I2C_EVENT0_MIS_CTXDONE_S 1U
2300 #define I2C_EVENT0_MIS_CTXDONE_SET 0x00000002U
2301 #define I2C_EVENT0_MIS_CTXDONE_CLR 0x00000000U
2302 /*
2303 
2304  Field: RXFIFOTRGC
2305  From..to bits: 2...2
2306  DefaultValue: 0x0
2307  Access type: read-only
2308  Description: RX FIFO trigger in controller mode
2309  Trigger when RX FIFO contains >= defined bytes
2310 
2311  ENUMs:
2312  SET: Masked interrupt occured
2313  CLR: Masked Interrupt did not occur
2314 */
2315 #define I2C_EVENT0_MIS_RXFIFOTRGC 0x00000004U
2316 #define I2C_EVENT0_MIS_RXFIFOTRGC_M 0x00000004U
2317 #define I2C_EVENT0_MIS_RXFIFOTRGC_S 2U
2318 #define I2C_EVENT0_MIS_RXFIFOTRGC_SET 0x00000004U
2319 #define I2C_EVENT0_MIS_RXFIFOTRGC_CLR 0x00000000U
2320 /*
2321 
2322  Field: TXFIFOTRGC
2323  From..to bits: 3...3
2324  DefaultValue: 0x0
2325  Access type: read-only
2326  Description: TX FIFO trigger in controller mode
2327  Trigger when TX FIFO contains <= defined bytes
2328 
2329  ENUMs:
2330  SET: Masked interrupt occured
2331  CLR: Masked Interrupt did not occur
2332 */
2333 #define I2C_EVENT0_MIS_TXFIFOTRGC 0x00000008U
2334 #define I2C_EVENT0_MIS_TXFIFOTRGC_M 0x00000008U
2335 #define I2C_EVENT0_MIS_TXFIFOTRGC_S 3U
2336 #define I2C_EVENT0_MIS_TXFIFOTRGC_SET 0x00000008U
2337 #define I2C_EVENT0_MIS_TXFIFOTRGC_CLR 0x00000000U
2338 /*
2339 
2340  Field: RXFIFOFULLC
2341  From..to bits: 4...4
2342  DefaultValue: 0x0
2343  Access type: read-only
2344  Description: RX FIFO full event. This interrupt is set if the RX FIFO is full in controller mode.
2345 
2346  ENUMs:
2347  SET: Masked interrupt occured
2348  CLR: Masked Interrupt did not occur
2349 */
2350 #define I2C_EVENT0_MIS_RXFIFOFULLC 0x00000010U
2351 #define I2C_EVENT0_MIS_RXFIFOFULLC_M 0x00000010U
2352 #define I2C_EVENT0_MIS_RXFIFOFULLC_S 4U
2353 #define I2C_EVENT0_MIS_RXFIFOFULLC_SET 0x00000010U
2354 #define I2C_EVENT0_MIS_RXFIFOFULLC_CLR 0x00000000U
2355 /*
2356 
2357  Field: TXEMPTYC
2358  From..to bits: 5...5
2359  DefaultValue: 0x0
2360  Access type: read-only
2361  Description: TX FIFO Empty interrupt mask in controller mode. This interrupt is set if all data in the TX FIFO in controller mode have been shifted out and the transmit goes into idle mode.
2362 
2363  ENUMs:
2364  SET: Masked interrupt occured
2365  CLR: Masked Interrupt did not occur
2366 */
2367 #define I2C_EVENT0_MIS_TXEMPTYC 0x00000020U
2368 #define I2C_EVENT0_MIS_TXEMPTYC_M 0x00000020U
2369 #define I2C_EVENT0_MIS_TXEMPTYC_S 5U
2370 #define I2C_EVENT0_MIS_TXEMPTYC_SET 0x00000020U
2371 #define I2C_EVENT0_MIS_TXEMPTYC_CLR 0x00000000U
2372 /*
2373 
2374  Field: CNACK
2375  From..to bits: 6...6
2376  DefaultValue: 0x0
2377  Access type: read-only
2378  Description: Address/Data NACK interrupt
2379 
2380  ENUMs:
2381  SET: Masked interrupt occured
2382  CLR: Masked Interrupt did not occur
2383 */
2384 #define I2C_EVENT0_MIS_CNACK 0x00000040U
2385 #define I2C_EVENT0_MIS_CNACK_M 0x00000040U
2386 #define I2C_EVENT0_MIS_CNACK_S 6U
2387 #define I2C_EVENT0_MIS_CNACK_SET 0x00000040U
2388 #define I2C_EVENT0_MIS_CNACK_CLR 0x00000000U
2389 /*
2390 
2391  Field: CSTART
2392  From..to bits: 7...7
2393  DefaultValue: 0x0
2394  Access type: read-only
2395  Description: START detection interrupt
2396 
2397  ENUMs:
2398  SET: Masked interrupt occured
2399  CLR: Masked Interrupt did not occur
2400 */
2401 #define I2C_EVENT0_MIS_CSTART 0x00000080U
2402 #define I2C_EVENT0_MIS_CSTART_M 0x00000080U
2403 #define I2C_EVENT0_MIS_CSTART_S 7U
2404 #define I2C_EVENT0_MIS_CSTART_SET 0x00000080U
2405 #define I2C_EVENT0_MIS_CSTART_CLR 0x00000000U
2406 /*
2407 
2408  Field: CSTOP
2409  From..to bits: 8...8
2410  DefaultValue: 0x0
2411  Access type: read-only
2412  Description: STOP detection interrupt
2413 
2414  ENUMs:
2415  SET: Masked interrupt occured
2416  CLR: Masked Interrupt did not occur
2417 */
2418 #define I2C_EVENT0_MIS_CSTOP 0x00000100U
2419 #define I2C_EVENT0_MIS_CSTOP_M 0x00000100U
2420 #define I2C_EVENT0_MIS_CSTOP_S 8U
2421 #define I2C_EVENT0_MIS_CSTOP_SET 0x00000100U
2422 #define I2C_EVENT0_MIS_CSTOP_CLR 0x00000000U
2423 /*
2424 
2425  Field: CARBLOST
2426  From..to bits: 9...9
2427  DefaultValue: 0x0
2428  Access type: read-only
2429  Description: Arbitration lost interrupt
2430 
2431  ENUMs:
2432  SET: Masked interrupt occured
2433  CLR: Masked Interrupt did not occur
2434 */
2435 #define I2C_EVENT0_MIS_CARBLOST 0x00000200U
2436 #define I2C_EVENT0_MIS_CARBLOST_M 0x00000200U
2437 #define I2C_EVENT0_MIS_CARBLOST_S 9U
2438 #define I2C_EVENT0_MIS_CARBLOST_SET 0x00000200U
2439 #define I2C_EVENT0_MIS_CARBLOST_CLR 0x00000000U
2440 /*
2441 
2442  Field: TRXDONE
2443  From..to bits: 16...16
2444  DefaultValue: 0x0
2445  Access type: read-only
2446  Description: Target receive data interrupt. Signals that a byte has been received
2447 
2448  ENUMs:
2449  SET: Masked interrupt occured
2450  CLR: Masked Interrupt did not occur
2451 */
2452 #define I2C_EVENT0_MIS_TRXDONE 0x00010000U
2453 #define I2C_EVENT0_MIS_TRXDONE_M 0x00010000U
2454 #define I2C_EVENT0_MIS_TRXDONE_S 16U
2455 #define I2C_EVENT0_MIS_TRXDONE_SET 0x00010000U
2456 #define I2C_EVENT0_MIS_TRXDONE_CLR 0x00000000U
2457 /*
2458 
2459  Field: TTXDONE
2460  From..to bits: 17...17
2461  DefaultValue: 0x0
2462  Access type: read-only
2463  Description: Target transmit transaction completed interrupt
2464 
2465  ENUMs:
2466  SET: Masked interrupt occured
2467  CLR: Masked Interrupt did not occur
2468 */
2469 #define I2C_EVENT0_MIS_TTXDONE 0x00020000U
2470 #define I2C_EVENT0_MIS_TTXDONE_M 0x00020000U
2471 #define I2C_EVENT0_MIS_TTXDONE_S 17U
2472 #define I2C_EVENT0_MIS_TTXDONE_SET 0x00020000U
2473 #define I2C_EVENT0_MIS_TTXDONE_CLR 0x00000000U
2474 /*
2475 
2476  Field: RXFIFOTRGT
2477  From..to bits: 18...18
2478  DefaultValue: 0x0
2479  Access type: read-only
2480  Description: Target RX FIFO trigger
2481 
2482  ENUMs:
2483  SET: Masked interrupt occured
2484  CLR: Masked Interrupt did not occur
2485 */
2486 #define I2C_EVENT0_MIS_RXFIFOTRGT 0x00040000U
2487 #define I2C_EVENT0_MIS_RXFIFOTRGT_M 0x00040000U
2488 #define I2C_EVENT0_MIS_RXFIFOTRGT_S 18U
2489 #define I2C_EVENT0_MIS_RXFIFOTRGT_SET 0x00040000U
2490 #define I2C_EVENT0_MIS_RXFIFOTRGT_CLR 0x00000000U
2491 /*
2492 
2493  Field: TXFIFOTRGT
2494  From..to bits: 19...19
2495  DefaultValue: 0x0
2496  Access type: read-only
2497  Description: TX FIFO trigger in target mode
2498 
2499  ENUMs:
2500  SET: Masked interrupt occured
2501  CLR: Masked Interrupt did not occur
2502 */
2503 #define I2C_EVENT0_MIS_TXFIFOTRGT 0x00080000U
2504 #define I2C_EVENT0_MIS_TXFIFOTRGT_M 0x00080000U
2505 #define I2C_EVENT0_MIS_TXFIFOTRGT_S 19U
2506 #define I2C_EVENT0_MIS_TXFIFOTRGT_SET 0x00080000U
2507 #define I2C_EVENT0_MIS_TXFIFOTRGT_CLR 0x00000000U
2508 /*
2509 
2510  Field: RXFIFOFULLT
2511  From..to bits: 20...20
2512  DefaultValue: 0x0
2513  Access type: read-only
2514  Description: RXFIFO full event in Target mode. This interrupt is set if an RX FIFO is full in target mode.
2515 
2516  ENUMs:
2517  SET: Masked interrupt occured
2518  CLR: Masked Interrupt did not occur
2519 */
2520 #define I2C_EVENT0_MIS_RXFIFOFULLT 0x00100000U
2521 #define I2C_EVENT0_MIS_RXFIFOFULLT_M 0x00100000U
2522 #define I2C_EVENT0_MIS_RXFIFOFULLT_S 20U
2523 #define I2C_EVENT0_MIS_RXFIFOFULLT_SET 0x00100000U
2524 #define I2C_EVENT0_MIS_RXFIFOFULLT_CLR 0x00000000U
2525 /*
2526 
2527  Field: TXEMPTYT
2528  From..to bits: 21...21
2529  DefaultValue: 0x0
2530  Access type: read-only
2531  Description: TX FIFO empty interrupt mask in target mode. This interrupt is set if all data in the TX FIFO in target mode have been shifted out and the transmit goes into idle mode.
2532 
2533  ENUMs:
2534  SET: Masked interrupt occured
2535  CLR: Masked Interrupt did not occur
2536 */
2537 #define I2C_EVENT0_MIS_TXEMPTYT 0x00200000U
2538 #define I2C_EVENT0_MIS_TXEMPTYT_M 0x00200000U
2539 #define I2C_EVENT0_MIS_TXEMPTYT_S 21U
2540 #define I2C_EVENT0_MIS_TXEMPTYT_SET 0x00200000U
2541 #define I2C_EVENT0_MIS_TXEMPTYT_CLR 0x00000000U
2542 /*
2543 
2544  Field: TSTART
2545  From..to bits: 22...22
2546  DefaultValue: 0x0
2547  Access type: read-only
2548  Description: Target start condition interrupt. Asserted when the received address matches the target address
2549 
2550  ENUMs:
2551  SET: Masked interrupt occured
2552  CLR: Masked Interrupt did not occur
2553 */
2554 #define I2C_EVENT0_MIS_TSTART 0x00400000U
2555 #define I2C_EVENT0_MIS_TSTART_M 0x00400000U
2556 #define I2C_EVENT0_MIS_TSTART_S 22U
2557 #define I2C_EVENT0_MIS_TSTART_SET 0x00400000U
2558 #define I2C_EVENT0_MIS_TSTART_CLR 0x00000000U
2559 /*
2560 
2561  Field: TSTOP
2562  From..to bits: 23...23
2563  DefaultValue: 0x0
2564  Access type: read-only
2565  Description: Target STOP detection interrupt
2566 
2567  ENUMs:
2568  SET: Masked interrupt occured
2569  CLR: Masked Interrupt did not occur
2570 */
2571 #define I2C_EVENT0_MIS_TSTOP 0x00800000U
2572 #define I2C_EVENT0_MIS_TSTOP_M 0x00800000U
2573 #define I2C_EVENT0_MIS_TSTOP_S 23U
2574 #define I2C_EVENT0_MIS_TSTOP_SET 0x00800000U
2575 #define I2C_EVENT0_MIS_TSTOP_CLR 0x00000000U
2576 /*
2577 
2578  Field: TGENCALL
2579  From..to bits: 24...24
2580  DefaultValue: 0x0
2581  Access type: read-only
2582  Description: General call interrupt
2583 
2584  ENUMs:
2585  SET: Masked interrupt occured
2586  CLR: Masked Interrupt did not occur
2587 */
2588 #define I2C_EVENT0_MIS_TGENCALL 0x01000000U
2589 #define I2C_EVENT0_MIS_TGENCALL_M 0x01000000U
2590 #define I2C_EVENT0_MIS_TGENCALL_S 24U
2591 #define I2C_EVENT0_MIS_TGENCALL_SET 0x01000000U
2592 #define I2C_EVENT0_MIS_TGENCALL_CLR 0x00000000U
2593 /*
2594 
2595  Field: TTX_UNFL
2596  From..to bits: 25...25
2597  DefaultValue: 0x0
2598  Access type: read-only
2599  Description: TX FIFO underflow in target mode
2600 
2601  ENUMs:
2602  SET: Masked interrupt occured
2603  CLR: Masked Interrupt did not occur
2604 */
2605 #define I2C_EVENT0_MIS_TTX_UNFL 0x02000000U
2606 #define I2C_EVENT0_MIS_TTX_UNFL_M 0x02000000U
2607 #define I2C_EVENT0_MIS_TTX_UNFL_S 25U
2608 #define I2C_EVENT0_MIS_TTX_UNFL_SET 0x02000000U
2609 #define I2C_EVENT0_MIS_TTX_UNFL_CLR 0x00000000U
2610 /*
2611 
2612  Field: TRX_OVFL
2613  From..to bits: 26...26
2614  DefaultValue: 0x0
2615  Access type: read-only
2616  Description: RX FIFO overflow in target mode
2617 
2618  ENUMs:
2619  SET: Masked interrupt occured
2620  CLR: Masked Interrupt did not occur
2621 */
2622 #define I2C_EVENT0_MIS_TRX_OVFL 0x04000000U
2623 #define I2C_EVENT0_MIS_TRX_OVFL_M 0x04000000U
2624 #define I2C_EVENT0_MIS_TRX_OVFL_S 26U
2625 #define I2C_EVENT0_MIS_TRX_OVFL_SET 0x04000000U
2626 #define I2C_EVENT0_MIS_TRX_OVFL_CLR 0x00000000U
2627 /*
2628 
2629  Field: TARBLOST
2630  From..to bits: 27...27
2631  DefaultValue: 0x0
2632  Access type: read-only
2633  Description: Target arbitration lost
2634 
2635  ENUMs:
2636  SET: Masked interrupt occured
2637  CLR: Clear interrupt mask
2638 */
2639 #define I2C_EVENT0_MIS_TARBLOST 0x08000000U
2640 #define I2C_EVENT0_MIS_TARBLOST_M 0x08000000U
2641 #define I2C_EVENT0_MIS_TARBLOST_S 27U
2642 #define I2C_EVENT0_MIS_TARBLOST_SET 0x08000000U
2643 #define I2C_EVENT0_MIS_TARBLOST_CLR 0x00000000U
2644 
2645 
2646 /*-----------------------------------REGISTER------------------------------------
2647  Register name: EVENT0_IEN
2648  Offset name: I2C_O_EVENT0_IEN
2649  Relative address: 0x10
2650  Description: Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a field in IEN will set the event and therefore the related RIS field also gets set. If the interrupt is enabled through the mask, then the corresponding MIS field is also set.
2651  Default Value: 0x00000000
2652 
2653  Field: CRXDONE
2654  From..to bits: 0...0
2655  DefaultValue: 0x0
2656  Access type: write-only
2657  Description: Controller receive data interrupt
2658  Signals that a byte has been received
2659 
2660  ENUMs:
2661  EN: Set Interrrupt
2662  DIS: Writing 0 has no effect
2663 */
2664 #define I2C_EVENT0_IEN_CRXDONE 0x00000001U
2665 #define I2C_EVENT0_IEN_CRXDONE_M 0x00000001U
2666 #define I2C_EVENT0_IEN_CRXDONE_S 0U
2667 #define I2C_EVENT0_IEN_CRXDONE_EN 0x00000001U
2668 #define I2C_EVENT0_IEN_CRXDONE_DIS 0x00000000U
2669 /*
2670 
2671  Field: CTXDONE
2672  From..to bits: 1...1
2673  DefaultValue: 0x0
2674  Access type: write-only
2675  Description: Controller transmit transaction completed interrupt
2676 
2677  ENUMs:
2678  EN: Set Interrrupt
2679  DIS: Writing 0 has no effect
2680 */
2681 #define I2C_EVENT0_IEN_CTXDONE 0x00000002U
2682 #define I2C_EVENT0_IEN_CTXDONE_M 0x00000002U
2683 #define I2C_EVENT0_IEN_CTXDONE_S 1U
2684 #define I2C_EVENT0_IEN_CTXDONE_EN 0x00000002U
2685 #define I2C_EVENT0_IEN_CTXDONE_DIS 0x00000000U
2686 /*
2687 
2688  Field: RXFIFOTRGC
2689  From..to bits: 2...2
2690  DefaultValue: 0x0
2691  Access type: write-only
2692  Description: RX FIFO trigger in controller mode
2693  Trigger when RX FIFO contains >= defined bytes
2694 
2695  ENUMs:
2696  EN: Set Interrrupt
2697  DIS: Writing 0 has no effect
2698 */
2699 #define I2C_EVENT0_IEN_RXFIFOTRGC 0x00000004U
2700 #define I2C_EVENT0_IEN_RXFIFOTRGC_M 0x00000004U
2701 #define I2C_EVENT0_IEN_RXFIFOTRGC_S 2U
2702 #define I2C_EVENT0_IEN_RXFIFOTRGC_EN 0x00000004U
2703 #define I2C_EVENT0_IEN_RXFIFOTRGC_DIS 0x00000000U
2704 /*
2705 
2706  Field: TXFIFOTRGC
2707  From..to bits: 3...3
2708  DefaultValue: 0x0
2709  Access type: write-only
2710  Description: TX FIFO trigger in controller mode
2711  Trigger when TX FIFO contains <= defined bytes
2712 
2713  ENUMs:
2714  EN: Set Interrrupt
2715  DIS: Writing 0 has no effect
2716 */
2717 #define I2C_EVENT0_IEN_TXFIFOTRGC 0x00000008U
2718 #define I2C_EVENT0_IEN_TXFIFOTRGC_M 0x00000008U
2719 #define I2C_EVENT0_IEN_TXFIFOTRGC_S 3U
2720 #define I2C_EVENT0_IEN_TXFIFOTRGC_EN 0x00000008U
2721 #define I2C_EVENT0_IEN_TXFIFOTRGC_DIS 0x00000000U
2722 /*
2723 
2724  Field: RXFIFOFULLC
2725  From..to bits: 4...4
2726  DefaultValue: 0x0
2727  Access type: write-only
2728  Description: RXFIFO full event in controller mode.
2729 
2730  ENUMs:
2731  EN: Set Interrrupt
2732  DIS: Writing 0 has no effect
2733 */
2734 #define I2C_EVENT0_IEN_RXFIFOFULLC 0x00000010U
2735 #define I2C_EVENT0_IEN_RXFIFOFULLC_M 0x00000010U
2736 #define I2C_EVENT0_IEN_RXFIFOFULLC_S 4U
2737 #define I2C_EVENT0_IEN_RXFIFOFULLC_EN 0x00000010U
2738 #define I2C_EVENT0_IEN_RXFIFOFULLC_DIS 0x00000000U
2739 /*
2740 
2741  Field: TXEMPTYC
2742  From..to bits: 5...5
2743  DefaultValue: 0x0
2744  Access type: write-only
2745  Description: TX FIFO empty interrupt mask in controller mode. This interrupt is set if all data in the TX FIFO in controller mode have been shifted out and the transmit goes into idle mode.
2746 
2747  ENUMs:
2748  EN: Set Interrrupt
2749  DIS: Writing 0 has no effect
2750 */
2751 #define I2C_EVENT0_IEN_TXEMPTYC 0x00000020U
2752 #define I2C_EVENT0_IEN_TXEMPTYC_M 0x00000020U
2753 #define I2C_EVENT0_IEN_TXEMPTYC_S 5U
2754 #define I2C_EVENT0_IEN_TXEMPTYC_EN 0x00000020U
2755 #define I2C_EVENT0_IEN_TXEMPTYC_DIS 0x00000000U
2756 /*
2757 
2758  Field: CNACK
2759  From..to bits: 6...6
2760  DefaultValue: 0x0
2761  Access type: write-only
2762  Description: Address/Data NACK interrupt
2763 
2764  ENUMs:
2765  EN: Set Interrrupt
2766  DIS: Writing 0 has no effect
2767 */
2768 #define I2C_EVENT0_IEN_CNACK 0x00000040U
2769 #define I2C_EVENT0_IEN_CNACK_M 0x00000040U
2770 #define I2C_EVENT0_IEN_CNACK_S 6U
2771 #define I2C_EVENT0_IEN_CNACK_EN 0x00000040U
2772 #define I2C_EVENT0_IEN_CNACK_DIS 0x00000000U
2773 /*
2774 
2775  Field: CSTART
2776  From..to bits: 7...7
2777  DefaultValue: 0x0
2778  Access type: write-only
2779  Description: START detection interrupt
2780 
2781  ENUMs:
2782  EN: Set Interrrupt
2783  DIS: Writing 0 has no effect
2784 */
2785 #define I2C_EVENT0_IEN_CSTART 0x00000080U
2786 #define I2C_EVENT0_IEN_CSTART_M 0x00000080U
2787 #define I2C_EVENT0_IEN_CSTART_S 7U
2788 #define I2C_EVENT0_IEN_CSTART_EN 0x00000080U
2789 #define I2C_EVENT0_IEN_CSTART_DIS 0x00000000U
2790 /*
2791 
2792  Field: CSTOP
2793  From..to bits: 8...8
2794  DefaultValue: 0x0
2795  Access type: write-only
2796  Description: STOP detection interrupt
2797 
2798  ENUMs:
2799  EN: Set Interrrupt
2800  DIS: Writing 0 has no effect
2801 */
2802 #define I2C_EVENT0_IEN_CSTOP 0x00000100U
2803 #define I2C_EVENT0_IEN_CSTOP_M 0x00000100U
2804 #define I2C_EVENT0_IEN_CSTOP_S 8U
2805 #define I2C_EVENT0_IEN_CSTOP_EN 0x00000100U
2806 #define I2C_EVENT0_IEN_CSTOP_DIS 0x00000000U
2807 /*
2808 
2809  Field: CARBLOST
2810  From..to bits: 9...9
2811  DefaultValue: 0x0
2812  Access type: write-only
2813  Description: Arbitration lost interrupt
2814 
2815  ENUMs:
2816  EN: Set Interrrupt
2817  DIS: Writing 0 has no effect
2818 */
2819 #define I2C_EVENT0_IEN_CARBLOST 0x00000200U
2820 #define I2C_EVENT0_IEN_CARBLOST_M 0x00000200U
2821 #define I2C_EVENT0_IEN_CARBLOST_S 9U
2822 #define I2C_EVENT0_IEN_CARBLOST_EN 0x00000200U
2823 #define I2C_EVENT0_IEN_CARBLOST_DIS 0x00000000U
2824 /*
2825 
2826  Field: TRXDONE
2827  From..to bits: 16...16
2828  DefaultValue: 0x0
2829  Access type: write-only
2830  Description: Target receive data interrupt. Signals that a byte has been received
2831 
2832  ENUMs:
2833  EN: Set Interrrupt
2834  DIS: Writing 0 has no effect
2835 */
2836 #define I2C_EVENT0_IEN_TRXDONE 0x00010000U
2837 #define I2C_EVENT0_IEN_TRXDONE_M 0x00010000U
2838 #define I2C_EVENT0_IEN_TRXDONE_S 16U
2839 #define I2C_EVENT0_IEN_TRXDONE_EN 0x00010000U
2840 #define I2C_EVENT0_IEN_TRXDONE_DIS 0x00000000U
2841 /*
2842 
2843  Field: TTXDONE
2844  From..to bits: 17...17
2845  DefaultValue: 0x0
2846  Access type: write-only
2847  Description: Target transmit transaction completed Interrupt
2848 
2849  ENUMs:
2850  EN: Set Interrrupt
2851  DIS: Writing 0 has no effect
2852 */
2853 #define I2C_EVENT0_IEN_TTXDONE 0x00020000U
2854 #define I2C_EVENT0_IEN_TTXDONE_M 0x00020000U
2855 #define I2C_EVENT0_IEN_TTXDONE_S 17U
2856 #define I2C_EVENT0_IEN_TTXDONE_EN 0x00020000U
2857 #define I2C_EVENT0_IEN_TTXDONE_DIS 0x00000000U
2858 /*
2859 
2860  Field: RXFIFOTRGT
2861  From..to bits: 18...18
2862  DefaultValue: 0x0
2863  Access type: write-only
2864  Description: RX FIFO trigger in target mode
2865 
2866  ENUMs:
2867  EN: Set Interrrupt
2868  DIS: Writing 0 has no effect
2869 */
2870 #define I2C_EVENT0_IEN_RXFIFOTRGT 0x00040000U
2871 #define I2C_EVENT0_IEN_RXFIFOTRGT_M 0x00040000U
2872 #define I2C_EVENT0_IEN_RXFIFOTRGT_S 18U
2873 #define I2C_EVENT0_IEN_RXFIFOTRGT_EN 0x00040000U
2874 #define I2C_EVENT0_IEN_RXFIFOTRGT_DIS 0x00000000U
2875 /*
2876 
2877  Field: TXFIFOTRGT
2878  From..to bits: 19...19
2879  DefaultValue: 0x0
2880  Access type: write-only
2881  Description: TX FIFO trigger in target mode
2882 
2883  ENUMs:
2884  EN: Set Interrrupt
2885  DIS: Writing 0 has no effect
2886 */
2887 #define I2C_EVENT0_IEN_TXFIFOTRGT 0x00080000U
2888 #define I2C_EVENT0_IEN_TXFIFOTRGT_M 0x00080000U
2889 #define I2C_EVENT0_IEN_TXFIFOTRGT_S 19U
2890 #define I2C_EVENT0_IEN_TXFIFOTRGT_EN 0x00080000U
2891 #define I2C_EVENT0_IEN_TXFIFOTRGT_DIS 0x00000000U
2892 /*
2893 
2894  Field: RXFIFOFULLT
2895  From..to bits: 20...20
2896  DefaultValue: 0x0
2897  Access type: write-only
2898  Description: RXFIFO full event in Target mode. This interrupt is set if an RX FIFO is full in Target mode.
2899 
2900  ENUMs:
2901  EN: Set Interrrupt
2902  DIS: Writing 0 has no effect
2903 */
2904 #define I2C_EVENT0_IEN_RXFIFOFULLT 0x00100000U
2905 #define I2C_EVENT0_IEN_RXFIFOFULLT_M 0x00100000U
2906 #define I2C_EVENT0_IEN_RXFIFOFULLT_S 20U
2907 #define I2C_EVENT0_IEN_RXFIFOFULLT_EN 0x00100000U
2908 #define I2C_EVENT0_IEN_RXFIFOFULLT_DIS 0x00000000U
2909 /*
2910 
2911  Field: TXEMPTYT
2912  From..to bits: 21...21
2913  DefaultValue: 0x0
2914  Access type: write-only
2915  Description: TX FIFO empty interrupt mask in target mode. This interrupt is set if all data in the TX FIFO in target mode have been shifted out and the transmit goes into idle mode.
2916 
2917  ENUMs:
2918  EN: Set Interrrupt
2919  DIS: Writing 0 has no effect
2920 */
2921 #define I2C_EVENT0_IEN_TXEMPTYT 0x00200000U
2922 #define I2C_EVENT0_IEN_TXEMPTYT_M 0x00200000U
2923 #define I2C_EVENT0_IEN_TXEMPTYT_S 21U
2924 #define I2C_EVENT0_IEN_TXEMPTYT_EN 0x00200000U
2925 #define I2C_EVENT0_IEN_TXEMPTYT_DIS 0x00000000U
2926 /*
2927 
2928  Field: TSTART
2929  From..to bits: 22...22
2930  DefaultValue: 0x0
2931  Access type: write-only
2932  Description: Target start condition interrupt. Asserted when the received address matches the target address
2933 
2934  ENUMs:
2935  EN: Set Interrrupt
2936  DIS: Writing 0 has no effect
2937 */
2938 #define I2C_EVENT0_IEN_TSTART 0x00400000U
2939 #define I2C_EVENT0_IEN_TSTART_M 0x00400000U
2940 #define I2C_EVENT0_IEN_TSTART_S 22U
2941 #define I2C_EVENT0_IEN_TSTART_EN 0x00400000U
2942 #define I2C_EVENT0_IEN_TSTART_DIS 0x00000000U
2943 /*
2944 
2945  Field: TSTOP
2946  From..to bits: 23...23
2947  DefaultValue: 0x0
2948  Access type: write-only
2949  Description: Stop condition interrupt
2950 
2951  ENUMs:
2952  EN: Set Interrrupt
2953  DIS: Writing 0 has no effect
2954 */
2955 #define I2C_EVENT0_IEN_TSTOP 0x00800000U
2956 #define I2C_EVENT0_IEN_TSTOP_M 0x00800000U
2957 #define I2C_EVENT0_IEN_TSTOP_S 23U
2958 #define I2C_EVENT0_IEN_TSTOP_EN 0x00800000U
2959 #define I2C_EVENT0_IEN_TSTOP_DIS 0x00000000U
2960 /*
2961 
2962  Field: TGENCALL
2963  From..to bits: 24...24
2964  DefaultValue: 0x0
2965  Access type: write-only
2966  Description: General call interrupt
2967 
2968  ENUMs:
2969  EN: Set Interrrupt
2970  DIS: Writing 0 has no effect
2971 */
2972 #define I2C_EVENT0_IEN_TGENCALL 0x01000000U
2973 #define I2C_EVENT0_IEN_TGENCALL_M 0x01000000U
2974 #define I2C_EVENT0_IEN_TGENCALL_S 24U
2975 #define I2C_EVENT0_IEN_TGENCALL_EN 0x01000000U
2976 #define I2C_EVENT0_IEN_TGENCALL_DIS 0x00000000U
2977 /*
2978 
2979  Field: TX_UNFL_T
2980  From..to bits: 25...25
2981  DefaultValue: 0x0
2982  Access type: write-only
2983  Description: TX FIFO underflow in target mode
2984 
2985  ENUMs:
2986  EN: Set interrupt
2987  DIS: Writing 0 has no effect
2988 */
2989 #define I2C_EVENT0_IEN_TX_UNFL_T 0x02000000U
2990 #define I2C_EVENT0_IEN_TX_UNFL_T_M 0x02000000U
2991 #define I2C_EVENT0_IEN_TX_UNFL_T_S 25U
2992 #define I2C_EVENT0_IEN_TX_UNFL_T_EN 0x02000000U
2993 #define I2C_EVENT0_IEN_TX_UNFL_T_DIS 0x00000000U
2994 /*
2995 
2996  Field: RX_OVFL_T
2997  From..to bits: 26...26
2998  DefaultValue: 0x0
2999  Access type: write-only
3000  Description: RX FIFO overflow in target mode
3001 
3002  ENUMs:
3003  EN: Set Interrrupt
3004  DIS: Writing 0 has no effect
3005 */
3006 #define I2C_EVENT0_IEN_RX_OVFL_T 0x04000000U
3007 #define I2C_EVENT0_IEN_RX_OVFL_T_M 0x04000000U
3008 #define I2C_EVENT0_IEN_RX_OVFL_T_S 26U
3009 #define I2C_EVENT0_IEN_RX_OVFL_T_EN 0x04000000U
3010 #define I2C_EVENT0_IEN_RX_OVFL_T_DIS 0x00000000U
3011 /*
3012 
3013  Field: TARBLOST
3014  From..to bits: 27...27
3015  DefaultValue: 0x0
3016  Access type: write-only
3017  Description: Target arbitration lost
3018 
3019  ENUMs:
3020  EN: Set Interrupt
3021  DIS: Writing 0 has no effect
3022 */
3023 #define I2C_EVENT0_IEN_TARBLOST 0x08000000U
3024 #define I2C_EVENT0_IEN_TARBLOST_M 0x08000000U
3025 #define I2C_EVENT0_IEN_TARBLOST_S 27U
3026 #define I2C_EVENT0_IEN_TARBLOST_EN 0x08000000U
3027 #define I2C_EVENT0_IEN_TARBLOST_DIS 0x00000000U
3028 
3029 
3030 /*-----------------------------------REGISTER------------------------------------
3031  Register name: EVENT0_IDIS
3032  Offset name: I2C_O_EVENT0_IDIS
3033  Relative address: 0x14
3034  Description: Interrupt clear. Write a 1 to clear corresponding Interrupt.
3035  Default Value: 0x00000000
3036 
3037  Field: CRXDONE
3038  From..to bits: 0...0
3039  DefaultValue: 0x0
3040  Access type: write-only
3041  Description: Controller receive data interrupt. Signals that a byte has been received
3042 
3043  ENUMs:
3044  EN: Clear Interrupt
3045  DIS: Writing 0 has no effect
3046 */
3047 #define I2C_EVENT0_IDIS_CRXDONE 0x00000001U
3048 #define I2C_EVENT0_IDIS_CRXDONE_M 0x00000001U
3049 #define I2C_EVENT0_IDIS_CRXDONE_S 0U
3050 #define I2C_EVENT0_IDIS_CRXDONE_EN 0x00000001U
3051 #define I2C_EVENT0_IDIS_CRXDONE_DIS 0x00000000U
3052 /*
3053 
3054  Field: CTXDONE
3055  From..to bits: 1...1
3056  DefaultValue: 0x0
3057  Access type: write-only
3058  Description: Controller transmit transaction completed interrupt
3059 
3060  ENUMs:
3061  EN: Clear Interrupt
3062  DIS: Writing 0 has no effect
3063 */
3064 #define I2C_EVENT0_IDIS_CTXDONE 0x00000002U
3065 #define I2C_EVENT0_IDIS_CTXDONE_M 0x00000002U
3066 #define I2C_EVENT0_IDIS_CTXDONE_S 1U
3067 #define I2C_EVENT0_IDIS_CTXDONE_EN 0x00000002U
3068 #define I2C_EVENT0_IDIS_CTXDONE_DIS 0x00000000U
3069 /*
3070 
3071  Field: RXFIFOTRGC
3072  From..to bits: 2...2
3073  DefaultValue: 0x0
3074  Access type: write-only
3075  Description: RX FIFO trigger in controller mode
3076  Trigger when RX FIFO contains >= defined bytes
3077 
3078  ENUMs:
3079  EN: Clear Interrupt
3080  DIS: Writing 0 has no effect
3081 */
3082 #define I2C_EVENT0_IDIS_RXFIFOTRGC 0x00000004U
3083 #define I2C_EVENT0_IDIS_RXFIFOTRGC_M 0x00000004U
3084 #define I2C_EVENT0_IDIS_RXFIFOTRGC_S 2U
3085 #define I2C_EVENT0_IDIS_RXFIFOTRGC_EN 0x00000004U
3086 #define I2C_EVENT0_IDIS_RXFIFOTRGC_DIS 0x00000000U
3087 /*
3088 
3089  Field: TXFIFOTRGC
3090  From..to bits: 3...3
3091  DefaultValue: 0x0
3092  Access type: write-only
3093  Description: TX FIFO trigger in controller mode
3094  Trigger when TX FIFO contains <= defined bytes
3095 
3096  ENUMs:
3097  EN: Clear Interrupt
3098  DIS: Writing 0 has no effect
3099 */
3100 #define I2C_EVENT0_IDIS_TXFIFOTRGC 0x00000008U
3101 #define I2C_EVENT0_IDIS_TXFIFOTRGC_M 0x00000008U
3102 #define I2C_EVENT0_IDIS_TXFIFOTRGC_S 3U
3103 #define I2C_EVENT0_IDIS_TXFIFOTRGC_EN 0x00000008U
3104 #define I2C_EVENT0_IDIS_TXFIFOTRGC_DIS 0x00000000U
3105 /*
3106 
3107  Field: RXFIFOFULLC
3108  From..to bits: 4...4
3109  DefaultValue: 0x0
3110  Access type: write-only
3111  Description: RXFIFO full event in controller mode.
3112 
3113  ENUMs:
3114  EN: Clear Interrupt
3115  DIS: Writing 0 has no effect
3116 */
3117 #define I2C_EVENT0_IDIS_RXFIFOFULLC 0x00000010U
3118 #define I2C_EVENT0_IDIS_RXFIFOFULLC_M 0x00000010U
3119 #define I2C_EVENT0_IDIS_RXFIFOFULLC_S 4U
3120 #define I2C_EVENT0_IDIS_RXFIFOFULLC_EN 0x00000010U
3121 #define I2C_EVENT0_IDIS_RXFIFOFULLC_DIS 0x00000000U
3122 /*
3123 
3124  Field: TXEMPTYC
3125  From..to bits: 5...5
3126  DefaultValue: 0x0
3127  Access type: write-only
3128  Description: TX FIFO empty interrupt mask. This interrupt is set if all data in the TX FIFO have been shifted out and the transmit goes into idle mode.
3129 
3130  ENUMs:
3131  EN: Clear Interrupt
3132  DIS: Writing 0 has no effect
3133 */
3134 #define I2C_EVENT0_IDIS_TXEMPTYC 0x00000020U
3135 #define I2C_EVENT0_IDIS_TXEMPTYC_M 0x00000020U
3136 #define I2C_EVENT0_IDIS_TXEMPTYC_S 5U
3137 #define I2C_EVENT0_IDIS_TXEMPTYC_EN 0x00000020U
3138 #define I2C_EVENT0_IDIS_TXEMPTYC_DIS 0x00000000U
3139 /*
3140 
3141  Field: CNACK
3142  From..to bits: 6...6
3143  DefaultValue: 0x0
3144  Access type: write-only
3145  Description: Address/Data NACK interrupt
3146 
3147  ENUMs:
3148  EN: Clear Interrupt
3149  DIS: Writing 0 has no effect
3150 */
3151 #define I2C_EVENT0_IDIS_CNACK 0x00000040U
3152 #define I2C_EVENT0_IDIS_CNACK_M 0x00000040U
3153 #define I2C_EVENT0_IDIS_CNACK_S 6U
3154 #define I2C_EVENT0_IDIS_CNACK_EN 0x00000040U
3155 #define I2C_EVENT0_IDIS_CNACK_DIS 0x00000000U
3156 /*
3157 
3158  Field: CSTART
3159  From..to bits: 7...7
3160  DefaultValue: 0x0
3161  Access type: write-only
3162  Description: START detection interrupt
3163 
3164  ENUMs:
3165  EN: Clear Interrupt
3166  DIS: Writing 0 has no effect
3167 */
3168 #define I2C_EVENT0_IDIS_CSTART 0x00000080U
3169 #define I2C_EVENT0_IDIS_CSTART_M 0x00000080U
3170 #define I2C_EVENT0_IDIS_CSTART_S 7U
3171 #define I2C_EVENT0_IDIS_CSTART_EN 0x00000080U
3172 #define I2C_EVENT0_IDIS_CSTART_DIS 0x00000000U
3173 /*
3174 
3175  Field: CSTOP
3176  From..to bits: 8...8
3177  DefaultValue: 0x0
3178  Access type: write-only
3179  Description: STOP detection interrupt
3180 
3181  ENUMs:
3182  EN: Clear Interrupt
3183  DIS: Writing 0 has no effect
3184 */
3185 #define I2C_EVENT0_IDIS_CSTOP 0x00000100U
3186 #define I2C_EVENT0_IDIS_CSTOP_M 0x00000100U
3187 #define I2C_EVENT0_IDIS_CSTOP_S 8U
3188 #define I2C_EVENT0_IDIS_CSTOP_EN 0x00000100U
3189 #define I2C_EVENT0_IDIS_CSTOP_DIS 0x00000000U
3190 /*
3191 
3192  Field: CARBLOST
3193  From..to bits: 9...9
3194  DefaultValue: 0x0
3195  Access type: write-only
3196  Description: Arbitration lost interrupt
3197 
3198  ENUMs:
3199  EN: Clear Interrupt
3200  DIS: Writing 0 has no effect
3201 */
3202 #define I2C_EVENT0_IDIS_CARBLOST 0x00000200U
3203 #define I2C_EVENT0_IDIS_CARBLOST_M 0x00000200U
3204 #define I2C_EVENT0_IDIS_CARBLOST_S 9U
3205 #define I2C_EVENT0_IDIS_CARBLOST_EN 0x00000200U
3206 #define I2C_EVENT0_IDIS_CARBLOST_DIS 0x00000000U
3207 /*
3208 
3209  Field: TRXDONE
3210  From..to bits: 16...16
3211  DefaultValue: 0x0
3212  Access type: write-only
3213  Description: Target receive data interrupt
3214  Signals that a byte has been received
3215 
3216  ENUMs:
3217  EN: Clear Interrupt
3218  DIS: Writing 0 has no effect
3219 */
3220 #define I2C_EVENT0_IDIS_TRXDONE 0x00010000U
3221 #define I2C_EVENT0_IDIS_TRXDONE_M 0x00010000U
3222 #define I2C_EVENT0_IDIS_TRXDONE_S 16U
3223 #define I2C_EVENT0_IDIS_TRXDONE_EN 0x00010000U
3224 #define I2C_EVENT0_IDIS_TRXDONE_DIS 0x00000000U
3225 /*
3226 
3227  Field: TTXDONE
3228  From..to bits: 17...17
3229  DefaultValue: 0x0
3230  Access type: write-only
3231  Description: Target transmit transaction completed interrupt
3232 
3233  ENUMs:
3234  EN: Clear Interrupt
3235  DIS: Writing 0 has no effect
3236 */
3237 #define I2C_EVENT0_IDIS_TTXDONE 0x00020000U
3238 #define I2C_EVENT0_IDIS_TTXDONE_M 0x00020000U
3239 #define I2C_EVENT0_IDIS_TTXDONE_S 17U
3240 #define I2C_EVENT0_IDIS_TTXDONE_EN 0x00020000U
3241 #define I2C_EVENT0_IDIS_TTXDONE_DIS 0x00000000U
3242 /*
3243 
3244  Field: RXFIFOTRGT
3245  From..to bits: 18...18
3246  DefaultValue: 0x0
3247  Access type: write-only
3248  Description: RX FIFO trigger in target mode
3249 
3250  ENUMs:
3251  EN: Clear Interrupt
3252  DIS: Writing 0 has no effect
3253 */
3254 #define I2C_EVENT0_IDIS_RXFIFOTRGT 0x00040000U
3255 #define I2C_EVENT0_IDIS_RXFIFOTRGT_M 0x00040000U
3256 #define I2C_EVENT0_IDIS_RXFIFOTRGT_S 18U
3257 #define I2C_EVENT0_IDIS_RXFIFOTRGT_EN 0x00040000U
3258 #define I2C_EVENT0_IDIS_RXFIFOTRGT_DIS 0x00000000U
3259 /*
3260 
3261  Field: TXFIFOTRGT
3262  From..to bits: 19...19
3263  DefaultValue: 0x0
3264  Access type: write-only
3265  Description: TX FIFO trigger in target mode
3266 
3267  ENUMs:
3268  EN: Clear Interrupt
3269  DIS: Writing 0 has no effect
3270 */
3271 #define I2C_EVENT0_IDIS_TXFIFOTRGT 0x00080000U
3272 #define I2C_EVENT0_IDIS_TXFIFOTRGT_M 0x00080000U
3273 #define I2C_EVENT0_IDIS_TXFIFOTRGT_S 19U
3274 #define I2C_EVENT0_IDIS_TXFIFOTRGT_EN 0x00080000U
3275 #define I2C_EVENT0_IDIS_TXFIFOTRGT_DIS 0x00000000U
3276 /*
3277 
3278  Field: RXFIFOFULLT
3279  From..to bits: 20...20
3280  DefaultValue: 0x0
3281  Access type: write-only
3282  Description: RXFIFO full event in target mode. This interrupt is set if an RX FIFO is full in target mode.
3283 
3284  ENUMs:
3285  EN: Clear Interrupt
3286  DIS: Writing 0 has no effect
3287 */
3288 #define I2C_EVENT0_IDIS_RXFIFOFULLT 0x00100000U
3289 #define I2C_EVENT0_IDIS_RXFIFOFULLT_M 0x00100000U
3290 #define I2C_EVENT0_IDIS_RXFIFOFULLT_S 20U
3291 #define I2C_EVENT0_IDIS_RXFIFOFULLT_EN 0x00100000U
3292 #define I2C_EVENT0_IDIS_RXFIFOFULLT_DIS 0x00000000U
3293 /*
3294 
3295  Field: TXEMPTYT
3296  From..to bits: 21...21
3297  DefaultValue: 0x0
3298  Access type: write-only
3299  Description: TX FIFO empty interrupt mask in target mode. This interrupt is set if all data in the TX FIFO in target mode have been shifted out and the transmit goes into idle mode.
3300 
3301  ENUMs:
3302  EN: Clear Interrupt
3303  DIS: Writing 0 has no effect
3304 */
3305 #define I2C_EVENT0_IDIS_TXEMPTYT 0x00200000U
3306 #define I2C_EVENT0_IDIS_TXEMPTYT_M 0x00200000U
3307 #define I2C_EVENT0_IDIS_TXEMPTYT_S 21U
3308 #define I2C_EVENT0_IDIS_TXEMPTYT_EN 0x00200000U
3309 #define I2C_EVENT0_IDIS_TXEMPTYT_DIS 0x00000000U
3310 /*
3311 
3312  Field: TSTART
3313  From..to bits: 22...22
3314  DefaultValue: 0x0
3315  Access type: write-only
3316  Description: Target start condition interrupt. Asserted when the received address matches the target address
3317 
3318  ENUMs:
3319  EN: Clear Interrupt
3320  DIS: Writing 0 has no effect
3321 */
3322 #define I2C_EVENT0_IDIS_TSTART 0x00400000U
3323 #define I2C_EVENT0_IDIS_TSTART_M 0x00400000U
3324 #define I2C_EVENT0_IDIS_TSTART_S 22U
3325 #define I2C_EVENT0_IDIS_TSTART_EN 0x00400000U
3326 #define I2C_EVENT0_IDIS_TSTART_DIS 0x00000000U
3327 /*
3328 
3329  Field: TSTOP
3330  From..to bits: 23...23
3331  DefaultValue: 0x0
3332  Access type: write-only
3333  Description: Target STOP detection interrupt
3334 
3335  ENUMs:
3336  EN: Clear Interrupt
3337  DIS: Writing 0 has no effect
3338 */
3339 #define I2C_EVENT0_IDIS_TSTOP 0x00800000U
3340 #define I2C_EVENT0_IDIS_TSTOP_M 0x00800000U
3341 #define I2C_EVENT0_IDIS_TSTOP_S 23U
3342 #define I2C_EVENT0_IDIS_TSTOP_EN 0x00800000U
3343 #define I2C_EVENT0_IDIS_TSTOP_DIS 0x00000000U
3344 /*
3345 
3346  Field: TGENCALL
3347  From..to bits: 24...24
3348  DefaultValue: 0x0
3349  Access type: write-only
3350  Description: General call interrupt
3351 
3352  ENUMs:
3353  EN: Clear Interrupt
3354  DIS: Writing 0 has no effect
3355 */
3356 #define I2C_EVENT0_IDIS_TGENCALL 0x01000000U
3357 #define I2C_EVENT0_IDIS_TGENCALL_M 0x01000000U
3358 #define I2C_EVENT0_IDIS_TGENCALL_S 24U
3359 #define I2C_EVENT0_IDIS_TGENCALL_EN 0x01000000U
3360 #define I2C_EVENT0_IDIS_TGENCALL_DIS 0x00000000U
3361 /*
3362 
3363  Field: TX_UNFL_T
3364  From..to bits: 25...25
3365  DefaultValue: 0x0
3366  Access type: write-only
3367  Description: TX FIFO underflow in target mode
3368 
3369  ENUMs:
3370  EN: Clear Interrupt
3371  DIS: Writing 0 has no effect
3372 */
3373 #define I2C_EVENT0_IDIS_TX_UNFL_T 0x02000000U
3374 #define I2C_EVENT0_IDIS_TX_UNFL_T_M 0x02000000U
3375 #define I2C_EVENT0_IDIS_TX_UNFL_T_S 25U
3376 #define I2C_EVENT0_IDIS_TX_UNFL_T_EN 0x02000000U
3377 #define I2C_EVENT0_IDIS_TX_UNFL_T_DIS 0x00000000U
3378 /*
3379 
3380  Field: RX_OVFL_T
3381  From..to bits: 26...26
3382  DefaultValue: 0x0
3383  Access type: write-only
3384  Description: RX FIFO overflow in target mode
3385 
3386  ENUMs:
3387  EN: Clear Interrupt
3388  DIS: Writing 0 has no effect
3389 */
3390 #define I2C_EVENT0_IDIS_RX_OVFL_T 0x04000000U
3391 #define I2C_EVENT0_IDIS_RX_OVFL_T_M 0x04000000U
3392 #define I2C_EVENT0_IDIS_RX_OVFL_T_S 26U
3393 #define I2C_EVENT0_IDIS_RX_OVFL_T_EN 0x04000000U
3394 #define I2C_EVENT0_IDIS_RX_OVFL_T_DIS 0x00000000U
3395 /*
3396 
3397  Field: TARBLOST
3398  From..to bits: 27...27
3399  DefaultValue: 0x0
3400  Access type: write-only
3401  Description: Target arbitration lost
3402 
3403  ENUMs:
3404  EN: Clear Interrupt
3405  DIS: Writing 0 has no effect
3406 */
3407 #define I2C_EVENT0_IDIS_TARBLOST 0x08000000U
3408 #define I2C_EVENT0_IDIS_TARBLOST_M 0x08000000U
3409 #define I2C_EVENT0_IDIS_TARBLOST_S 27U
3410 #define I2C_EVENT0_IDIS_TARBLOST_EN 0x08000000U
3411 #define I2C_EVENT0_IDIS_TARBLOST_DIS 0x00000000U
3412 
3413 
3414 /*-----------------------------------REGISTER------------------------------------
3415  Register name: EVENT0_IMEN
3416  Offset name: I2C_O_EVENT0_IMEN
3417  Relative address: 0x18
3418  Description: Interrupt mask set. Writing a 1 to a field in IMEN will set the related IMASK field.
3419  Default Value: 0x00000000
3420 
3421  Field: CRXDONE
3422  From..to bits: 0...0
3423  DefaultValue: 0x0
3424  Access type: write-only
3425  Description: Controller receive data interrupt. Signals that a byte has been received
3426 
3427  ENUMs:
3428  EN: Set masked interrrupt
3429  DIS: Writing 0 has no effect
3430 */
3431 #define I2C_EVENT0_IMEN_CRXDONE 0x00000001U
3432 #define I2C_EVENT0_IMEN_CRXDONE_M 0x00000001U
3433 #define I2C_EVENT0_IMEN_CRXDONE_S 0U
3434 #define I2C_EVENT0_IMEN_CRXDONE_EN 0x00000001U
3435 #define I2C_EVENT0_IMEN_CRXDONE_DIS 0x00000000U
3436 /*
3437 
3438  Field: CTXDONE
3439  From..to bits: 1...1
3440  DefaultValue: 0x0
3441  Access type: write-only
3442  Description: Controller transmit transaction completed interrupt
3443 
3444  ENUMs:
3445  EN: Set masked interrrupt
3446  DIS: Writing 0 has no effect
3447 */
3448 #define I2C_EVENT0_IMEN_CTXDONE 0x00000002U
3449 #define I2C_EVENT0_IMEN_CTXDONE_M 0x00000002U
3450 #define I2C_EVENT0_IMEN_CTXDONE_S 1U
3451 #define I2C_EVENT0_IMEN_CTXDONE_EN 0x00000002U
3452 #define I2C_EVENT0_IMEN_CTXDONE_DIS 0x00000000U
3453 /*
3454 
3455  Field: RXFIFOTRGC
3456  From..to bits: 2...2
3457  DefaultValue: 0x0
3458  Access type: write-only
3459  Description: RX FIFO trigger in controller mode
3460  Trigger when RX FIFO contains >= defined bytes
3461 
3462  ENUMs:
3463  EN: Set masked interrrupt
3464  DIS: Writing 0 has no effect
3465 */
3466 #define I2C_EVENT0_IMEN_RXFIFOTRGC 0x00000004U
3467 #define I2C_EVENT0_IMEN_RXFIFOTRGC_M 0x00000004U
3468 #define I2C_EVENT0_IMEN_RXFIFOTRGC_S 2U
3469 #define I2C_EVENT0_IMEN_RXFIFOTRGC_EN 0x00000004U
3470 #define I2C_EVENT0_IMEN_RXFIFOTRGC_DIS 0x00000000U
3471 /*
3472 
3473  Field: TXFIFOTRGC
3474  From..to bits: 3...3
3475  DefaultValue: 0x0
3476  Access type: write-only
3477  Description: TX FIFO trigger in Controller mode
3478  Trigger when TX FIFO contains <= defined bytes
3479 
3480  ENUMs:
3481  EN: Set masked interrrupt
3482  DIS: Writing 0 has no effect
3483 */
3484 #define I2C_EVENT0_IMEN_TXFIFOTRGC 0x00000008U
3485 #define I2C_EVENT0_IMEN_TXFIFOTRGC_M 0x00000008U
3486 #define I2C_EVENT0_IMEN_TXFIFOTRGC_S 3U
3487 #define I2C_EVENT0_IMEN_TXFIFOTRGC_EN 0x00000008U
3488 #define I2C_EVENT0_IMEN_TXFIFOTRGC_DIS 0x00000000U
3489 /*
3490 
3491  Field: RXFIFOFULLC
3492  From..to bits: 4...4
3493  DefaultValue: 0x0
3494  Access type: write-only
3495  Description: RXFIFO full event in controller mode.
3496 
3497  ENUMs:
3498  EN: Set masked interrrupt
3499  DIS: Writing 0 has no effect
3500 */
3501 #define I2C_EVENT0_IMEN_RXFIFOFULLC 0x00000010U
3502 #define I2C_EVENT0_IMEN_RXFIFOFULLC_M 0x00000010U
3503 #define I2C_EVENT0_IMEN_RXFIFOFULLC_S 4U
3504 #define I2C_EVENT0_IMEN_RXFIFOFULLC_EN 0x00000010U
3505 #define I2C_EVENT0_IMEN_RXFIFOFULLC_DIS 0x00000000U
3506 /*
3507 
3508  Field: TXEMPTYC
3509  From..to bits: 5...5
3510  DefaultValue: 0x0
3511  Access type: write-only
3512  Description: TX FIFO empty interrupt mask in controller mode. This interrupt is set if all data in the TX FIFO in controller mode have been shifted out and the transmit goes into idle mode.
3513 
3514  ENUMs:
3515  EN: Set masked interrrupt
3516  DIS: Writing 0 has no effect
3517 */
3518 #define I2C_EVENT0_IMEN_TXEMPTYC 0x00000020U
3519 #define I2C_EVENT0_IMEN_TXEMPTYC_M 0x00000020U
3520 #define I2C_EVENT0_IMEN_TXEMPTYC_S 5U
3521 #define I2C_EVENT0_IMEN_TXEMPTYC_EN 0x00000020U
3522 #define I2C_EVENT0_IMEN_TXEMPTYC_DIS 0x00000000U
3523 /*
3524 
3525  Field: CNACK
3526  From..to bits: 6...6
3527  DefaultValue: 0x0
3528  Access type: write-only
3529  Description: Address/Data NACK interrupt
3530 
3531  ENUMs:
3532  EN: Set masked interrrupt
3533  DIS: Writing 0 has no effect
3534 */
3535 #define I2C_EVENT0_IMEN_CNACK 0x00000040U
3536 #define I2C_EVENT0_IMEN_CNACK_M 0x00000040U
3537 #define I2C_EVENT0_IMEN_CNACK_S 6U
3538 #define I2C_EVENT0_IMEN_CNACK_EN 0x00000040U
3539 #define I2C_EVENT0_IMEN_CNACK_DIS 0x00000000U
3540 /*
3541 
3542  Field: CSTART
3543  From..to bits: 7...7
3544  DefaultValue: 0x0
3545  Access type: write-only
3546  Description: START detection interrupt
3547 
3548  ENUMs:
3549  EN: Set masked interrrupt
3550  DIS: Writing 0 has no effect
3551 */
3552 #define I2C_EVENT0_IMEN_CSTART 0x00000080U
3553 #define I2C_EVENT0_IMEN_CSTART_M 0x00000080U
3554 #define I2C_EVENT0_IMEN_CSTART_S 7U
3555 #define I2C_EVENT0_IMEN_CSTART_EN 0x00000080U
3556 #define I2C_EVENT0_IMEN_CSTART_DIS 0x00000000U
3557 /*
3558 
3559  Field: CSTOP
3560  From..to bits: 8...8
3561  DefaultValue: 0x0
3562  Access type: write-only
3563  Description: STOP detection interrupt
3564 
3565  ENUMs:
3566  EN: Set masked interrrupt
3567  DIS: Writing 0 has no effect
3568 */
3569 #define I2C_EVENT0_IMEN_CSTOP 0x00000100U
3570 #define I2C_EVENT0_IMEN_CSTOP_M 0x00000100U
3571 #define I2C_EVENT0_IMEN_CSTOP_S 8U
3572 #define I2C_EVENT0_IMEN_CSTOP_EN 0x00000100U
3573 #define I2C_EVENT0_IMEN_CSTOP_DIS 0x00000000U
3574 /*
3575 
3576  Field: CARBLOST
3577  From..to bits: 9...9
3578  DefaultValue: 0x0
3579  Access type: write-only
3580  Description: Arbitration lost interrupt
3581 
3582  ENUMs:
3583  EN: Set masked interrrupt
3584  DIS: Writing 0 has no effect
3585 */
3586 #define I2C_EVENT0_IMEN_CARBLOST 0x00000200U
3587 #define I2C_EVENT0_IMEN_CARBLOST_M 0x00000200U
3588 #define I2C_EVENT0_IMEN_CARBLOST_S 9U
3589 #define I2C_EVENT0_IMEN_CARBLOST_EN 0x00000200U
3590 #define I2C_EVENT0_IMEN_CARBLOST_DIS 0x00000000U
3591 /*
3592 
3593  Field: SRXDONE
3594  From..to bits: 16...16
3595  DefaultValue: 0x0
3596  Access type: write-only
3597  Description: Target receive data interrupt. Signals that a byte has been received
3598 
3599  ENUMs:
3600  EN: Set masked interrrupt
3601  DIS: Writing 0 has no effect
3602 */
3603 #define I2C_EVENT0_IMEN_SRXDONE 0x00010000U
3604 #define I2C_EVENT0_IMEN_SRXDONE_M 0x00010000U
3605 #define I2C_EVENT0_IMEN_SRXDONE_S 16U
3606 #define I2C_EVENT0_IMEN_SRXDONE_EN 0x00010000U
3607 #define I2C_EVENT0_IMEN_SRXDONE_DIS 0x00000000U
3608 /*
3609 
3610  Field: TTXDONE
3611  From..to bits: 17...17
3612  DefaultValue: 0x0
3613  Access type: write-only
3614  Description: Target transmit transaction completed interrupt
3615 
3616  ENUMs:
3617  EN: Set masked interrrupt
3618  DIS: Writing 0 has no effect
3619 */
3620 #define I2C_EVENT0_IMEN_TTXDONE 0x00020000U
3621 #define I2C_EVENT0_IMEN_TTXDONE_M 0x00020000U
3622 #define I2C_EVENT0_IMEN_TTXDONE_S 17U
3623 #define I2C_EVENT0_IMEN_TTXDONE_EN 0x00020000U
3624 #define I2C_EVENT0_IMEN_TTXDONE_DIS 0x00000000U
3625 /*
3626 
3627  Field: RXFIFOTRGT
3628  From..to bits: 18...18
3629  DefaultValue: 0x0
3630  Access type: write-only
3631  Description: RX FIFO trigger in target mode
3632 
3633  ENUMs:
3634  EN: Set masked interrrupt
3635  DIS: Writing 0 has no effect
3636 */
3637 #define I2C_EVENT0_IMEN_RXFIFOTRGT 0x00040000U
3638 #define I2C_EVENT0_IMEN_RXFIFOTRGT_M 0x00040000U
3639 #define I2C_EVENT0_IMEN_RXFIFOTRGT_S 18U
3640 #define I2C_EVENT0_IMEN_RXFIFOTRGT_EN 0x00040000U
3641 #define I2C_EVENT0_IMEN_RXFIFOTRGT_DIS 0x00000000U
3642 /*
3643 
3644  Field: TXFIFOTRGST
3645  From..to bits: 19...19
3646  DefaultValue: 0x0
3647  Access type: write-only
3648  Description: TX FIFO trigger in target mode
3649 
3650  ENUMs:
3651  EN: Set masked interrrupt
3652  DIS: Writing 0 has no effect
3653 */
3654 #define I2C_EVENT0_IMEN_TXFIFOTRGST 0x00080000U
3655 #define I2C_EVENT0_IMEN_TXFIFOTRGST_M 0x00080000U
3656 #define I2C_EVENT0_IMEN_TXFIFOTRGST_S 19U
3657 #define I2C_EVENT0_IMEN_TXFIFOTRGST_EN 0x00080000U
3658 #define I2C_EVENT0_IMEN_TXFIFOTRGST_DIS 0x00000000U
3659 /*
3660 
3661  Field: RXFIFOFULLT
3662  From..to bits: 20...20
3663  DefaultValue: 0x0
3664  Access type: write-only
3665  Description: RXFIFO full event in target mode. This interrupt is set if an RX FIFO is full in target mode.
3666 
3667  ENUMs:
3668  EN: Set masked interrrupt
3669  DIS: Writing 0 has no effect
3670 */
3671 #define I2C_EVENT0_IMEN_RXFIFOFULLT 0x00100000U
3672 #define I2C_EVENT0_IMEN_RXFIFOFULLT_M 0x00100000U
3673 #define I2C_EVENT0_IMEN_RXFIFOFULLT_S 20U
3674 #define I2C_EVENT0_IMEN_RXFIFOFULLT_EN 0x00100000U
3675 #define I2C_EVENT0_IMEN_RXFIFOFULLT_DIS 0x00000000U
3676 /*
3677 
3678  Field: TXEMPTYT
3679  From..to bits: 21...21
3680  DefaultValue: 0x0
3681  Access type: write-only
3682  Description: TX FIFO Empty interrupt mask in target mode. This interrupt is set if all data in the TX FIFO in target mode have been shifted out and the transmit goes into idle mode.
3683 
3684  ENUMs:
3685  EN: Set masked interrrupt
3686  DIS: Writing 0 has no effect
3687 */
3688 #define I2C_EVENT0_IMEN_TXEMPTYT 0x00200000U
3689 #define I2C_EVENT0_IMEN_TXEMPTYT_M 0x00200000U
3690 #define I2C_EVENT0_IMEN_TXEMPTYT_S 21U
3691 #define I2C_EVENT0_IMEN_TXEMPTYT_EN 0x00200000U
3692 #define I2C_EVENT0_IMEN_TXEMPTYT_DIS 0x00000000U
3693 /*
3694 
3695  Field: TSTART
3696  From..to bits: 22...22
3697  DefaultValue: 0x0
3698  Access type: write-only
3699  Description: Target start condition interrupt. Asserted when the received address matches the target address
3700 
3701  ENUMs:
3702  EN: Set masked interrrupt
3703  DIS: Writing 0 has no effect
3704 */
3705 #define I2C_EVENT0_IMEN_TSTART 0x00400000U
3706 #define I2C_EVENT0_IMEN_TSTART_M 0x00400000U
3707 #define I2C_EVENT0_IMEN_TSTART_S 22U
3708 #define I2C_EVENT0_IMEN_TSTART_EN 0x00400000U
3709 #define I2C_EVENT0_IMEN_TSTART_DIS 0x00000000U
3710 /*
3711 
3712  Field: TSTOP
3713  From..to bits: 23...23
3714  DefaultValue: 0x0
3715  Access type: write-only
3716  Description: Stop condition interrupt
3717 
3718  ENUMs:
3719  EN: Set masked interrrupt
3720  DIS: Writing 0 has no effect
3721 */
3722 #define I2C_EVENT0_IMEN_TSTOP 0x00800000U
3723 #define I2C_EVENT0_IMEN_TSTOP_M 0x00800000U
3724 #define I2C_EVENT0_IMEN_TSTOP_S 23U
3725 #define I2C_EVENT0_IMEN_TSTOP_EN 0x00800000U
3726 #define I2C_EVENT0_IMEN_TSTOP_DIS 0x00000000U
3727 /*
3728 
3729  Field: TGENCALL
3730  From..to bits: 24...24
3731  DefaultValue: 0x0
3732  Access type: write-only
3733  Description: General call interrupt
3734 
3735  ENUMs:
3736  EN: Set masked interrrupt
3737  DIS: Writing 0 has no effect
3738 */
3739 #define I2C_EVENT0_IMEN_TGENCALL 0x01000000U
3740 #define I2C_EVENT0_IMEN_TGENCALL_M 0x01000000U
3741 #define I2C_EVENT0_IMEN_TGENCALL_S 24U
3742 #define I2C_EVENT0_IMEN_TGENCALL_EN 0x01000000U
3743 #define I2C_EVENT0_IMEN_TGENCALL_DIS 0x00000000U
3744 /*
3745 
3746  Field: TX_UNFL_T
3747  From..to bits: 25...25
3748  DefaultValue: 0x0
3749  Access type: write-only
3750  Description: TX FIFO underflow in target mode
3751 
3752  ENUMs:
3753  EN: Set masked interrrupt
3754  DIS: Writing 0 has no effect
3755 */
3756 #define I2C_EVENT0_IMEN_TX_UNFL_T 0x02000000U
3757 #define I2C_EVENT0_IMEN_TX_UNFL_T_M 0x02000000U
3758 #define I2C_EVENT0_IMEN_TX_UNFL_T_S 25U
3759 #define I2C_EVENT0_IMEN_TX_UNFL_T_EN 0x02000000U
3760 #define I2C_EVENT0_IMEN_TX_UNFL_T_DIS 0x00000000U
3761 /*
3762 
3763  Field: RX_OVFL_T
3764  From..to bits: 26...26
3765  DefaultValue: 0x0
3766  Access type: write-only
3767  Description: RX FIFO overflow in target mode
3768 
3769  ENUMs:
3770  EN: Set masked interrrupt
3771  DIS: Writing 0 has no effect
3772 */
3773 #define I2C_EVENT0_IMEN_RX_OVFL_T 0x04000000U
3774 #define I2C_EVENT0_IMEN_RX_OVFL_T_M 0x04000000U
3775 #define I2C_EVENT0_IMEN_RX_OVFL_T_S 26U
3776 #define I2C_EVENT0_IMEN_RX_OVFL_T_EN 0x04000000U
3777 #define I2C_EVENT0_IMEN_RX_OVFL_T_DIS 0x00000000U
3778 /*
3779 
3780  Field: TARBLOST
3781  From..to bits: 27...27
3782  DefaultValue: 0x0
3783  Access type: write-only
3784  Description: Target srbitration lost
3785 
3786  ENUMs:
3787  EN: Set masked interrrupt
3788  DIS: Writing 0 has no effect
3789 */
3790 #define I2C_EVENT0_IMEN_TARBLOST 0x08000000U
3791 #define I2C_EVENT0_IMEN_TARBLOST_M 0x08000000U
3792 #define I2C_EVENT0_IMEN_TARBLOST_S 27U
3793 #define I2C_EVENT0_IMEN_TARBLOST_EN 0x08000000U
3794 #define I2C_EVENT0_IMEN_TARBLOST_DIS 0x00000000U
3795 
3796 
3797 /*-----------------------------------REGISTER------------------------------------
3798  Register name: EVENT0_IMDIS
3799  Offset name: I2C_O_EVENT0_IMDIS
3800  Relative address: 0x1C
3801  Description: Interrupt clear. Write a 1 to clear corresponding Interrupt.
3802  Default Value: 0x00000000
3803 
3804  Field: CRXDONE
3805  From..to bits: 0...0
3806  DefaultValue: 0x0
3807  Access type: write-only
3808  Description: Controller receive data interrupt. Signals that a byte has been received
3809 
3810  ENUMs:
3811  EN: Clear masked interrupt
3812  DIS: Writing 0 has no effect
3813 */
3814 #define I2C_EVENT0_IMDIS_CRXDONE 0x00000001U
3815 #define I2C_EVENT0_IMDIS_CRXDONE_M 0x00000001U
3816 #define I2C_EVENT0_IMDIS_CRXDONE_S 0U
3817 #define I2C_EVENT0_IMDIS_CRXDONE_EN 0x00000001U
3818 #define I2C_EVENT0_IMDIS_CRXDONE_DIS 0x00000000U
3819 /*
3820 
3821  Field: CTXDONE
3822  From..to bits: 1...1
3823  DefaultValue: 0x0
3824  Access type: write-only
3825  Description: Controller transmit transaction completed interrupt
3826 
3827  ENUMs:
3828  EN: Clear masked interrupt
3829  DIS: Writing 0 has no effect
3830 */
3831 #define I2C_EVENT0_IMDIS_CTXDONE 0x00000002U
3832 #define I2C_EVENT0_IMDIS_CTXDONE_M 0x00000002U
3833 #define I2C_EVENT0_IMDIS_CTXDONE_S 1U
3834 #define I2C_EVENT0_IMDIS_CTXDONE_EN 0x00000002U
3835 #define I2C_EVENT0_IMDIS_CTXDONE_DIS 0x00000000U
3836 /*
3837 
3838  Field: RXFIFOTRGC
3839  From..to bits: 2...2
3840  DefaultValue: 0x0
3841  Access type: write-only
3842  Description: RX FIFO trigger in controller mode
3843  Trigger when RX FIFO contains >= defined bytes
3844 
3845  ENUMs:
3846  EN: Clear masked interrupt
3847  DIS: Writing 0 has no effect
3848 */
3849 #define I2C_EVENT0_IMDIS_RXFIFOTRGC 0x00000004U
3850 #define I2C_EVENT0_IMDIS_RXFIFOTRGC_M 0x00000004U
3851 #define I2C_EVENT0_IMDIS_RXFIFOTRGC_S 2U
3852 #define I2C_EVENT0_IMDIS_RXFIFOTRGC_EN 0x00000004U
3853 #define I2C_EVENT0_IMDIS_RXFIFOTRGC_DIS 0x00000000U
3854 /*
3855 
3856  Field: TXFIFOTRGC
3857  From..to bits: 3...3
3858  DefaultValue: 0x0
3859  Access type: write-only
3860  Description: TX FIFO trigger in controller mode
3861  Trigger when TX FIFO contains <= defined bytes
3862 
3863  ENUMs:
3864  EN: Clear masked interrupt
3865  DIS: Writing 0 has no effect
3866 */
3867 #define I2C_EVENT0_IMDIS_TXFIFOTRGC 0x00000008U
3868 #define I2C_EVENT0_IMDIS_TXFIFOTRGC_M 0x00000008U
3869 #define I2C_EVENT0_IMDIS_TXFIFOTRGC_S 3U
3870 #define I2C_EVENT0_IMDIS_TXFIFOTRGC_EN 0x00000008U
3871 #define I2C_EVENT0_IMDIS_TXFIFOTRGC_DIS 0x00000000U
3872 /*
3873 
3874  Field: RXFIFOFULLC
3875  From..to bits: 4...4
3876  DefaultValue: 0x0
3877  Access type: write-only
3878  Description: RX FIFO full event in controller mode.
3879 
3880  ENUMs:
3881  EN: Clear masked interrupt
3882  DIS: Writing 0 has no effect
3883 */
3884 #define I2C_EVENT0_IMDIS_RXFIFOFULLC 0x00000010U
3885 #define I2C_EVENT0_IMDIS_RXFIFOFULLC_M 0x00000010U
3886 #define I2C_EVENT0_IMDIS_RXFIFOFULLC_S 4U
3887 #define I2C_EVENT0_IMDIS_RXFIFOFULLC_EN 0x00000010U
3888 #define I2C_EVENT0_IMDIS_RXFIFOFULLC_DIS 0x00000000U
3889 /*
3890 
3891  Field: TXEMPTYC
3892  From..to bits: 5...5
3893  DefaultValue: 0x0
3894  Access type: write-only
3895  Description: TX FIFO empty interrupt mask. This interrupt is set if all data in the TX FIFO have been shifted out and the transmit goes into idle mode.
3896 
3897  ENUMs:
3898  EN: Clear masked interrupt
3899  DIS: Writing 0 has no effect
3900 */
3901 #define I2C_EVENT0_IMDIS_TXEMPTYC 0x00000020U
3902 #define I2C_EVENT0_IMDIS_TXEMPTYC_M 0x00000020U
3903 #define I2C_EVENT0_IMDIS_TXEMPTYC_S 5U
3904 #define I2C_EVENT0_IMDIS_TXEMPTYC_EN 0x00000020U
3905 #define I2C_EVENT0_IMDIS_TXEMPTYC_DIS 0x00000000U
3906 /*
3907 
3908  Field: CNACK
3909  From..to bits: 6...6
3910  DefaultValue: 0x0
3911  Access type: write-only
3912  Description: Address/Data NACK interrupt
3913 
3914  ENUMs:
3915  EN: Clear masked interrupt
3916  DIS: Writing 0 has no effect
3917 */
3918 #define I2C_EVENT0_IMDIS_CNACK 0x00000040U
3919 #define I2C_EVENT0_IMDIS_CNACK_M 0x00000040U
3920 #define I2C_EVENT0_IMDIS_CNACK_S 6U
3921 #define I2C_EVENT0_IMDIS_CNACK_EN 0x00000040U
3922 #define I2C_EVENT0_IMDIS_CNACK_DIS 0x00000000U
3923 /*
3924 
3925  Field: CSTART
3926  From..to bits: 7...7
3927  DefaultValue: 0x0
3928  Access type: write-only
3929  Description: START detection interrupt
3930 
3931  ENUMs:
3932  EN: Clear masked interrupt
3933  DIS: Writing 0 has no effect
3934 */
3935 #define I2C_EVENT0_IMDIS_CSTART 0x00000080U
3936 #define I2C_EVENT0_IMDIS_CSTART_M 0x00000080U
3937 #define I2C_EVENT0_IMDIS_CSTART_S 7U
3938 #define I2C_EVENT0_IMDIS_CSTART_EN 0x00000080U
3939 #define I2C_EVENT0_IMDIS_CSTART_DIS 0x00000000U
3940 /*
3941 
3942  Field: CSTOP
3943  From..to bits: 8...8
3944  DefaultValue: 0x0
3945  Access type: write-only
3946  Description: STOP detection interrupt
3947 
3948  ENUMs:
3949  EN: Clear masked interrupt
3950  DIS: Writing 0 has no effect
3951 */
3952 #define I2C_EVENT0_IMDIS_CSTOP 0x00000100U
3953 #define I2C_EVENT0_IMDIS_CSTOP_M 0x00000100U
3954 #define I2C_EVENT0_IMDIS_CSTOP_S 8U
3955 #define I2C_EVENT0_IMDIS_CSTOP_EN 0x00000100U
3956 #define I2C_EVENT0_IMDIS_CSTOP_DIS 0x00000000U
3957 /*
3958 
3959  Field: CARBLOST
3960  From..to bits: 9...9
3961  DefaultValue: 0x0
3962  Access type: write-only
3963  Description: Arbitration lost interrupt
3964 
3965  ENUMs:
3966  EN: Clear masked interrupt
3967  DIS: Writing 0 has no effect
3968 */
3969 #define I2C_EVENT0_IMDIS_CARBLOST 0x00000200U
3970 #define I2C_EVENT0_IMDIS_CARBLOST_M 0x00000200U
3971 #define I2C_EVENT0_IMDIS_CARBLOST_S 9U
3972 #define I2C_EVENT0_IMDIS_CARBLOST_EN 0x00000200U
3973 #define I2C_EVENT0_IMDIS_CARBLOST_DIS 0x00000000U
3974 /*
3975 
3976  Field: TRXDONE
3977  From..to bits: 16...16
3978  DefaultValue: 0x0
3979  Access type: write-only
3980  Description: Target receive data interrupt. Signals that a byte has been received
3981 
3982  ENUMs:
3983  EN: Clear masked interrupt
3984  DIS: Writing 0 has no effect
3985 */
3986 #define I2C_EVENT0_IMDIS_TRXDONE 0x00010000U
3987 #define I2C_EVENT0_IMDIS_TRXDONE_M 0x00010000U
3988 #define I2C_EVENT0_IMDIS_TRXDONE_S 16U
3989 #define I2C_EVENT0_IMDIS_TRXDONE_EN 0x00010000U
3990 #define I2C_EVENT0_IMDIS_TRXDONE_DIS 0x00000000U
3991 /*
3992 
3993  Field: TTXDONE
3994  From..to bits: 17...17
3995  DefaultValue: 0x0
3996  Access type: write-only
3997  Description: Target transmit transaction completed interrupt
3998 
3999  ENUMs:
4000  EN: Clear masked interrupt
4001  DIS: Writing 0 has no effect
4002 */
4003 #define I2C_EVENT0_IMDIS_TTXDONE 0x00020000U
4004 #define I2C_EVENT0_IMDIS_TTXDONE_M 0x00020000U
4005 #define I2C_EVENT0_IMDIS_TTXDONE_S 17U
4006 #define I2C_EVENT0_IMDIS_TTXDONE_EN 0x00020000U
4007 #define I2C_EVENT0_IMDIS_TTXDONE_DIS 0x00000000U
4008 /*
4009 
4010  Field: RXFIFOTRGT
4011  From..to bits: 18...18
4012  DefaultValue: 0x0
4013  Access type: write-only
4014  Description: RX FIFO trigger in target mode
4015 
4016  ENUMs:
4017  EN: Clear masked interrupt
4018  DIS: Writing 0 has no effect
4019 */
4020 #define I2C_EVENT0_IMDIS_RXFIFOTRGT 0x00040000U
4021 #define I2C_EVENT0_IMDIS_RXFIFOTRGT_M 0x00040000U
4022 #define I2C_EVENT0_IMDIS_RXFIFOTRGT_S 18U
4023 #define I2C_EVENT0_IMDIS_RXFIFOTRGT_EN 0x00040000U
4024 #define I2C_EVENT0_IMDIS_RXFIFOTRGT_DIS 0x00000000U
4025 /*
4026 
4027  Field: TXFIFOTRGT
4028  From..to bits: 19...19
4029  DefaultValue: 0x0
4030  Access type: write-only
4031  Description: TX FIFO trigger in target mode
4032 
4033  ENUMs:
4034  EN: Clear masked interrupt
4035  DIS: Writing 0 has no effect
4036 */
4037 #define I2C_EVENT0_IMDIS_TXFIFOTRGT 0x00080000U
4038 #define I2C_EVENT0_IMDIS_TXFIFOTRGT_M 0x00080000U
4039 #define I2C_EVENT0_IMDIS_TXFIFOTRGT_S 19U
4040 #define I2C_EVENT0_IMDIS_TXFIFOTRGT_EN 0x00080000U
4041 #define I2C_EVENT0_IMDIS_TXFIFOTRGT_DIS 0x00000000U
4042 /*
4043 
4044  Field: RXFIFOFULLT
4045  From..to bits: 20...20
4046  DefaultValue: 0x0
4047  Access type: write-only
4048  Description: RXFIFO full event in target mode. This interrupt is set if an RX FIFO is full in target mode.
4049 
4050  ENUMs:
4051  EN: Clear masked interrupt
4052  DIS: Writing 0 has no effect
4053 */
4054 #define I2C_EVENT0_IMDIS_RXFIFOFULLT 0x00100000U
4055 #define I2C_EVENT0_IMDIS_RXFIFOFULLT_M 0x00100000U
4056 #define I2C_EVENT0_IMDIS_RXFIFOFULLT_S 20U
4057 #define I2C_EVENT0_IMDIS_RXFIFOFULLT_EN 0x00100000U
4058 #define I2C_EVENT0_IMDIS_RXFIFOFULLT_DIS 0x00000000U
4059 /*
4060 
4061  Field: TXEMPTYT
4062  From..to bits: 21...21
4063  DefaultValue: 0x0
4064  Access type: write-only
4065  Description: TX FIFO empty interrupt mask in target mode. This interrupt is set if all data in the TX FIFO in target mode have been shifted out and the transmit goes into idle mode.
4066 
4067  ENUMs:
4068  EN: Clear masked interrupt
4069  DIS: Writing 0 has no effect
4070 */
4071 #define I2C_EVENT0_IMDIS_TXEMPTYT 0x00200000U
4072 #define I2C_EVENT0_IMDIS_TXEMPTYT_M 0x00200000U
4073 #define I2C_EVENT0_IMDIS_TXEMPTYT_S 21U
4074 #define I2C_EVENT0_IMDIS_TXEMPTYT_EN 0x00200000U
4075 #define I2C_EVENT0_IMDIS_TXEMPTYT_DIS 0x00000000U
4076 /*
4077 
4078  Field: TSTART
4079  From..to bits: 22...22
4080  DefaultValue: 0x0
4081  Access type: write-only
4082  Description: Target start condition interrupt. Asserted when the received address matches the target address.
4083 
4084  ENUMs:
4085  EN: Clear masked interrupt
4086  DIS: Writing 0 has no effect
4087 */
4088 #define I2C_EVENT0_IMDIS_TSTART 0x00400000U
4089 #define I2C_EVENT0_IMDIS_TSTART_M 0x00400000U
4090 #define I2C_EVENT0_IMDIS_TSTART_S 22U
4091 #define I2C_EVENT0_IMDIS_TSTART_EN 0x00400000U
4092 #define I2C_EVENT0_IMDIS_TSTART_DIS 0x00000000U
4093 /*
4094 
4095  Field: TSTOP
4096  From..to bits: 23...23
4097  DefaultValue: 0x0
4098  Access type: write-only
4099  Description: Target STOP detection interrupt
4100 
4101  ENUMs:
4102  EN: Clear masked interrupt
4103  DIS: Writing 0 has no effect
4104 */
4105 #define I2C_EVENT0_IMDIS_TSTOP 0x00800000U
4106 #define I2C_EVENT0_IMDIS_TSTOP_M 0x00800000U
4107 #define I2C_EVENT0_IMDIS_TSTOP_S 23U
4108 #define I2C_EVENT0_IMDIS_TSTOP_EN 0x00800000U
4109 #define I2C_EVENT0_IMDIS_TSTOP_DIS 0x00000000U
4110 /*
4111 
4112  Field: TGENCALL
4113  From..to bits: 24...24
4114  DefaultValue: 0x0
4115  Access type: write-only
4116  Description: General call interrupt
4117 
4118  ENUMs:
4119  EN: Clear masked interrupt
4120  DIS: Writing 0 has no effect
4121 */
4122 #define I2C_EVENT0_IMDIS_TGENCALL 0x01000000U
4123 #define I2C_EVENT0_IMDIS_TGENCALL_M 0x01000000U
4124 #define I2C_EVENT0_IMDIS_TGENCALL_S 24U
4125 #define I2C_EVENT0_IMDIS_TGENCALL_EN 0x01000000U
4126 #define I2C_EVENT0_IMDIS_TGENCALL_DIS 0x00000000U
4127 /*
4128 
4129  Field: TX_UNFL_T
4130  From..to bits: 25...25
4131  DefaultValue: 0x0
4132  Access type: write-only
4133  Description: TX FIFO underflow in target mode
4134 
4135  ENUMs:
4136  EN: Clear masked interrupt
4137  DIS: Writing 0 has no effect
4138 */
4139 #define I2C_EVENT0_IMDIS_TX_UNFL_T 0x02000000U
4140 #define I2C_EVENT0_IMDIS_TX_UNFL_T_M 0x02000000U
4141 #define I2C_EVENT0_IMDIS_TX_UNFL_T_S 25U
4142 #define I2C_EVENT0_IMDIS_TX_UNFL_T_EN 0x02000000U
4143 #define I2C_EVENT0_IMDIS_TX_UNFL_T_DIS 0x00000000U
4144 /*
4145 
4146  Field: RX_OVFL_T
4147  From..to bits: 26...26
4148  DefaultValue: 0x0
4149  Access type: write-only
4150  Description: RX FIFO overflow in target mode
4151 
4152  ENUMs:
4153  EN: Clear masked interrupt
4154  DIS: Writing 0 has no effect
4155 */
4156 #define I2C_EVENT0_IMDIS_RX_OVFL_T 0x04000000U
4157 #define I2C_EVENT0_IMDIS_RX_OVFL_T_M 0x04000000U
4158 #define I2C_EVENT0_IMDIS_RX_OVFL_T_S 26U
4159 #define I2C_EVENT0_IMDIS_RX_OVFL_T_EN 0x04000000U
4160 #define I2C_EVENT0_IMDIS_RX_OVFL_T_DIS 0x00000000U
4161 /*
4162 
4163  Field: TARBLOST
4164  From..to bits: 27...27
4165  DefaultValue: 0x0
4166  Access type: write-only
4167  Description: Target arbitration lost
4168 
4169  ENUMs:
4170  EN: Clear masked interrupt
4171  DIS: Writing 0 has no effect
4172 */
4173 #define I2C_EVENT0_IMDIS_TARBLOST 0x08000000U
4174 #define I2C_EVENT0_IMDIS_TARBLOST_M 0x08000000U
4175 #define I2C_EVENT0_IMDIS_TARBLOST_S 27U
4176 #define I2C_EVENT0_IMDIS_TARBLOST_EN 0x08000000U
4177 #define I2C_EVENT0_IMDIS_TARBLOST_DIS 0x00000000U
4178 
4179 
4180 /*-----------------------------------REGISTER------------------------------------
4181  Register name: EVT_MODE
4182  Offset name: I2C_O_EVT_MODE
4183  Relative address: 0x20
4184  Description: Event mode register. It is used to select whether each line is disabled, in software mode (software clears the [RIS]) or in hardware mode (hardware clears the [RIS])
4185  Default Value: 0x00000001
4186 
4187  Field: INT0_CFG
4188  From..to bits: 0...1
4189  DefaultValue: 0x1
4190  Access type: read-only
4191  Description: Event line mode select for event corresponding to [INT_EVENT0]
4192 
4193  ENUMs:
4194  DIS: The interrupt or event line is disabled.
4195  SOFTWARE: The interrupt or event line is in software mode. Software must clear the RIS.
4196  HARDWARE: The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
4197 */
4198 #define I2C_EVT_MODE_INT0_CFG_W 2U
4199 #define I2C_EVT_MODE_INT0_CFG_M 0x00000003U
4200 #define I2C_EVT_MODE_INT0_CFG_S 0U
4201 #define I2C_EVT_MODE_INT0_CFG_DIS 0x00000000U
4202 #define I2C_EVT_MODE_INT0_CFG_SOFTWARE 0x00000001U
4203 #define I2C_EVT_MODE_INT0_CFG_HARDWARE 0x00000002U
4204 
4205 
4206 /*-----------------------------------REGISTER------------------------------------
4207  Register name: DESC
4208  Offset name: I2C_O_DESC
4209  Relative address: 0x24
4210  Description: This register identifies the peripheral and its exact version.
4211  Default Value: 0x00000000
4212 
4213  Field: MINREV
4214  From..to bits: 0...3
4215  DefaultValue: 0x0
4216  Access type: read-only
4217  Description: Minor rev of the IP
4218 
4219  ENUMs:
4220  MINIMUM: Smallest value
4221  MAXIMUM: Highest possible value
4222 */
4223 #define I2C_DESC_MINREV_W 4U
4224 #define I2C_DESC_MINREV_M 0x0000000FU
4225 #define I2C_DESC_MINREV_S 0U
4226 #define I2C_DESC_MINREV_MINIMUM 0x00000000U
4227 #define I2C_DESC_MINREV_MAXIMUM 0x0000000FU
4228 /*
4229 
4230  Field: MAJREV
4231  From..to bits: 4...7
4232  DefaultValue: 0x0
4233  Access type: read-only
4234  Description: Major rev of the IP
4235 
4236  ENUMs:
4237  MINIMUM: Smallest value
4238  MAXIMUM: Highest possible value
4239 */
4240 #define I2C_DESC_MAJREV_W 4U
4241 #define I2C_DESC_MAJREV_M 0x000000F0U
4242 #define I2C_DESC_MAJREV_S 4U
4243 #define I2C_DESC_MAJREV_MINIMUM 0x00000000U
4244 #define I2C_DESC_MAJREV_MAXIMUM 0x000000F0U
4245 /*
4246 
4247  Field: INSTNUM
4248  From..to bits: 8...11
4249  DefaultValue: 0x0
4250  Access type: read-only
4251  Description: Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances
4252 
4253  ENUMs:
4254  MINIMUM: Smallest value
4255  MAXIMUM: Highest possible value
4256 */
4257 #define I2C_DESC_INSTNUM_W 4U
4258 #define I2C_DESC_INSTNUM_M 0x00000F00U
4259 #define I2C_DESC_INSTNUM_S 8U
4260 #define I2C_DESC_INSTNUM_MINIMUM 0x00000000U
4261 #define I2C_DESC_INSTNUM_MAXIMUM 0x00000F00U
4262 /*
4263 
4264  Field: FEATUREVER
4265  From..to bits: 12...15
4266  DefaultValue: 0x0
4267  Access type: read-only
4268  Description: Feature Set for the module *instance*
4269 
4270  ENUMs:
4271  MINIMUM: Smallest value
4272  MAXIMUM: Highest possible value
4273 */
4274 #define I2C_DESC_FEATUREVER_W 4U
4275 #define I2C_DESC_FEATUREVER_M 0x0000F000U
4276 #define I2C_DESC_FEATUREVER_S 12U
4277 #define I2C_DESC_FEATUREVER_MINIMUM 0x00000000U
4278 #define I2C_DESC_FEATUREVER_MAXIMUM 0x0000F000U
4279 /*
4280 
4281  Field: MODULEID
4282  From..to bits: 16...31
4283  DefaultValue: 0x0
4284  Access type: read-only
4285  Description: Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
4286 
4287  ENUMs:
4288  MINIMUM: Smallest value
4289  MAXIMUM: Highest possible value
4290 */
4291 #define I2C_DESC_MODULEID_W 16U
4292 #define I2C_DESC_MODULEID_M 0xFFFF0000U
4293 #define I2C_DESC_MODULEID_S 16U
4294 #define I2C_DESC_MODULEID_MINIMUM 0x00000000U
4295 #define I2C_DESC_MODULEID_MAXIMUM 0xFFFF0000U
4296 
4297 
4298 /*-----------------------------------REGISTER------------------------------------
4299  Register name: CLKCFG
4300  Offset name: I2C_O_CLKCFG
4301  Relative address: 0x1000
4302  Description: This register controls the bus clock to *I2C*
4303  Default Value: NA
4304 
4305  Field: ENABLE
4306  From..to bits: 0...0
4307  DefaultValue: NA
4308  Access type: read-write
4309  Description: This field enables or disables the bus clock to *I2C*
4310 
4311  ENUMs:
4312  DIS: I2C clock disabled
4313  EN: I2C clock disabled
4314 */
4315 #define I2C_CLKCFG_ENABLE 0x00000001U
4316 #define I2C_CLKCFG_ENABLE_M 0x00000001U
4317 #define I2C_CLKCFG_ENABLE_S 0U
4318 #define I2C_CLKCFG_ENABLE_DIS 0x00000000U
4319 #define I2C_CLKCFG_ENABLE_EN 0x00000001U
4320 
4321 #endif /* __HW_I2C_H__*/