CC35xxDriverLibrary
hw_hsm_sec.h
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1 /******************************************************************************
2 * Filename: hw_hsm_sec.h
3 *
4 * Description: Defines and prototypes for the HSM_SEC peripheral.
5 *
6 * Copyright (c) 2023, Texas Instruments Incorporated
7 * All rights reserved.
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13 * this list of conditions and the following disclaimer.
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35 ******************************************************************************/
36 #ifndef __HW_HSM_SEC_H__
37 #define __HW_HSM_SEC_H__
38 /*-------------------------------------------------------------------------------
39 
40 This section defines the register offsets of the HSM_SEC component
41 
42 --------------------------------------------------------------------------------- */
43 
44 //Clock Control Secured Register
45 #define HSM_SEC_O_CLKCTL 0x00000000U
46 
47 //Soft Reset Control
48 #define HSM_SEC_O_SRSTCTL 0x00000004U
49 
50 //PKA Abort Control Secured Register
51 #define HSM_SEC_O_PKACTL 0x00000008U
52 
53 //Debug Control
54 #define HSM_SEC_O_DBGCTL 0x0000000CU
55 
56 //DFT Control
57 #define HSM_SEC_O_DFTCTL 0x00000010U
58 
59 //Clock FRO Divide Configuration
60 #define HSM_SEC_O_CLKFRODIV 0x00000014U
61 
62 //Sleep Control
63 #define HSM_SEC_O_SLPCTL 0x00000018U
64 
65 
66 
67 /*-----------------------------------REGISTER------------------------------------
68  Register name: CLKCTL
69  Offset name: HSM_SEC_O_CLKCTL
70  Relative address: 0x0
71  Description: Clock Control Secured Register.
72 
73  This register is used for enabling clock to the module.
74  Default Value: 0x00000000
75 
76  Field: CLKGO
77  From..to bits: 0...0
78  DefaultValue: 0x0
79  Access type: read-write
80  Description: Write this bit to enable clock to the module
81 
82  ENUMs:
83  DIS: Write 0 to disable clock
84  EN: Write 1 to enable clock
85 */
86 #define HSM_SEC_CLKCTL_CLKGO 0x00000001U
87 #define HSM_SEC_CLKCTL_CLKGO_M 0x00000001U
88 #define HSM_SEC_CLKCTL_CLKGO_S 0U
89 #define HSM_SEC_CLKCTL_CLKGO_DIS 0x00000000U
90 #define HSM_SEC_CLKCTL_CLKGO_EN 0x00000001U
91 /*
92 
93  Field: HIFCLKGO
94  From..to bits: 1...1
95  DefaultValue: 0x0
96  Access type: read-write
97  Description: Write this bit to enable host interface clock
98 
99  ENUMs:
100  DIS: Write 0 to disable clock
101 
102  EN: Write 1 to enable clock
103 */
104 #define HSM_SEC_CLKCTL_HIFCLKGO 0x00000002U
105 #define HSM_SEC_CLKCTL_HIFCLKGO_M 0x00000002U
106 #define HSM_SEC_CLKCTL_HIFCLKGO_S 1U
107 #define HSM_SEC_CLKCTL_HIFCLKGO_DIS 0x00000000U
108 #define HSM_SEC_CLKCTL_HIFCLKGO_EN 0x00000002U
109 /*
110 
111  Field: CNTCLKGO
112  From..to bits: 2...2
113  DefaultValue: 0x0
114  Access type: read-write
115  Description: Write this bit to enable counter clock
116 
117  ENUMs:
118  DIS: Write 0 to disable clock
119 
120  EN: Write 1 to enable clock
121 */
122 #define HSM_SEC_CLKCTL_CNTCLKGO 0x00000004U
123 #define HSM_SEC_CLKCTL_CNTCLKGO_M 0x00000004U
124 #define HSM_SEC_CLKCTL_CNTCLKGO_S 2U
125 #define HSM_SEC_CLKCTL_CNTCLKGO_DIS 0x00000000U
126 #define HSM_SEC_CLKCTL_CNTCLKGO_EN 0x00000004U
127 /*
128 
129  Field: CLKDISREQ
130  From..to bits: 3...3
131  DefaultValue: 0x0
132  Access type: read-write
133  Description: This bit is set to disable all clock sources.
134 
135  ENUMs:
136  DIS: Write 1 to disable clock
137 */
138 #define HSM_SEC_CLKCTL_CLKDISREQ 0x00000008U
139 #define HSM_SEC_CLKCTL_CLKDISREQ_M 0x00000008U
140 #define HSM_SEC_CLKCTL_CLKDISREQ_S 3U
141 #define HSM_SEC_CLKCTL_CLKDISREQ_DIS 0x00000008U
142 /*
143 
144  Field: CLKBUSY
145  From..to bits: 4...4
146  DefaultValue: 0x0
147  Access type: read-only
148  Description: when 1b, indicates that the module is active and busy with processing data and tokens.
149 
150 */
151 #define HSM_SEC_CLKCTL_CLKBUSY 0x00000010U
152 #define HSM_SEC_CLKCTL_CLKBUSY_M 0x00000010U
153 #define HSM_SEC_CLKCTL_CLKBUSY_S 4U
154 /*
155 
156  Field: HIFCLKBUSY
157  From..to bits: 5...5
158  DefaultValue: 0x0
159  Access type: read-only
160  Description: When 1b indicates the Host interface is active and busy with Host bus transfers.
161 
162 */
163 #define HSM_SEC_CLKCTL_HIFCLKBUSY 0x00000020U
164 #define HSM_SEC_CLKCTL_HIFCLKBUSY_M 0x00000020U
165 #define HSM_SEC_CLKCTL_HIFCLKBUSY_S 5U
166 /*
167 
168  Field: CTLCLKBUSY
169  From..to bits: 6...6
170  DefaultValue: 0x0
171  Access type: read-only
172  Description: When 1b, indicates that the counter clock domain is active. This signal is always asserted (set to '1'), except when the
173  counter module is in reset (ctr_reset_n set to '0').
174 
175 */
176 #define HSM_SEC_CLKCTL_CTLCLKBUSY 0x00000040U
177 #define HSM_SEC_CLKCTL_CTLCLKBUSY_M 0x00000040U
178 #define HSM_SEC_CLKCTL_CTLCLKBUSY_S 6U
179 
180 
181 /*-----------------------------------REGISTER------------------------------------
182  Register name: SRSTCTL
183  Offset name: HSM_SEC_O_SRSTCTL
184  Relative address: 0x4
185  Description: Soft Reset Control.
186 
187  This register is used for controlling soft reset mechanism.
188  Default Value: 0x00000000
189 
190  Field: ABORTREQ
191  From..to bits: 0...0
192  DefaultValue: 0x0
193  Access type: write-only
194  Description: Write this bit to request soft reset. It is a write-clear or auto clear register.
195 
196  ENUMs:
197  REQ: To enable Abort request
198 */
199 #define HSM_SEC_SRSTCTL_ABORTREQ 0x00000001U
200 #define HSM_SEC_SRSTCTL_ABORTREQ_M 0x00000001U
201 #define HSM_SEC_SRSTCTL_ABORTREQ_S 0U
202 #define HSM_SEC_SRSTCTL_ABORTREQ_REQ 0x00000001U
203 /*
204 
205  Field: ABORTACK
206  From..to bits: 1...1
207  DefaultValue: 0x0
208  Access type: read-only
209  Description: when 1b, indicates abort request is acknowledged by EIP and soft reset is asserted
210 
211 */
212 #define HSM_SEC_SRSTCTL_ABORTACK 0x00000002U
213 #define HSM_SEC_SRSTCTL_ABORTACK_M 0x00000002U
214 #define HSM_SEC_SRSTCTL_ABORTACK_S 1U
215 /*
216 
217  Field: FRCACK
218  From..to bits: 2...2
219  DefaultValue: 0x0
220  Access type: write-only
221  Description: Write 1b, to forcely assert soft reset without waiting for abort acknowledge from EIP.
222 
223  ENUMs:
224  EN: To force soft reset
225 */
226 #define HSM_SEC_SRSTCTL_FRCACK 0x00000004U
227 #define HSM_SEC_SRSTCTL_FRCACK_M 0x00000004U
228 #define HSM_SEC_SRSTCTL_FRCACK_S 2U
229 #define HSM_SEC_SRSTCTL_FRCACK_EN 0x00000004U
230 /*
231 
232  Field: STA
233  From..to bits: 3...3
234  DefaultValue: 0x0
235  Access type: read-only
236  Description: When 1b, soft reset is asserted to the module
237 
238 */
239 #define HSM_SEC_SRSTCTL_STA 0x00000008U
240 #define HSM_SEC_SRSTCTL_STA_M 0x00000008U
241 #define HSM_SEC_SRSTCTL_STA_S 3U
242 /*
243 
244  Field: STATE
245  From..to bits: 4...6
246  DefaultValue: 0x0
247  Access type: read-only
248  Description: It indicates state of soft reset assertion.
249 
250  ENUMs:
251  IDLE: soft reset is not requested
252  REQ: Soft reset is requested
253  ACK: Soft reset is acknowledged.
254  ASSERT: Soft reset can be asserted
255  SET: soft reset is set
256 */
257 #define HSM_SEC_SRSTCTL_STATE_W 3U
258 #define HSM_SEC_SRSTCTL_STATE_M 0x00000070U
259 #define HSM_SEC_SRSTCTL_STATE_S 4U
260 #define HSM_SEC_SRSTCTL_STATE_IDLE 0x00000000U
261 #define HSM_SEC_SRSTCTL_STATE_REQ 0x00000010U
262 #define HSM_SEC_SRSTCTL_STATE_ACK 0x00000020U
263 #define HSM_SEC_SRSTCTL_STATE_ASSERT 0x00000030U
264 #define HSM_SEC_SRSTCTL_STATE_SET 0x00000040U
265 
266 
267 /*-----------------------------------REGISTER------------------------------------
268  Register name: PKACTL
269  Offset name: HSM_SEC_O_PKACTL
270  Relative address: 0x8
271  Description: PKA Abort Control Secured Register.
272 
273  This register is used for aborting PKA operation.
274  Default Value: 0x00000000
275 
276  Field: ABORT
277  From..to bits: 0...0
278  DefaultValue: 0x0
279  Access type: read-write
280  Description: Write 1 to Abort.
281 
282  ENUMs:
283  ABORT: Write 1 to this bit to abort PKA operation
284 */
285 #define HSM_SEC_PKACTL_ABORT 0x00000001U
286 #define HSM_SEC_PKACTL_ABORT_M 0x00000001U
287 #define HSM_SEC_PKACTL_ABORT_S 0U
288 #define HSM_SEC_PKACTL_ABORT_ABORT 0x00000001U
289 /*
290 
291  Field: NSMASKREQ
292  From..to bits: 1...1
293  DefaultValue: 0x0
294  Access type: read-write
295  Description: This bit is used to mask PKA abort request generated by non-secure controller.
296 
297  ENUMs:
298  MASK: Mask request
299 */
300 #define HSM_SEC_PKACTL_NSMASKREQ 0x00000002U
301 #define HSM_SEC_PKACTL_NSMASKREQ_M 0x00000002U
302 #define HSM_SEC_PKACTL_NSMASKREQ_S 1U
303 #define HSM_SEC_PKACTL_NSMASKREQ_MASK 0x00000002U
304 
305 
306 /*-----------------------------------REGISTER------------------------------------
307  Register name: DBGCTL
308  Offset name: HSM_SEC_O_DBGCTL
309  Relative address: 0xC
310  Description: Debug Control.
311 
312  This register is used for HSM memory and asset debug through OCP only if TI debug access is enabled
313  Default Value: 0x00000000
314 
315  Field: SEL
316  From..to bits: 0...6
317  DefaultValue: 0x0
318  Access type: read-write
319  Description: This register enables debug through OCP.
320  To enable FIFO0 , bit0 should be set.
321  To enable FIFO1 , bit1 should be set.
322  To enable MBIN , bit2 should be set.
323  To enable MBOUT, bit3 should be set.
324  To enable OTP , bit4 should be set.
325  To enable DRAM , bit5 should be set.
326  To enable PROM , bit6 should be set.
327 
328 */
329 #define HSM_SEC_DBGCTL_SEL_W 7U
330 #define HSM_SEC_DBGCTL_SEL_M 0x0000007FU
331 #define HSM_SEC_DBGCTL_SEL_S 0U
332 
333 
334 /*-----------------------------------REGISTER------------------------------------
335  Register name: DFTCTL
336  Offset name: HSM_SEC_O_DFTCTL
337  Relative address: 0x10
338  Description: DFT Control.
339 
340  This register is used for enabling FRO controls if TI test access is enabled
341  Default Value: 0x00000000
342 
343  Field: SEL
344  From..to bits: 0...4
345  DefaultValue: 0x0
346  Access type: read-write
347  Description: FRO selection input. A selected FRO will have its fro_testin input forced low. Valid value to select FRO's is 0-7.
348 
349 */
350 #define HSM_SEC_DFTCTL_SEL_W 5U
351 #define HSM_SEC_DFTCTL_SEL_M 0x0000001FU
352 #define HSM_SEC_DFTCTL_SEL_S 0U
353 /*
354 
355  Field: CTLEN
356  From..to bits: 5...5
357  DefaultValue: 0x0
358  Access type: read-write
359  Description: Active HIGH enable signal for FRO characterization (enables the tst_fro_select, tst_fro_enable and tst_fro_delay inputs).
360  This is a combinatorial function. The TRNG module clocks do not need to run for this to work.
361 
362 */
363 #define HSM_SEC_DFTCTL_CTLEN 0x00000020U
364 #define HSM_SEC_DFTCTL_CTLEN_M 0x00000020U
365 #define HSM_SEC_DFTCTL_CTLEN_S 5U
366 /*
367 
368  Field: ENABLE
369  From..to bits: 6...6
370  DefaultValue: 0x0
371  Access type: read-write
372  Description: Active HIGH enable signal for FRO selected by tst_fro_select
373 
374 */
375 #define HSM_SEC_DFTCTL_ENABLE 0x00000040U
376 #define HSM_SEC_DFTCTL_ENABLE_M 0x00000040U
377 #define HSM_SEC_DFTCTL_ENABLE_S 6U
378 /*
379 
380  Field: DLY
381  From..to bits: 7...7
382  DefaultValue: 0x0
383  Access type: read-write
384  Description: Delay chain length selection for FRO selected by tst_fro_select. This input should only be changed while
385  tst_fro_enable is LOW.
386 
387 */
388 #define HSM_SEC_DFTCTL_DLY 0x00000080U
389 #define HSM_SEC_DFTCTL_DLY_M 0x00000080U
390 #define HSM_SEC_DFTCTL_DLY_S 7U
391 
392 
393 /*-----------------------------------REGISTER------------------------------------
394  Register name: CLKFRODIV
395  Offset name: HSM_SEC_O_CLKFRODIV
396  Relative address: 0x14
397  Description: Clock FRO Divide Configuration.
398 
399  This register is used for controlling FRO clock measurements.
400  Default Value: 0x00000002
401 
402  Field: VAL
403  From..to bits: 0...6
404  DefaultValue: 0x2
405  Access type: read-write
406  Description: It is used for dividing FRO clock withe the division value specified by this register.
407  Division value should be from 2-80.
408 
409 */
410 #define HSM_SEC_CLKFRODIV_VAL_W 7U
411 #define HSM_SEC_CLKFRODIV_VAL_M 0x0000007FU
412 #define HSM_SEC_CLKFRODIV_VAL_S 0U
413 /*
414 
415  Field: EN
416  From..to bits: 7...7
417  DefaultValue: 0x0
418  Access type: read-write
419  Description: It is write enable signal used for loading division value onto divider.
420  It should be disable and re-enable after changing the mem_value
421 
422 */
423 #define HSM_SEC_CLKFRODIV_EN 0x00000080U
424 #define HSM_SEC_CLKFRODIV_EN_M 0x00000080U
425 #define HSM_SEC_CLKFRODIV_EN_S 7U
426 
427 
428 /*-----------------------------------REGISTER------------------------------------
429  Register name: SLPCTL
430  Offset name: HSM_SEC_O_SLPCTL
431  Relative address: 0x18
432  Description: Sleep Control.
433  Default Value: 0x00000000
434 
435  Field: OVRVAL
436  From..to bits: 0...0
437  DefaultValue: 0x0
438  Access type: read-write
439  Description: power_mode_in override value by FW. FW can set to 1 after cold boot
440 
441 */
442 #define HSM_SEC_SLPCTL_OVRVAL 0x00000001U
443 #define HSM_SEC_SLPCTL_OVRVAL_M 0x00000001U
444 #define HSM_SEC_SLPCTL_OVRVAL_S 0U
445 /*
446 
447  Field: SRCVAL
448  From..to bits: 1...1
449  DefaultValue: 0x0
450  Access type: read-write
451  Description: power_mode_in source select MMR
452  0-power_mode_in comes from logic
453  1-power_mode_in comes from mem_slp_ovr_val
454 
455 */
456 #define HSM_SEC_SLPCTL_SRCVAL 0x00000002U
457 #define HSM_SEC_SLPCTL_SRCVAL_M 0x00000002U
458 #define HSM_SEC_SLPCTL_SRCVAL_S 1U
459 
460 #endif /* __HW_HSM_SEC_H__*/