CC35xxDriverLibrary
Macros
hw_hostmcu_aon.h File Reference
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define HOSTMCU_AON_O_WUCSKPCFG   0x00000004U
 
#define HOSTMCU_AON_O_CFGWICSNS   0x00000008U
 
#define HOSTMCU_AON_O_CFGWUTP   0x0000000CU
 
#define HOSTMCU_AON_O_ELPTMREN   0x00000010U
 
#define HOSTMCU_AON_O_CFGTMRWU   0x00000014U
 
#define HOSTMCU_AON_O_TMRWUREQ   0x00000018U
 
#define HOSTMCU_AON_O_CFGWDT   0x0000001CU
 
#define HOSTMCU_AON_O_WDTREQ   0x00000020U
 
#define HOSTMCU_AON_O_GPWUAND   0x00000028U
 
#define HOSTMCU_AON_O_GPWUOR   0x0000002CU
 
#define HOSTMCU_AON_O_GPWUAND1   0x00000030U
 
#define HOSTMCU_AON_O_GPWUOR1   0x00000034U
 
#define HOSTMCU_AON_O_FCLKARM   0x00000038U
 
#define HOSTMCU_AON_O_SLPTIMES   0x0000003CU
 
#define HOSTMCU_AON_O_SLPTIMEF   0x00000040U
 
#define HOSTMCU_AON_O_WUREQ   0x0000004CU
 
#define HOSTMCU_AON_O_OREFCLK   0x00000050U
 
#define HOSTMCU_AON_O_WUC   0x0000005CU
 
#define HOSTMCU_AON_WUCSKPCFG_SKPPRCMVLD   0x00000001U
 
#define HOSTMCU_AON_WUCSKPCFG_SKPPRCMVLD_M   0x00000001U
 
#define HOSTMCU_AON_WUCSKPCFG_SKPPRCMVLD_S   0U
 
#define HOSTMCU_AON_WUCSKPCFG_SKPPRCMVLD_DIS   0x00000000U
 
#define HOSTMCU_AON_WUCSKPCFG_SKPPRCMVLD_EN   0x00000001U
 
#define HOSTMCU_AON_WUCSKPCFG_SKPPDVLD   0x00000002U
 
#define HOSTMCU_AON_WUCSKPCFG_SKPPDVLD_M   0x00000002U
 
#define HOSTMCU_AON_WUCSKPCFG_SKPPDVLD_S   1U
 
#define HOSTMCU_AON_WUCSKPCFG_SKPPDVLD_DIS   0x00000000U
 
#define HOSTMCU_AON_WUCSKPCFG_SKPPDVLD_EN   0x00000002U
 
#define HOSTMCU_AON_CFGWICSNS_VAL_W   18U
 
#define HOSTMCU_AON_CFGWICSNS_VAL_M   0x0003FFFFU
 
#define HOSTMCU_AON_CFGWICSNS_VAL_S   0U
 
#define HOSTMCU_AON_CFGWICSNS_VAL_DIS   0x00000000U
 
#define HOSTMCU_AON_CFGWICSNS_VAL_TMRREQ_EN   0x00000001U
 
#define HOSTMCU_AON_CFGWICSNS_VAL_WUSRC0_EN   0x00000002U
 
#define HOSTMCU_AON_CFGWICSNS_VAL_WUSRC1_EN   0x00000004U
 
#define HOSTMCU_AON_CFGWICSNS_VAL_DRBL0_EN   0x00000008U
 
#define HOSTMCU_AON_CFGWICSNS_VAL_DRBL1_EN   0x00000010U
 
#define HOSTMCU_AON_CFGWICSNS_VAL_DRBL2_EN   0x00000020U
 
#define HOSTMCU_AON_CFGWICSNS_VAL_DRBL3_EN   0x00000040U
 
#define HOSTMCU_AON_CFGWICSNS_VAL_DRBL4_EN   0x00000080U
 
#define HOSTMCU_AON_CFGWICSNS_VAL_DRBL5_EN   0x00000100U
 
#define HOSTMCU_AON_CFGWICSNS_VAL_DRBL6_EN   0x00000200U
 
#define HOSTMCU_AON_CFGWICSNS_VAL_DRBL7_EN   0x00000400U
 
#define HOSTMCU_AON_CFGWICSNS_VAL_NAB_EN   0x00000800U
 
#define HOSTMCU_AON_CFGWICSNS_VAL_BLERFCGPO_EN   0x00001000U
 
#define HOSTMCU_AON_CFGWICSNS_VAL_RTC_EN   0x00002000U
 
#define HOSTMCU_AON_CFGWICSNS_VAL_DBGPWRUP_EN   0x00004000U
 
#define HOSTMCU_AON_CFGWICSNS_VAL_DBGFRCACT_EN   0x00008000U
 
#define HOSTMCU_AON_CFGWICSNS_VAL_SECERR_EN   0x00010000U
 
#define HOSTMCU_AON_CFGWICSNS_VAL_COREWDT_EN   0x00020000U
 
#define HOSTMCU_AON_CFGWUTP_VAL_W   18U
 
#define HOSTMCU_AON_CFGWUTP_VAL_M   0x0003FFFFU
 
#define HOSTMCU_AON_CFGWUTP_VAL_S   0U
 
#define HOSTMCU_AON_CFGWUTP_VAL_SLOW   0x00000000U
 
#define HOSTMCU_AON_CFGWUTP_VAL_TMRREQ   0x00000001U
 
#define HOSTMCU_AON_CFGWUTP_VAL_WUSRC0   0x00000002U
 
#define HOSTMCU_AON_CFGWUTP_VAL_WUSRC1   0x00000004U
 
#define HOSTMCU_AON_CFGWUTP_VAL_DRBL0   0x00000008U
 
#define HOSTMCU_AON_CFGWUTP_VAL_DRBL1   0x00000010U
 
#define HOSTMCU_AON_CFGWUTP_VAL_DRBL2   0x00000020U
 
#define HOSTMCU_AON_CFGWUTP_VAL_DRBL3   0x00000040U
 
#define HOSTMCU_AON_CFGWUTP_VAL_DRBL4   0x00000080U
 
#define HOSTMCU_AON_CFGWUTP_VAL_DRBL5   0x00000100U
 
#define HOSTMCU_AON_CFGWUTP_VAL_DRBL6   0x00000200U
 
#define HOSTMCU_AON_CFGWUTP_VAL_DRBL7   0x00000400U
 
#define HOSTMCU_AON_CFGWUTP_VAL_NAB   0x00000800U
 
#define HOSTMCU_AON_CFGWUTP_VAL_BLERFCGPO   0x00001000U
 
#define HOSTMCU_AON_CFGWUTP_VAL_RTC   0x00002000U
 
#define HOSTMCU_AON_CFGWUTP_VAL_DBGPWRUP   0x00004000U
 
#define HOSTMCU_AON_CFGWUTP_VAL_DBGFRCACT   0x00008000U
 
#define HOSTMCU_AON_CFGWUTP_VAL_SECERR   0x00010000U
 
#define HOSTMCU_AON_CFGWUTP_VAL_COREWDT   0x00020000U
 
#define HOSTMCU_AON_ELPTMREN_VAL   0x00000001U
 
#define HOSTMCU_AON_ELPTMREN_VAL_M   0x00000001U
 
#define HOSTMCU_AON_ELPTMREN_VAL_S   0U
 
#define HOSTMCU_AON_ELPTMREN_VAL_DIS   0x00000000U
 
#define HOSTMCU_AON_ELPTMREN_VAL_EN   0x00000001U
 
#define HOSTMCU_AON_ELPTMREN_TMRSWCTL   0x00000002U
 
#define HOSTMCU_AON_ELPTMREN_TMRSWCTL_M   0x00000002U
 
#define HOSTMCU_AON_ELPTMREN_TMRSWCTL_S   1U
 
#define HOSTMCU_AON_ELPTMREN_TMRSWCTL_HW   0x00000000U
 
#define HOSTMCU_AON_ELPTMREN_TMRSWCTL_SW   0x00000002U
 
#define HOSTMCU_AON_ELPTMREN_ELPTMRSET   0x00000004U
 
#define HOSTMCU_AON_ELPTMREN_ELPTMRSET_M   0x00000004U
 
#define HOSTMCU_AON_ELPTMREN_ELPTMRSET_S   2U
 
#define HOSTMCU_AON_ELPTMREN_ELPTMRRST   0x00000008U
 
#define HOSTMCU_AON_ELPTMREN_ELPTMRRST_M   0x00000008U
 
#define HOSTMCU_AON_ELPTMREN_ELPTMRRST_S   3U
 
#define HOSTMCU_AON_ELPTMREN_ELPTMRLD   0x00010000U
 
#define HOSTMCU_AON_ELPTMREN_ELPTMRLD_M   0x00010000U
 
#define HOSTMCU_AON_ELPTMREN_ELPTMRLD_S   16U
 
#define HOSTMCU_AON_CFGTMRWU_THR_W   31U
 
#define HOSTMCU_AON_CFGTMRWU_THR_M   0x7FFFFFFFU
 
#define HOSTMCU_AON_CFGTMRWU_THR_S   0U
 
#define HOSTMCU_AON_CFGTMRWU_EN   0x80000000U
 
#define HOSTMCU_AON_CFGTMRWU_EN_M   0x80000000U
 
#define HOSTMCU_AON_CFGTMRWU_EN_S   31U
 
#define HOSTMCU_AON_CFGTMRWU_EN_DIS   0x00000000U
 
#define HOSTMCU_AON_CFGTMRWU_EN_EN   0x80000000U
 
#define HOSTMCU_AON_TMRWUREQ_CLR   0x00000001U
 
#define HOSTMCU_AON_TMRWUREQ_CLR_M   0x00000001U
 
#define HOSTMCU_AON_TMRWUREQ_CLR_S   0U
 
#define HOSTMCU_AON_CFGWDT_THR_W   23U
 
#define HOSTMCU_AON_CFGWDT_THR_M   0x7FFFFF00U
 
#define HOSTMCU_AON_CFGWDT_THR_S   8U
 
#define HOSTMCU_AON_CFGWDT_EN   0x80000000U
 
#define HOSTMCU_AON_CFGWDT_EN_M   0x80000000U
 
#define HOSTMCU_AON_CFGWDT_EN_S   31U
 
#define HOSTMCU_AON_CFGWDT_EN_DIS   0x00000000U
 
#define HOSTMCU_AON_CFGWDT_EN_EN   0x80000000U
 
#define HOSTMCU_AON_WDTREQ_CLR   0x00000001U
 
#define HOSTMCU_AON_WDTREQ_CLR_M   0x00000001U
 
#define HOSTMCU_AON_WDTREQ_CLR_S   0U
 
#define HOSTMCU_AON_GPWUAND_BM0T31_W   32U
 
#define HOSTMCU_AON_GPWUAND_BM0T31_M   0xFFFFFFFFU
 
#define HOSTMCU_AON_GPWUAND_BM0T31_S   0U
 
#define HOSTMCU_AON_GPWUOR_BM0T31_W   32U
 
#define HOSTMCU_AON_GPWUOR_BM0T31_M   0xFFFFFFFFU
 
#define HOSTMCU_AON_GPWUOR_BM0T31_S   0U
 
#define HOSTMCU_AON_GPWUAND1_BM32T44_W   13U
 
#define HOSTMCU_AON_GPWUAND1_BM32T44_M   0x00001FFFU
 
#define HOSTMCU_AON_GPWUAND1_BM32T44_S   0U
 
#define HOSTMCU_AON_GPWUOR1_BM32T44_W   13U
 
#define HOSTMCU_AON_GPWUOR1_BM32T44_M   0x00001FFFU
 
#define HOSTMCU_AON_GPWUOR1_BM32T44_S   0U
 
#define HOSTMCU_AON_FCLKARM_CMD_W   16U
 
#define HOSTMCU_AON_FCLKARM_CMD_M   0x0000FFFFU
 
#define HOSTMCU_AON_FCLKARM_CMD_S   0U
 
#define HOSTMCU_AON_SLPTIMES_CLK_W   32U
 
#define HOSTMCU_AON_SLPTIMES_CLK_M   0xFFFFFFFFU
 
#define HOSTMCU_AON_SLPTIMES_CLK_S   0U
 
#define HOSTMCU_AON_SLPTIMEF_CLK_W   11U
 
#define HOSTMCU_AON_SLPTIMEF_CLK_M   0x000007FFU
 
#define HOSTMCU_AON_SLPTIMEF_CLK_S   0U
 
#define HOSTMCU_AON_WUREQ_VAL_W   18U
 
#define HOSTMCU_AON_WUREQ_VAL_M   0x0003FFFFU
 
#define HOSTMCU_AON_WUREQ_VAL_S   0U
 
#define HOSTMCU_AON_WUREQ_VAL_CLEAR   0x00000000U
 
#define HOSTMCU_AON_WUREQ_VAL_TMRREQ   0x00000001U
 
#define HOSTMCU_AON_WUREQ_VAL_WUSRC0   0x00000002U
 
#define HOSTMCU_AON_WUREQ_VAL_WUSRC1   0x00000004U
 
#define HOSTMCU_AON_WUREQ_VAL_DRBL0   0x00000008U
 
#define HOSTMCU_AON_WUREQ_VAL_DRBL1   0x00000010U
 
#define HOSTMCU_AON_WUREQ_VAL_DRBL2   0x00000020U
 
#define HOSTMCU_AON_WUREQ_VAL_DRBL3   0x00000040U
 
#define HOSTMCU_AON_WUREQ_VAL_DRBL4   0x00000080U
 
#define HOSTMCU_AON_WUREQ_VAL_DRBL5   0x00000100U
 
#define HOSTMCU_AON_WUREQ_VAL_DRBL6   0x00000200U
 
#define HOSTMCU_AON_WUREQ_VAL_DRBL7   0x00000400U
 
#define HOSTMCU_AON_WUREQ_VAL_NAB   0x00000800U
 
#define HOSTMCU_AON_WUREQ_VAL_BLERFCGPO   0x00001000U
 
#define HOSTMCU_AON_WUREQ_VAL_RTC   0x00002000U
 
#define HOSTMCU_AON_WUREQ_VAL_DBGPWRUP   0x00004000U
 
#define HOSTMCU_AON_WUREQ_VAL_DBGFRCACT   0x00008000U
 
#define HOSTMCU_AON_WUREQ_VAL_SECERR   0x00010000U
 
#define HOSTMCU_AON_WUREQ_VAL_COREWDT   0x00020000U
 
#define HOSTMCU_AON_OREFCLK_SEL   0x00000001U
 
#define HOSTMCU_AON_OREFCLK_SEL_M   0x00000001U
 
#define HOSTMCU_AON_OREFCLK_SEL_S   0U
 
#define HOSTMCU_AON_OREFCLK_SEL_SEL_0   0x00000000U
 
#define HOSTMCU_AON_OREFCLK_SEL_SEL_1   0x00000001U
 
#define HOSTMCU_AON_WUC_STA_W   3U
 
#define HOSTMCU_AON_WUC_STA_M   0x00000007U
 
#define HOSTMCU_AON_WUC_STA_S   0U
 
#define HOSTMCU_AON_WUC_STA_RD_0   0x00000000U
 
#define HOSTMCU_AON_WUC_STA_RD_1   0x00000001U
 
#define HOSTMCU_AON_WUC_STA_RD_2   0x00000002U
 
#define HOSTMCU_AON_WUC_STA_RD_3   0x00000003U
 

Macro Definition Documentation

§ HOSTMCU_AON_O_WUCSKPCFG

#define HOSTMCU_AON_O_WUCSKPCFG   0x00000004U

§ HOSTMCU_AON_O_CFGWICSNS

#define HOSTMCU_AON_O_CFGWICSNS   0x00000008U

Referenced by WatchdogDisableWakeUpEvent(), and WatchdogEnableWakeUpEvent().

§ HOSTMCU_AON_O_CFGWUTP

#define HOSTMCU_AON_O_CFGWUTP   0x0000000CU

Referenced by WatchdogEnableWakeUpEvent().

§ HOSTMCU_AON_O_ELPTMREN

#define HOSTMCU_AON_O_ELPTMREN   0x00000010U

Referenced by WatchdogReset(), WatchdogSetSwMode(), WatchdogStartSequence(), WatchdogStatus(), and WatchdogStopSequence().

§ HOSTMCU_AON_O_CFGTMRWU

#define HOSTMCU_AON_O_CFGTMRWU   0x00000014U

Referenced by WatchdogDisableWakeUpEvent(), WatchdogEnableWakeUpEvent(), and WatchdogSetWakeUpThreshold().

§ HOSTMCU_AON_O_TMRWUREQ

#define HOSTMCU_AON_O_TMRWUREQ   0x00000018U

Referenced by WatchdogClearWakeUpEvent().

§ HOSTMCU_AON_O_CFGWDT

#define HOSTMCU_AON_O_CFGWDT   0x0000001CU

Referenced by WatchdogDisableResetEvent(), WatchdogEnableResetEvent(), and WatchdogSetResetThreshold().

§ HOSTMCU_AON_O_WDTREQ

#define HOSTMCU_AON_O_WDTREQ   0x00000020U

§ HOSTMCU_AON_O_GPWUAND

#define HOSTMCU_AON_O_GPWUAND   0x00000028U

§ HOSTMCU_AON_O_GPWUOR

#define HOSTMCU_AON_O_GPWUOR   0x0000002CU

§ HOSTMCU_AON_O_GPWUAND1

#define HOSTMCU_AON_O_GPWUAND1   0x00000030U

§ HOSTMCU_AON_O_GPWUOR1

#define HOSTMCU_AON_O_GPWUOR1   0x00000034U

§ HOSTMCU_AON_O_FCLKARM

#define HOSTMCU_AON_O_FCLKARM   0x00000038U

§ HOSTMCU_AON_O_SLPTIMES

#define HOSTMCU_AON_O_SLPTIMES   0x0000003CU

§ HOSTMCU_AON_O_SLPTIMEF

#define HOSTMCU_AON_O_SLPTIMEF   0x00000040U

§ HOSTMCU_AON_O_WUREQ

#define HOSTMCU_AON_O_WUREQ   0x0000004CU

§ HOSTMCU_AON_O_OREFCLK

#define HOSTMCU_AON_O_OREFCLK   0x00000050U

§ HOSTMCU_AON_O_WUC

#define HOSTMCU_AON_O_WUC   0x0000005CU

§ HOSTMCU_AON_WUCSKPCFG_SKPPRCMVLD

#define HOSTMCU_AON_WUCSKPCFG_SKPPRCMVLD   0x00000001U

§ HOSTMCU_AON_WUCSKPCFG_SKPPRCMVLD_M

#define HOSTMCU_AON_WUCSKPCFG_SKPPRCMVLD_M   0x00000001U

§ HOSTMCU_AON_WUCSKPCFG_SKPPRCMVLD_S

#define HOSTMCU_AON_WUCSKPCFG_SKPPRCMVLD_S   0U

§ HOSTMCU_AON_WUCSKPCFG_SKPPRCMVLD_DIS

#define HOSTMCU_AON_WUCSKPCFG_SKPPRCMVLD_DIS   0x00000000U

§ HOSTMCU_AON_WUCSKPCFG_SKPPRCMVLD_EN

#define HOSTMCU_AON_WUCSKPCFG_SKPPRCMVLD_EN   0x00000001U

§ HOSTMCU_AON_WUCSKPCFG_SKPPDVLD

#define HOSTMCU_AON_WUCSKPCFG_SKPPDVLD   0x00000002U

§ HOSTMCU_AON_WUCSKPCFG_SKPPDVLD_M

#define HOSTMCU_AON_WUCSKPCFG_SKPPDVLD_M   0x00000002U

§ HOSTMCU_AON_WUCSKPCFG_SKPPDVLD_S

#define HOSTMCU_AON_WUCSKPCFG_SKPPDVLD_S   1U

§ HOSTMCU_AON_WUCSKPCFG_SKPPDVLD_DIS

#define HOSTMCU_AON_WUCSKPCFG_SKPPDVLD_DIS   0x00000000U

§ HOSTMCU_AON_WUCSKPCFG_SKPPDVLD_EN

#define HOSTMCU_AON_WUCSKPCFG_SKPPDVLD_EN   0x00000002U

§ HOSTMCU_AON_CFGWICSNS_VAL_W

#define HOSTMCU_AON_CFGWICSNS_VAL_W   18U

§ HOSTMCU_AON_CFGWICSNS_VAL_M

#define HOSTMCU_AON_CFGWICSNS_VAL_M   0x0003FFFFU

§ HOSTMCU_AON_CFGWICSNS_VAL_S

#define HOSTMCU_AON_CFGWICSNS_VAL_S   0U

§ HOSTMCU_AON_CFGWICSNS_VAL_DIS

#define HOSTMCU_AON_CFGWICSNS_VAL_DIS   0x00000000U

§ HOSTMCU_AON_CFGWICSNS_VAL_TMRREQ_EN

#define HOSTMCU_AON_CFGWICSNS_VAL_TMRREQ_EN   0x00000001U

§ HOSTMCU_AON_CFGWICSNS_VAL_WUSRC0_EN

#define HOSTMCU_AON_CFGWICSNS_VAL_WUSRC0_EN   0x00000002U

§ HOSTMCU_AON_CFGWICSNS_VAL_WUSRC1_EN

#define HOSTMCU_AON_CFGWICSNS_VAL_WUSRC1_EN   0x00000004U

§ HOSTMCU_AON_CFGWICSNS_VAL_DRBL0_EN

#define HOSTMCU_AON_CFGWICSNS_VAL_DRBL0_EN   0x00000008U

§ HOSTMCU_AON_CFGWICSNS_VAL_DRBL1_EN

#define HOSTMCU_AON_CFGWICSNS_VAL_DRBL1_EN   0x00000010U

§ HOSTMCU_AON_CFGWICSNS_VAL_DRBL2_EN

#define HOSTMCU_AON_CFGWICSNS_VAL_DRBL2_EN   0x00000020U

§ HOSTMCU_AON_CFGWICSNS_VAL_DRBL3_EN

#define HOSTMCU_AON_CFGWICSNS_VAL_DRBL3_EN   0x00000040U

§ HOSTMCU_AON_CFGWICSNS_VAL_DRBL4_EN

#define HOSTMCU_AON_CFGWICSNS_VAL_DRBL4_EN   0x00000080U

§ HOSTMCU_AON_CFGWICSNS_VAL_DRBL5_EN

#define HOSTMCU_AON_CFGWICSNS_VAL_DRBL5_EN   0x00000100U

§ HOSTMCU_AON_CFGWICSNS_VAL_DRBL6_EN

#define HOSTMCU_AON_CFGWICSNS_VAL_DRBL6_EN   0x00000200U

§ HOSTMCU_AON_CFGWICSNS_VAL_DRBL7_EN

#define HOSTMCU_AON_CFGWICSNS_VAL_DRBL7_EN   0x00000400U

§ HOSTMCU_AON_CFGWICSNS_VAL_NAB_EN

#define HOSTMCU_AON_CFGWICSNS_VAL_NAB_EN   0x00000800U

§ HOSTMCU_AON_CFGWICSNS_VAL_BLERFCGPO_EN

#define HOSTMCU_AON_CFGWICSNS_VAL_BLERFCGPO_EN   0x00001000U

§ HOSTMCU_AON_CFGWICSNS_VAL_RTC_EN

#define HOSTMCU_AON_CFGWICSNS_VAL_RTC_EN   0x00002000U

§ HOSTMCU_AON_CFGWICSNS_VAL_DBGPWRUP_EN

#define HOSTMCU_AON_CFGWICSNS_VAL_DBGPWRUP_EN   0x00004000U

§ HOSTMCU_AON_CFGWICSNS_VAL_DBGFRCACT_EN

#define HOSTMCU_AON_CFGWICSNS_VAL_DBGFRCACT_EN   0x00008000U

§ HOSTMCU_AON_CFGWICSNS_VAL_SECERR_EN

#define HOSTMCU_AON_CFGWICSNS_VAL_SECERR_EN   0x00010000U

§ HOSTMCU_AON_CFGWICSNS_VAL_COREWDT_EN

#define HOSTMCU_AON_CFGWICSNS_VAL_COREWDT_EN   0x00020000U

§ HOSTMCU_AON_CFGWUTP_VAL_W

#define HOSTMCU_AON_CFGWUTP_VAL_W   18U

§ HOSTMCU_AON_CFGWUTP_VAL_M

#define HOSTMCU_AON_CFGWUTP_VAL_M   0x0003FFFFU

§ HOSTMCU_AON_CFGWUTP_VAL_S

#define HOSTMCU_AON_CFGWUTP_VAL_S   0U

§ HOSTMCU_AON_CFGWUTP_VAL_SLOW

#define HOSTMCU_AON_CFGWUTP_VAL_SLOW   0x00000000U

§ HOSTMCU_AON_CFGWUTP_VAL_TMRREQ

#define HOSTMCU_AON_CFGWUTP_VAL_TMRREQ   0x00000001U

§ HOSTMCU_AON_CFGWUTP_VAL_WUSRC0

#define HOSTMCU_AON_CFGWUTP_VAL_WUSRC0   0x00000002U

§ HOSTMCU_AON_CFGWUTP_VAL_WUSRC1

#define HOSTMCU_AON_CFGWUTP_VAL_WUSRC1   0x00000004U

§ HOSTMCU_AON_CFGWUTP_VAL_DRBL0

#define HOSTMCU_AON_CFGWUTP_VAL_DRBL0   0x00000008U

§ HOSTMCU_AON_CFGWUTP_VAL_DRBL1

#define HOSTMCU_AON_CFGWUTP_VAL_DRBL1   0x00000010U

§ HOSTMCU_AON_CFGWUTP_VAL_DRBL2

#define HOSTMCU_AON_CFGWUTP_VAL_DRBL2   0x00000020U

§ HOSTMCU_AON_CFGWUTP_VAL_DRBL3

#define HOSTMCU_AON_CFGWUTP_VAL_DRBL3   0x00000040U

§ HOSTMCU_AON_CFGWUTP_VAL_DRBL4

#define HOSTMCU_AON_CFGWUTP_VAL_DRBL4   0x00000080U

§ HOSTMCU_AON_CFGWUTP_VAL_DRBL5

#define HOSTMCU_AON_CFGWUTP_VAL_DRBL5   0x00000100U

§ HOSTMCU_AON_CFGWUTP_VAL_DRBL6

#define HOSTMCU_AON_CFGWUTP_VAL_DRBL6   0x00000200U

§ HOSTMCU_AON_CFGWUTP_VAL_DRBL7

#define HOSTMCU_AON_CFGWUTP_VAL_DRBL7   0x00000400U

§ HOSTMCU_AON_CFGWUTP_VAL_NAB

#define HOSTMCU_AON_CFGWUTP_VAL_NAB   0x00000800U

§ HOSTMCU_AON_CFGWUTP_VAL_BLERFCGPO

#define HOSTMCU_AON_CFGWUTP_VAL_BLERFCGPO   0x00001000U

§ HOSTMCU_AON_CFGWUTP_VAL_RTC

#define HOSTMCU_AON_CFGWUTP_VAL_RTC   0x00002000U

§ HOSTMCU_AON_CFGWUTP_VAL_DBGPWRUP

#define HOSTMCU_AON_CFGWUTP_VAL_DBGPWRUP   0x00004000U

§ HOSTMCU_AON_CFGWUTP_VAL_DBGFRCACT

#define HOSTMCU_AON_CFGWUTP_VAL_DBGFRCACT   0x00008000U

§ HOSTMCU_AON_CFGWUTP_VAL_SECERR

#define HOSTMCU_AON_CFGWUTP_VAL_SECERR   0x00010000U

§ HOSTMCU_AON_CFGWUTP_VAL_COREWDT

#define HOSTMCU_AON_CFGWUTP_VAL_COREWDT   0x00020000U

§ HOSTMCU_AON_ELPTMREN_VAL

#define HOSTMCU_AON_ELPTMREN_VAL   0x00000001U

§ HOSTMCU_AON_ELPTMREN_VAL_M

#define HOSTMCU_AON_ELPTMREN_VAL_M   0x00000001U

Referenced by WatchdogStatus().

§ HOSTMCU_AON_ELPTMREN_VAL_S

#define HOSTMCU_AON_ELPTMREN_VAL_S   0U

Referenced by WatchdogStatus().

§ HOSTMCU_AON_ELPTMREN_VAL_DIS

#define HOSTMCU_AON_ELPTMREN_VAL_DIS   0x00000000U

Referenced by WatchdogWaitUntilDisabled().

§ HOSTMCU_AON_ELPTMREN_VAL_EN

#define HOSTMCU_AON_ELPTMREN_VAL_EN   0x00000001U

Referenced by WatchdogWaitUntilEnabled().

§ HOSTMCU_AON_ELPTMREN_TMRSWCTL

#define HOSTMCU_AON_ELPTMREN_TMRSWCTL   0x00000002U

§ HOSTMCU_AON_ELPTMREN_TMRSWCTL_M

#define HOSTMCU_AON_ELPTMREN_TMRSWCTL_M   0x00000002U

§ HOSTMCU_AON_ELPTMREN_TMRSWCTL_S

#define HOSTMCU_AON_ELPTMREN_TMRSWCTL_S   1U

§ HOSTMCU_AON_ELPTMREN_TMRSWCTL_HW

#define HOSTMCU_AON_ELPTMREN_TMRSWCTL_HW   0x00000000U

§ HOSTMCU_AON_ELPTMREN_TMRSWCTL_SW

#define HOSTMCU_AON_ELPTMREN_TMRSWCTL_SW   0x00000002U

Referenced by WatchdogSetSwMode().

§ HOSTMCU_AON_ELPTMREN_ELPTMRSET

#define HOSTMCU_AON_ELPTMREN_ELPTMRSET   0x00000004U

Referenced by WatchdogStartSequence().

§ HOSTMCU_AON_ELPTMREN_ELPTMRSET_M

#define HOSTMCU_AON_ELPTMREN_ELPTMRSET_M   0x00000004U

§ HOSTMCU_AON_ELPTMREN_ELPTMRSET_S

#define HOSTMCU_AON_ELPTMREN_ELPTMRSET_S   2U

§ HOSTMCU_AON_ELPTMREN_ELPTMRRST

#define HOSTMCU_AON_ELPTMREN_ELPTMRRST   0x00000008U

Referenced by WatchdogStartSequence(), and WatchdogStopSequence().

§ HOSTMCU_AON_ELPTMREN_ELPTMRRST_M

#define HOSTMCU_AON_ELPTMREN_ELPTMRRST_M   0x00000008U

§ HOSTMCU_AON_ELPTMREN_ELPTMRRST_S

#define HOSTMCU_AON_ELPTMREN_ELPTMRRST_S   3U

§ HOSTMCU_AON_ELPTMREN_ELPTMRLD

#define HOSTMCU_AON_ELPTMREN_ELPTMRLD   0x00010000U

Referenced by WatchdogReset().

§ HOSTMCU_AON_ELPTMREN_ELPTMRLD_M

#define HOSTMCU_AON_ELPTMREN_ELPTMRLD_M   0x00010000U

§ HOSTMCU_AON_ELPTMREN_ELPTMRLD_S

#define HOSTMCU_AON_ELPTMREN_ELPTMRLD_S   16U

§ HOSTMCU_AON_CFGTMRWU_THR_W

#define HOSTMCU_AON_CFGTMRWU_THR_W   31U

§ HOSTMCU_AON_CFGTMRWU_THR_M

#define HOSTMCU_AON_CFGTMRWU_THR_M   0x7FFFFFFFU

Referenced by WatchdogSetWakeUpThreshold().

§ HOSTMCU_AON_CFGTMRWU_THR_S

#define HOSTMCU_AON_CFGTMRWU_THR_S   0U

§ HOSTMCU_AON_CFGTMRWU_EN

#define HOSTMCU_AON_CFGTMRWU_EN   0x80000000U

Referenced by WatchdogDisableWakeUpEvent(), and WatchdogEnableWakeUpEvent().

§ HOSTMCU_AON_CFGTMRWU_EN_M

#define HOSTMCU_AON_CFGTMRWU_EN_M   0x80000000U

§ HOSTMCU_AON_CFGTMRWU_EN_S

#define HOSTMCU_AON_CFGTMRWU_EN_S   31U

§ HOSTMCU_AON_CFGTMRWU_EN_DIS

#define HOSTMCU_AON_CFGTMRWU_EN_DIS   0x00000000U

§ HOSTMCU_AON_CFGTMRWU_EN_EN

#define HOSTMCU_AON_CFGTMRWU_EN_EN   0x80000000U

§ HOSTMCU_AON_TMRWUREQ_CLR

#define HOSTMCU_AON_TMRWUREQ_CLR   0x00000001U

§ HOSTMCU_AON_TMRWUREQ_CLR_M

#define HOSTMCU_AON_TMRWUREQ_CLR_M   0x00000001U

Referenced by WatchdogClearWakeUpEvent().

§ HOSTMCU_AON_TMRWUREQ_CLR_S

#define HOSTMCU_AON_TMRWUREQ_CLR_S   0U

§ HOSTMCU_AON_CFGWDT_THR_W

#define HOSTMCU_AON_CFGWDT_THR_W   23U

§ HOSTMCU_AON_CFGWDT_THR_M

#define HOSTMCU_AON_CFGWDT_THR_M   0x7FFFFF00U

Referenced by WatchdogSetResetThreshold(), and WatchdogSetWakeUpThreshold().

§ HOSTMCU_AON_CFGWDT_THR_S

#define HOSTMCU_AON_CFGWDT_THR_S   8U

Referenced by WatchdogSetResetThreshold(), and WatchdogSetWakeUpThreshold().

§ HOSTMCU_AON_CFGWDT_EN

#define HOSTMCU_AON_CFGWDT_EN   0x80000000U

Referenced by WatchdogDisableResetEvent(), and WatchdogEnableResetEvent().

§ HOSTMCU_AON_CFGWDT_EN_M

#define HOSTMCU_AON_CFGWDT_EN_M   0x80000000U

§ HOSTMCU_AON_CFGWDT_EN_S

#define HOSTMCU_AON_CFGWDT_EN_S   31U

§ HOSTMCU_AON_CFGWDT_EN_DIS

#define HOSTMCU_AON_CFGWDT_EN_DIS   0x00000000U

§ HOSTMCU_AON_CFGWDT_EN_EN

#define HOSTMCU_AON_CFGWDT_EN_EN   0x80000000U

§ HOSTMCU_AON_WDTREQ_CLR

#define HOSTMCU_AON_WDTREQ_CLR   0x00000001U

§ HOSTMCU_AON_WDTREQ_CLR_M

#define HOSTMCU_AON_WDTREQ_CLR_M   0x00000001U

§ HOSTMCU_AON_WDTREQ_CLR_S

#define HOSTMCU_AON_WDTREQ_CLR_S   0U

§ HOSTMCU_AON_GPWUAND_BM0T31_W

#define HOSTMCU_AON_GPWUAND_BM0T31_W   32U

§ HOSTMCU_AON_GPWUAND_BM0T31_M

#define HOSTMCU_AON_GPWUAND_BM0T31_M   0xFFFFFFFFU

§ HOSTMCU_AON_GPWUAND_BM0T31_S

#define HOSTMCU_AON_GPWUAND_BM0T31_S   0U

§ HOSTMCU_AON_GPWUOR_BM0T31_W

#define HOSTMCU_AON_GPWUOR_BM0T31_W   32U

§ HOSTMCU_AON_GPWUOR_BM0T31_M

#define HOSTMCU_AON_GPWUOR_BM0T31_M   0xFFFFFFFFU

§ HOSTMCU_AON_GPWUOR_BM0T31_S

#define HOSTMCU_AON_GPWUOR_BM0T31_S   0U

§ HOSTMCU_AON_GPWUAND1_BM32T44_W

#define HOSTMCU_AON_GPWUAND1_BM32T44_W   13U

§ HOSTMCU_AON_GPWUAND1_BM32T44_M

#define HOSTMCU_AON_GPWUAND1_BM32T44_M   0x00001FFFU

§ HOSTMCU_AON_GPWUAND1_BM32T44_S

#define HOSTMCU_AON_GPWUAND1_BM32T44_S   0U

§ HOSTMCU_AON_GPWUOR1_BM32T44_W

#define HOSTMCU_AON_GPWUOR1_BM32T44_W   13U

§ HOSTMCU_AON_GPWUOR1_BM32T44_M

#define HOSTMCU_AON_GPWUOR1_BM32T44_M   0x00001FFFU

§ HOSTMCU_AON_GPWUOR1_BM32T44_S

#define HOSTMCU_AON_GPWUOR1_BM32T44_S   0U

§ HOSTMCU_AON_FCLKARM_CMD_W

#define HOSTMCU_AON_FCLKARM_CMD_W   16U

§ HOSTMCU_AON_FCLKARM_CMD_M

#define HOSTMCU_AON_FCLKARM_CMD_M   0x0000FFFFU

§ HOSTMCU_AON_FCLKARM_CMD_S

#define HOSTMCU_AON_FCLKARM_CMD_S   0U

§ HOSTMCU_AON_SLPTIMES_CLK_W

#define HOSTMCU_AON_SLPTIMES_CLK_W   32U

§ HOSTMCU_AON_SLPTIMES_CLK_M

#define HOSTMCU_AON_SLPTIMES_CLK_M   0xFFFFFFFFU

§ HOSTMCU_AON_SLPTIMES_CLK_S

#define HOSTMCU_AON_SLPTIMES_CLK_S   0U

§ HOSTMCU_AON_SLPTIMEF_CLK_W

#define HOSTMCU_AON_SLPTIMEF_CLK_W   11U

§ HOSTMCU_AON_SLPTIMEF_CLK_M

#define HOSTMCU_AON_SLPTIMEF_CLK_M   0x000007FFU

§ HOSTMCU_AON_SLPTIMEF_CLK_S

#define HOSTMCU_AON_SLPTIMEF_CLK_S   0U

§ HOSTMCU_AON_WUREQ_VAL_W

#define HOSTMCU_AON_WUREQ_VAL_W   18U

§ HOSTMCU_AON_WUREQ_VAL_M

#define HOSTMCU_AON_WUREQ_VAL_M   0x0003FFFFU

§ HOSTMCU_AON_WUREQ_VAL_S

#define HOSTMCU_AON_WUREQ_VAL_S   0U

§ HOSTMCU_AON_WUREQ_VAL_CLEAR

#define HOSTMCU_AON_WUREQ_VAL_CLEAR   0x00000000U

§ HOSTMCU_AON_WUREQ_VAL_TMRREQ

#define HOSTMCU_AON_WUREQ_VAL_TMRREQ   0x00000001U

§ HOSTMCU_AON_WUREQ_VAL_WUSRC0

#define HOSTMCU_AON_WUREQ_VAL_WUSRC0   0x00000002U

§ HOSTMCU_AON_WUREQ_VAL_WUSRC1

#define HOSTMCU_AON_WUREQ_VAL_WUSRC1   0x00000004U

§ HOSTMCU_AON_WUREQ_VAL_DRBL0

#define HOSTMCU_AON_WUREQ_VAL_DRBL0   0x00000008U

§ HOSTMCU_AON_WUREQ_VAL_DRBL1

#define HOSTMCU_AON_WUREQ_VAL_DRBL1   0x00000010U

§ HOSTMCU_AON_WUREQ_VAL_DRBL2

#define HOSTMCU_AON_WUREQ_VAL_DRBL2   0x00000020U

§ HOSTMCU_AON_WUREQ_VAL_DRBL3

#define HOSTMCU_AON_WUREQ_VAL_DRBL3   0x00000040U

§ HOSTMCU_AON_WUREQ_VAL_DRBL4

#define HOSTMCU_AON_WUREQ_VAL_DRBL4   0x00000080U

§ HOSTMCU_AON_WUREQ_VAL_DRBL5

#define HOSTMCU_AON_WUREQ_VAL_DRBL5   0x00000100U

§ HOSTMCU_AON_WUREQ_VAL_DRBL6

#define HOSTMCU_AON_WUREQ_VAL_DRBL6   0x00000200U

§ HOSTMCU_AON_WUREQ_VAL_DRBL7

#define HOSTMCU_AON_WUREQ_VAL_DRBL7   0x00000400U

§ HOSTMCU_AON_WUREQ_VAL_NAB

#define HOSTMCU_AON_WUREQ_VAL_NAB   0x00000800U

§ HOSTMCU_AON_WUREQ_VAL_BLERFCGPO

#define HOSTMCU_AON_WUREQ_VAL_BLERFCGPO   0x00001000U

§ HOSTMCU_AON_WUREQ_VAL_RTC

#define HOSTMCU_AON_WUREQ_VAL_RTC   0x00002000U

§ HOSTMCU_AON_WUREQ_VAL_DBGPWRUP

#define HOSTMCU_AON_WUREQ_VAL_DBGPWRUP   0x00004000U

§ HOSTMCU_AON_WUREQ_VAL_DBGFRCACT

#define HOSTMCU_AON_WUREQ_VAL_DBGFRCACT   0x00008000U

§ HOSTMCU_AON_WUREQ_VAL_SECERR

#define HOSTMCU_AON_WUREQ_VAL_SECERR   0x00010000U

§ HOSTMCU_AON_WUREQ_VAL_COREWDT

#define HOSTMCU_AON_WUREQ_VAL_COREWDT   0x00020000U

§ HOSTMCU_AON_OREFCLK_SEL

#define HOSTMCU_AON_OREFCLK_SEL   0x00000001U

§ HOSTMCU_AON_OREFCLK_SEL_M

#define HOSTMCU_AON_OREFCLK_SEL_M   0x00000001U

§ HOSTMCU_AON_OREFCLK_SEL_S

#define HOSTMCU_AON_OREFCLK_SEL_S   0U

§ HOSTMCU_AON_OREFCLK_SEL_SEL_0

#define HOSTMCU_AON_OREFCLK_SEL_SEL_0   0x00000000U

§ HOSTMCU_AON_OREFCLK_SEL_SEL_1

#define HOSTMCU_AON_OREFCLK_SEL_SEL_1   0x00000001U

§ HOSTMCU_AON_WUC_STA_W

#define HOSTMCU_AON_WUC_STA_W   3U

§ HOSTMCU_AON_WUC_STA_M

#define HOSTMCU_AON_WUC_STA_M   0x00000007U

§ HOSTMCU_AON_WUC_STA_S

#define HOSTMCU_AON_WUC_STA_S   0U

§ HOSTMCU_AON_WUC_STA_RD_0

#define HOSTMCU_AON_WUC_STA_RD_0   0x00000000U

§ HOSTMCU_AON_WUC_STA_RD_1

#define HOSTMCU_AON_WUC_STA_RD_1   0x00000001U

§ HOSTMCU_AON_WUC_STA_RD_2

#define HOSTMCU_AON_WUC_STA_RD_2   0x00000002U

§ HOSTMCU_AON_WUC_STA_RD_3

#define HOSTMCU_AON_WUC_STA_RD_3   0x00000003U