![]() |
![]() |
|
CC35xxDriverLibrary
|

Go to the source code of this file.
| #define HOST_XIP_O_ARBCTL 0x00000000U |
| #define HOST_XIP_O_ARBHALT 0x00000004U |
| #define HOST_XIP_O_ARBCFG0 0x00000008U |
| #define HOST_XIP_O_ARBCFG1 0x0000000CU |
| #define HOST_XIP_O_ARBCFG2 0x00000010U |
| #define HOST_XIP_O_SWCHDLY 0x00000014U |
| #define HOST_XIP_O_RCMCLKDIS 0x00000020U |
| #define HOST_XIP_O_RCMCLKFRC 0x00000024U |
| #define HOST_XIP_O_RCMCLKSTA 0x00000028U |
| #define HOST_XIP_O_OSPICFG 0x00000040U |
| #define HOST_XIP_O_UDSCFG0 0x00001000U |
Referenced by XIPStartUDMATransaction().
| #define HOST_XIP_O_UDSCFG1 0x00001004U |
Referenced by XIPStartUDMATransaction().
| #define HOST_XIP_O_UDSCFG2 0x00001008U |
Referenced by XIPStartUDMATransaction().
| #define HOST_XIP_O_UDSCFG3 0x0000100CU |
Referenced by XIPStartUDMATransaction().
| #define HOST_XIP_O_UDSCTL0 0x00001010U |
Referenced by XIPStartUDMATransaction().
| #define HOST_XIP_O_UDSCTL1 0x00001014U |
| #define HOST_XIP_O_UDSSTA 0x00001020U |
Referenced by XIPGetUDMAChannelProgressingStatus(), XIPGetUDMAChannelWordsLeft(), and XIPStartUDMATransaction().
| #define HOST_XIP_O_UDSIRQ 0x00001024U |
Referenced by XIPGetUDMAIrqStatus().
| #define HOST_XIP_O_UDSSTA1 0x0000102CU |
| #define HOST_XIP_O_UDSPERCFG 0x00001040U |
| #define HOST_XIP_O_UDSPERSEL 0x00001060U |
| #define HOST_XIP_O_UDNSPERSEL 0x00001064U |
| #define HOST_XIP_O_UDNSCFG0 0x00002000U |
| #define HOST_XIP_O_UDNSCFG1 0x00002004U |
| #define HOST_XIP_O_UDNSCFG2 0x00002008U |
| #define HOST_XIP_O_UDNSCFG3 0x0000200CU |
| #define HOST_XIP_O_UDNSCTL0 0x00002010U |
| #define HOST_XIP_O_UDNSCTL1 0x00002014U |
| #define HOST_XIP_O_UDNSSTA 0x00002020U |
| #define HOST_XIP_O_UDNSIRQ 0x00002024U |
| #define HOST_XIP_O_UTHRCNF 0x00002028U |
| #define HOST_XIP_O_UDNSSTA1 0x0000202CU |
| #define HOST_XIP_O_UDNSPERCFG 0x00002040U |
| #define HOST_XIP_O_OTOSMEM 0x00003000U |
| #define HOST_XIP_O_OTPRTCFG 0x00004000U |
| #define HOST_XIP_O_RGN0CFG0 0x00004004U |
| #define HOST_XIP_O_RGN0CFG1 0x00004008U |
| #define HOST_XIP_O_RGN0CFG2 0x0000400CU |
| #define HOST_XIP_O_RGN0CFG3 0x00004010U |
| #define HOST_XIP_O_RGN0CFG4 0x00004014U |
| #define HOST_XIP_O_RGN0CFG5 0x00004018U |
| #define HOST_XIP_O_RGN1CFG0 0x00004020U |
| #define HOST_XIP_O_RGN1CFG1 0x00004024U |
| #define HOST_XIP_O_RGN1CFG2 0x00004028U |
| #define HOST_XIP_O_RGN1CFG3 0x0000402CU |
| #define HOST_XIP_O_RGN1CFG4 0x00004030U |
| #define HOST_XIP_O_RGN1CFG5 0x00004034U |
| #define HOST_XIP_O_RGN2CFG0 0x00004040U |
| #define HOST_XIP_O_RGN2CFG1 0x00004044U |
| #define HOST_XIP_O_RGN2CFG2 0x00004048U |
| #define HOST_XIP_O_RGN2CFG3 0x0000404CU |
| #define HOST_XIP_O_RGN2CFG4 0x00004050U |
| #define HOST_XIP_O_RGN2CFG5 0x00004054U |
| #define HOST_XIP_O_RGN3CFG0 0x00004060U |
| #define HOST_XIP_O_RGN3CFG1 0x00004064U |
| #define HOST_XIP_O_RGN3CFG2 0x00004068U |
| #define HOST_XIP_O_RGN3CFG3 0x0000406CU |
| #define HOST_XIP_O_RGN3CFG4 0x00004070U |
| #define HOST_XIP_O_RGN3CFG5 0x00004074U |
| #define HOST_XIP_O_OTSWCTL0 0x00005000U |
Referenced by __attribute__().
| #define HOST_XIP_O_OTSWCTL1 0x00005004U |
Referenced by __attribute__().
| #define HOST_XIP_O_OTSWCTL2 0x00005008U |
| #define HOST_XIP_O_OTSWCTL3 0x0000500CU |
| #define HOST_XIP_O_OTSWCTL4 0x00005010U |
| #define HOST_XIP_O_OTSTA 0x00005020U |
Referenced by __attribute__().
| #define HOST_XIP_O_OTINDSTA 0x00005030U |
| #define HOST_XIP_O_OTINDMASK 0x00005040U |
| #define HOST_XIP_O_OTINDNEXT 0x00005050U |
| #define HOST_XIP_O_OTSTGSEL 0x00005060U |
| #define HOST_XIP_O_OTD0CFG 0x00005070U |
| #define HOST_XIP_O_OTD0PTMR 0x00005074U |
| #define HOST_XIP_O_OTD0WRAP 0x00005078U |
| #define HOST_XIP_O_OTD1CFG 0x00005080U |
| #define HOST_XIP_O_OTD1WRAP 0x00005084U |
| #define HOST_XIP_O_OTGLBTMR 0x00005090U |
| #define HOST_XIP_O_OTR0CFG0 0x00006000U |
| #define HOST_XIP_O_OTR0CFG1 0x00006004U |
| #define HOST_XIP_O_OTR0CFG2 0x00006008U |
| #define HOST_XIP_O_OTR0CFG3 0x0000600CU |
| #define HOST_XIP_O_OTR1CFG0 0x00007000U |
| #define HOST_XIP_O_OTR1CFG1 0x00007004U |
| #define HOST_XIP_O_OTR1CFG2 0x00007008U |
| #define HOST_XIP_O_OTR1CFG3 0x0000700CU |
| #define HOST_XIP_O_OTR2CFG0 0x00008000U |
| #define HOST_XIP_O_OTR2CFG1 0x00008004U |
| #define HOST_XIP_O_OTR2CFG2 0x00008008U |
| #define HOST_XIP_O_OTR2CFG3 0x0000800CU |
| #define HOST_XIP_O_OTR3CFG0 0x00009000U |
| #define HOST_XIP_O_OTR3CFG1 0x00009004U |
| #define HOST_XIP_O_OTR3CFG2 0x00009008U |
| #define HOST_XIP_O_OTR3CFG3 0x0000900CU |
| #define HOST_XIP_ARBCTL_WRR 0x00000001U |
| #define HOST_XIP_ARBCTL_WRR_M 0x00000001U |
| #define HOST_XIP_ARBCTL_WRR_S 0U |
| #define HOST_XIP_ARBCTL_WRRCFG 0x00000002U |
| #define HOST_XIP_ARBCTL_WRRCFG_M 0x00000002U |
| #define HOST_XIP_ARBCTL_WRRCFG_S 1U |
| #define HOST_XIP_ARBHALT_EN 0x00000001U |
| #define HOST_XIP_ARBHALT_EN_M 0x00000001U |
| #define HOST_XIP_ARBHALT_EN_S 0U |
| #define HOST_XIP_ARBHALT_STS 0x00000002U |
| #define HOST_XIP_ARBHALT_STS_M 0x00000002U |
| #define HOST_XIP_ARBHALT_STS_S 1U |
| #define HOST_XIP_ARBCFG0_NUMWORDS_W 13U |
| #define HOST_XIP_ARBCFG0_NUMWORDS_M 0x00001FFFU |
| #define HOST_XIP_ARBCFG0_NUMWORDS_S 0U |
| #define HOST_XIP_ARBCFG0_FIXPRI_W 2U |
| #define HOST_XIP_ARBCFG0_FIXPRI_M 0x00030000U |
| #define HOST_XIP_ARBCFG0_FIXPRI_S 16U |
| #define HOST_XIP_ARBCFG0_TRANSDLY_W 5U |
| #define HOST_XIP_ARBCFG0_TRANSDLY_M 0x1F000000U |
| #define HOST_XIP_ARBCFG0_TRANSDLY_S 24U |
| #define HOST_XIP_ARBCFG1_NUMWORDS_W 13U |
| #define HOST_XIP_ARBCFG1_NUMWORDS_M 0x00001FFFU |
| #define HOST_XIP_ARBCFG1_NUMWORDS_S 0U |
| #define HOST_XIP_ARBCFG1_FIXPRI_W 2U |
| #define HOST_XIP_ARBCFG1_FIXPRI_M 0x00030000U |
| #define HOST_XIP_ARBCFG1_FIXPRI_S 16U |
| #define HOST_XIP_ARBCFG1_TRANSDLY_W 5U |
| #define HOST_XIP_ARBCFG1_TRANSDLY_M 0x1F000000U |
| #define HOST_XIP_ARBCFG1_TRANSDLY_S 24U |
| #define HOST_XIP_ARBCFG2_NUMWORDS_W 13U |
| #define HOST_XIP_ARBCFG2_NUMWORDS_M 0x00001FFFU |
| #define HOST_XIP_ARBCFG2_NUMWORDS_S 0U |
| #define HOST_XIP_ARBCFG2_FIXPRI_W 2U |
| #define HOST_XIP_ARBCFG2_FIXPRI_M 0x00030000U |
| #define HOST_XIP_ARBCFG2_FIXPRI_S 16U |
| #define HOST_XIP_ARBCFG2_TRANSDLY_W 5U |
| #define HOST_XIP_ARBCFG2_TRANSDLY_M 0x1F000000U |
| #define HOST_XIP_ARBCFG2_TRANSDLY_S 24U |
| #define HOST_XIP_SWCHDLY_DEVSWCHDLY_W 2U |
| #define HOST_XIP_SWCHDLY_DEVSWCHDLY_M 0x00000003U |
| #define HOST_XIP_SWCHDLY_DEVSWCHDLY_S 0U |
| #define HOST_XIP_SWCHDLY_DEVSWCHDLY_SEL0 0x00000000U |
| #define HOST_XIP_SWCHDLY_DEVSWCHDLY_SEL1 0x00000001U |
| #define HOST_XIP_SWCHDLY_DEVSWCHDLY_SEL2 0x00000002U |
| #define HOST_XIP_SWCHDLY_DEVSWCHDLY_SEL3 0x00000003U |
| #define HOST_XIP_RCMCLKDIS_HOSTXIP 0x00000001U |
| #define HOST_XIP_RCMCLKDIS_HOSTXIP_M 0x00000001U |
| #define HOST_XIP_RCMCLKDIS_HOSTXIP_S 0U |
| #define HOST_XIP_RCMCLKDIS_SOC 0x00000002U |
| #define HOST_XIP_RCMCLKDIS_SOC_M 0x00000002U |
| #define HOST_XIP_RCMCLKDIS_SOC_S 1U |
| #define HOST_XIP_RCMCLKDIS_OSPIREF 0x00000004U |
| #define HOST_XIP_RCMCLKDIS_OSPIREF_M 0x00000004U |
| #define HOST_XIP_RCMCLKDIS_OSPIREF_S 2U |
| #define HOST_XIP_RCMCLKFRC_HOSTXIP 0x00000001U |
| #define HOST_XIP_RCMCLKFRC_HOSTXIP_M 0x00000001U |
| #define HOST_XIP_RCMCLKFRC_HOSTXIP_S 0U |
| #define HOST_XIP_RCMCLKFRC_SOC 0x00000002U |
| #define HOST_XIP_RCMCLKFRC_SOC_M 0x00000002U |
| #define HOST_XIP_RCMCLKFRC_SOC_S 1U |
| #define HOST_XIP_RCMCLKFRC_OSPIREF 0x00000004U |
| #define HOST_XIP_RCMCLKFRC_OSPIREF_M 0x00000004U |
| #define HOST_XIP_RCMCLKFRC_OSPIREF_S 2U |
| #define HOST_XIP_RCMCLKSTA_HOSTXIP 0x00000001U |
| #define HOST_XIP_RCMCLKSTA_HOSTXIP_M 0x00000001U |
| #define HOST_XIP_RCMCLKSTA_HOSTXIP_S 0U |
| #define HOST_XIP_RCMCLKSTA_SOC 0x00000002U |
| #define HOST_XIP_RCMCLKSTA_SOC_M 0x00000002U |
| #define HOST_XIP_RCMCLKSTA_SOC_S 1U |
| #define HOST_XIP_RCMCLKSTA_OSPIREF 0x00000004U |
| #define HOST_XIP_RCMCLKSTA_OSPIREF_M 0x00000004U |
| #define HOST_XIP_RCMCLKSTA_OSPIREF_S 2U |
| #define HOST_XIP_OSPICFG_HLDFIXEN 0x00000001U |
| #define HOST_XIP_OSPICFG_HLDFIXEN_M 0x00000001U |
| #define HOST_XIP_OSPICFG_HLDFIXEN_S 0U |
| #define HOST_XIP_OSPICFG_HLDFIXEN_DIS 0x00000000U |
| #define HOST_XIP_OSPICFG_HLDFIXEN_EN 0x00000001U |
| #define HOST_XIP_OSPICFG_GLTFIXEN 0x00000002U |
| #define HOST_XIP_OSPICFG_GLTFIXEN_M 0x00000002U |
| #define HOST_XIP_OSPICFG_GLTFIXEN_S 1U |
| #define HOST_XIP_OSPICFG_GLTFIXEN_DIS 0x00000000U |
| #define HOST_XIP_OSPICFG_GLTFIXEN_EN 0x00000002U |
| #define HOST_XIP_UDSCFG0_JSRCADDR_W 32U |
| #define HOST_XIP_UDSCFG0_JSRCADDR_M 0xFFFFFFFFU |
Referenced by XIPStartUDMATransaction().
| #define HOST_XIP_UDSCFG0_JSRCADDR_S 0U |
Referenced by XIPStartUDMATransaction().
| #define HOST_XIP_UDSCFG1_JDESTADDR_W 32U |
| #define HOST_XIP_UDSCFG1_JDESTADDR_M 0xFFFFFFFFU |
Referenced by XIPStartUDMATransaction().
| #define HOST_XIP_UDSCFG1_JDESTADDR_S 0U |
Referenced by XIPStartUDMATransaction().
| #define HOST_XIP_UDSCFG2_JLEN_W 18U |
| #define HOST_XIP_UDSCFG2_JLEN_M 0x0003FFFFU |
Referenced by XIPStartUDMATransaction().
| #define HOST_XIP_UDSCFG2_JLEN_S 0U |
Referenced by XIPStartUDMATransaction().
| #define HOST_XIP_UDSCFG3_JDIR 0x00000001U |
| #define HOST_XIP_UDSCFG3_JDIR_M 0x00000001U |
Referenced by XIPStartUDMATransaction().
| #define HOST_XIP_UDSCFG3_JDIR_S 0U |
Referenced by XIPStartUDMATransaction().
| #define HOST_XIP_UDSCFG3_SMODE 0x00000002U |
| #define HOST_XIP_UDSCFG3_SMODE_M 0x00000002U |
| #define HOST_XIP_UDSCFG3_SMODE_S 1U |
| #define HOST_XIP_UDSCTL0_JSTART 0x00000001U |
Referenced by XIPStartUDMATransaction().
| #define HOST_XIP_UDSCTL0_JSTART_M 0x00000001U |
| #define HOST_XIP_UDSCTL0_JSTART_S 0U |
| #define HOST_XIP_UDSCTL1_JCLR 0x00000001U |
| #define HOST_XIP_UDSCTL1_JCLR_M 0x00000001U |
| #define HOST_XIP_UDSCTL1_JCLR_S 0U |
| #define HOST_XIP_UDSSTA_JSTA 0x00000001U |
| #define HOST_XIP_UDSSTA_JSTA_M 0x00000001U |
Referenced by XIPStartUDMATransaction().
| #define HOST_XIP_UDSSTA_JSTA_S 0U |
| #define HOST_XIP_UDSSTA_JINPROG 0x00000010U |
| #define HOST_XIP_UDSSTA_JINPROG_M 0x00000010U |
Referenced by XIPGetUDMAChannelProgressingStatus().
| #define HOST_XIP_UDSSTA_JINPROG_S 4U |
Referenced by XIPGetUDMAChannelProgressingStatus().
| #define HOST_XIP_UDSSTA_RDWRDSLFT_W 20U |
| #define HOST_XIP_UDSSTA_RDWRDSLFT_M 0x0FFFFF00U |
Referenced by XIPGetUDMAChannelWordsLeft().
| #define HOST_XIP_UDSSTA_RDWRDSLFT_S 8U |
Referenced by XIPGetUDMAChannelWordsLeft().
| #define HOST_XIP_UDSIRQ_JIRQSTA_W 2U |
| #define HOST_XIP_UDSIRQ_JIRQSTA_M 0x00000003U |
Referenced by XIPGetUDMAIrqStatus().
| #define HOST_XIP_UDSIRQ_JIRQSTA_S 0U |
Referenced by XIPGetUDMAIrqStatus().
| #define HOST_XIP_UDSIRQ_JIRQBEDIR 0x00000004U |
| #define HOST_XIP_UDSIRQ_JIRQBEDIR_M 0x00000004U |
| #define HOST_XIP_UDSIRQ_JIRQBEDIR_S 2U |
| #define HOST_XIP_UDSSTA1_WRDOFST_W 8U |
| #define HOST_XIP_UDSSTA1_WRDOFST_M 0x000000FFU |
| #define HOST_XIP_UDSSTA1_WRDOFST_S 0U |
| #define HOST_XIP_UDSSTA1_WRWRDSLFT_W 20U |
| #define HOST_XIP_UDSSTA1_WRWRDSLFT_M 0x0FFFFF00U |
| #define HOST_XIP_UDSSTA1_WRWRDSLFT_S 8U |
| #define HOST_XIP_UDSPERCFG_SPERWDSZ_W 2U |
| #define HOST_XIP_UDSPERCFG_SPERWDSZ_M 0x00000003U |
| #define HOST_XIP_UDSPERCFG_SPERWDSZ_S 0U |
| #define HOST_XIP_UDSPERCFG_SPERBLKSZ_W 6U |
| #define HOST_XIP_UDSPERCFG_SPERBLKSZ_M 0x000000FCU |
| #define HOST_XIP_UDSPERCFG_SPERBLKSZ_S 2U |
| #define HOST_XIP_UDSPERCFG_SENCLRSRT 0x00000100U |
| #define HOST_XIP_UDSPERCFG_SENCLRSRT_M 0x00000100U |
| #define HOST_XIP_UDSPERCFG_SENCLRSRT_S 8U |
| #define HOST_XIP_UDSPERSEL_SPERSEL_W 4U |
| #define HOST_XIP_UDSPERSEL_SPERSEL_M 0x0000000FU |
| #define HOST_XIP_UDSPERSEL_SPERSEL_S 0U |
| #define HOST_XIP_UDNSPERSEL_NSPERSEL_W 4U |
| #define HOST_XIP_UDNSPERSEL_NSPERSEL_M 0x0000000FU |
| #define HOST_XIP_UDNSPERSEL_NSPERSEL_S 0U |
| #define HOST_XIP_UDNSCFG0_JSRCADDR_W 32U |
| #define HOST_XIP_UDNSCFG0_JSRCADDR_M 0xFFFFFFFFU |
| #define HOST_XIP_UDNSCFG0_JSRCADDR_S 0U |
| #define HOST_XIP_UDNSCFG1_JDESTADDR_W 32U |
| #define HOST_XIP_UDNSCFG1_JDESTADDR_M 0xFFFFFFFFU |
| #define HOST_XIP_UDNSCFG1_JDESTADDR_S 0U |
| #define HOST_XIP_UDNSCFG2_JLEN_W 18U |
| #define HOST_XIP_UDNSCFG2_JLEN_M 0x0003FFFFU |
| #define HOST_XIP_UDNSCFG2_JLEN_S 0U |
| #define HOST_XIP_UDNSCFG3_JDIR 0x00000001U |
| #define HOST_XIP_UDNSCFG3_JDIR_M 0x00000001U |
| #define HOST_XIP_UDNSCFG3_JDIR_S 0U |
| #define HOST_XIP_UDNSCFG3_NSMODE 0x00000002U |
| #define HOST_XIP_UDNSCFG3_NSMODE_M 0x00000002U |
| #define HOST_XIP_UDNSCFG3_NSMODE_S 1U |
| #define HOST_XIP_UDNSCTL0_JSTART 0x00000001U |
| #define HOST_XIP_UDNSCTL0_JSTART_M 0x00000001U |
| #define HOST_XIP_UDNSCTL0_JSTART_S 0U |
| #define HOST_XIP_UDNSCTL1_JCLR 0x00000001U |
| #define HOST_XIP_UDNSCTL1_JCLR_M 0x00000001U |
| #define HOST_XIP_UDNSCTL1_JCLR_S 0U |
| #define HOST_XIP_UDNSSTA_JSTA 0x00000001U |
| #define HOST_XIP_UDNSSTA_JSTA_M 0x00000001U |
| #define HOST_XIP_UDNSSTA_JSTA_S 0U |
| #define HOST_XIP_UDNSSTA_JINPROG 0x00000010U |
| #define HOST_XIP_UDNSSTA_JINPROG_M 0x00000010U |
| #define HOST_XIP_UDNSSTA_JINPROG_S 4U |
| #define HOST_XIP_UDNSSTA_RDWRDSLFT_W 20U |
| #define HOST_XIP_UDNSSTA_RDWRDSLFT_M 0x0FFFFF00U |
| #define HOST_XIP_UDNSSTA_RDWRDSLFT_S 8U |
| #define HOST_XIP_UDNSIRQ_JIRQSTA_W 2U |
| #define HOST_XIP_UDNSIRQ_JIRQSTA_M 0x00000003U |
| #define HOST_XIP_UDNSIRQ_JIRQSTA_S 0U |
| #define HOST_XIP_UDNSIRQ_JIRQBEDIR 0x00000004U |
| #define HOST_XIP_UDNSIRQ_JIRQBEDIR_M 0x00000004U |
| #define HOST_XIP_UDNSIRQ_JIRQBEDIR_S 2U |
| #define HOST_XIP_UTHRCNF_THRVAL_W 5U |
| #define HOST_XIP_UTHRCNF_THRVAL_M 0x0000001FU |
| #define HOST_XIP_UTHRCNF_THRVAL_S 0U |
| #define HOST_XIP_UTHRCNF_BURSTVAL_W 2U |
| #define HOST_XIP_UTHRCNF_BURSTVAL_M 0x00000060U |
| #define HOST_XIP_UTHRCNF_BURSTVAL_S 5U |
| #define HOST_XIP_UDNSSTA1_WRWRDSLFT_W 8U |
| #define HOST_XIP_UDNSSTA1_WRWRDSLFT_M 0x000000FFU |
| #define HOST_XIP_UDNSSTA1_WRWRDSLFT_S 0U |
| #define HOST_XIP_UDNSSTA1_WRDOFST_W 20U |
| #define HOST_XIP_UDNSSTA1_WRDOFST_M 0x0FFFFF00U |
| #define HOST_XIP_UDNSSTA1_WRDOFST_S 8U |
| #define HOST_XIP_UDNSPERCFG_NSPERWDSZ_W 2U |
| #define HOST_XIP_UDNSPERCFG_NSPERWDSZ_M 0x00000003U |
| #define HOST_XIP_UDNSPERCFG_NSPERWDSZ_S 0U |
| #define HOST_XIP_UDNSPERCFG_NSPERBLSZ_W 6U |
| #define HOST_XIP_UDNSPERCFG_NSPERBLSZ_M 0x000000FCU |
| #define HOST_XIP_UDNSPERCFG_NSPERBLSZ_S 2U |
| #define HOST_XIP_UDNSPERCFG_NSENCLRSRT 0x00000100U |
| #define HOST_XIP_UDNSPERCFG_NSENCLRSRT_M 0x00000100U |
| #define HOST_XIP_UDNSPERCFG_NSENCLRSRT_S 8U |
| #define HOST_XIP_OTOSMEM_WDATACFG_W 32U |
| #define HOST_XIP_OTOSMEM_WDATACFG_M 0xFFFFFFFFU |
| #define HOST_XIP_OTOSMEM_WDATACFG_S 0U |
| #define HOST_XIP_OTPRTCFG_INITDLY_W 4U |
| #define HOST_XIP_OTPRTCFG_INITDLY_M 0x0000000FU |
| #define HOST_XIP_OTPRTCFG_INITDLY_S 0U |
| #define HOST_XIP_OTPRTCFG_R0WRLOCK 0x00000010U |
| #define HOST_XIP_OTPRTCFG_R0WRLOCK_M 0x00000010U |
| #define HOST_XIP_OTPRTCFG_R0WRLOCK_S 4U |
| #define HOST_XIP_OTPRTCFG_R0ENCBPASS 0x00000020U |
| #define HOST_XIP_OTPRTCFG_R0ENCBPASS_M 0x00000020U |
| #define HOST_XIP_OTPRTCFG_R0ENCBPASS_S 5U |
| #define HOST_XIP_OTPRTCFG_R1WRLOCK 0x00000100U |
| #define HOST_XIP_OTPRTCFG_R1WRLOCK_M 0x00000100U |
| #define HOST_XIP_OTPRTCFG_R1WRLOCK_S 8U |
| #define HOST_XIP_OTPRTCFG_R1ENCBPASS 0x00000200U |
| #define HOST_XIP_OTPRTCFG_R1ENCBPASS_M 0x00000200U |
| #define HOST_XIP_OTPRTCFG_R1ENCBPASS_S 9U |
| #define HOST_XIP_OTPRTCFG_R2WRLOCK 0x00001000U |
| #define HOST_XIP_OTPRTCFG_R2WRLOCK_M 0x00001000U |
| #define HOST_XIP_OTPRTCFG_R2WRLOCK_S 12U |
| #define HOST_XIP_OTPRTCFG_R2ENCBPASS 0x00002000U |
| #define HOST_XIP_OTPRTCFG_R2ENCBPASS_M 0x00002000U |
| #define HOST_XIP_OTPRTCFG_R2ENCBPASS_S 13U |
| #define HOST_XIP_OTPRTCFG_R3WRLOCK 0x00010000U |
| #define HOST_XIP_OTPRTCFG_R3WRLOCK_M 0x00010000U |
| #define HOST_XIP_OTPRTCFG_R3WRLOCK_S 16U |
| #define HOST_XIP_OTPRTCFG_R3ENCBPASS 0x00020000U |
| #define HOST_XIP_OTPRTCFG_R3ENCBPASS_M 0x00020000U |
| #define HOST_XIP_OTPRTCFG_R3ENCBPASS_S 17U |
| #define HOST_XIP_RGN0CFG0_KEY0_W 32U |
| #define HOST_XIP_RGN0CFG0_KEY0_M 0xFFFFFFFFU |
| #define HOST_XIP_RGN0CFG0_KEY0_S 0U |
| #define HOST_XIP_RGN0CFG1_KEY1_W 32U |
| #define HOST_XIP_RGN0CFG1_KEY1_M 0xFFFFFFFFU |
| #define HOST_XIP_RGN0CFG1_KEY1_S 0U |
| #define HOST_XIP_RGN0CFG2_KEY2_W 32U |
| #define HOST_XIP_RGN0CFG2_KEY2_M 0xFFFFFFFFU |
| #define HOST_XIP_RGN0CFG2_KEY2_S 0U |
| #define HOST_XIP_RGN0CFG3_KEY3_W 32U |
| #define HOST_XIP_RGN0CFG3_KEY3_M 0xFFFFFFFFU |
| #define HOST_XIP_RGN0CFG3_KEY3_S 0U |
| #define HOST_XIP_RGN0CFG4_NONCE0_W 32U |
| #define HOST_XIP_RGN0CFG4_NONCE0_M 0xFFFFFFFFU |
| #define HOST_XIP_RGN0CFG4_NONCE0_S 0U |
| #define HOST_XIP_RGN0CFG5_NONCE1_W 32U |
| #define HOST_XIP_RGN0CFG5_NONCE1_M 0xFFFFFFFFU |
| #define HOST_XIP_RGN0CFG5_NONCE1_S 0U |
| #define HOST_XIP_RGN1CFG0_KEY0_W 32U |
| #define HOST_XIP_RGN1CFG0_KEY0_M 0xFFFFFFFFU |
| #define HOST_XIP_RGN1CFG0_KEY0_S 0U |
| #define HOST_XIP_RGN1CFG1_KEY1_W 32U |
| #define HOST_XIP_RGN1CFG1_KEY1_M 0xFFFFFFFFU |
| #define HOST_XIP_RGN1CFG1_KEY1_S 0U |
| #define HOST_XIP_RGN1CFG2_KEY2_W 32U |
| #define HOST_XIP_RGN1CFG2_KEY2_M 0xFFFFFFFFU |
| #define HOST_XIP_RGN1CFG2_KEY2_S 0U |
| #define HOST_XIP_RGN1CFG3_KEY3_W 32U |
| #define HOST_XIP_RGN1CFG3_KEY3_M 0xFFFFFFFFU |
| #define HOST_XIP_RGN1CFG3_KEY3_S 0U |
| #define HOST_XIP_RGN1CFG4_NONCE0_W 32U |
| #define HOST_XIP_RGN1CFG4_NONCE0_M 0xFFFFFFFFU |
| #define HOST_XIP_RGN1CFG4_NONCE0_S 0U |
| #define HOST_XIP_RGN1CFG5_NONCE1_W 32U |
| #define HOST_XIP_RGN1CFG5_NONCE1_M 0xFFFFFFFFU |
| #define HOST_XIP_RGN1CFG5_NONCE1_S 0U |
| #define HOST_XIP_RGN2CFG0_KEY0_W 32U |
| #define HOST_XIP_RGN2CFG0_KEY0_M 0xFFFFFFFFU |
| #define HOST_XIP_RGN2CFG0_KEY0_S 0U |
| #define HOST_XIP_RGN2CFG1_KEY1_W 32U |
| #define HOST_XIP_RGN2CFG1_KEY1_M 0xFFFFFFFFU |
| #define HOST_XIP_RGN2CFG1_KEY1_S 0U |
| #define HOST_XIP_RGN2CFG2_KEY2_W 32U |
| #define HOST_XIP_RGN2CFG2_KEY2_M 0xFFFFFFFFU |
| #define HOST_XIP_RGN2CFG2_KEY2_S 0U |
| #define HOST_XIP_RGN2CFG3_KEY3_W 32U |
| #define HOST_XIP_RGN2CFG3_KEY3_M 0xFFFFFFFFU |
| #define HOST_XIP_RGN2CFG3_KEY3_S 0U |
| #define HOST_XIP_RGN2CFG4_NONCE0_W 32U |
| #define HOST_XIP_RGN2CFG4_NONCE0_M 0xFFFFFFFFU |
| #define HOST_XIP_RGN2CFG4_NONCE0_S 0U |
| #define HOST_XIP_RGN2CFG5_NONCE1_W 32U |
| #define HOST_XIP_RGN2CFG5_NONCE1_M 0xFFFFFFFFU |
| #define HOST_XIP_RGN2CFG5_NONCE1_S 0U |
| #define HOST_XIP_RGN3CFG0_KEY0_W 32U |
| #define HOST_XIP_RGN3CFG0_KEY0_M 0xFFFFFFFFU |
| #define HOST_XIP_RGN3CFG0_KEY0_S 0U |
| #define HOST_XIP_RGN3CFG1_KEY1_W 32U |
| #define HOST_XIP_RGN3CFG1_KEY1_M 0xFFFFFFFFU |
| #define HOST_XIP_RGN3CFG1_KEY1_S 0U |
| #define HOST_XIP_RGN3CFG2_KEY2_W 32U |
| #define HOST_XIP_RGN3CFG2_KEY2_M 0xFFFFFFFFU |
| #define HOST_XIP_RGN3CFG2_KEY2_S 0U |
| #define HOST_XIP_RGN3CFG3_KEY3_W 32U |
| #define HOST_XIP_RGN3CFG3_KEY3_M 0xFFFFFFFFU |
| #define HOST_XIP_RGN3CFG3_KEY3_S 0U |
| #define HOST_XIP_RGN3CFG4_NONCE0_W 32U |
| #define HOST_XIP_RGN3CFG4_NONCE0_M 0xFFFFFFFFU |
| #define HOST_XIP_RGN3CFG4_NONCE0_S 0U |
| #define HOST_XIP_RGN3CFG5_NONCE1_W 32U |
| #define HOST_XIP_RGN3CFG5_NONCE1_M 0xFFFFFFFFU |
| #define HOST_XIP_RGN3CFG5_NONCE1_S 0U |
| #define HOST_XIP_OTSWCTL0_ENREQ 0x00000001U |
Referenced by __attribute__().
| #define HOST_XIP_OTSWCTL0_ENREQ_M 0x00000001U |
| #define HOST_XIP_OTSWCTL0_ENREQ_S 0U |
| #define HOST_XIP_OTSWCTL1_DISREQ 0x00000001U |
Referenced by __attribute__().
| #define HOST_XIP_OTSWCTL1_DISREQ_M 0x00000001U |
| #define HOST_XIP_OTSWCTL1_DISREQ_S 0U |
| #define HOST_XIP_OTSWCTL2_SUSPENDREQ 0x00000001U |
| #define HOST_XIP_OTSWCTL2_SUSPENDREQ_M 0x00000001U |
| #define HOST_XIP_OTSWCTL2_SUSPENDREQ_S 0U |
| #define HOST_XIP_OTSWCTL3_RESUMEREQ 0x00000001U |
| #define HOST_XIP_OTSWCTL3_RESUMEREQ_M 0x00000001U |
| #define HOST_XIP_OTSWCTL3_RESUMEREQ_S 0U |
| #define HOST_XIP_OTSWCTL4_RSTREQ 0x00000001U |
| #define HOST_XIP_OTSWCTL4_RSTREQ_M 0x00000001U |
| #define HOST_XIP_OTSWCTL4_RSTREQ_S 0U |
| #define HOST_XIP_OTSTA_ACTIVESTA 0x00000001U |
Referenced by __attribute__().
| #define HOST_XIP_OTSTA_ACTIVESTA_M 0x00000001U |
Referenced by __attribute__().
| #define HOST_XIP_OTSTA_ACTIVESTA_S 0U |
| #define HOST_XIP_OTSTA_TASKSUS 0x00000002U |
| #define HOST_XIP_OTSTA_TASKSUS_M 0x00000002U |
| #define HOST_XIP_OTSTA_TASKSUS_S 1U |
| #define HOST_XIP_OTSTA_EXTMUX 0x00000004U |
| #define HOST_XIP_OTSTA_EXTMUX_M 0x00000004U |
| #define HOST_XIP_OTSTA_EXTMUX_S 2U |
| #define HOST_XIP_OTSTA_TASKACTIVE 0x00000008U |
| #define HOST_XIP_OTSTA_TASKACTIVE_M 0x00000008U |
| #define HOST_XIP_OTSTA_TASKACTIVE_S 3U |
| #define HOST_XIP_OTSTA_TASKDIR 0x00000010U |
| #define HOST_XIP_OTSTA_TASKDIR_M 0x00000010U |
| #define HOST_XIP_OTSTA_TASKDIR_S 4U |
| #define HOST_XIP_OTSTA_TASKDEVICE 0x00000020U |
| #define HOST_XIP_OTSTA_TASKDEVICE_M 0x00000020U |
| #define HOST_XIP_OTSTA_TASKDEVICE_S 5U |
| #define HOST_XIP_OTSTA_TASKREGION_W 2U |
| #define HOST_XIP_OTSTA_TASKREGION_M 0x000000C0U |
| #define HOST_XIP_OTSTA_TASKREGION_S 6U |
| #define HOST_XIP_OTSTA_OTFDENBUSY 0x00000100U |
| #define HOST_XIP_OTSTA_OTFDENBUSY_M 0x00000100U |
| #define HOST_XIP_OTSTA_OTFDENBUSY_S 8U |
| #define HOST_XIP_OTINDSTA_RSTEV 0x00000001U |
| #define HOST_XIP_OTINDSTA_RSTEV_M 0x00000001U |
| #define HOST_XIP_OTINDSTA_RSTEV_S 0U |
| #define HOST_XIP_OTINDSTA_SWRSTEV 0x00000002U |
| #define HOST_XIP_OTINDSTA_SWRSTEV_M 0x00000002U |
| #define HOST_XIP_OTINDSTA_SWRSTEV_S 1U |
| #define HOST_XIP_OTINDSTA_BYPASSEV 0x00000004U |
| #define HOST_XIP_OTINDSTA_BYPASSEV_M 0x00000004U |
| #define HOST_XIP_OTINDSTA_BYPASSEV_S 2U |
| #define HOST_XIP_OTINDSTA_GENERALERR 0x00000010U |
| #define HOST_XIP_OTINDSTA_GENERALERR_M 0x00000010U |
| #define HOST_XIP_OTINDSTA_GENERALERR_S 4U |
| #define HOST_XIP_OTINDSTA_DATPATHERR 0x00000020U |
| #define HOST_XIP_OTINDSTA_DATPATHERR_M 0x00000020U |
| #define HOST_XIP_OTINDSTA_DATPATHERR_S 5U |
| #define HOST_XIP_OTINDSTA_XSPICFGERR 0x00000040U |
| #define HOST_XIP_OTINDSTA_XSPICFGERR_M 0x00000040U |
| #define HOST_XIP_OTINDSTA_XSPICFGERR_S 6U |
| #define HOST_XIP_OTINDSTA_XSPIINT 0x00000080U |
| #define HOST_XIP_OTINDSTA_XSPIINT_M 0x00000080U |
| #define HOST_XIP_OTINDSTA_XSPIINT_S 7U |
| #define HOST_XIP_OTINDSTA_DEVDISERR 0x00000100U |
| #define HOST_XIP_OTINDSTA_DEVDISERR_M 0x00000100U |
| #define HOST_XIP_OTINDSTA_DEVDISERR_S 8U |
| #define HOST_XIP_OTINDSTA_REGDISERR 0x00000200U |
| #define HOST_XIP_OTINDSTA_REGDISERR_M 0x00000200U |
| #define HOST_XIP_OTINDSTA_REGDISERR_S 9U |
| #define HOST_XIP_OTINDSTA_POLLITREXP 0x00000400U |
| #define HOST_XIP_OTINDSTA_POLLITREXP_M 0x00000400U |
| #define HOST_XIP_OTINDSTA_POLLITREXP_S 10U |
| #define HOST_XIP_OTINDSTA_REGMAPERR 0x00000800U |
| #define HOST_XIP_OTINDSTA_REGMAPERR_M 0x00000800U |
| #define HOST_XIP_OTINDSTA_REGMAPERR_S 11U |
| #define HOST_XIP_OTINDSTA_ADDRNOALGN 0x00001000U |
| #define HOST_XIP_OTINDSTA_ADDRNOALGN_M 0x00001000U |
| #define HOST_XIP_OTINDSTA_ADDRNOALGN_S 12U |
| #define HOST_XIP_OTINDSTA_SIZENOALGN 0x00002000U |
| #define HOST_XIP_OTINDSTA_SIZENOALGN_M 0x00002000U |
| #define HOST_XIP_OTINDSTA_SIZENOALGN_S 13U |
| #define HOST_XIP_OTINDSTA_BURNOALGN 0x00004000U |
| #define HOST_XIP_OTINDSTA_BURNOALGN_M 0x00004000U |
| #define HOST_XIP_OTINDSTA_BURNOALGN_S 14U |
| #define HOST_XIP_OTINDSTA_REGDIRERR 0x00008000U |
| #define HOST_XIP_OTINDSTA_REGDIRERR_M 0x00008000U |
| #define HOST_XIP_OTINDSTA_REGDIRERR_S 15U |
| #define HOST_XIP_OTINDSTA_SUSPENDDIS 0x00010000U |
| #define HOST_XIP_OTINDSTA_SUSPENDDIS_M 0x00010000U |
| #define HOST_XIP_OTINDSTA_SUSPENDDIS_S 16U |
| #define HOST_XIP_OTINDMASK_RSTEV 0x00000001U |
| #define HOST_XIP_OTINDMASK_RSTEV_M 0x00000001U |
| #define HOST_XIP_OTINDMASK_RSTEV_S 0U |
| #define HOST_XIP_OTINDMASK_SWRSTEV 0x00000002U |
| #define HOST_XIP_OTINDMASK_SWRSTEV_M 0x00000002U |
| #define HOST_XIP_OTINDMASK_SWRSTEV_S 1U |
| #define HOST_XIP_OTINDMASK_BYPASSEV 0x00000004U |
| #define HOST_XIP_OTINDMASK_BYPASSEV_M 0x00000004U |
| #define HOST_XIP_OTINDMASK_BYPASSEV_S 2U |
| #define HOST_XIP_OTINDMASK_GENERALERR 0x00000010U |
| #define HOST_XIP_OTINDMASK_GENERALERR_M 0x00000010U |
| #define HOST_XIP_OTINDMASK_GENERALERR_S 4U |
| #define HOST_XIP_OTINDMASK_DATPATHERR 0x00000020U |
| #define HOST_XIP_OTINDMASK_DATPATHERR_M 0x00000020U |
| #define HOST_XIP_OTINDMASK_DATPATHERR_S 5U |
| #define HOST_XIP_OTINDMASK_XSPICFGERR 0x00000040U |
| #define HOST_XIP_OTINDMASK_XSPICFGERR_M 0x00000040U |
| #define HOST_XIP_OTINDMASK_XSPICFGERR_S 6U |
| #define HOST_XIP_OTINDMASK_XSPIINT 0x00000080U |
| #define HOST_XIP_OTINDMASK_XSPIINT_M 0x00000080U |
| #define HOST_XIP_OTINDMASK_XSPIINT_S 7U |
| #define HOST_XIP_OTINDMASK_DEVDISERR 0x00000100U |
| #define HOST_XIP_OTINDMASK_DEVDISERR_M 0x00000100U |
| #define HOST_XIP_OTINDMASK_DEVDISERR_S 8U |
| #define HOST_XIP_OTINDMASK_REGDISERR 0x00000200U |
| #define HOST_XIP_OTINDMASK_REGDISERR_M 0x00000200U |
| #define HOST_XIP_OTINDMASK_REGDISERR_S 9U |
| #define HOST_XIP_OTINDMASK_POLLITREXP 0x00000400U |
| #define HOST_XIP_OTINDMASK_POLLITREXP_M 0x00000400U |
| #define HOST_XIP_OTINDMASK_POLLITREXP_S 10U |
| #define HOST_XIP_OTINDMASK_REGMAPERR 0x00000800U |
| #define HOST_XIP_OTINDMASK_REGMAPERR_M 0x00000800U |
| #define HOST_XIP_OTINDMASK_REGMAPERR_S 11U |
| #define HOST_XIP_OTINDMASK_ADDRNOALGN 0x00001000U |
| #define HOST_XIP_OTINDMASK_ADDRNOALGN_M 0x00001000U |
| #define HOST_XIP_OTINDMASK_ADDRNOALGN_S 12U |
| #define HOST_XIP_OTINDMASK_SIZENOALGN 0x00002000U |
| #define HOST_XIP_OTINDMASK_SIZENOALGN_M 0x00002000U |
| #define HOST_XIP_OTINDMASK_SIZENOALGN_S 13U |
| #define HOST_XIP_OTINDMASK_BURNOALGN 0x00004000U |
| #define HOST_XIP_OTINDMASK_BURNOALGN_M 0x00004000U |
| #define HOST_XIP_OTINDMASK_BURNOALGN_S 14U |
| #define HOST_XIP_OTINDMASK_REGDIRERR 0x00008000U |
| #define HOST_XIP_OTINDMASK_REGDIRERR_M 0x00008000U |
| #define HOST_XIP_OTINDMASK_REGDIRERR_S 15U |
| #define HOST_XIP_OTINDMASK_SUSPENDDIS 0x00010000U |
| #define HOST_XIP_OTINDMASK_SUSPENDDIS_M 0x00010000U |
| #define HOST_XIP_OTINDMASK_SUSPENDDIS_S 16U |
| #define HOST_XIP_OTINDNEXT_RSTNS 0x00000001U |
| #define HOST_XIP_OTINDNEXT_RSTNS_M 0x00000001U |
| #define HOST_XIP_OTINDNEXT_RSTNS_S 0U |
| #define HOST_XIP_OTINDNEXT_SWRSTEV 0x00000002U |
| #define HOST_XIP_OTINDNEXT_SWRSTEV_M 0x00000002U |
| #define HOST_XIP_OTINDNEXT_SWRSTEV_S 1U |
| #define HOST_XIP_OTINDNEXT_BYPMDCH 0x00000004U |
| #define HOST_XIP_OTINDNEXT_BYPMDCH_M 0x00000004U |
| #define HOST_XIP_OTINDNEXT_BYPMDCH_S 2U |
| #define HOST_XIP_OTINDNEXT_GENERALERR 0x00000010U |
| #define HOST_XIP_OTINDNEXT_GENERALERR_M 0x00000010U |
| #define HOST_XIP_OTINDNEXT_GENERALERR_S 4U |
| #define HOST_XIP_OTINDNEXT_DATPATHERR 0x00000020U |
| #define HOST_XIP_OTINDNEXT_DATPATHERR_M 0x00000020U |
| #define HOST_XIP_OTINDNEXT_DATPATHERR_S 5U |
| #define HOST_XIP_OTINDNEXT_XSPICFGERR 0x00000040U |
| #define HOST_XIP_OTINDNEXT_XSPICFGERR_M 0x00000040U |
| #define HOST_XIP_OTINDNEXT_XSPICFGERR_S 6U |
| #define HOST_XIP_OTINDNEXT_XSPISERINT 0x00000080U |
| #define HOST_XIP_OTINDNEXT_XSPISERINT_M 0x00000080U |
| #define HOST_XIP_OTINDNEXT_XSPISERINT_S 7U |
| #define HOST_XIP_OTINDNEXT_DEVDISERR 0x00000100U |
| #define HOST_XIP_OTINDNEXT_DEVDISERR_M 0x00000100U |
| #define HOST_XIP_OTINDNEXT_DEVDISERR_S 8U |
| #define HOST_XIP_OTINDNEXT_REGDISERR 0x00000200U |
| #define HOST_XIP_OTINDNEXT_REGDISERR_M 0x00000200U |
| #define HOST_XIP_OTINDNEXT_REGDISERR_S 9U |
| #define HOST_XIP_OTINDNEXT_REGMAPERR 0x00000800U |
| #define HOST_XIP_OTINDNEXT_REGMAPERR_M 0x00000800U |
| #define HOST_XIP_OTINDNEXT_REGMAPERR_S 11U |
| #define HOST_XIP_OTINDNEXT_ADDRNOALGN 0x00001000U |
| #define HOST_XIP_OTINDNEXT_ADDRNOALGN_M 0x00001000U |
| #define HOST_XIP_OTINDNEXT_ADDRNOALGN_S 12U |
| #define HOST_XIP_OTINDNEXT_SIZENOALGN 0x00002000U |
| #define HOST_XIP_OTINDNEXT_SIZENOALGN_M 0x00002000U |
| #define HOST_XIP_OTINDNEXT_SIZENOALGN_S 13U |
| #define HOST_XIP_OTINDNEXT_BURNOALGN 0x00004000U |
| #define HOST_XIP_OTINDNEXT_BURNOALGN_M 0x00004000U |
| #define HOST_XIP_OTINDNEXT_BURNOALGN_S 14U |
| #define HOST_XIP_OTINDNEXT_REGDIRERR 0x00008000U |
| #define HOST_XIP_OTINDNEXT_REGDIRERR_M 0x00008000U |
| #define HOST_XIP_OTINDNEXT_REGDIRERR_S 15U |
| #define HOST_XIP_OTINDNEXT_SUSPENDDIS 0x00010000U |
| #define HOST_XIP_OTINDNEXT_SUSPENDDIS_M 0x00010000U |
| #define HOST_XIP_OTINDNEXT_SUSPENDDIS_S 16U |
| #define HOST_XIP_OTSTGSEL_DEV0JOB0 0x00000001U |
| #define HOST_XIP_OTSTGSEL_DEV0JOB0_M 0x00000001U |
| #define HOST_XIP_OTSTGSEL_DEV0JOB0_S 0U |
| #define HOST_XIP_OTSTGSEL_DEV0JOB4 0x00000010U |
| #define HOST_XIP_OTSTGSEL_DEV0JOB4_M 0x00000010U |
| #define HOST_XIP_OTSTGSEL_DEV0JOB4_S 4U |
| #define HOST_XIP_OTSTGSEL_DEV0JOB5 0x00000020U |
| #define HOST_XIP_OTSTGSEL_DEV0JOB5_M 0x00000020U |
| #define HOST_XIP_OTSTGSEL_DEV0JOB5_S 5U |
| #define HOST_XIP_OTSTGSEL_DEV0JOB6 0x00000040U |
| #define HOST_XIP_OTSTGSEL_DEV0JOB6_M 0x00000040U |
| #define HOST_XIP_OTSTGSEL_DEV0JOB6_S 6U |
| #define HOST_XIP_OTSTGSEL_DEV0JOB7 0x00000080U |
| #define HOST_XIP_OTSTGSEL_DEV0JOB7_M 0x00000080U |
| #define HOST_XIP_OTSTGSEL_DEV0JOB7_S 7U |
| #define HOST_XIP_OTSTGSEL_DEV1JOB0 0x00000100U |
| #define HOST_XIP_OTSTGSEL_DEV1JOB0_M 0x00000100U |
| #define HOST_XIP_OTSTGSEL_DEV1JOB0_S 8U |
| #define HOST_XIP_OTSTGSEL_DEV1JOB4 0x00001000U |
| #define HOST_XIP_OTSTGSEL_DEV1JOB4_M 0x00001000U |
| #define HOST_XIP_OTSTGSEL_DEV1JOB4_S 12U |
| #define HOST_XIP_OTSTGSEL_DEV1JOB5 0x00002000U |
| #define HOST_XIP_OTSTGSEL_DEV1JOB5_M 0x00002000U |
| #define HOST_XIP_OTSTGSEL_DEV1JOB5_S 13U |
| #define HOST_XIP_OTSTGSEL_DEV1JOB6 0x00004000U |
| #define HOST_XIP_OTSTGSEL_DEV1JOB6_M 0x00004000U |
| #define HOST_XIP_OTSTGSEL_DEV1JOB6_S 14U |
| #define HOST_XIP_OTSTGSEL_DEV1JOB7 0x00008000U |
| #define HOST_XIP_OTSTGSEL_DEV1JOB7_M 0x00008000U |
| #define HOST_XIP_OTSTGSEL_DEV1JOB7_S 15U |
| #define HOST_XIP_OTD0CFG_DEVICE 0x00000001U |
| #define HOST_XIP_OTD0CFG_DEVICE_M 0x00000001U |
| #define HOST_XIP_OTD0CFG_DEVICE_S 0U |
| #define HOST_XIP_OTD0CFG_WRPROTTIME 0x00000002U |
| #define HOST_XIP_OTD0CFG_WRPROTTIME_M 0x00000002U |
| #define HOST_XIP_OTD0CFG_WRPROTTIME_S 1U |
| #define HOST_XIP_OTD0CFG_PREWRCMD 0x00000004U |
| #define HOST_XIP_OTD0CFG_PREWRCMD_M 0x00000004U |
| #define HOST_XIP_OTD0CFG_PREWRCMD_S 2U |
| #define HOST_XIP_OTD0CFG_POSTWRCMD 0x00000008U |
| #define HOST_XIP_OTD0CFG_POSTWRCMD_M 0x00000008U |
| #define HOST_XIP_OTD0CFG_POSTWRCMD_S 3U |
| #define HOST_XIP_OTD0CFG_WRBUFTMMOD_W 2U |
| #define HOST_XIP_OTD0CFG_WRBUFTMMOD_M 0x00000030U |
| #define HOST_XIP_OTD0CFG_WRBUFTMMOD_S 4U |
| #define HOST_XIP_OTD0CFG_WRBUFTMRNG_W 6U |
| #define HOST_XIP_OTD0CFG_WRBUFTMRNG_M 0x00003F00U |
| #define HOST_XIP_OTD0CFG_WRBUFTMRNG_S 8U |
| #define HOST_XIP_OTD0CFG_RWW 0x00010000U |
| #define HOST_XIP_OTD0CFG_RWW_M 0x00010000U |
| #define HOST_XIP_OTD0CFG_RWW_S 16U |
| #define HOST_XIP_OTD0CFG_DEVICESIZE_W 3U |
| #define HOST_XIP_OTD0CFG_DEVICESIZE_M 0x00700000U |
| #define HOST_XIP_OTD0CFG_DEVICESIZE_S 20U |
| #define HOST_XIP_OTD0CFG_NUMBANKS_W 3U |
| #define HOST_XIP_OTD0CFG_NUMBANKS_M 0x07000000U |
| #define HOST_XIP_OTD0CFG_NUMBANKS_S 24U |
| #define HOST_XIP_OTD0CFG_INTCRT_W 4U |
| #define HOST_XIP_OTD0CFG_INTCRT_M 0xF0000000U |
| #define HOST_XIP_OTD0CFG_INTCRT_S 28U |
| #define HOST_XIP_OTD0PTMR_RESPCNT_W 10U |
| #define HOST_XIP_OTD0PTMR_RESPCNT_M 0x000003FFU |
| #define HOST_XIP_OTD0PTMR_RESPCNT_S 0U |
| #define HOST_XIP_OTD0PTMR_POLLITERA_W 5U |
| #define HOST_XIP_OTD0PTMR_POLLITERA_M 0x001F0000U |
| #define HOST_XIP_OTD0PTMR_POLLITERA_S 16U |
| #define HOST_XIP_OTD0WRAP_EN 0x00000001U |
| #define HOST_XIP_OTD0WRAP_EN_M 0x00000001U |
| #define HOST_XIP_OTD0WRAP_EN_S 0U |
| #define HOST_XIP_OTD0WRAP_SIZE_W 4U |
| #define HOST_XIP_OTD0WRAP_SIZE_M 0x0000001EU |
| #define HOST_XIP_OTD0WRAP_SIZE_S 1U |
| #define HOST_XIP_OTD1CFG_DEVICE 0x00000001U |
| #define HOST_XIP_OTD1CFG_DEVICE_M 0x00000001U |
| #define HOST_XIP_OTD1CFG_DEVICE_S 0U |
| #define HOST_XIP_OTD1CFG_WRPROTTIME 0x00000002U |
| #define HOST_XIP_OTD1CFG_WRPROTTIME_M 0x00000002U |
| #define HOST_XIP_OTD1CFG_WRPROTTIME_S 1U |
| #define HOST_XIP_OTD1CFG_PREWRCMD 0x00000004U |
| #define HOST_XIP_OTD1CFG_PREWRCMD_M 0x00000004U |
| #define HOST_XIP_OTD1CFG_PREWRCMD_S 2U |
| #define HOST_XIP_OTD1CFG_POSTWRCMD 0x00000008U |
| #define HOST_XIP_OTD1CFG_POSTWRCMD_M 0x00000008U |
| #define HOST_XIP_OTD1CFG_POSTWRCMD_S 3U |
| #define HOST_XIP_OTD1CFG_WRBUFTMMOD_W 2U |
| #define HOST_XIP_OTD1CFG_WRBUFTMMOD_M 0x00000030U |
| #define HOST_XIP_OTD1CFG_WRBUFTMMOD_S 4U |
| #define HOST_XIP_OTD1CFG_WRBUFTMRNG_W 6U |
| #define HOST_XIP_OTD1CFG_WRBUFTMRNG_M 0x00003F00U |
| #define HOST_XIP_OTD1CFG_WRBUFTMRNG_S 8U |
| #define HOST_XIP_OTD1CFG_INTCRT_W 4U |
| #define HOST_XIP_OTD1CFG_INTCRT_M 0x000F0000U |
| #define HOST_XIP_OTD1CFG_INTCRT_S 16U |
| #define HOST_XIP_OTD1WRAP_EN 0x00000001U |
| #define HOST_XIP_OTD1WRAP_EN_M 0x00000001U |
| #define HOST_XIP_OTD1WRAP_EN_S 0U |
| #define HOST_XIP_OTD1WRAP_SIZE_W 4U |
| #define HOST_XIP_OTD1WRAP_SIZE_M 0x0000001EU |
| #define HOST_XIP_OTD1WRAP_SIZE_S 1U |
| #define HOST_XIP_OTGLBTMR_VAL_W 3U |
| #define HOST_XIP_OTGLBTMR_VAL_M 0x00000007U |
| #define HOST_XIP_OTGLBTMR_VAL_S 0U |
| #define HOST_XIP_OTR0CFG0_REGION 0x00000001U |
| #define HOST_XIP_OTR0CFG0_REGION_M 0x00000001U |
| #define HOST_XIP_OTR0CFG0_REGION_S 0U |
| #define HOST_XIP_OTR0CFG0_DEVICE 0x00000002U |
| #define HOST_XIP_OTR0CFG0_DEVICE_M 0x00000002U |
| #define HOST_XIP_OTR0CFG0_DEVICE_S 1U |
| #define HOST_XIP_OTR0CFG0_SPIWR 0x00000004U |
| #define HOST_XIP_OTR0CFG0_SPIWR_M 0x00000004U |
| #define HOST_XIP_OTR0CFG0_SPIWR_S 2U |
| #define HOST_XIP_OTR0CFG0_SPIRD 0x00000008U |
| #define HOST_XIP_OTR0CFG0_SPIRD_M 0x00000008U |
| #define HOST_XIP_OTR0CFG0_SPIRD_S 3U |
| #define HOST_XIP_OTR0CFG0_OFFSET_W 14U |
| #define HOST_XIP_OTR0CFG0_OFFSET_M 0x0003FFF0U |
| #define HOST_XIP_OTR0CFG0_OFFSET_S 4U |
| #define HOST_XIP_OTR0CFG0_SECID1_W 6U |
| #define HOST_XIP_OTR0CFG0_SECID1_M 0x03F00000U |
| #define HOST_XIP_OTR0CFG0_SECID1_S 20U |
| #define HOST_XIP_OTR0CFG1_STARTADDR_W 20U |
| #define HOST_XIP_OTR0CFG1_STARTADDR_M 0x000FFFFFU |
| #define HOST_XIP_OTR0CFG1_STARTADDR_S 0U |
| #define HOST_XIP_OTR0CFG2_ENDADDR_W 20U |
| #define HOST_XIP_OTR0CFG2_ENDADDR_M 0x000FFFFFU |
| #define HOST_XIP_OTR0CFG2_ENDADDR_S 0U |
| #define HOST_XIP_OTR0CFG3_SECID0_W 32U |
| #define HOST_XIP_OTR0CFG3_SECID0_M 0xFFFFFFFFU |
| #define HOST_XIP_OTR0CFG3_SECID0_S 0U |
| #define HOST_XIP_OTR1CFG0_REGION 0x00000001U |
| #define HOST_XIP_OTR1CFG0_REGION_M 0x00000001U |
| #define HOST_XIP_OTR1CFG0_REGION_S 0U |
| #define HOST_XIP_OTR1CFG0_DEVICE 0x00000002U |
| #define HOST_XIP_OTR1CFG0_DEVICE_M 0x00000002U |
| #define HOST_XIP_OTR1CFG0_DEVICE_S 1U |
| #define HOST_XIP_OTR1CFG0_SPIWR 0x00000004U |
| #define HOST_XIP_OTR1CFG0_SPIWR_M 0x00000004U |
| #define HOST_XIP_OTR1CFG0_SPIWR_S 2U |
| #define HOST_XIP_OTR1CFG0_SPIRD 0x00000008U |
| #define HOST_XIP_OTR1CFG0_SPIRD_M 0x00000008U |
| #define HOST_XIP_OTR1CFG0_SPIRD_S 3U |
| #define HOST_XIP_OTR1CFG0_OFFSET_W 14U |
| #define HOST_XIP_OTR1CFG0_OFFSET_M 0x0003FFF0U |
| #define HOST_XIP_OTR1CFG0_OFFSET_S 4U |
| #define HOST_XIP_OTR1CFG0_SECID1_W 6U |
| #define HOST_XIP_OTR1CFG0_SECID1_M 0x03F00000U |
| #define HOST_XIP_OTR1CFG0_SECID1_S 20U |
| #define HOST_XIP_OTR1CFG1_STARTADDR_W 20U |
| #define HOST_XIP_OTR1CFG1_STARTADDR_M 0x000FFFFFU |
| #define HOST_XIP_OTR1CFG1_STARTADDR_S 0U |
| #define HOST_XIP_OTR1CFG2_ENDADDR_W 20U |
| #define HOST_XIP_OTR1CFG2_ENDADDR_M 0x000FFFFFU |
| #define HOST_XIP_OTR1CFG2_ENDADDR_S 0U |
| #define HOST_XIP_OTR1CFG3_SECID0_W 32U |
| #define HOST_XIP_OTR1CFG3_SECID0_M 0xFFFFFFFFU |
| #define HOST_XIP_OTR1CFG3_SECID0_S 0U |
| #define HOST_XIP_OTR2CFG0_REGION 0x00000001U |
| #define HOST_XIP_OTR2CFG0_REGION_M 0x00000001U |
| #define HOST_XIP_OTR2CFG0_REGION_S 0U |
| #define HOST_XIP_OTR2CFG0_DEVICE 0x00000002U |
| #define HOST_XIP_OTR2CFG0_DEVICE_M 0x00000002U |
| #define HOST_XIP_OTR2CFG0_DEVICE_S 1U |
| #define HOST_XIP_OTR2CFG0_SPIWR 0x00000004U |
| #define HOST_XIP_OTR2CFG0_SPIWR_M 0x00000004U |
| #define HOST_XIP_OTR2CFG0_SPIWR_S 2U |
| #define HOST_XIP_OTR2CFG0_SPIRD 0x00000008U |
| #define HOST_XIP_OTR2CFG0_SPIRD_M 0x00000008U |
| #define HOST_XIP_OTR2CFG0_SPIRD_S 3U |
| #define HOST_XIP_OTR2CFG0_OFFSET_W 14U |
| #define HOST_XIP_OTR2CFG0_OFFSET_M 0x0003FFF0U |
| #define HOST_XIP_OTR2CFG0_OFFSET_S 4U |
| #define HOST_XIP_OTR2CFG0_SECID1_W 6U |
| #define HOST_XIP_OTR2CFG0_SECID1_M 0x03F00000U |
| #define HOST_XIP_OTR2CFG0_SECID1_S 20U |
| #define HOST_XIP_OTR2CFG1_STARTADDR_W 20U |
| #define HOST_XIP_OTR2CFG1_STARTADDR_M 0x000FFFFFU |
| #define HOST_XIP_OTR2CFG1_STARTADDR_S 0U |
| #define HOST_XIP_OTR2CFG2_ENDADDR_W 20U |
| #define HOST_XIP_OTR2CFG2_ENDADDR_M 0x000FFFFFU |
| #define HOST_XIP_OTR2CFG2_ENDADDR_S 0U |
| #define HOST_XIP_OTR2CFG3_SECID0_W 32U |
| #define HOST_XIP_OTR2CFG3_SECID0_M 0xFFFFFFFFU |
| #define HOST_XIP_OTR2CFG3_SECID0_S 0U |
| #define HOST_XIP_OTR3CFG0_REGION 0x00000001U |
| #define HOST_XIP_OTR3CFG0_REGION_M 0x00000001U |
| #define HOST_XIP_OTR3CFG0_REGION_S 0U |
| #define HOST_XIP_OTR3CFG0_DEVICE 0x00000002U |
| #define HOST_XIP_OTR3CFG0_DEVICE_M 0x00000002U |
| #define HOST_XIP_OTR3CFG0_DEVICE_S 1U |
| #define HOST_XIP_OTR3CFG0_SPIWR 0x00000004U |
| #define HOST_XIP_OTR3CFG0_SPIWR_M 0x00000004U |
| #define HOST_XIP_OTR3CFG0_SPIWR_S 2U |
| #define HOST_XIP_OTR3CFG0_SPIRD 0x00000008U |
| #define HOST_XIP_OTR3CFG0_SPIRD_M 0x00000008U |
| #define HOST_XIP_OTR3CFG0_SPIRD_S 3U |
| #define HOST_XIP_OTR3CFG0_OFFSET_W 14U |
| #define HOST_XIP_OTR3CFG0_OFFSET_M 0x0003FFF0U |
| #define HOST_XIP_OTR3CFG0_OFFSET_S 4U |
| #define HOST_XIP_OTR3CFG0_SECID1_W 6U |
| #define HOST_XIP_OTR3CFG0_SECID1_M 0x03F00000U |
| #define HOST_XIP_OTR3CFG0_SECID1_S 20U |
| #define HOST_XIP_OTR3CFG1_STARTADDR_W 20U |
| #define HOST_XIP_OTR3CFG1_STARTADDR_M 0x000FFFFFU |
| #define HOST_XIP_OTR3CFG1_STARTADDR_S 0U |
| #define HOST_XIP_OTR3CFG2_ENDADDR_W 20U |
| #define HOST_XIP_OTR3CFG2_ENDADDR_M 0x000FFFFFU |
| #define HOST_XIP_OTR3CFG2_ENDADDR_S 0U |
| #define HOST_XIP_OTR3CFG3_SECID0_W 32U |
| #define HOST_XIP_OTR3CFG3_SECID0_M 0xFFFFFFFFU |
| #define HOST_XIP_OTR3CFG3_SECID0_S 0U |