CC35xxDriverLibrary
hw_host_mcu_sec.h
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1 /******************************************************************************
2 * Filename: hw_host_mcu_sec.h
3 *
4 * Description: Defines and prototypes for the HOST_MCU_SEC peripheral.
5 *
6 * Copyright (c) 2023-2025, Texas Instruments Incorporated
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35 ******************************************************************************/
36 #ifndef __HW_HOST_MCU_SEC_H__
37 #define __HW_HOST_MCU_SEC_H__
38 /*-------------------------------------------------------------------------------
39 
40 This section defines the register offsets of the HOST_MCU_SEC component
41 
42 --------------------------------------------------------------------------------- */
43 
44 //Secure Software Interrupt
45 #define HOST_MCU_SEC_O_SSWIRQ2NS 0x00000000U
46 
47 //Software Interrupt to CM3
48 #define HOST_MCU_SEC_O_SWIRQ2CM3 0x00000004U
49 
50 //Software Interrupt to CM3
51 #define HOST_MCU_SEC_O_LCKUP 0x00000008U
52 
53 
54 
55 /*-----------------------------------REGISTER------------------------------------
56  Register name: SSWIRQ2NS
57  Offset name: HOST_MCU_SEC_O_SSWIRQ2NS
58  Relative address: 0x0
59  Description: Secure Software Interrupt
60  Default Value: 0x00000000
61 
62  Field: EN
63  From..to bits: 0...7
64  DefaultValue: 0x0
65  Access type: read-write
66  Description: Secure context of CM33 can use this register to interrupt non secure context of CM33.
67 
68 
69 */
70 #define HOST_MCU_SEC_SSWIRQ2NS_EN_W 8U
71 #define HOST_MCU_SEC_SSWIRQ2NS_EN_M 0x000000FFU
72 #define HOST_MCU_SEC_SSWIRQ2NS_EN_S 0U
73 
74 
75 /*-----------------------------------REGISTER------------------------------------
76  Register name: SWIRQ2CM3
77  Offset name: HOST_MCU_SEC_O_SWIRQ2CM3
78  Relative address: 0x4
79  Description: Software Interrupt to CM3
80  Default Value: 0x00000000
81 
82  Field: EN
83  From..to bits: 0...0
84  DefaultValue: 0x0
85  Access type: read-write
86  Description: Secure context of CM33 can use this register to interrupt CM3.
87 
88 
89 */
90 #define HOST_MCU_SEC_SWIRQ2CM3_EN 0x00000001U
91 #define HOST_MCU_SEC_SWIRQ2CM3_EN_M 0x00000001U
92 #define HOST_MCU_SEC_SWIRQ2CM3_EN_S 0U
93 
94 
95 /*-----------------------------------REGISTER------------------------------------
96  Register name: LCKUP
97  Offset name: HOST_MCU_SEC_O_LCKUP
98  Relative address: 0x8
99  Description: Software Interrupt to CM3
100  Default Value: 0x00000000
101 
102  Field: VAL
103  From..to bits: 0...0
104  DefaultValue: 0x0
105  Access type: read-only
106  Description: The processor enters a lockup state if a fault occurs when it cannot be serviced or escalated. When
107  the processor is in lockup state, it does not execute any instructions.
108  The processor remains in lockup state until either:
109  * It is reset.
110  * Preemption by a higher priority exception occurs.
111  * It is halted by a debugger.
112 
113 */
114 #define HOST_MCU_SEC_LCKUP_VAL 0x00000001U
115 #define HOST_MCU_SEC_LCKUP_VAL_M 0x00000001U
116 #define HOST_MCU_SEC_LCKUP_VAL_S 0U
117 
118 #endif /* __HW_HOST_MCU_SEC_H__*/