CC35xxDriverLibrary
Macros
hw_host_dma.h File Reference
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Macros

#define HOST_DMA_O_CHCTL0   0x00000000U
 
#define HOST_DMA_O_CHCTL1   0x00000004U
 
#define HOST_DMA_O_PRIOCFG   0x00000018U
 
#define HOST_DMA_O_CH0STA   0x00001000U
 
#define HOST_DMA_O_CH0TIPTR   0x00001004U
 
#define HOST_DMA_O_CH0OPTR   0x00001008U
 
#define HOST_DMA_O_CH0TCTL   0x0000100CU
 
#define HOST_DMA_O_CH0TCTL2   0x00001010U
 
#define HOST_DMA_O_CH0TSTA   0x00001014U
 
#define HOST_DMA_O_CH0JCTL   0x0000101CU
 
#define HOST_DMA_O_CH1STA   0x00002000U
 
#define HOST_DMA_O_CH1TIPTR   0x00002004U
 
#define HOST_DMA_O_CH1TOPTR   0x00002008U
 
#define HOST_DMA_O_CH1TCTL   0x0000200CU
 
#define HOST_DMA_O_CH1TCTRL2   0x00002010U
 
#define HOST_DMA_O_CH1TSTA   0x00002014U
 
#define HOST_DMA_O_CH1JCTL   0x0000201CU
 
#define HOST_DMA_O_CH2STA   0x00003000U
 
#define HOST_DMA_O_CH2TIPTR   0x00003004U
 
#define HOST_DMA_O_CH2TOPTR   0x00003008U
 
#define HOST_DMA_O_CH2TCTL   0x0000300CU
 
#define HOST_DMA_O_CH2TCTL2   0x00003010U
 
#define HOST_DMA_O_CH2TSTA   0x00003014U
 
#define HOST_DMA_O_CH2JCTL   0x0000301CU
 
#define HOST_DMA_O_CH3STA   0x00004000U
 
#define HOST_DMA_O_CH3TIPTR   0x00004004U
 
#define HOST_DMA_O_CH3TOPTR   0x00004008U
 
#define HOST_DMA_O_CH3TCTL   0x0000400CU
 
#define HOST_DMA_O_CH3TCTL2   0x00004010U
 
#define HOST_DMA_O_CH3TSTA   0x00004014U
 
#define HOST_DMA_O_CH3JCTL   0x0000401CU
 
#define HOST_DMA_O_CH4STA   0x00005000U
 
#define HOST_DMA_O_CH4TIPTR   0x00005004U
 
#define HOST_DMA_O_CH4TOPTR   0x00005008U
 
#define HOST_DMA_O_CH4TCTL   0x0000500CU
 
#define HOST_DMA_O_CH4TCTL2   0x00005010U
 
#define HOST_DMA_O_CH4TSTA   0x00005014U
 
#define HOST_DMA_O_CH4JCTL   0x0000501CU
 
#define HOST_DMA_O_CH5STA   0x00006000U
 
#define HOST_DMA_O_CH5TIPTR   0x00006004U
 
#define HOST_DMA_O_CH5TOPTR   0x00006008U
 
#define HOST_DMA_O_CH5TCTL   0x0000600CU
 
#define HOST_DMA_O_CH5TCTL2   0x00006010U
 
#define HOST_DMA_O_CH5TSTA   0x00006014U
 
#define HOST_DMA_O_CH5JCTL   0x0000601CU
 
#define HOST_DMA_O_CH6STA   0x00007000U
 
#define HOST_DMA_O_CH6TIPTR   0x00007004U
 
#define HOST_DMA_O_CH6TOPTR   0x00007008U
 
#define HOST_DMA_O_CH6TCTL   0x0000700CU
 
#define HOST_DMA_O_CH6TCTL2   0x00007010U
 
#define HOST_DMA_O_CH6TSTA   0x00007014U
 
#define HOST_DMA_O_CH6JCTL   0x0000701CU
 
#define HOST_DMA_O_CH7STA   0x00008000U
 
#define HOST_DMA_O_CH7TIPTR   0x00008004U
 
#define HOST_DMA_O_CH7TOPTR   0x00008008U
 
#define HOST_DMA_O_CH7TCTL   0x0000800CU
 
#define HOST_DMA_O_CH7TCTL2   0x00008010U
 
#define HOST_DMA_O_CH7TSTA   0x00008014U
 
#define HOST_DMA_O_CH7JCTL   0x0000801CU
 
#define HOST_DMA_O_CH8STA   0x00009000U
 
#define HOST_DMA_O_CH8TIPTR   0x00009004U
 
#define HOST_DMA_O_CH8TOPTR   0x00009008U
 
#define HOST_DMA_O_CH8TCTL   0x0000900CU
 
#define HOST_DMA_O_CH8TCTL2   0x00009010U
 
#define HOST_DMA_O_CH8TSTA   0x00009014U
 
#define HOST_DMA_O_CH8JCTL   0x0000901CU
 
#define HOST_DMA_O_CH9STA   0x0000A000U
 
#define HOST_DMA_O_CH9TIPTR   0x0000A004U
 
#define HOST_DMA_O_CH9TOPTR   0x0000A008U
 
#define HOST_DMA_O_CH9TCTL   0x0000A00CU
 
#define HOST_DMA_O_CH9TCTL2   0x0000A010U
 
#define HOST_DMA_O_CH9TSTA   0x0000A014U
 
#define HOST_DMA_O_CH9JCTL   0x0000A01CU
 
#define HOST_DMA_O_CH10STA   0x0000B000U
 
#define HOST_DMA_O_CH10TIPTR   0x0000B004U
 
#define HOST_DMA_O_CH10TOPTR   0x0000B008U
 
#define HOST_DMA_O_CH10TCTL   0x0000B00CU
 
#define HOST_DMA_O_CH10TCTL2   0x0000B010U
 
#define HOST_DMA_O_CH10TSTA   0x0000B014U
 
#define HOST_DMA_O_CH10JCTL   0x0000B01CU
 
#define HOST_DMA_O_CH11STA   0x0000C000U
 
#define HOST_DMA_O_CH11TIPTR   0x0000C004U
 
#define HOST_DMA_O_CH11TOPTR   0x0000C008U
 
#define HOST_DMA_O_CH11TCTL   0x0000C00CU
 
#define HOST_DMA_O_CH11TCTL2   0x0000C010U
 
#define HOST_DMA_O_CH11TSTA   0x0000C014U
 
#define HOST_DMA_O_CH11JCTL   0x0000C01CU
 
#define HOST_DMA_O_CH12STA   0x0000D000U
 
#define HOST_DMA_O_CH12TIPTR   0x0000D004U
 
#define HOST_DMA_O_CH12TOPTR   0x0000D008U
 
#define HOST_DMA_O_CH12TCTL   0x0000D00CU
 
#define HOST_DMA_O_CH12TCTL2   0x0000D010U
 
#define HOST_DMA_O_CH12TSTA   0x0000D014U
 
#define HOST_DMA_O_CH12JCTL   0x0000D01CU
 
#define HOST_DMA_O_CH13STA   0x0000E000U
 
#define HOST_DMA_O_CH13TIPTR   0x0000E004U
 
#define HOST_DMA_O_CH13TOPTR   0x0000E008U
 
#define HOST_DMA_O_CH13TCTL   0x0000E00CU
 
#define HOST_DMA_O_CH13TCTL2   0x0000E010U
 
#define HOST_DMA_O_CH13TSTA   0x0000E014U
 
#define HOST_DMA_O_CH13JCTL   0x0000E01CU
 
#define HOST_DMA_CHCTL0_CH0_W   4U
 
#define HOST_DMA_CHCTL0_CH0_M   0x0000000FU
 
#define HOST_DMA_CHCTL0_CH0_S   0U
 
#define HOST_DMA_CHCTL0_CH0_UART0   0x00000000U
 
#define HOST_DMA_CHCTL0_CH0_UART1   0x00000001U
 
#define HOST_DMA_CHCTL0_CH0_SPIO   0x00000002U
 
#define HOST_DMA_CHCTL0_CH0_SPI1   0x00000003U
 
#define HOST_DMA_CHCTL0_CH0_I2C0   0x00000004U
 
#define HOST_DMA_CHCTL0_CH0_I2C1   0x00000005U
 
#define HOST_DMA_CHCTL0_CH0_SDMMC   0x00000006U
 
#define HOST_DMA_CHCTL0_CH0_SDIO   0x00000007U
 
#define HOST_DMA_CHCTL0_CH0_MCAN   0x00000008U
 
#define HOST_DMA_CHCTL0_CH0_ADC   0x00000009U
 
#define HOST_DMA_CHCTL0_CH0_PDM   0x0000000AU
 
#define HOST_DMA_CHCTL0_CH0_HIF   0x0000000BU
 
#define HOST_DMA_CHCTL0_CH0_UART2   0x0000000CU
 
#define HOST_DMA_CHCTL0_CH1_W   4U
 
#define HOST_DMA_CHCTL0_CH1_M   0x000000F0U
 
#define HOST_DMA_CHCTL0_CH1_S   4U
 
#define HOST_DMA_CHCTL0_CH1_UART0   0x00000000U
 
#define HOST_DMA_CHCTL0_CH1_UART1   0x00000010U
 
#define HOST_DMA_CHCTL0_CH1_SPIO   0x00000020U
 
#define HOST_DMA_CHCTL0_CH1_SPI1   0x00000030U
 
#define HOST_DMA_CHCTL0_CH1_I2C0   0x00000040U
 
#define HOST_DMA_CHCTL0_CH1_I2C1   0x00000050U
 
#define HOST_DMA_CHCTL0_CH1_SDMMC   0x00000060U
 
#define HOST_DMA_CHCTL0_CH1_SDIO   0x00000070U
 
#define HOST_DMA_CHCTL0_CH1_MCAN   0x00000080U
 
#define HOST_DMA_CHCTL0_CH1_ADC   0x00000090U
 
#define HOST_DMA_CHCTL0_CH1_PDM   0x000000A0U
 
#define HOST_DMA_CHCTL0_CH1_HIF   0x000000B0U
 
#define HOST_DMA_CHCTL0_CH1_UART2   0x000000C0U
 
#define HOST_DMA_CHCTL0_CH2_W   4U
 
#define HOST_DMA_CHCTL0_CH2_M   0x00000F00U
 
#define HOST_DMA_CHCTL0_CH2_S   8U
 
#define HOST_DMA_CHCTL0_CH2_UART0   0x00000000U
 
#define HOST_DMA_CHCTL0_CH2_UART1   0x00000100U
 
#define HOST_DMA_CHCTL0_CH2_SPIO   0x00000200U
 
#define HOST_DMA_CHCTL0_CH2_SPI1   0x00000300U
 
#define HOST_DMA_CHCTL0_CH2_I2C0   0x00000400U
 
#define HOST_DMA_CHCTL0_CH2_I2C1   0x00000500U
 
#define HOST_DMA_CHCTL0_CH2_SDMMC   0x00000600U
 
#define HOST_DMA_CHCTL0_CH2_SDIO   0x00000700U
 
#define HOST_DMA_CHCTL0_CH2_MCAN   0x00000800U
 
#define HOST_DMA_CHCTL0_CH2_ADC   0x00000900U
 
#define HOST_DMA_CHCTL0_CH2_PDM   0x00000A00U
 
#define HOST_DMA_CHCTL0_CH2_HIF   0x00000B00U
 
#define HOST_DMA_CHCTL0_CH2_UART2   0x00000C00U
 
#define HOST_DMA_CHCTL0_CH3_W   4U
 
#define HOST_DMA_CHCTL0_CH3_M   0x0000F000U
 
#define HOST_DMA_CHCTL0_CH3_S   12U
 
#define HOST_DMA_CHCTL0_CH3_UART0   0x00000000U
 
#define HOST_DMA_CHCTL0_CH3_UART1   0x00001000U
 
#define HOST_DMA_CHCTL0_CH3_SPIO   0x00002000U
 
#define HOST_DMA_CHCTL0_CH3_SPI1   0x00003000U
 
#define HOST_DMA_CHCTL0_CH3_I2C0   0x00004000U
 
#define HOST_DMA_CHCTL0_CH3_I2C1   0x00005000U
 
#define HOST_DMA_CHCTL0_CH3_SDMMC   0x00006000U
 
#define HOST_DMA_CHCTL0_CH3_SDIO   0x00007000U
 
#define HOST_DMA_CHCTL0_CH3_MCAN   0x00008000U
 
#define HOST_DMA_CHCTL0_CH3_ADC   0x00009000U
 
#define HOST_DMA_CHCTL0_CH3_PDM   0x0000A000U
 
#define HOST_DMA_CHCTL0_CH3_HIF   0x0000B000U
 
#define HOST_DMA_CHCTL0_CH3_UART2   0x0000C000U
 
#define HOST_DMA_CHCTL0_CH4_W   4U
 
#define HOST_DMA_CHCTL0_CH4_M   0x000F0000U
 
#define HOST_DMA_CHCTL0_CH4_S   16U
 
#define HOST_DMA_CHCTL0_CH4_UART0   0x00000000U
 
#define HOST_DMA_CHCTL0_CH4_UART1   0x00010000U
 
#define HOST_DMA_CHCTL0_CH4_SPIO   0x00020000U
 
#define HOST_DMA_CHCTL0_CH4_SPI1   0x00030000U
 
#define HOST_DMA_CHCTL0_CH4_I2C0   0x00040000U
 
#define HOST_DMA_CHCTL0_CH4_I2C1   0x00050000U
 
#define HOST_DMA_CHCTL0_CH4_SDMMC   0x00060000U
 
#define HOST_DMA_CHCTL0_CH4_SDIO   0x00070000U
 
#define HOST_DMA_CHCTL0_CH4_MCAN   0x00080000U
 
#define HOST_DMA_CHCTL0_CH4_ADC   0x00090000U
 
#define HOST_DMA_CHCTL0_CH4_PDM   0x000A0000U
 
#define HOST_DMA_CHCTL0_CH4_HIF   0x000B0000U
 
#define HOST_DMA_CHCTL0_CH4_UART2   0x000C0000U
 
#define HOST_DMA_CHCTL0_CH5_W   4U
 
#define HOST_DMA_CHCTL0_CH5_M   0x00F00000U
 
#define HOST_DMA_CHCTL0_CH5_S   20U
 
#define HOST_DMA_CHCTL0_CH5_UART0   0x00000000U
 
#define HOST_DMA_CHCTL0_CH5_UART1   0x00100000U
 
#define HOST_DMA_CHCTL0_CH5_SPIO   0x00200000U
 
#define HOST_DMA_CHCTL0_CH5_SPI1   0x00300000U
 
#define HOST_DMA_CHCTL0_CH5_I2C0   0x00400000U
 
#define HOST_DMA_CHCTL0_CH5_I2C1   0x00500000U
 
#define HOST_DMA_CHCTL0_CH5_SDMMC   0x00600000U
 
#define HOST_DMA_CHCTL0_CH5_SDIO   0x00700000U
 
#define HOST_DMA_CHCTL0_CH5_MCAN   0x00800000U
 
#define HOST_DMA_CHCTL0_CH5_ADC   0x00900000U
 
#define HOST_DMA_CHCTL0_CH5_PDM   0x00A00000U
 
#define HOST_DMA_CHCTL0_CH5_HIF   0x00B00000U
 
#define HOST_DMA_CHCTL0_CH5_UART2   0x00C00000U
 
#define HOST_DMA_CHCTL0_CH6_W   4U
 
#define HOST_DMA_CHCTL0_CH6_M   0x0F000000U
 
#define HOST_DMA_CHCTL0_CH6_S   24U
 
#define HOST_DMA_CHCTL0_CH6_UART0   0x00000000U
 
#define HOST_DMA_CHCTL0_CH6_UART1   0x01000000U
 
#define HOST_DMA_CHCTL0_CH6_SPIO   0x02000000U
 
#define HOST_DMA_CHCTL0_CH6_SPI1   0x03000000U
 
#define HOST_DMA_CHCTL0_CH6_I2C0   0x04000000U
 
#define HOST_DMA_CHCTL0_CH6_I2C1   0x05000000U
 
#define HOST_DMA_CHCTL0_CH6_SDMMC   0x06000000U
 
#define HOST_DMA_CHCTL0_CH6_SDIO   0x07000000U
 
#define HOST_DMA_CHCTL0_CH6_MCAN   0x08000000U
 
#define HOST_DMA_CHCTL0_CH6_ADC   0x09000000U
 
#define HOST_DMA_CHCTL0_CH6_PDM   0x0A000000U
 
#define HOST_DMA_CHCTL0_CH6_HIF   0x0B000000U
 
#define HOST_DMA_CHCTL0_CH6_UART2   0x0C000000U
 
#define HOST_DMA_CHCTL0_CH7_W   4U
 
#define HOST_DMA_CHCTL0_CH7_M   0xF0000000U
 
#define HOST_DMA_CHCTL0_CH7_S   28U
 
#define HOST_DMA_CHCTL0_CH7_UART0   0x00000000U
 
#define HOST_DMA_CHCTL0_CH7_UART1   0x10000000U
 
#define HOST_DMA_CHCTL0_CH7_SPIO   0x20000000U
 
#define HOST_DMA_CHCTL0_CH7_SPI1   0x30000000U
 
#define HOST_DMA_CHCTL0_CH7_I2C0   0x40000000U
 
#define HOST_DMA_CHCTL0_CH7_I2C1   0x50000000U
 
#define HOST_DMA_CHCTL0_CH7_SDMMC   0x60000000U
 
#define HOST_DMA_CHCTL0_CH7_SDIO   0x70000000U
 
#define HOST_DMA_CHCTL0_CH7_MCAN   0x80000000U
 
#define HOST_DMA_CHCTL0_CH7_ADC   0x90000000U
 
#define HOST_DMA_CHCTL0_CH7_PDM   0xA0000000U
 
#define HOST_DMA_CHCTL0_CH7_HIF   0xB0000000U
 
#define HOST_DMA_CHCTL0_CH7_UART2   0xC0000000U
 
#define HOST_DMA_CHCTL1_CH8_W   4U
 
#define HOST_DMA_CHCTL1_CH8_M   0x0000000FU
 
#define HOST_DMA_CHCTL1_CH8_S   0U
 
#define HOST_DMA_CHCTL1_CH8_UART0   0x00000000U
 
#define HOST_DMA_CHCTL1_CH8_UART1   0x00000001U
 
#define HOST_DMA_CHCTL1_CH8_SPIO   0x00000002U
 
#define HOST_DMA_CHCTL1_CH8_SPI1   0x00000003U
 
#define HOST_DMA_CHCTL1_CH8_I2C0   0x00000004U
 
#define HOST_DMA_CHCTL1_CH8_I2C1   0x00000005U
 
#define HOST_DMA_CHCTL1_CH8_SDMMC   0x00000006U
 
#define HOST_DMA_CHCTL1_CH8_SDIO   0x00000007U
 
#define HOST_DMA_CHCTL1_CH8_MCAN   0x00000008U
 
#define HOST_DMA_CHCTL1_CH8_ADC   0x00000009U
 
#define HOST_DMA_CHCTL1_CH8_PDM   0x0000000AU
 
#define HOST_DMA_CHCTL1_CH8_HIF   0x0000000BU
 
#define HOST_DMA_CHCTL1_CH8_UART2   0x0000000CU
 
#define HOST_DMA_CHCTL1_CH9_W   4U
 
#define HOST_DMA_CHCTL1_CH9_M   0x000000F0U
 
#define HOST_DMA_CHCTL1_CH9_S   4U
 
#define HOST_DMA_CHCTL1_CH9_UART0   0x00000000U
 
#define HOST_DMA_CHCTL1_CH9_UART1   0x00000010U
 
#define HOST_DMA_CHCTL1_CH9_SPIO   0x00000020U
 
#define HOST_DMA_CHCTL1_CH9_SPI1   0x00000030U
 
#define HOST_DMA_CHCTL1_CH9_I2C0   0x00000040U
 
#define HOST_DMA_CHCTL1_CH9_I2C1   0x00000050U
 
#define HOST_DMA_CHCTL1_CH9_SDMMC   0x00000060U
 
#define HOST_DMA_CHCTL1_CH9_SDIO   0x00000070U
 
#define HOST_DMA_CHCTL1_CH9_MCAN   0x00000080U
 
#define HOST_DMA_CHCTL1_CH9_ADC   0x00000090U
 
#define HOST_DMA_CHCTL1_CH9_PDM   0x000000A0U
 
#define HOST_DMA_CHCTL1_CH9_HIF   0x000000B0U
 
#define HOST_DMA_CHCTL1_CH9_UART2   0x000000C0U
 
#define HOST_DMA_CHCTL1_CH10_W   4U
 
#define HOST_DMA_CHCTL1_CH10_M   0x00000F00U
 
#define HOST_DMA_CHCTL1_CH10_S   8U
 
#define HOST_DMA_CHCTL1_CH10_UART0   0x00000000U
 
#define HOST_DMA_CHCTL1_CH10_UART1   0x00000100U
 
#define HOST_DMA_CHCTL1_CH10_SPIO   0x00000200U
 
#define HOST_DMA_CHCTL1_CH10_SPI1   0x00000300U
 
#define HOST_DMA_CHCTL1_CH10_I2C0   0x00000400U
 
#define HOST_DMA_CHCTL1_CH10_I2C1   0x00000500U
 
#define HOST_DMA_CHCTL1_CH10_SDMMC   0x00000600U
 
#define HOST_DMA_CHCTL1_CH10_SDIO   0x00000700U
 
#define HOST_DMA_CHCTL1_CH10_MCAN   0x00000800U
 
#define HOST_DMA_CHCTL1_CH10_ADC   0x00000900U
 
#define HOST_DMA_CHCTL1_CH10_PDM   0x00000A00U
 
#define HOST_DMA_CHCTL1_CH10_HIF   0x00000B00U
 
#define HOST_DMA_CHCTL1_CH10_UART2   0x00000C00U
 
#define HOST_DMA_CHCTL1_CH11_W   4U
 
#define HOST_DMA_CHCTL1_CH11_M   0x0000F000U
 
#define HOST_DMA_CHCTL1_CH11_S   12U
 
#define HOST_DMA_CHCTL1_CH11_UART0   0x00000000U
 
#define HOST_DMA_CHCTL1_CH11_UART1   0x00001000U
 
#define HOST_DMA_CHCTL1_CH11_SPIO   0x00002000U
 
#define HOST_DMA_CHCTL1_CH11_SPI1   0x00003000U
 
#define HOST_DMA_CHCTL1_CH11_I2C0   0x00004000U
 
#define HOST_DMA_CHCTL1_CH11_I2C1   0x00005000U
 
#define HOST_DMA_CHCTL1_CH11_SDMMC   0x00006000U
 
#define HOST_DMA_CHCTL1_CH11_SDIO   0x00007000U
 
#define HOST_DMA_CHCTL1_CH11_MCAN   0x00008000U
 
#define HOST_DMA_CHCTL1_CH11_ADC   0x00009000U
 
#define HOST_DMA_CHCTL1_CH11_PDM   0x0000A000U
 
#define HOST_DMA_CHCTL1_CH11_HIF   0x0000B000U
 
#define HOST_DMA_CHCTL1_CH11_UART2   0x0000C000U
 
#define HOST_DMA_CHCTL1_CH12_W   4U
 
#define HOST_DMA_CHCTL1_CH12_M   0x000F0000U
 
#define HOST_DMA_CHCTL1_CH12_S   16U
 
#define HOST_DMA_CHCTL1_CH12_UART0   0x00000000U
 
#define HOST_DMA_CHCTL1_CH12_UART1   0x00010000U
 
#define HOST_DMA_CHCTL1_CH12_SPIO   0x00020000U
 
#define HOST_DMA_CHCTL1_CH12_SPI1   0x00030000U
 
#define HOST_DMA_CHCTL1_CH12_I2C0   0x00040000U
 
#define HOST_DMA_CHCTL1_CH12_I2C1   0x00050000U
 
#define HOST_DMA_CHCTL1_CH12_SDMMC   0x00060000U
 
#define HOST_DMA_CHCTL1_CH12_SDIO   0x00070000U
 
#define HOST_DMA_CHCTL1_CH12_MCAN   0x00080000U
 
#define HOST_DMA_CHCTL1_CH12_ADC   0x00090000U
 
#define HOST_DMA_CHCTL1_CH12_PDM   0x000A0000U
 
#define HOST_DMA_CHCTL1_CH12_HIF   0x000B0000U
 
#define HOST_DMA_CHCTL1_CH12_UART2   0x000C0000U
 
#define HOST_DMA_CHCTL1_CH13_W   4U
 
#define HOST_DMA_CHCTL1_CH13_M   0x00F00000U
 
#define HOST_DMA_CHCTL1_CH13_S   20U
 
#define HOST_DMA_CHCTL1_CH13_UART0   0x00000000U
 
#define HOST_DMA_CHCTL1_CH13_UART1   0x00100000U
 
#define HOST_DMA_CHCTL1_CH13_SPIO   0x00200000U
 
#define HOST_DMA_CHCTL1_CH13_SPI1   0x00300000U
 
#define HOST_DMA_CHCTL1_CH13_I2C0   0x00400000U
 
#define HOST_DMA_CHCTL1_CH13_I2C1   0x00500000U
 
#define HOST_DMA_CHCTL1_CH13_SDMMC   0x00600000U
 
#define HOST_DMA_CHCTL1_CH13_SDIO   0x00700000U
 
#define HOST_DMA_CHCTL1_CH13_MCAN   0x00800000U
 
#define HOST_DMA_CHCTL1_CH13_ADC   0x00900000U
 
#define HOST_DMA_CHCTL1_CH13_PDM   0x00A00000U
 
#define HOST_DMA_CHCTL1_CH13_HIF   0x00B00000U
 
#define HOST_DMA_CHCTL1_CH13_UART2   0x00C00000U
 
#define HOST_DMA_PRIOCFG_PRIOEN   0x00000001U
 
#define HOST_DMA_PRIOCFG_PRIOEN_M   0x00000001U
 
#define HOST_DMA_PRIOCFG_PRIOEN_S   0U
 
#define HOST_DMA_PRIOCFG_CH1ST_W   4U
 
#define HOST_DMA_PRIOCFG_CH1ST_M   0x00000F00U
 
#define HOST_DMA_PRIOCFG_CH1ST_S   8U
 
#define HOST_DMA_PRIOCFG_CH2ND_W   4U
 
#define HOST_DMA_PRIOCFG_CH2ND_M   0x000F0000U
 
#define HOST_DMA_PRIOCFG_CH2ND_S   16U
 
#define HOST_DMA_PRIOCFG_MAXBLOCKS_W   5U
 
#define HOST_DMA_PRIOCFG_MAXBLOCKS_M   0x1F000000U
 
#define HOST_DMA_PRIOCFG_MAXBLOCKS_S   24U
 
#define HOST_DMA_CH0STA_HWEVENT_W   3U
 
#define HOST_DMA_CH0STA_HWEVENT_M   0x00000007U
 
#define HOST_DMA_CH0STA_HWEVENT_S   0U
 
#define HOST_DMA_CH0STA_FSMSTATE_W   4U
 
#define HOST_DMA_CH0STA_FSMSTATE_M   0x00000F00U
 
#define HOST_DMA_CH0STA_FSMSTATE_S   8U
 
#define HOST_DMA_CH0STA_RUN   0x00010000U
 
#define HOST_DMA_CH0STA_RUN_M   0x00010000U
 
#define HOST_DMA_CH0STA_RUN_S   16U
 
#define HOST_DMA_CH0TIPTR_IPTR_W   32U
 
#define HOST_DMA_CH0TIPTR_IPTR_M   0xFFFFFFFFU
 
#define HOST_DMA_CH0TIPTR_IPTR_S   0U
 
#define HOST_DMA_CH0OPTR_OPTR_W   32U
 
#define HOST_DMA_CH0OPTR_OPTR_M   0xFFFFFFFFU
 
#define HOST_DMA_CH0OPTR_OPTR_S   0U
 
#define HOST_DMA_CH0TCTL_TRANSB_W   14U
 
#define HOST_DMA_CH0TCTL_TRANSB_M   0x00003FFFU
 
#define HOST_DMA_CH0TCTL_TRANSB_S   0U
 
#define HOST_DMA_CH0TCTL_BURSTREQ   0x00010000U
 
#define HOST_DMA_CH0TCTL_BURSTREQ_M   0x00010000U
 
#define HOST_DMA_CH0TCTL_BURSTREQ_S   16U
 
#define HOST_DMA_CH0TCTL_SPARE   0x00020000U
 
#define HOST_DMA_CH0TCTL_SPARE_M   0x00020000U
 
#define HOST_DMA_CH0TCTL_SPARE_S   17U
 
#define HOST_DMA_CH0TCTL_ENDIANESS_W   2U
 
#define HOST_DMA_CH0TCTL_ENDIANESS_M   0x03000000U
 
#define HOST_DMA_CH0TCTL_ENDIANESS_S   24U
 
#define HOST_DMA_CH0TCTL2_CMD_W   3U
 
#define HOST_DMA_CH0TCTL2_CMD_M   0x00000007U
 
#define HOST_DMA_CH0TCTL2_CMD_S   0U
 
#define HOST_DMA_CH0TSTA_STA   0x00000001U
 
#define HOST_DMA_CH0TSTA_STA_M   0x00000001U
 
#define HOST_DMA_CH0TSTA_STA_S   0U
 
#define HOST_DMA_CH0TSTA_OFFSET_W   8U
 
#define HOST_DMA_CH0TSTA_OFFSET_M   0x0000FF00U
 
#define HOST_DMA_CH0TSTA_OFFSET_S   8U
 
#define HOST_DMA_CH0TSTA_REMAINB_W   14U
 
#define HOST_DMA_CH0TSTA_REMAINB_M   0x3FFF0000U
 
#define HOST_DMA_CH0TSTA_REMAINB_S   16U
 
#define HOST_DMA_CH0JCTL_WORDSIZE_W   2U
 
#define HOST_DMA_CH0JCTL_WORDSIZE_M   0x00000003U
 
#define HOST_DMA_CH0JCTL_WORDSIZE_S   0U
 
#define HOST_DMA_CH0JCTL_BLKSIZE_W   6U
 
#define HOST_DMA_CH0JCTL_BLKSIZE_M   0x003F0000U
 
#define HOST_DMA_CH0JCTL_BLKSIZE_S   16U
 
#define HOST_DMA_CH0JCTL_BLKMODESRC   0x01000000U
 
#define HOST_DMA_CH0JCTL_BLKMODESRC_M   0x01000000U
 
#define HOST_DMA_CH0JCTL_BLKMODESRC_S   24U
 
#define HOST_DMA_CH0JCTL_BLKMODEDST   0x02000000U
 
#define HOST_DMA_CH0JCTL_BLKMODEDST_M   0x02000000U
 
#define HOST_DMA_CH0JCTL_BLKMODEDST_S   25U
 
#define HOST_DMA_CH0JCTL_DMASIGBPS   0x04000000U
 
#define HOST_DMA_CH0JCTL_DMASIGBPS_M   0x04000000U
 
#define HOST_DMA_CH0JCTL_DMASIGBPS_S   26U
 
#define HOST_DMA_CH0JCTL_FIFOMODS   0x08000000U
 
#define HOST_DMA_CH0JCTL_FIFOMODS_M   0x08000000U
 
#define HOST_DMA_CH0JCTL_FIFOMODS_S   27U
 
#define HOST_DMA_CH0JCTL_FIFOMODD   0x10000000U
 
#define HOST_DMA_CH0JCTL_FIFOMODD_M   0x10000000U
 
#define HOST_DMA_CH0JCTL_FIFOMODD_S   28U
 
#define HOST_DMA_CH0JCTL_SRCDSTCFG   0x20000000U
 
#define HOST_DMA_CH0JCTL_SRCDSTCFG_M   0x20000000U
 
#define HOST_DMA_CH0JCTL_SRCDSTCFG_S   29U
 
#define HOST_DMA_CH0JCTL_ENCLR   0x40000000U
 
#define HOST_DMA_CH0JCTL_ENCLR_M   0x40000000U
 
#define HOST_DMA_CH0JCTL_ENCLR_S   30U
 
#define HOST_DMA_CH1STA_HWEVENT_W   3U
 
#define HOST_DMA_CH1STA_HWEVENT_M   0x00000007U
 
#define HOST_DMA_CH1STA_HWEVENT_S   0U
 
#define HOST_DMA_CH1STA_FSMSTATE_W   4U
 
#define HOST_DMA_CH1STA_FSMSTATE_M   0x00000F00U
 
#define HOST_DMA_CH1STA_FSMSTATE_S   8U
 
#define HOST_DMA_CH1STA_RUN   0x00010000U
 
#define HOST_DMA_CH1STA_RUN_M   0x00010000U
 
#define HOST_DMA_CH1STA_RUN_S   16U
 
#define HOST_DMA_CH1TIPTR_IPTR_W   32U
 
#define HOST_DMA_CH1TIPTR_IPTR_M   0xFFFFFFFFU
 
#define HOST_DMA_CH1TIPTR_IPTR_S   0U
 
#define HOST_DMA_CH1TOPTR_OPTR_W   32U
 
#define HOST_DMA_CH1TOPTR_OPTR_M   0xFFFFFFFFU
 
#define HOST_DMA_CH1TOPTR_OPTR_S   0U
 
#define HOST_DMA_CH1TCTL_TRANSB_W   14U
 
#define HOST_DMA_CH1TCTL_TRANSB_M   0x00003FFFU
 
#define HOST_DMA_CH1TCTL_TRANSB_S   0U
 
#define HOST_DMA_CH1TCTL_BURSTREQ   0x00010000U
 
#define HOST_DMA_CH1TCTL_BURSTREQ_M   0x00010000U
 
#define HOST_DMA_CH1TCTL_BURSTREQ_S   16U
 
#define HOST_DMA_CH1TCTL_SPARE   0x00020000U
 
#define HOST_DMA_CH1TCTL_SPARE_M   0x00020000U
 
#define HOST_DMA_CH1TCTL_SPARE_S   17U
 
#define HOST_DMA_CH1TCTL_ENDIANESS_W   2U
 
#define HOST_DMA_CH1TCTL_ENDIANESS_M   0x03000000U
 
#define HOST_DMA_CH1TCTL_ENDIANESS_S   24U
 
#define HOST_DMA_CH1TCTRL2_CMD_W   3U
 
#define HOST_DMA_CH1TCTRL2_CMD_M   0x00000007U
 
#define HOST_DMA_CH1TCTRL2_CMD_S   0U
 
#define HOST_DMA_CH1TSTA_STA   0x00000001U
 
#define HOST_DMA_CH1TSTA_STA_M   0x00000001U
 
#define HOST_DMA_CH1TSTA_STA_S   0U
 
#define HOST_DMA_CH1TSTA_OFFSET_W   8U
 
#define HOST_DMA_CH1TSTA_OFFSET_M   0x0000FF00U
 
#define HOST_DMA_CH1TSTA_OFFSET_S   8U
 
#define HOST_DMA_CH1TSTA_REMAINB_W   14U
 
#define HOST_DMA_CH1TSTA_REMAINB_M   0x3FFF0000U
 
#define HOST_DMA_CH1TSTA_REMAINB_S   16U
 
#define HOST_DMA_CH1JCTL_WORDSIZE_W   2U
 
#define HOST_DMA_CH1JCTL_WORDSIZE_M   0x00000003U
 
#define HOST_DMA_CH1JCTL_WORDSIZE_S   0U
 
#define HOST_DMA_CH1JCTL_BLKSIZE_W   6U
 
#define HOST_DMA_CH1JCTL_BLKSIZE_M   0x003F0000U
 
#define HOST_DMA_CH1JCTL_BLKSIZE_S   16U
 
#define HOST_DMA_CH1JCTL_BLKMODESRC   0x01000000U
 
#define HOST_DMA_CH1JCTL_BLKMODESRC_M   0x01000000U
 
#define HOST_DMA_CH1JCTL_BLKMODESRC_S   24U
 
#define HOST_DMA_CH1JCTL_BLKMODEDST   0x02000000U
 
#define HOST_DMA_CH1JCTL_BLKMODEDST_M   0x02000000U
 
#define HOST_DMA_CH1JCTL_BLKMODEDST_S   25U
 
#define HOST_DMA_CH1JCTL_DMASIGBPS   0x04000000U
 
#define HOST_DMA_CH1JCTL_DMASIGBPS_M   0x04000000U
 
#define HOST_DMA_CH1JCTL_DMASIGBPS_S   26U
 
#define HOST_DMA_CH1JCTL_FIFOMODS   0x08000000U
 
#define HOST_DMA_CH1JCTL_FIFOMODS_M   0x08000000U
 
#define HOST_DMA_CH1JCTL_FIFOMODS_S   27U
 
#define HOST_DMA_CH1JCTL_FIFOMODD   0x10000000U
 
#define HOST_DMA_CH1JCTL_FIFOMODD_M   0x10000000U
 
#define HOST_DMA_CH1JCTL_FIFOMODD_S   28U
 
#define HOST_DMA_CH1JCTL_SRCDSTCFG   0x20000000U
 
#define HOST_DMA_CH1JCTL_SRCDSTCFG_M   0x20000000U
 
#define HOST_DMA_CH1JCTL_SRCDSTCFG_S   29U
 
#define HOST_DMA_CH1JCTL_ENCLR   0x40000000U
 
#define HOST_DMA_CH1JCTL_ENCLR_M   0x40000000U
 
#define HOST_DMA_CH1JCTL_ENCLR_S   30U
 
#define HOST_DMA_CH2STA_HWEVENT_W   3U
 
#define HOST_DMA_CH2STA_HWEVENT_M   0x00000007U
 
#define HOST_DMA_CH2STA_HWEVENT_S   0U
 
#define HOST_DMA_CH2STA_FSMSTATE_W   4U
 
#define HOST_DMA_CH2STA_FSMSTATE_M   0x00000F00U
 
#define HOST_DMA_CH2STA_FSMSTATE_S   8U
 
#define HOST_DMA_CH2STA_RUN   0x00010000U
 
#define HOST_DMA_CH2STA_RUN_M   0x00010000U
 
#define HOST_DMA_CH2STA_RUN_S   16U
 
#define HOST_DMA_CH2TIPTR_IPTR_W   32U
 
#define HOST_DMA_CH2TIPTR_IPTR_M   0xFFFFFFFFU
 
#define HOST_DMA_CH2TIPTR_IPTR_S   0U
 
#define HOST_DMA_CH2TOPTR_OPTR_W   32U
 
#define HOST_DMA_CH2TOPTR_OPTR_M   0xFFFFFFFFU
 
#define HOST_DMA_CH2TOPTR_OPTR_S   0U
 
#define HOST_DMA_CH2TCTL_TRANSB_W   14U
 
#define HOST_DMA_CH2TCTL_TRANSB_M   0x00003FFFU
 
#define HOST_DMA_CH2TCTL_TRANSB_S   0U
 
#define HOST_DMA_CH2TCTL_BURSTREQ   0x00010000U
 
#define HOST_DMA_CH2TCTL_BURSTREQ_M   0x00010000U
 
#define HOST_DMA_CH2TCTL_BURSTREQ_S   16U
 
#define HOST_DMA_CH2TCTL_SPARE   0x00020000U
 
#define HOST_DMA_CH2TCTL_SPARE_M   0x00020000U
 
#define HOST_DMA_CH2TCTL_SPARE_S   17U
 
#define HOST_DMA_CH2TCTL_ENDIANESS_W   2U
 
#define HOST_DMA_CH2TCTL_ENDIANESS_M   0x03000000U
 
#define HOST_DMA_CH2TCTL_ENDIANESS_S   24U
 
#define HOST_DMA_CH2TCTL2_CMD_W   3U
 
#define HOST_DMA_CH2TCTL2_CMD_M   0x00000007U
 
#define HOST_DMA_CH2TCTL2_CMD_S   0U
 
#define HOST_DMA_CH2TSTA_STA   0x00000001U
 
#define HOST_DMA_CH2TSTA_STA_M   0x00000001U
 
#define HOST_DMA_CH2TSTA_STA_S   0U
 
#define HOST_DMA_CH2TSTA_OFFSET_W   8U
 
#define HOST_DMA_CH2TSTA_OFFSET_M   0x0000FF00U
 
#define HOST_DMA_CH2TSTA_OFFSET_S   8U
 
#define HOST_DMA_CH2TSTA_REMAINB_W   14U
 
#define HOST_DMA_CH2TSTA_REMAINB_M   0x3FFF0000U
 
#define HOST_DMA_CH2TSTA_REMAINB_S   16U
 
#define HOST_DMA_CH2JCTL_WORDSIZE_W   2U
 
#define HOST_DMA_CH2JCTL_WORDSIZE_M   0x00000003U
 
#define HOST_DMA_CH2JCTL_WORDSIZE_S   0U
 
#define HOST_DMA_CH2JCTL_BLKSIZE_W   6U
 
#define HOST_DMA_CH2JCTL_BLKSIZE_M   0x003F0000U
 
#define HOST_DMA_CH2JCTL_BLKSIZE_S   16U
 
#define HOST_DMA_CH2JCTL_DMASIGBPS   0x04000000U
 
#define HOST_DMA_CH2JCTL_DMASIGBPS_M   0x04000000U
 
#define HOST_DMA_CH2JCTL_DMASIGBPS_S   26U
 
#define HOST_DMA_CH2JCTL_FIFOMODS   0x08000000U
 
#define HOST_DMA_CH2JCTL_FIFOMODS_M   0x08000000U
 
#define HOST_DMA_CH2JCTL_FIFOMODS_S   27U
 
#define HOST_DMA_CH2JCTL_FIFOMODD   0x10000000U
 
#define HOST_DMA_CH2JCTL_FIFOMODD_M   0x10000000U
 
#define HOST_DMA_CH2JCTL_FIFOMODD_S   28U
 
#define HOST_DMA_CH2JCTL_SRCDSTCFG   0x20000000U
 
#define HOST_DMA_CH2JCTL_SRCDSTCFG_M   0x20000000U
 
#define HOST_DMA_CH2JCTL_SRCDSTCFG_S   29U
 
#define HOST_DMA_CH2JCTL_ENCLR   0x40000000U
 
#define HOST_DMA_CH2JCTL_ENCLR_M   0x40000000U
 
#define HOST_DMA_CH2JCTL_ENCLR_S   30U
 
#define HOST_DMA_CH3STA_HWEVENT_W   3U
 
#define HOST_DMA_CH3STA_HWEVENT_M   0x00000007U
 
#define HOST_DMA_CH3STA_HWEVENT_S   0U
 
#define HOST_DMA_CH3STA_FSMSTATE_W   4U
 
#define HOST_DMA_CH3STA_FSMSTATE_M   0x00000F00U
 
#define HOST_DMA_CH3STA_FSMSTATE_S   8U
 
#define HOST_DMA_CH3STA_RUN   0x00010000U
 
#define HOST_DMA_CH3STA_RUN_M   0x00010000U
 
#define HOST_DMA_CH3STA_RUN_S   16U
 
#define HOST_DMA_CH3TIPTR_IPTR_W   32U
 
#define HOST_DMA_CH3TIPTR_IPTR_M   0xFFFFFFFFU
 
#define HOST_DMA_CH3TIPTR_IPTR_S   0U
 
#define HOST_DMA_CH3TOPTR_OPTR_W   32U
 
#define HOST_DMA_CH3TOPTR_OPTR_M   0xFFFFFFFFU
 
#define HOST_DMA_CH3TOPTR_OPTR_S   0U
 
#define HOST_DMA_CH3TCTL_TRANSB_W   14U
 
#define HOST_DMA_CH3TCTL_TRANSB_M   0x00003FFFU
 
#define HOST_DMA_CH3TCTL_TRANSB_S   0U
 
#define HOST_DMA_CH3TCTL_BURSTREQ   0x00010000U
 
#define HOST_DMA_CH3TCTL_BURSTREQ_M   0x00010000U
 
#define HOST_DMA_CH3TCTL_BURSTREQ_S   16U
 
#define HOST_DMA_CH3TCTL_SPARE   0x00020000U
 
#define HOST_DMA_CH3TCTL_SPARE_M   0x00020000U
 
#define HOST_DMA_CH3TCTL_SPARE_S   17U
 
#define HOST_DMA_CH3TCTL_ENDIANESS_W   2U
 
#define HOST_DMA_CH3TCTL_ENDIANESS_M   0x03000000U
 
#define HOST_DMA_CH3TCTL_ENDIANESS_S   24U
 
#define HOST_DMA_CH3TCTL2_CMD_W   3U
 
#define HOST_DMA_CH3TCTL2_CMD_M   0x00000007U
 
#define HOST_DMA_CH3TCTL2_CMD_S   0U
 
#define HOST_DMA_CH3TSTA_STA   0x00000001U
 
#define HOST_DMA_CH3TSTA_STA_M   0x00000001U
 
#define HOST_DMA_CH3TSTA_STA_S   0U
 
#define HOST_DMA_CH3TSTA_OFFSET_W   8U
 
#define HOST_DMA_CH3TSTA_OFFSET_M   0x0000FF00U
 
#define HOST_DMA_CH3TSTA_OFFSET_S   8U
 
#define HOST_DMA_CH3TSTA_REMAINB_W   14U
 
#define HOST_DMA_CH3TSTA_REMAINB_M   0x3FFF0000U
 
#define HOST_DMA_CH3TSTA_REMAINB_S   16U
 
#define HOST_DMA_CH3JCTL_WORDSIZE_W   2U
 
#define HOST_DMA_CH3JCTL_WORDSIZE_M   0x00000003U
 
#define HOST_DMA_CH3JCTL_WORDSIZE_S   0U
 
#define HOST_DMA_CH3JCTL_BLKSIZE_W   6U
 
#define HOST_DMA_CH3JCTL_BLKSIZE_M   0x003F0000U
 
#define HOST_DMA_CH3JCTL_BLKSIZE_S   16U
 
#define HOST_DMA_CH3JCTL_DMASIGBPS   0x04000000U
 
#define HOST_DMA_CH3JCTL_DMASIGBPS_M   0x04000000U
 
#define HOST_DMA_CH3JCTL_DMASIGBPS_S   26U
 
#define HOST_DMA_CH3JCTL_FIFOMODS   0x08000000U
 
#define HOST_DMA_CH3JCTL_FIFOMODS_M   0x08000000U
 
#define HOST_DMA_CH3JCTL_FIFOMODS_S   27U
 
#define HOST_DMA_CH3JCTL_FIFOMODD   0x10000000U
 
#define HOST_DMA_CH3JCTL_FIFOMODD_M   0x10000000U
 
#define HOST_DMA_CH3JCTL_FIFOMODD_S   28U
 
#define HOST_DMA_CH3JCTL_SRCDSTCFG   0x20000000U
 
#define HOST_DMA_CH3JCTL_SRCDSTCFG_M   0x20000000U
 
#define HOST_DMA_CH3JCTL_SRCDSTCFG_S   29U
 
#define HOST_DMA_CH3JCTL_ENCLR   0x40000000U
 
#define HOST_DMA_CH3JCTL_ENCLR_M   0x40000000U
 
#define HOST_DMA_CH3JCTL_ENCLR_S   30U
 
#define HOST_DMA_CH4STA_HWEVENT_W   3U
 
#define HOST_DMA_CH4STA_HWEVENT_M   0x00000007U
 
#define HOST_DMA_CH4STA_HWEVENT_S   0U
 
#define HOST_DMA_CH4STA_FSMSTATE_W   4U
 
#define HOST_DMA_CH4STA_FSMSTATE_M   0x00000F00U
 
#define HOST_DMA_CH4STA_FSMSTATE_S   8U
 
#define HOST_DMA_CH4STA_RUN   0x00010000U
 
#define HOST_DMA_CH4STA_RUN_M   0x00010000U
 
#define HOST_DMA_CH4STA_RUN_S   16U
 
#define HOST_DMA_CH4TIPTR_INPTR_W   32U
 
#define HOST_DMA_CH4TIPTR_INPTR_M   0xFFFFFFFFU
 
#define HOST_DMA_CH4TIPTR_INPTR_S   0U
 
#define HOST_DMA_CH4TOPTR_OPTR_W   32U
 
#define HOST_DMA_CH4TOPTR_OPTR_M   0xFFFFFFFFU
 
#define HOST_DMA_CH4TOPTR_OPTR_S   0U
 
#define HOST_DMA_CH4TCTL_TRANSB_W   14U
 
#define HOST_DMA_CH4TCTL_TRANSB_M   0x00003FFFU
 
#define HOST_DMA_CH4TCTL_TRANSB_S   0U
 
#define HOST_DMA_CH4TCTL_BURSTREQ   0x00010000U
 
#define HOST_DMA_CH4TCTL_BURSTREQ_M   0x00010000U
 
#define HOST_DMA_CH4TCTL_BURSTREQ_S   16U
 
#define HOST_DMA_CH4TCTL_SPARE   0x00020000U
 
#define HOST_DMA_CH4TCTL_SPARE_M   0x00020000U
 
#define HOST_DMA_CH4TCTL_SPARE_S   17U
 
#define HOST_DMA_CH4TCTL_ENDIANESS_W   2U
 
#define HOST_DMA_CH4TCTL_ENDIANESS_M   0x03000000U
 
#define HOST_DMA_CH4TCTL_ENDIANESS_S   24U
 
#define HOST_DMA_CH4TCTL2_CMD_W   3U
 
#define HOST_DMA_CH4TCTL2_CMD_M   0x00000007U
 
#define HOST_DMA_CH4TCTL2_CMD_S   0U
 
#define HOST_DMA_CH4TSTA_STA   0x00000001U
 
#define HOST_DMA_CH4TSTA_STA_M   0x00000001U
 
#define HOST_DMA_CH4TSTA_STA_S   0U
 
#define HOST_DMA_CH4TSTA_OFFSET_W   8U
 
#define HOST_DMA_CH4TSTA_OFFSET_M   0x0000FF00U
 
#define HOST_DMA_CH4TSTA_OFFSET_S   8U
 
#define HOST_DMA_CH4TSTA_REMAINB_W   14U
 
#define HOST_DMA_CH4TSTA_REMAINB_M   0x3FFF0000U
 
#define HOST_DMA_CH4TSTA_REMAINB_S   16U
 
#define HOST_DMA_CH4JCTL_WORDSIZE_W   2U
 
#define HOST_DMA_CH4JCTL_WORDSIZE_M   0x00000003U
 
#define HOST_DMA_CH4JCTL_WORDSIZE_S   0U
 
#define HOST_DMA_CH4JCTL_BLKSIZE_W   6U
 
#define HOST_DMA_CH4JCTL_BLKSIZE_M   0x003F0000U
 
#define HOST_DMA_CH4JCTL_BLKSIZE_S   16U
 
#define HOST_DMA_CH4JCTL_DMASIGBPS   0x04000000U
 
#define HOST_DMA_CH4JCTL_DMASIGBPS_M   0x04000000U
 
#define HOST_DMA_CH4JCTL_DMASIGBPS_S   26U
 
#define HOST_DMA_CH4JCTL_FIFOMODS   0x08000000U
 
#define HOST_DMA_CH4JCTL_FIFOMODS_M   0x08000000U
 
#define HOST_DMA_CH4JCTL_FIFOMODS_S   27U
 
#define HOST_DMA_CH4JCTL_FIFOMODD   0x10000000U
 
#define HOST_DMA_CH4JCTL_FIFOMODD_M   0x10000000U
 
#define HOST_DMA_CH4JCTL_FIFOMODD_S   28U
 
#define HOST_DMA_CH4JCTL_SRCDSTCFG   0x20000000U
 
#define HOST_DMA_CH4JCTL_SRCDSTCFG_M   0x20000000U
 
#define HOST_DMA_CH4JCTL_SRCDSTCFG_S   29U
 
#define HOST_DMA_CH4JCTL_ENCLR   0x40000000U
 
#define HOST_DMA_CH4JCTL_ENCLR_M   0x40000000U
 
#define HOST_DMA_CH4JCTL_ENCLR_S   30U
 
#define HOST_DMA_CH5STA_HWEVENT_W   3U
 
#define HOST_DMA_CH5STA_HWEVENT_M   0x00000007U
 
#define HOST_DMA_CH5STA_HWEVENT_S   0U
 
#define HOST_DMA_CH5STA_FSMSTATE_W   4U
 
#define HOST_DMA_CH5STA_FSMSTATE_M   0x00000F00U
 
#define HOST_DMA_CH5STA_FSMSTATE_S   8U
 
#define HOST_DMA_CH5STA_RUN   0x00010000U
 
#define HOST_DMA_CH5STA_RUN_M   0x00010000U
 
#define HOST_DMA_CH5STA_RUN_S   16U
 
#define HOST_DMA_CH5TIPTR_IPTR_W   32U
 
#define HOST_DMA_CH5TIPTR_IPTR_M   0xFFFFFFFFU
 
#define HOST_DMA_CH5TIPTR_IPTR_S   0U
 
#define HOST_DMA_CH5TOPTR_OPTR_W   32U
 
#define HOST_DMA_CH5TOPTR_OPTR_M   0xFFFFFFFFU
 
#define HOST_DMA_CH5TOPTR_OPTR_S   0U
 
#define HOST_DMA_CH5TCTL_TRANSB_W   14U
 
#define HOST_DMA_CH5TCTL_TRANSB_M   0x00003FFFU
 
#define HOST_DMA_CH5TCTL_TRANSB_S   0U
 
#define HOST_DMA_CH5TCTL_BURSTREQ   0x00010000U
 
#define HOST_DMA_CH5TCTL_BURSTREQ_M   0x00010000U
 
#define HOST_DMA_CH5TCTL_BURSTREQ_S   16U
 
#define HOST_DMA_CH5TCTL_SPARE   0x00020000U
 
#define HOST_DMA_CH5TCTL_SPARE_M   0x00020000U
 
#define HOST_DMA_CH5TCTL_SPARE_S   17U
 
#define HOST_DMA_CH5TCTL_ENDIANESS_W   2U
 
#define HOST_DMA_CH5TCTL_ENDIANESS_M   0x03000000U
 
#define HOST_DMA_CH5TCTL_ENDIANESS_S   24U
 
#define HOST_DMA_CH5TCTL2_CMD_W   3U
 
#define HOST_DMA_CH5TCTL2_CMD_M   0x00000007U
 
#define HOST_DMA_CH5TCTL2_CMD_S   0U
 
#define HOST_DMA_CH5TSTA_STA   0x00000001U
 
#define HOST_DMA_CH5TSTA_STA_M   0x00000001U
 
#define HOST_DMA_CH5TSTA_STA_S   0U
 
#define HOST_DMA_CH5TSTA_OFFSET_W   8U
 
#define HOST_DMA_CH5TSTA_OFFSET_M   0x0000FF00U
 
#define HOST_DMA_CH5TSTA_OFFSET_S   8U
 
#define HOST_DMA_CH5TSTA_REMAINB_W   14U
 
#define HOST_DMA_CH5TSTA_REMAINB_M   0x3FFF0000U
 
#define HOST_DMA_CH5TSTA_REMAINB_S   16U
 
#define HOST_DMA_CH5JCTL_WORDSIZE_W   2U
 
#define HOST_DMA_CH5JCTL_WORDSIZE_M   0x00000003U
 
#define HOST_DMA_CH5JCTL_WORDSIZE_S   0U
 
#define HOST_DMA_CH5JCTL_BLKSIZE_W   6U
 
#define HOST_DMA_CH5JCTL_BLKSIZE_M   0x003F0000U
 
#define HOST_DMA_CH5JCTL_BLKSIZE_S   16U
 
#define HOST_DMA_CH5JCTL_DMASIGBPS   0x04000000U
 
#define HOST_DMA_CH5JCTL_DMASIGBPS_M   0x04000000U
 
#define HOST_DMA_CH5JCTL_DMASIGBPS_S   26U
 
#define HOST_DMA_CH5JCTL_FIFOMODS   0x08000000U
 
#define HOST_DMA_CH5JCTL_FIFOMODS_M   0x08000000U
 
#define HOST_DMA_CH5JCTL_FIFOMODS_S   27U
 
#define HOST_DMA_CH5JCTL_FIFOMODD   0x10000000U
 
#define HOST_DMA_CH5JCTL_FIFOMODD_M   0x10000000U
 
#define HOST_DMA_CH5JCTL_FIFOMODD_S   28U
 
#define HOST_DMA_CH5JCTL_SRCDSTCFG   0x20000000U
 
#define HOST_DMA_CH5JCTL_SRCDSTCFG_M   0x20000000U
 
#define HOST_DMA_CH5JCTL_SRCDSTCFG_S   29U
 
#define HOST_DMA_CH5JCTL_ENCLR   0x40000000U
 
#define HOST_DMA_CH5JCTL_ENCLR_M   0x40000000U
 
#define HOST_DMA_CH5JCTL_ENCLR_S   30U
 
#define HOST_DMA_CH6STA_HWEVENT_W   3U
 
#define HOST_DMA_CH6STA_HWEVENT_M   0x00000007U
 
#define HOST_DMA_CH6STA_HWEVENT_S   0U
 
#define HOST_DMA_CH6STA_FSMSTATE_W   4U
 
#define HOST_DMA_CH6STA_FSMSTATE_M   0x00000F00U
 
#define HOST_DMA_CH6STA_FSMSTATE_S   8U
 
#define HOST_DMA_CH6STA_RUN   0x00010000U
 
#define HOST_DMA_CH6STA_RUN_M   0x00010000U
 
#define HOST_DMA_CH6STA_RUN_S   16U
 
#define HOST_DMA_CH6TIPTR_IPTR_W   32U
 
#define HOST_DMA_CH6TIPTR_IPTR_M   0xFFFFFFFFU
 
#define HOST_DMA_CH6TIPTR_IPTR_S   0U
 
#define HOST_DMA_CH6TOPTR_OPTR_W   32U
 
#define HOST_DMA_CH6TOPTR_OPTR_M   0xFFFFFFFFU
 
#define HOST_DMA_CH6TOPTR_OPTR_S   0U
 
#define HOST_DMA_CH6TCTL_TRANSB_W   14U
 
#define HOST_DMA_CH6TCTL_TRANSB_M   0x00003FFFU
 
#define HOST_DMA_CH6TCTL_TRANSB_S   0U
 
#define HOST_DMA_CH6TCTL_BURSTREQ   0x00010000U
 
#define HOST_DMA_CH6TCTL_BURSTREQ_M   0x00010000U
 
#define HOST_DMA_CH6TCTL_BURSTREQ_S   16U
 
#define HOST_DMA_CH6TCTL_SPARE   0x00020000U
 
#define HOST_DMA_CH6TCTL_SPARE_M   0x00020000U
 
#define HOST_DMA_CH6TCTL_SPARE_S   17U
 
#define HOST_DMA_CH6TCTL_ENDIANESS_W   2U
 
#define HOST_DMA_CH6TCTL_ENDIANESS_M   0x03000000U
 
#define HOST_DMA_CH6TCTL_ENDIANESS_S   24U
 
#define HOST_DMA_CH6TCTL2_CMD_W   3U
 
#define HOST_DMA_CH6TCTL2_CMD_M   0x00000007U
 
#define HOST_DMA_CH6TCTL2_CMD_S   0U
 
#define HOST_DMA_CH6TSTA_STA   0x00000001U
 
#define HOST_DMA_CH6TSTA_STA_M   0x00000001U
 
#define HOST_DMA_CH6TSTA_STA_S   0U
 
#define HOST_DMA_CH6TSTA_WORDOFFSET_W   8U
 
#define HOST_DMA_CH6TSTA_WORDOFFSET_M   0x0000FF00U
 
#define HOST_DMA_CH6TSTA_WORDOFFSET_S   8U
 
#define HOST_DMA_CH6TSTA_REMAINB_W   14U
 
#define HOST_DMA_CH6TSTA_REMAINB_M   0x3FFF0000U
 
#define HOST_DMA_CH6TSTA_REMAINB_S   16U
 
#define HOST_DMA_CH6JCTL_WORDSIZE_W   2U
 
#define HOST_DMA_CH6JCTL_WORDSIZE_M   0x00000003U
 
#define HOST_DMA_CH6JCTL_WORDSIZE_S   0U
 
#define HOST_DMA_CH6JCTL_BLKSIZE_W   6U
 
#define HOST_DMA_CH6JCTL_BLKSIZE_M   0x003F0000U
 
#define HOST_DMA_CH6JCTL_BLKSIZE_S   16U
 
#define HOST_DMA_CH6JCTL_DMASIGBPS   0x04000000U
 
#define HOST_DMA_CH6JCTL_DMASIGBPS_M   0x04000000U
 
#define HOST_DMA_CH6JCTL_DMASIGBPS_S   26U
 
#define HOST_DMA_CH6JCTL_FIFOMODS   0x08000000U
 
#define HOST_DMA_CH6JCTL_FIFOMODS_M   0x08000000U
 
#define HOST_DMA_CH6JCTL_FIFOMODS_S   27U
 
#define HOST_DMA_CH6JCTL_FIFOMODD   0x10000000U
 
#define HOST_DMA_CH6JCTL_FIFOMODD_M   0x10000000U
 
#define HOST_DMA_CH6JCTL_FIFOMODD_S   28U
 
#define HOST_DMA_CH6JCTL_SRCDSTCFG   0x20000000U
 
#define HOST_DMA_CH6JCTL_SRCDSTCFG_M   0x20000000U
 
#define HOST_DMA_CH6JCTL_SRCDSTCFG_S   29U
 
#define HOST_DMA_CH6JCTL_ENCLR   0x40000000U
 
#define HOST_DMA_CH6JCTL_ENCLR_M   0x40000000U
 
#define HOST_DMA_CH6JCTL_ENCLR_S   30U
 
#define HOST_DMA_CH7STA_HWEVENT_W   3U
 
#define HOST_DMA_CH7STA_HWEVENT_M   0x00000007U
 
#define HOST_DMA_CH7STA_HWEVENT_S   0U
 
#define HOST_DMA_CH7STA_FSMSTATE_W   4U
 
#define HOST_DMA_CH7STA_FSMSTATE_M   0x00000F00U
 
#define HOST_DMA_CH7STA_FSMSTATE_S   8U
 
#define HOST_DMA_CH7STA_RUN   0x00010000U
 
#define HOST_DMA_CH7STA_RUN_M   0x00010000U
 
#define HOST_DMA_CH7STA_RUN_S   16U
 
#define HOST_DMA_CH7TIPTR_IPTR_W   32U
 
#define HOST_DMA_CH7TIPTR_IPTR_M   0xFFFFFFFFU
 
#define HOST_DMA_CH7TIPTR_IPTR_S   0U
 
#define HOST_DMA_CH7TOPTR_OPTR_W   32U
 
#define HOST_DMA_CH7TOPTR_OPTR_M   0xFFFFFFFFU
 
#define HOST_DMA_CH7TOPTR_OPTR_S   0U
 
#define HOST_DMA_CH7TCTL_TRANSB_W   14U
 
#define HOST_DMA_CH7TCTL_TRANSB_M   0x00003FFFU
 
#define HOST_DMA_CH7TCTL_TRANSB_S   0U
 
#define HOST_DMA_CH7TCTL_BURSTREQ   0x00010000U
 
#define HOST_DMA_CH7TCTL_BURSTREQ_M   0x00010000U
 
#define HOST_DMA_CH7TCTL_BURSTREQ_S   16U
 
#define HOST_DMA_CH7TCTL_SPARE   0x00020000U
 
#define HOST_DMA_CH7TCTL_SPARE_M   0x00020000U
 
#define HOST_DMA_CH7TCTL_SPARE_S   17U
 
#define HOST_DMA_CH7TCTL_ENDIANESS_W   2U
 
#define HOST_DMA_CH7TCTL_ENDIANESS_M   0x03000000U
 
#define HOST_DMA_CH7TCTL_ENDIANESS_S   24U
 
#define HOST_DMA_CH7TCTL2_CMD_W   3U
 
#define HOST_DMA_CH7TCTL2_CMD_M   0x00000007U
 
#define HOST_DMA_CH7TCTL2_CMD_S   0U
 
#define HOST_DMA_CH7TSTA_STA   0x00000001U
 
#define HOST_DMA_CH7TSTA_STA_M   0x00000001U
 
#define HOST_DMA_CH7TSTA_STA_S   0U
 
#define HOST_DMA_CH7TSTA_OFFSET_W   8U
 
#define HOST_DMA_CH7TSTA_OFFSET_M   0x0000FF00U
 
#define HOST_DMA_CH7TSTA_OFFSET_S   8U
 
#define HOST_DMA_CH7TSTA_REMAINB_W   14U
 
#define HOST_DMA_CH7TSTA_REMAINB_M   0x3FFF0000U
 
#define HOST_DMA_CH7TSTA_REMAINB_S   16U
 
#define HOST_DMA_CH7JCTL_WORDSIZE_W   2U
 
#define HOST_DMA_CH7JCTL_WORDSIZE_M   0x00000003U
 
#define HOST_DMA_CH7JCTL_WORDSIZE_S   0U
 
#define HOST_DMA_CH7JCTL_BLKSIZE_W   6U
 
#define HOST_DMA_CH7JCTL_BLKSIZE_M   0x003F0000U
 
#define HOST_DMA_CH7JCTL_BLKSIZE_S   16U
 
#define HOST_DMA_CH7JCTL_DMASIGBPS   0x04000000U
 
#define HOST_DMA_CH7JCTL_DMASIGBPS_M   0x04000000U
 
#define HOST_DMA_CH7JCTL_DMASIGBPS_S   26U
 
#define HOST_DMA_CH7JCTL_FIFOMODS   0x08000000U
 
#define HOST_DMA_CH7JCTL_FIFOMODS_M   0x08000000U
 
#define HOST_DMA_CH7JCTL_FIFOMODS_S   27U
 
#define HOST_DMA_CH7JCTL_FIFOMODD   0x10000000U
 
#define HOST_DMA_CH7JCTL_FIFOMODD_M   0x10000000U
 
#define HOST_DMA_CH7JCTL_FIFOMODD_S   28U
 
#define HOST_DMA_CH7JCTL_SRCDSTCFG   0x20000000U
 
#define HOST_DMA_CH7JCTL_SRCDSTCFG_M   0x20000000U
 
#define HOST_DMA_CH7JCTL_SRCDSTCFG_S   29U
 
#define HOST_DMA_CH7JCTL_ENCLR   0x40000000U
 
#define HOST_DMA_CH7JCTL_ENCLR_M   0x40000000U
 
#define HOST_DMA_CH7JCTL_ENCLR_S   30U
 
#define HOST_DMA_CH8STA_HWEVENT_W   3U
 
#define HOST_DMA_CH8STA_HWEVENT_M   0x00000007U
 
#define HOST_DMA_CH8STA_HWEVENT_S   0U
 
#define HOST_DMA_CH8STA_FSMSTATE_W   4U
 
#define HOST_DMA_CH8STA_FSMSTATE_M   0x00000F00U
 
#define HOST_DMA_CH8STA_FSMSTATE_S   8U
 
#define HOST_DMA_CH8STA_RUN   0x00010000U
 
#define HOST_DMA_CH8STA_RUN_M   0x00010000U
 
#define HOST_DMA_CH8STA_RUN_S   16U
 
#define HOST_DMA_CH8TIPTR_IPTR_W   32U
 
#define HOST_DMA_CH8TIPTR_IPTR_M   0xFFFFFFFFU
 
#define HOST_DMA_CH8TIPTR_IPTR_S   0U
 
#define HOST_DMA_CH8TOPTR_OPTR_W   32U
 
#define HOST_DMA_CH8TOPTR_OPTR_M   0xFFFFFFFFU
 
#define HOST_DMA_CH8TOPTR_OPTR_S   0U
 
#define HOST_DMA_CH8TCTL_TRANSB_W   14U
 
#define HOST_DMA_CH8TCTL_TRANSB_M   0x00003FFFU
 
#define HOST_DMA_CH8TCTL_TRANSB_S   0U
 
#define HOST_DMA_CH8TCTL_BURSTREQ   0x00010000U
 
#define HOST_DMA_CH8TCTL_BURSTREQ_M   0x00010000U
 
#define HOST_DMA_CH8TCTL_BURSTREQ_S   16U
 
#define HOST_DMA_CH8TCTL_SPARE   0x00020000U
 
#define HOST_DMA_CH8TCTL_SPARE_M   0x00020000U
 
#define HOST_DMA_CH8TCTL_SPARE_S   17U
 
#define HOST_DMA_CH8TCTL_ENDIANESS_W   2U
 
#define HOST_DMA_CH8TCTL_ENDIANESS_M   0x03000000U
 
#define HOST_DMA_CH8TCTL_ENDIANESS_S   24U
 
#define HOST_DMA_CH8TCTL2_CMD_W   3U
 
#define HOST_DMA_CH8TCTL2_CMD_M   0x00000007U
 
#define HOST_DMA_CH8TCTL2_CMD_S   0U
 
#define HOST_DMA_CH8TSTA_STA   0x00000001U
 
#define HOST_DMA_CH8TSTA_STA_M   0x00000001U
 
#define HOST_DMA_CH8TSTA_STA_S   0U
 
#define HOST_DMA_CH8TSTA_OFFSET_W   8U
 
#define HOST_DMA_CH8TSTA_OFFSET_M   0x0000FF00U
 
#define HOST_DMA_CH8TSTA_OFFSET_S   8U
 
#define HOST_DMA_CH8TSTA_REMAINB_W   14U
 
#define HOST_DMA_CH8TSTA_REMAINB_M   0x3FFF0000U
 
#define HOST_DMA_CH8TSTA_REMAINB_S   16U
 
#define HOST_DMA_CH8JCTL_WORDSIZE_W   2U
 
#define HOST_DMA_CH8JCTL_WORDSIZE_M   0x00000003U
 
#define HOST_DMA_CH8JCTL_WORDSIZE_S   0U
 
#define HOST_DMA_CH8JCTL_BLKSIZE_W   6U
 
#define HOST_DMA_CH8JCTL_BLKSIZE_M   0x003F0000U
 
#define HOST_DMA_CH8JCTL_BLKSIZE_S   16U
 
#define HOST_DMA_CH8JCTL_DMASIGBPS   0x04000000U
 
#define HOST_DMA_CH8JCTL_DMASIGBPS_M   0x04000000U
 
#define HOST_DMA_CH8JCTL_DMASIGBPS_S   26U
 
#define HOST_DMA_CH8JCTL_FIFOMODS   0x08000000U
 
#define HOST_DMA_CH8JCTL_FIFOMODS_M   0x08000000U
 
#define HOST_DMA_CH8JCTL_FIFOMODS_S   27U
 
#define HOST_DMA_CH8JCTL_FIFOMODD   0x10000000U
 
#define HOST_DMA_CH8JCTL_FIFOMODD_M   0x10000000U
 
#define HOST_DMA_CH8JCTL_FIFOMODD_S   28U
 
#define HOST_DMA_CH8JCTL_SRCDSTCFG   0x20000000U
 
#define HOST_DMA_CH8JCTL_SRCDSTCFG_M   0x20000000U
 
#define HOST_DMA_CH8JCTL_SRCDSTCFG_S   29U
 
#define HOST_DMA_CH8JCTL_ENCLR   0x40000000U
 
#define HOST_DMA_CH8JCTL_ENCLR_M   0x40000000U
 
#define HOST_DMA_CH8JCTL_ENCLR_S   30U
 
#define HOST_DMA_CH9STA_HWEVENT_W   3U
 
#define HOST_DMA_CH9STA_HWEVENT_M   0x00000007U
 
#define HOST_DMA_CH9STA_HWEVENT_S   0U
 
#define HOST_DMA_CH9STA_FSMSTATE_W   4U
 
#define HOST_DMA_CH9STA_FSMSTATE_M   0x00000F00U
 
#define HOST_DMA_CH9STA_FSMSTATE_S   8U
 
#define HOST_DMA_CH9STA_RUN   0x00010000U
 
#define HOST_DMA_CH9STA_RUN_M   0x00010000U
 
#define HOST_DMA_CH9STA_RUN_S   16U
 
#define HOST_DMA_CH9TIPTR_IPTR_W   32U
 
#define HOST_DMA_CH9TIPTR_IPTR_M   0xFFFFFFFFU
 
#define HOST_DMA_CH9TIPTR_IPTR_S   0U
 
#define HOST_DMA_CH9TOPTR_OPTR_W   32U
 
#define HOST_DMA_CH9TOPTR_OPTR_M   0xFFFFFFFFU
 
#define HOST_DMA_CH9TOPTR_OPTR_S   0U
 
#define HOST_DMA_CH9TCTL_TRANSB_W   14U
 
#define HOST_DMA_CH9TCTL_TRANSB_M   0x00003FFFU
 
#define HOST_DMA_CH9TCTL_TRANSB_S   0U
 
#define HOST_DMA_CH9TCTL_BURSTREQ   0x00010000U
 
#define HOST_DMA_CH9TCTL_BURSTREQ_M   0x00010000U
 
#define HOST_DMA_CH9TCTL_BURSTREQ_S   16U
 
#define HOST_DMA_CH9TCTL_SPARE   0x00020000U
 
#define HOST_DMA_CH9TCTL_SPARE_M   0x00020000U
 
#define HOST_DMA_CH9TCTL_SPARE_S   17U
 
#define HOST_DMA_CH9TCTL_ENDIANESS_W   2U
 
#define HOST_DMA_CH9TCTL_ENDIANESS_M   0x03000000U
 
#define HOST_DMA_CH9TCTL_ENDIANESS_S   24U
 
#define HOST_DMA_CH9TCTL2_CMD_W   3U
 
#define HOST_DMA_CH9TCTL2_CMD_M   0x00000007U
 
#define HOST_DMA_CH9TCTL2_CMD_S   0U
 
#define HOST_DMA_CH9TSTA_STA   0x00000001U
 
#define HOST_DMA_CH9TSTA_STA_M   0x00000001U
 
#define HOST_DMA_CH9TSTA_STA_S   0U
 
#define HOST_DMA_CH9TSTA_OFFSET_W   8U
 
#define HOST_DMA_CH9TSTA_OFFSET_M   0x0000FF00U
 
#define HOST_DMA_CH9TSTA_OFFSET_S   8U
 
#define HOST_DMA_CH9TSTA_REMAINB_W   14U
 
#define HOST_DMA_CH9TSTA_REMAINB_M   0x3FFF0000U
 
#define HOST_DMA_CH9TSTA_REMAINB_S   16U
 
#define HOST_DMA_CH9JCTL_WORDSIZE_W   2U
 
#define HOST_DMA_CH9JCTL_WORDSIZE_M   0x00000003U
 
#define HOST_DMA_CH9JCTL_WORDSIZE_S   0U
 
#define HOST_DMA_CH9JCTL_BLKSIZE_W   6U
 
#define HOST_DMA_CH9JCTL_BLKSIZE_M   0x003F0000U
 
#define HOST_DMA_CH9JCTL_BLKSIZE_S   16U
 
#define HOST_DMA_CH9JCTL_DMASIGBPS   0x04000000U
 
#define HOST_DMA_CH9JCTL_DMASIGBPS_M   0x04000000U
 
#define HOST_DMA_CH9JCTL_DMASIGBPS_S   26U
 
#define HOST_DMA_CH9JCTL_FIFOMODS   0x08000000U
 
#define HOST_DMA_CH9JCTL_FIFOMODS_M   0x08000000U
 
#define HOST_DMA_CH9JCTL_FIFOMODS_S   27U
 
#define HOST_DMA_CH9JCTL_FIFOMODD   0x10000000U
 
#define HOST_DMA_CH9JCTL_FIFOMODD_M   0x10000000U
 
#define HOST_DMA_CH9JCTL_FIFOMODD_S   28U
 
#define HOST_DMA_CH9JCTL_SRCDSTCFG   0x20000000U
 
#define HOST_DMA_CH9JCTL_SRCDSTCFG_M   0x20000000U
 
#define HOST_DMA_CH9JCTL_SRCDSTCFG_S   29U
 
#define HOST_DMA_CH9JCTL_ENCLR   0x40000000U
 
#define HOST_DMA_CH9JCTL_ENCLR_M   0x40000000U
 
#define HOST_DMA_CH9JCTL_ENCLR_S   30U
 
#define HOST_DMA_CH10STA_HWEVENT_W   3U
 
#define HOST_DMA_CH10STA_HWEVENT_M   0x00000007U
 
#define HOST_DMA_CH10STA_HWEVENT_S   0U
 
#define HOST_DMA_CH10STA_FSMSTATE_W   4U
 
#define HOST_DMA_CH10STA_FSMSTATE_M   0x00000F00U
 
#define HOST_DMA_CH10STA_FSMSTATE_S   8U
 
#define HOST_DMA_CH10STA_RUN   0x00010000U
 
#define HOST_DMA_CH10STA_RUN_M   0x00010000U
 
#define HOST_DMA_CH10STA_RUN_S   16U
 
#define HOST_DMA_CH10TIPTR_IPTR_W   32U
 
#define HOST_DMA_CH10TIPTR_IPTR_M   0xFFFFFFFFU
 
#define HOST_DMA_CH10TIPTR_IPTR_S   0U
 
#define HOST_DMA_CH10TOPTR_OPTR_W   32U
 
#define HOST_DMA_CH10TOPTR_OPTR_M   0xFFFFFFFFU
 
#define HOST_DMA_CH10TOPTR_OPTR_S   0U
 
#define HOST_DMA_CH10TCTL_TRANSB_W   14U
 
#define HOST_DMA_CH10TCTL_TRANSB_M   0x00003FFFU
 
#define HOST_DMA_CH10TCTL_TRANSB_S   0U
 
#define HOST_DMA_CH10TCTL_BURSTREQ   0x00010000U
 
#define HOST_DMA_CH10TCTL_BURSTREQ_M   0x00010000U
 
#define HOST_DMA_CH10TCTL_BURSTREQ_S   16U
 
#define HOST_DMA_CH10TCTL_SPARE   0x00020000U
 
#define HOST_DMA_CH10TCTL_SPARE_M   0x00020000U
 
#define HOST_DMA_CH10TCTL_SPARE_S   17U
 
#define HOST_DMA_CH10TCTL_ENDIANESS_W   2U
 
#define HOST_DMA_CH10TCTL_ENDIANESS_M   0x03000000U
 
#define HOST_DMA_CH10TCTL_ENDIANESS_S   24U
 
#define HOST_DMA_CH10TCTL2_CMD_W   3U
 
#define HOST_DMA_CH10TCTL2_CMD_M   0x00000007U
 
#define HOST_DMA_CH10TCTL2_CMD_S   0U
 
#define HOST_DMA_CH10TSTA_STA   0x00000001U
 
#define HOST_DMA_CH10TSTA_STA_M   0x00000001U
 
#define HOST_DMA_CH10TSTA_STA_S   0U
 
#define HOST_DMA_CH10TSTA_OFFSET_W   8U
 
#define HOST_DMA_CH10TSTA_OFFSET_M   0x0000FF00U
 
#define HOST_DMA_CH10TSTA_OFFSET_S   8U
 
#define HOST_DMA_CH10TSTA_REMAINB_W   14U
 
#define HOST_DMA_CH10TSTA_REMAINB_M   0x3FFF0000U
 
#define HOST_DMA_CH10TSTA_REMAINB_S   16U
 
#define HOST_DMA_CH10JCTL_WORDSIZE_W   2U
 
#define HOST_DMA_CH10JCTL_WORDSIZE_M   0x00000003U
 
#define HOST_DMA_CH10JCTL_WORDSIZE_S   0U
 
#define HOST_DMA_CH10JCTL_BLKSIZE_W   8U
 
#define HOST_DMA_CH10JCTL_BLKSIZE_M   0x00FF0000U
 
#define HOST_DMA_CH10JCTL_BLKSIZE_S   16U
 
#define HOST_DMA_CH10JCTL_DMASIGBPS   0x04000000U
 
#define HOST_DMA_CH10JCTL_DMASIGBPS_M   0x04000000U
 
#define HOST_DMA_CH10JCTL_DMASIGBPS_S   26U
 
#define HOST_DMA_CH10JCTL_FIFOMODS   0x08000000U
 
#define HOST_DMA_CH10JCTL_FIFOMODS_M   0x08000000U
 
#define HOST_DMA_CH10JCTL_FIFOMODS_S   27U
 
#define HOST_DMA_CH10JCTL_FIFOMODD   0x10000000U
 
#define HOST_DMA_CH10JCTL_FIFOMODD_M   0x10000000U
 
#define HOST_DMA_CH10JCTL_FIFOMODD_S   28U
 
#define HOST_DMA_CH10JCTL_SRCDSTCFG   0x20000000U
 
#define HOST_DMA_CH10JCTL_SRCDSTCFG_M   0x20000000U
 
#define HOST_DMA_CH10JCTL_SRCDSTCFG_S   29U
 
#define HOST_DMA_CH10JCTL_ENCLR   0x40000000U
 
#define HOST_DMA_CH10JCTL_ENCLR_M   0x40000000U
 
#define HOST_DMA_CH10JCTL_ENCLR_S   30U
 
#define HOST_DMA_CH11STA_HWEVENT_W   3U
 
#define HOST_DMA_CH11STA_HWEVENT_M   0x00000007U
 
#define HOST_DMA_CH11STA_HWEVENT_S   0U
 
#define HOST_DMA_CH11STA_FSMSTATE_W   4U
 
#define HOST_DMA_CH11STA_FSMSTATE_M   0x00000F00U
 
#define HOST_DMA_CH11STA_FSMSTATE_S   8U
 
#define HOST_DMA_CH11STA_RUN   0x00010000U
 
#define HOST_DMA_CH11STA_RUN_M   0x00010000U
 
#define HOST_DMA_CH11STA_RUN_S   16U
 
#define HOST_DMA_CH11TIPTR_IPTR_W   32U
 
#define HOST_DMA_CH11TIPTR_IPTR_M   0xFFFFFFFFU
 
#define HOST_DMA_CH11TIPTR_IPTR_S   0U
 
#define HOST_DMA_CH11TOPTR_OPTR_W   32U
 
#define HOST_DMA_CH11TOPTR_OPTR_M   0xFFFFFFFFU
 
#define HOST_DMA_CH11TOPTR_OPTR_S   0U
 
#define HOST_DMA_CH11TCTL_TRANSB_W   14U
 
#define HOST_DMA_CH11TCTL_TRANSB_M   0x00003FFFU
 
#define HOST_DMA_CH11TCTL_TRANSB_S   0U
 
#define HOST_DMA_CH11TCTL_BURSTREQ   0x00010000U
 
#define HOST_DMA_CH11TCTL_BURSTREQ_M   0x00010000U
 
#define HOST_DMA_CH11TCTL_BURSTREQ_S   16U
 
#define HOST_DMA_CH11TCTL_SPARE   0x00020000U
 
#define HOST_DMA_CH11TCTL_SPARE_M   0x00020000U
 
#define HOST_DMA_CH11TCTL_SPARE_S   17U
 
#define HOST_DMA_CH11TCTL_ENDIANESS_W   2U
 
#define HOST_DMA_CH11TCTL_ENDIANESS_M   0x03000000U
 
#define HOST_DMA_CH11TCTL_ENDIANESS_S   24U
 
#define HOST_DMA_CH11TCTL2_CMD_W   3U
 
#define HOST_DMA_CH11TCTL2_CMD_M   0x00000007U
 
#define HOST_DMA_CH11TCTL2_CMD_S   0U
 
#define HOST_DMA_CH11TSTA_STA   0x00000001U
 
#define HOST_DMA_CH11TSTA_STA_M   0x00000001U
 
#define HOST_DMA_CH11TSTA_STA_S   0U
 
#define HOST_DMA_CH11TSTA_OFFSET_W   8U
 
#define HOST_DMA_CH11TSTA_OFFSET_M   0x0000FF00U
 
#define HOST_DMA_CH11TSTA_OFFSET_S   8U
 
#define HOST_DMA_CH11TSTA_REMAINB_W   14U
 
#define HOST_DMA_CH11TSTA_REMAINB_M   0x3FFF0000U
 
#define HOST_DMA_CH11TSTA_REMAINB_S   16U
 
#define HOST_DMA_CH11JCTL_WORDSIZE_W   2U
 
#define HOST_DMA_CH11JCTL_WORDSIZE_M   0x00000003U
 
#define HOST_DMA_CH11JCTL_WORDSIZE_S   0U
 
#define HOST_DMA_CH11JCTL_BLKSIZE_W   6U
 
#define HOST_DMA_CH11JCTL_BLKSIZE_M   0x003F0000U
 
#define HOST_DMA_CH11JCTL_BLKSIZE_S   16U
 
#define HOST_DMA_CH11JCTL_DMASIGBPS   0x04000000U
 
#define HOST_DMA_CH11JCTL_DMASIGBPS_M   0x04000000U
 
#define HOST_DMA_CH11JCTL_DMASIGBPS_S   26U
 
#define HOST_DMA_CH11JCTL_FIFOMODS   0x08000000U
 
#define HOST_DMA_CH11JCTL_FIFOMODS_M   0x08000000U
 
#define HOST_DMA_CH11JCTL_FIFOMODS_S   27U
 
#define HOST_DMA_CH11JCTL_FIFOMODD   0x10000000U
 
#define HOST_DMA_CH11JCTL_FIFOMODD_M   0x10000000U
 
#define HOST_DMA_CH11JCTL_FIFOMODD_S   28U
 
#define HOST_DMA_CH11JCTL_SRCDSTCFG   0x20000000U
 
#define HOST_DMA_CH11JCTL_SRCDSTCFG_M   0x20000000U
 
#define HOST_DMA_CH11JCTL_SRCDSTCFG_S   29U
 
#define HOST_DMA_CH11JCTL_ENCLR   0x40000000U
 
#define HOST_DMA_CH11JCTL_ENCLR_M   0x40000000U
 
#define HOST_DMA_CH11JCTL_ENCLR_S   30U
 
#define HOST_DMA_CH12STA_HWEVENT_W   3U
 
#define HOST_DMA_CH12STA_HWEVENT_M   0x00000007U
 
#define HOST_DMA_CH12STA_HWEVENT_S   0U
 
#define HOST_DMA_CH12STA_FSMSTATE_W   4U
 
#define HOST_DMA_CH12STA_FSMSTATE_M   0x00000F00U
 
#define HOST_DMA_CH12STA_FSMSTATE_S   8U
 
#define HOST_DMA_CH12STA_RUN   0x00010000U
 
#define HOST_DMA_CH12STA_RUN_M   0x00010000U
 
#define HOST_DMA_CH12STA_RUN_S   16U
 
#define HOST_DMA_CH12TIPTR_IPTR_W   32U
 
#define HOST_DMA_CH12TIPTR_IPTR_M   0xFFFFFFFFU
 
#define HOST_DMA_CH12TIPTR_IPTR_S   0U
 
#define HOST_DMA_CH12TOPTR_OPTR_W   32U
 
#define HOST_DMA_CH12TOPTR_OPTR_M   0xFFFFFFFFU
 
#define HOST_DMA_CH12TOPTR_OPTR_S   0U
 
#define HOST_DMA_CH12TCTL_TRANSB_W   14U
 
#define HOST_DMA_CH12TCTL_TRANSB_M   0x00003FFFU
 
#define HOST_DMA_CH12TCTL_TRANSB_S   0U
 
#define HOST_DMA_CH12TCTL_BURSTREQ   0x00010000U
 
#define HOST_DMA_CH12TCTL_BURSTREQ_M   0x00010000U
 
#define HOST_DMA_CH12TCTL_BURSTREQ_S   16U
 
#define HOST_DMA_CH12TCTL_SPARE   0x00020000U
 
#define HOST_DMA_CH12TCTL_SPARE_M   0x00020000U
 
#define HOST_DMA_CH12TCTL_SPARE_S   17U
 
#define HOST_DMA_CH12TCTL_ENDIANESS_W   2U
 
#define HOST_DMA_CH12TCTL_ENDIANESS_M   0x03000000U
 
#define HOST_DMA_CH12TCTL_ENDIANESS_S   24U
 
#define HOST_DMA_CH12TCTL2_CMD_W   3U
 
#define HOST_DMA_CH12TCTL2_CMD_M   0x00000007U
 
#define HOST_DMA_CH12TCTL2_CMD_S   0U
 
#define HOST_DMA_CH12TSTA_STA   0x00000001U
 
#define HOST_DMA_CH12TSTA_STA_M   0x00000001U
 
#define HOST_DMA_CH12TSTA_STA_S   0U
 
#define HOST_DMA_CH12TSTA_OFFSET_W   8U
 
#define HOST_DMA_CH12TSTA_OFFSET_M   0x0000FF00U
 
#define HOST_DMA_CH12TSTA_OFFSET_S   8U
 
#define HOST_DMA_CH12TSTA_REMAINB_W   14U
 
#define HOST_DMA_CH12TSTA_REMAINB_M   0x3FFF0000U
 
#define HOST_DMA_CH12TSTA_REMAINB_S   16U
 
#define HOST_DMA_CH12JCTL_WORDSIZE_W   2U
 
#define HOST_DMA_CH12JCTL_WORDSIZE_M   0x00000003U
 
#define HOST_DMA_CH12JCTL_WORDSIZE_S   0U
 
#define HOST_DMA_CH12JCTL_BLKSIZE_W   6U
 
#define HOST_DMA_CH12JCTL_BLKSIZE_M   0x003F0000U
 
#define HOST_DMA_CH12JCTL_BLKSIZE_S   16U
 
#define HOST_DMA_CH12JCTL_DMASIGBPS   0x04000000U
 
#define HOST_DMA_CH12JCTL_DMASIGBPS_M   0x04000000U
 
#define HOST_DMA_CH12JCTL_DMASIGBPS_S   26U
 
#define HOST_DMA_CH12JCTL_FIFOMODS   0x08000000U
 
#define HOST_DMA_CH12JCTL_FIFOMODS_M   0x08000000U
 
#define HOST_DMA_CH12JCTL_FIFOMODS_S   27U
 
#define HOST_DMA_CH12JCTL_FIFOMODD   0x10000000U
 
#define HOST_DMA_CH12JCTL_FIFOMODD_M   0x10000000U
 
#define HOST_DMA_CH12JCTL_FIFOMODD_S   28U
 
#define HOST_DMA_CH12JCTL_SRCDSTCFG   0x20000000U
 
#define HOST_DMA_CH12JCTL_SRCDSTCFG_M   0x20000000U
 
#define HOST_DMA_CH12JCTL_SRCDSTCFG_S   29U
 
#define HOST_DMA_CH12JCTL_ENCLR   0x40000000U
 
#define HOST_DMA_CH12JCTL_ENCLR_M   0x40000000U
 
#define HOST_DMA_CH12JCTL_ENCLR_S   30U
 
#define HOST_DMA_CH13STA_HWEVENT_W   3U
 
#define HOST_DMA_CH13STA_HWEVENT_M   0x00000007U
 
#define HOST_DMA_CH13STA_HWEVENT_S   0U
 
#define HOST_DMA_CH13STA_FSMSTATE_W   4U
 
#define HOST_DMA_CH13STA_FSMSTATE_M   0x00000F00U
 
#define HOST_DMA_CH13STA_FSMSTATE_S   8U
 
#define HOST_DMA_CH13STA_RUN   0x00010000U
 
#define HOST_DMA_CH13STA_RUN_M   0x00010000U
 
#define HOST_DMA_CH13STA_RUN_S   16U
 
#define HOST_DMA_CH13TIPTR_IPTR_W   32U
 
#define HOST_DMA_CH13TIPTR_IPTR_M   0xFFFFFFFFU
 
#define HOST_DMA_CH13TIPTR_IPTR_S   0U
 
#define HOST_DMA_CH13TOPTR_OPTR_W   32U
 
#define HOST_DMA_CH13TOPTR_OPTR_M   0xFFFFFFFFU
 
#define HOST_DMA_CH13TOPTR_OPTR_S   0U
 
#define HOST_DMA_CH13TCTL_TRANSB_W   14U
 
#define HOST_DMA_CH13TCTL_TRANSB_M   0x00003FFFU
 
#define HOST_DMA_CH13TCTL_TRANSB_S   0U
 
#define HOST_DMA_CH13TCTL_BURSTREQ   0x00010000U
 
#define HOST_DMA_CH13TCTL_BURSTREQ_M   0x00010000U
 
#define HOST_DMA_CH13TCTL_BURSTREQ_S   16U
 
#define HOST_DMA_CH13TCTL_SPARE   0x00020000U
 
#define HOST_DMA_CH13TCTL_SPARE_M   0x00020000U
 
#define HOST_DMA_CH13TCTL_SPARE_S   17U
 
#define HOST_DMA_CH13TCTL_ENDIANESS_W   2U
 
#define HOST_DMA_CH13TCTL_ENDIANESS_M   0x03000000U
 
#define HOST_DMA_CH13TCTL_ENDIANESS_S   24U
 
#define HOST_DMA_CH13TCTL2_CMD_W   3U
 
#define HOST_DMA_CH13TCTL2_CMD_M   0x00000007U
 
#define HOST_DMA_CH13TCTL2_CMD_S   0U
 
#define HOST_DMA_CH13TSTA_STA   0x00000001U
 
#define HOST_DMA_CH13TSTA_STA_M   0x00000001U
 
#define HOST_DMA_CH13TSTA_STA_S   0U
 
#define HOST_DMA_CH13TSTA_OFFSET_W   8U
 
#define HOST_DMA_CH13TSTA_OFFSET_M   0x0000FF00U
 
#define HOST_DMA_CH13TSTA_OFFSET_S   8U
 
#define HOST_DMA_CH13TSTA_REMAINB_W   14U
 
#define HOST_DMA_CH13TSTA_REMAINB_M   0x3FFF0000U
 
#define HOST_DMA_CH13TSTA_REMAINB_S   16U
 
#define HOST_DMA_CH13JCTL_WORDSIZE_W   2U
 
#define HOST_DMA_CH13JCTL_WORDSIZE_M   0x00000003U
 
#define HOST_DMA_CH13JCTL_WORDSIZE_S   0U
 
#define HOST_DMA_CH13JCTL_BLKSIZE_W   6U
 
#define HOST_DMA_CH13JCTL_BLKSIZE_M   0x003F0000U
 
#define HOST_DMA_CH13JCTL_BLKSIZE_S   16U
 
#define HOST_DMA_CH13JCTL_DMASIGBPS   0x04000000U
 
#define HOST_DMA_CH13JCTL_DMASIGBPS_M   0x04000000U
 
#define HOST_DMA_CH13JCTL_DMASIGBPS_S   26U
 
#define HOST_DMA_CH13JCTL_FIFOMODS   0x08000000U
 
#define HOST_DMA_CH13JCTL_FIFOMODS_M   0x08000000U
 
#define HOST_DMA_CH13JCTL_FIFOMODS_S   27U
 
#define HOST_DMA_CH13JCTL_FIFOMODD   0x10000000U
 
#define HOST_DMA_CH13JCTL_FIFOMODD_M   0x10000000U
 
#define HOST_DMA_CH13JCTL_FIFOMODD_S   28U
 
#define HOST_DMA_CH13JCTL_SRCDSTCFG   0x20000000U
 
#define HOST_DMA_CH13JCTL_SRCDSTCFG_M   0x20000000U
 
#define HOST_DMA_CH13JCTL_SRCDSTCFG_S   29U
 
#define HOST_DMA_CH13JCTL_ENCLR   0x40000000U
 
#define HOST_DMA_CH13JCTL_ENCLR_M   0x40000000U
 
#define HOST_DMA_CH13JCTL_ENCLR_S   30U
 

Macro Definition Documentation

§ HOST_DMA_O_CHCTL0

#define HOST_DMA_O_CHCTL0   0x00000000U

Referenced by DMAGetChannelPeripheral(), and DMAInitChannel().

§ HOST_DMA_O_CHCTL1

#define HOST_DMA_O_CHCTL1   0x00000004U

§ HOST_DMA_O_PRIOCFG

#define HOST_DMA_O_PRIOCFG   0x00000018U

§ HOST_DMA_O_CH0STA

#define HOST_DMA_O_CH0STA   0x00001000U

Referenced by DMAGetChannelStatus().

§ HOST_DMA_O_CH0TIPTR

#define HOST_DMA_O_CH0TIPTR   0x00001004U

Referenced by DMAStartTransaction().

§ HOST_DMA_O_CH0OPTR

#define HOST_DMA_O_CH0OPTR   0x00001008U

Referenced by DMAStartTransaction().

§ HOST_DMA_O_CH0TCTL

#define HOST_DMA_O_CH0TCTL   0x0000100CU

Referenced by DMAStartTransaction().

§ HOST_DMA_O_CH0TCTL2

#define HOST_DMA_O_CH0TCTL2   0x00001010U

Referenced by DMAStartTransaction().

§ HOST_DMA_O_CH0TSTA

#define HOST_DMA_O_CH0TSTA   0x00001014U

§ HOST_DMA_O_CH0JCTL

#define HOST_DMA_O_CH0JCTL   0x0000101CU

Referenced by DMAConfigureChannel(), DMAConfigureChannelFlags(), DMADisableDestinationFifoMode(), DMAEnableDestinationFifoMode(), and DMAGetChannelDirection().

§ HOST_DMA_O_CH1STA

#define HOST_DMA_O_CH1STA   0x00002000U

§ HOST_DMA_O_CH1TIPTR

#define HOST_DMA_O_CH1TIPTR   0x00002004U

§ HOST_DMA_O_CH1TOPTR

#define HOST_DMA_O_CH1TOPTR   0x00002008U

§ HOST_DMA_O_CH1TCTL

#define HOST_DMA_O_CH1TCTL   0x0000200CU

§ HOST_DMA_O_CH1TCTRL2

#define HOST_DMA_O_CH1TCTRL2   0x00002010U

§ HOST_DMA_O_CH1TSTA

#define HOST_DMA_O_CH1TSTA   0x00002014U

§ HOST_DMA_O_CH1JCTL

#define HOST_DMA_O_CH1JCTL   0x0000201CU

§ HOST_DMA_O_CH2STA

#define HOST_DMA_O_CH2STA   0x00003000U

§ HOST_DMA_O_CH2TIPTR

#define HOST_DMA_O_CH2TIPTR   0x00003004U

§ HOST_DMA_O_CH2TOPTR

#define HOST_DMA_O_CH2TOPTR   0x00003008U

§ HOST_DMA_O_CH2TCTL

#define HOST_DMA_O_CH2TCTL   0x0000300CU

§ HOST_DMA_O_CH2TCTL2

#define HOST_DMA_O_CH2TCTL2   0x00003010U

§ HOST_DMA_O_CH2TSTA

#define HOST_DMA_O_CH2TSTA   0x00003014U

§ HOST_DMA_O_CH2JCTL

#define HOST_DMA_O_CH2JCTL   0x0000301CU

§ HOST_DMA_O_CH3STA

#define HOST_DMA_O_CH3STA   0x00004000U

§ HOST_DMA_O_CH3TIPTR

#define HOST_DMA_O_CH3TIPTR   0x00004004U

§ HOST_DMA_O_CH3TOPTR

#define HOST_DMA_O_CH3TOPTR   0x00004008U

§ HOST_DMA_O_CH3TCTL

#define HOST_DMA_O_CH3TCTL   0x0000400CU

§ HOST_DMA_O_CH3TCTL2

#define HOST_DMA_O_CH3TCTL2   0x00004010U

§ HOST_DMA_O_CH3TSTA

#define HOST_DMA_O_CH3TSTA   0x00004014U

§ HOST_DMA_O_CH3JCTL

#define HOST_DMA_O_CH3JCTL   0x0000401CU

§ HOST_DMA_O_CH4STA

#define HOST_DMA_O_CH4STA   0x00005000U

§ HOST_DMA_O_CH4TIPTR

#define HOST_DMA_O_CH4TIPTR   0x00005004U

§ HOST_DMA_O_CH4TOPTR

#define HOST_DMA_O_CH4TOPTR   0x00005008U

§ HOST_DMA_O_CH4TCTL

#define HOST_DMA_O_CH4TCTL   0x0000500CU

§ HOST_DMA_O_CH4TCTL2

#define HOST_DMA_O_CH4TCTL2   0x00005010U

§ HOST_DMA_O_CH4TSTA

#define HOST_DMA_O_CH4TSTA   0x00005014U

§ HOST_DMA_O_CH4JCTL

#define HOST_DMA_O_CH4JCTL   0x0000501CU

§ HOST_DMA_O_CH5STA

#define HOST_DMA_O_CH5STA   0x00006000U

§ HOST_DMA_O_CH5TIPTR

#define HOST_DMA_O_CH5TIPTR   0x00006004U

§ HOST_DMA_O_CH5TOPTR

#define HOST_DMA_O_CH5TOPTR   0x00006008U

§ HOST_DMA_O_CH5TCTL

#define HOST_DMA_O_CH5TCTL   0x0000600CU

§ HOST_DMA_O_CH5TCTL2

#define HOST_DMA_O_CH5TCTL2   0x00006010U

§ HOST_DMA_O_CH5TSTA

#define HOST_DMA_O_CH5TSTA   0x00006014U

§ HOST_DMA_O_CH5JCTL

#define HOST_DMA_O_CH5JCTL   0x0000601CU

§ HOST_DMA_O_CH6STA

#define HOST_DMA_O_CH6STA   0x00007000U

§ HOST_DMA_O_CH6TIPTR

#define HOST_DMA_O_CH6TIPTR   0x00007004U

§ HOST_DMA_O_CH6TOPTR

#define HOST_DMA_O_CH6TOPTR   0x00007008U

§ HOST_DMA_O_CH6TCTL

#define HOST_DMA_O_CH6TCTL   0x0000700CU

§ HOST_DMA_O_CH6TCTL2

#define HOST_DMA_O_CH6TCTL2   0x00007010U

§ HOST_DMA_O_CH6TSTA

#define HOST_DMA_O_CH6TSTA   0x00007014U

§ HOST_DMA_O_CH6JCTL

#define HOST_DMA_O_CH6JCTL   0x0000701CU

§ HOST_DMA_O_CH7STA

#define HOST_DMA_O_CH7STA   0x00008000U

§ HOST_DMA_O_CH7TIPTR

#define HOST_DMA_O_CH7TIPTR   0x00008004U

§ HOST_DMA_O_CH7TOPTR

#define HOST_DMA_O_CH7TOPTR   0x00008008U

§ HOST_DMA_O_CH7TCTL

#define HOST_DMA_O_CH7TCTL   0x0000800CU

§ HOST_DMA_O_CH7TCTL2

#define HOST_DMA_O_CH7TCTL2   0x00008010U

§ HOST_DMA_O_CH7TSTA

#define HOST_DMA_O_CH7TSTA   0x00008014U

§ HOST_DMA_O_CH7JCTL

#define HOST_DMA_O_CH7JCTL   0x0000801CU

§ HOST_DMA_O_CH8STA

#define HOST_DMA_O_CH8STA   0x00009000U

§ HOST_DMA_O_CH8TIPTR

#define HOST_DMA_O_CH8TIPTR   0x00009004U

§ HOST_DMA_O_CH8TOPTR

#define HOST_DMA_O_CH8TOPTR   0x00009008U

§ HOST_DMA_O_CH8TCTL

#define HOST_DMA_O_CH8TCTL   0x0000900CU

§ HOST_DMA_O_CH8TCTL2

#define HOST_DMA_O_CH8TCTL2   0x00009010U

§ HOST_DMA_O_CH8TSTA

#define HOST_DMA_O_CH8TSTA   0x00009014U

§ HOST_DMA_O_CH8JCTL

#define HOST_DMA_O_CH8JCTL   0x0000901CU

§ HOST_DMA_O_CH9STA

#define HOST_DMA_O_CH9STA   0x0000A000U

§ HOST_DMA_O_CH9TIPTR

#define HOST_DMA_O_CH9TIPTR   0x0000A004U

§ HOST_DMA_O_CH9TOPTR

#define HOST_DMA_O_CH9TOPTR   0x0000A008U

§ HOST_DMA_O_CH9TCTL

#define HOST_DMA_O_CH9TCTL   0x0000A00CU

§ HOST_DMA_O_CH9TCTL2

#define HOST_DMA_O_CH9TCTL2   0x0000A010U

§ HOST_DMA_O_CH9TSTA

#define HOST_DMA_O_CH9TSTA   0x0000A014U

§ HOST_DMA_O_CH9JCTL

#define HOST_DMA_O_CH9JCTL   0x0000A01CU

§ HOST_DMA_O_CH10STA

#define HOST_DMA_O_CH10STA   0x0000B000U

§ HOST_DMA_O_CH10TIPTR

#define HOST_DMA_O_CH10TIPTR   0x0000B004U

§ HOST_DMA_O_CH10TOPTR

#define HOST_DMA_O_CH10TOPTR   0x0000B008U

§ HOST_DMA_O_CH10TCTL

#define HOST_DMA_O_CH10TCTL   0x0000B00CU

§ HOST_DMA_O_CH10TCTL2

#define HOST_DMA_O_CH10TCTL2   0x0000B010U

§ HOST_DMA_O_CH10TSTA

#define HOST_DMA_O_CH10TSTA   0x0000B014U

§ HOST_DMA_O_CH10JCTL

#define HOST_DMA_O_CH10JCTL   0x0000B01CU

§ HOST_DMA_O_CH11STA

#define HOST_DMA_O_CH11STA   0x0000C000U

§ HOST_DMA_O_CH11TIPTR

#define HOST_DMA_O_CH11TIPTR   0x0000C004U

§ HOST_DMA_O_CH11TOPTR

#define HOST_DMA_O_CH11TOPTR   0x0000C008U

§ HOST_DMA_O_CH11TCTL

#define HOST_DMA_O_CH11TCTL   0x0000C00CU

§ HOST_DMA_O_CH11TCTL2

#define HOST_DMA_O_CH11TCTL2   0x0000C010U

§ HOST_DMA_O_CH11TSTA

#define HOST_DMA_O_CH11TSTA   0x0000C014U

§ HOST_DMA_O_CH11JCTL

#define HOST_DMA_O_CH11JCTL   0x0000C01CU

§ HOST_DMA_O_CH12STA

#define HOST_DMA_O_CH12STA   0x0000D000U

§ HOST_DMA_O_CH12TIPTR

#define HOST_DMA_O_CH12TIPTR   0x0000D004U

§ HOST_DMA_O_CH12TOPTR

#define HOST_DMA_O_CH12TOPTR   0x0000D008U

§ HOST_DMA_O_CH12TCTL

#define HOST_DMA_O_CH12TCTL   0x0000D00CU

§ HOST_DMA_O_CH12TCTL2

#define HOST_DMA_O_CH12TCTL2   0x0000D010U

§ HOST_DMA_O_CH12TSTA

#define HOST_DMA_O_CH12TSTA   0x0000D014U

§ HOST_DMA_O_CH12JCTL

#define HOST_DMA_O_CH12JCTL   0x0000D01CU

§ HOST_DMA_O_CH13STA

#define HOST_DMA_O_CH13STA   0x0000E000U

§ HOST_DMA_O_CH13TIPTR

#define HOST_DMA_O_CH13TIPTR   0x0000E004U

§ HOST_DMA_O_CH13TOPTR

#define HOST_DMA_O_CH13TOPTR   0x0000E008U

§ HOST_DMA_O_CH13TCTL

#define HOST_DMA_O_CH13TCTL   0x0000E00CU

§ HOST_DMA_O_CH13TCTL2

#define HOST_DMA_O_CH13TCTL2   0x0000E010U

§ HOST_DMA_O_CH13TSTA

#define HOST_DMA_O_CH13TSTA   0x0000E014U

§ HOST_DMA_O_CH13JCTL

#define HOST_DMA_O_CH13JCTL   0x0000E01CU

§ HOST_DMA_CHCTL0_CH0_W

#define HOST_DMA_CHCTL0_CH0_W   4U

§ HOST_DMA_CHCTL0_CH0_M

#define HOST_DMA_CHCTL0_CH0_M   0x0000000FU

Referenced by DMAInitChannel().

§ HOST_DMA_CHCTL0_CH0_S

#define HOST_DMA_CHCTL0_CH0_S   0U

§ HOST_DMA_CHCTL0_CH0_UART0

#define HOST_DMA_CHCTL0_CH0_UART0   0x00000000U

§ HOST_DMA_CHCTL0_CH0_UART1

#define HOST_DMA_CHCTL0_CH0_UART1   0x00000001U

§ HOST_DMA_CHCTL0_CH0_SPIO

#define HOST_DMA_CHCTL0_CH0_SPIO   0x00000002U

§ HOST_DMA_CHCTL0_CH0_SPI1

#define HOST_DMA_CHCTL0_CH0_SPI1   0x00000003U

§ HOST_DMA_CHCTL0_CH0_I2C0

#define HOST_DMA_CHCTL0_CH0_I2C0   0x00000004U

§ HOST_DMA_CHCTL0_CH0_I2C1

#define HOST_DMA_CHCTL0_CH0_I2C1   0x00000005U

§ HOST_DMA_CHCTL0_CH0_SDMMC

#define HOST_DMA_CHCTL0_CH0_SDMMC   0x00000006U

§ HOST_DMA_CHCTL0_CH0_SDIO

#define HOST_DMA_CHCTL0_CH0_SDIO   0x00000007U

§ HOST_DMA_CHCTL0_CH0_MCAN

#define HOST_DMA_CHCTL0_CH0_MCAN   0x00000008U

§ HOST_DMA_CHCTL0_CH0_ADC

#define HOST_DMA_CHCTL0_CH0_ADC   0x00000009U

§ HOST_DMA_CHCTL0_CH0_PDM

#define HOST_DMA_CHCTL0_CH0_PDM   0x0000000AU

§ HOST_DMA_CHCTL0_CH0_HIF

#define HOST_DMA_CHCTL0_CH0_HIF   0x0000000BU

§ HOST_DMA_CHCTL0_CH0_UART2

#define HOST_DMA_CHCTL0_CH0_UART2   0x0000000CU

§ HOST_DMA_CHCTL0_CH1_W

#define HOST_DMA_CHCTL0_CH1_W   4U

§ HOST_DMA_CHCTL0_CH1_M

#define HOST_DMA_CHCTL0_CH1_M   0x000000F0U

§ HOST_DMA_CHCTL0_CH1_S

#define HOST_DMA_CHCTL0_CH1_S   4U

§ HOST_DMA_CHCTL0_CH1_UART0

#define HOST_DMA_CHCTL0_CH1_UART0   0x00000000U

§ HOST_DMA_CHCTL0_CH1_UART1

#define HOST_DMA_CHCTL0_CH1_UART1   0x00000010U

§ HOST_DMA_CHCTL0_CH1_SPIO

#define HOST_DMA_CHCTL0_CH1_SPIO   0x00000020U

§ HOST_DMA_CHCTL0_CH1_SPI1

#define HOST_DMA_CHCTL0_CH1_SPI1   0x00000030U

§ HOST_DMA_CHCTL0_CH1_I2C0

#define HOST_DMA_CHCTL0_CH1_I2C0   0x00000040U

§ HOST_DMA_CHCTL0_CH1_I2C1

#define HOST_DMA_CHCTL0_CH1_I2C1   0x00000050U

§ HOST_DMA_CHCTL0_CH1_SDMMC

#define HOST_DMA_CHCTL0_CH1_SDMMC   0x00000060U

§ HOST_DMA_CHCTL0_CH1_SDIO

#define HOST_DMA_CHCTL0_CH1_SDIO   0x00000070U

§ HOST_DMA_CHCTL0_CH1_MCAN

#define HOST_DMA_CHCTL0_CH1_MCAN   0x00000080U

§ HOST_DMA_CHCTL0_CH1_ADC

#define HOST_DMA_CHCTL0_CH1_ADC   0x00000090U

§ HOST_DMA_CHCTL0_CH1_PDM

#define HOST_DMA_CHCTL0_CH1_PDM   0x000000A0U

§ HOST_DMA_CHCTL0_CH1_HIF

#define HOST_DMA_CHCTL0_CH1_HIF   0x000000B0U

§ HOST_DMA_CHCTL0_CH1_UART2

#define HOST_DMA_CHCTL0_CH1_UART2   0x000000C0U

§ HOST_DMA_CHCTL0_CH2_W

#define HOST_DMA_CHCTL0_CH2_W   4U

§ HOST_DMA_CHCTL0_CH2_M

#define HOST_DMA_CHCTL0_CH2_M   0x00000F00U

§ HOST_DMA_CHCTL0_CH2_S

#define HOST_DMA_CHCTL0_CH2_S   8U

§ HOST_DMA_CHCTL0_CH2_UART0

#define HOST_DMA_CHCTL0_CH2_UART0   0x00000000U

§ HOST_DMA_CHCTL0_CH2_UART1

#define HOST_DMA_CHCTL0_CH2_UART1   0x00000100U

§ HOST_DMA_CHCTL0_CH2_SPIO

#define HOST_DMA_CHCTL0_CH2_SPIO   0x00000200U

§ HOST_DMA_CHCTL0_CH2_SPI1

#define HOST_DMA_CHCTL0_CH2_SPI1   0x00000300U

§ HOST_DMA_CHCTL0_CH2_I2C0

#define HOST_DMA_CHCTL0_CH2_I2C0   0x00000400U

§ HOST_DMA_CHCTL0_CH2_I2C1

#define HOST_DMA_CHCTL0_CH2_I2C1   0x00000500U

§ HOST_DMA_CHCTL0_CH2_SDMMC

#define HOST_DMA_CHCTL0_CH2_SDMMC   0x00000600U

§ HOST_DMA_CHCTL0_CH2_SDIO

#define HOST_DMA_CHCTL0_CH2_SDIO   0x00000700U

§ HOST_DMA_CHCTL0_CH2_MCAN

#define HOST_DMA_CHCTL0_CH2_MCAN   0x00000800U

§ HOST_DMA_CHCTL0_CH2_ADC

#define HOST_DMA_CHCTL0_CH2_ADC   0x00000900U

§ HOST_DMA_CHCTL0_CH2_PDM

#define HOST_DMA_CHCTL0_CH2_PDM   0x00000A00U

§ HOST_DMA_CHCTL0_CH2_HIF

#define HOST_DMA_CHCTL0_CH2_HIF   0x00000B00U

§ HOST_DMA_CHCTL0_CH2_UART2

#define HOST_DMA_CHCTL0_CH2_UART2   0x00000C00U

§ HOST_DMA_CHCTL0_CH3_W

#define HOST_DMA_CHCTL0_CH3_W   4U

§ HOST_DMA_CHCTL0_CH3_M

#define HOST_DMA_CHCTL0_CH3_M   0x0000F000U

§ HOST_DMA_CHCTL0_CH3_S

#define HOST_DMA_CHCTL0_CH3_S   12U

§ HOST_DMA_CHCTL0_CH3_UART0

#define HOST_DMA_CHCTL0_CH3_UART0   0x00000000U

§ HOST_DMA_CHCTL0_CH3_UART1

#define HOST_DMA_CHCTL0_CH3_UART1   0x00001000U

§ HOST_DMA_CHCTL0_CH3_SPIO

#define HOST_DMA_CHCTL0_CH3_SPIO   0x00002000U

§ HOST_DMA_CHCTL0_CH3_SPI1

#define HOST_DMA_CHCTL0_CH3_SPI1   0x00003000U

§ HOST_DMA_CHCTL0_CH3_I2C0

#define HOST_DMA_CHCTL0_CH3_I2C0   0x00004000U

§ HOST_DMA_CHCTL0_CH3_I2C1

#define HOST_DMA_CHCTL0_CH3_I2C1   0x00005000U

§ HOST_DMA_CHCTL0_CH3_SDMMC

#define HOST_DMA_CHCTL0_CH3_SDMMC   0x00006000U

§ HOST_DMA_CHCTL0_CH3_SDIO

#define HOST_DMA_CHCTL0_CH3_SDIO   0x00007000U

§ HOST_DMA_CHCTL0_CH3_MCAN

#define HOST_DMA_CHCTL0_CH3_MCAN   0x00008000U

§ HOST_DMA_CHCTL0_CH3_ADC

#define HOST_DMA_CHCTL0_CH3_ADC   0x00009000U

§ HOST_DMA_CHCTL0_CH3_PDM

#define HOST_DMA_CHCTL0_CH3_PDM   0x0000A000U

§ HOST_DMA_CHCTL0_CH3_HIF

#define HOST_DMA_CHCTL0_CH3_HIF   0x0000B000U

§ HOST_DMA_CHCTL0_CH3_UART2

#define HOST_DMA_CHCTL0_CH3_UART2   0x0000C000U

§ HOST_DMA_CHCTL0_CH4_W

#define HOST_DMA_CHCTL0_CH4_W   4U

§ HOST_DMA_CHCTL0_CH4_M

#define HOST_DMA_CHCTL0_CH4_M   0x000F0000U

§ HOST_DMA_CHCTL0_CH4_S

#define HOST_DMA_CHCTL0_CH4_S   16U

§ HOST_DMA_CHCTL0_CH4_UART0

#define HOST_DMA_CHCTL0_CH4_UART0   0x00000000U

§ HOST_DMA_CHCTL0_CH4_UART1

#define HOST_DMA_CHCTL0_CH4_UART1   0x00010000U

§ HOST_DMA_CHCTL0_CH4_SPIO

#define HOST_DMA_CHCTL0_CH4_SPIO   0x00020000U

§ HOST_DMA_CHCTL0_CH4_SPI1

#define HOST_DMA_CHCTL0_CH4_SPI1   0x00030000U

§ HOST_DMA_CHCTL0_CH4_I2C0

#define HOST_DMA_CHCTL0_CH4_I2C0   0x00040000U

§ HOST_DMA_CHCTL0_CH4_I2C1

#define HOST_DMA_CHCTL0_CH4_I2C1   0x00050000U

§ HOST_DMA_CHCTL0_CH4_SDMMC

#define HOST_DMA_CHCTL0_CH4_SDMMC   0x00060000U

§ HOST_DMA_CHCTL0_CH4_SDIO

#define HOST_DMA_CHCTL0_CH4_SDIO   0x00070000U

§ HOST_DMA_CHCTL0_CH4_MCAN

#define HOST_DMA_CHCTL0_CH4_MCAN   0x00080000U

§ HOST_DMA_CHCTL0_CH4_ADC

#define HOST_DMA_CHCTL0_CH4_ADC   0x00090000U

§ HOST_DMA_CHCTL0_CH4_PDM

#define HOST_DMA_CHCTL0_CH4_PDM   0x000A0000U

§ HOST_DMA_CHCTL0_CH4_HIF

#define HOST_DMA_CHCTL0_CH4_HIF   0x000B0000U

§ HOST_DMA_CHCTL0_CH4_UART2

#define HOST_DMA_CHCTL0_CH4_UART2   0x000C0000U

§ HOST_DMA_CHCTL0_CH5_W

#define HOST_DMA_CHCTL0_CH5_W   4U

§ HOST_DMA_CHCTL0_CH5_M

#define HOST_DMA_CHCTL0_CH5_M   0x00F00000U

§ HOST_DMA_CHCTL0_CH5_S

#define HOST_DMA_CHCTL0_CH5_S   20U

§ HOST_DMA_CHCTL0_CH5_UART0

#define HOST_DMA_CHCTL0_CH5_UART0   0x00000000U

§ HOST_DMA_CHCTL0_CH5_UART1

#define HOST_DMA_CHCTL0_CH5_UART1   0x00100000U

§ HOST_DMA_CHCTL0_CH5_SPIO

#define HOST_DMA_CHCTL0_CH5_SPIO   0x00200000U

§ HOST_DMA_CHCTL0_CH5_SPI1

#define HOST_DMA_CHCTL0_CH5_SPI1   0x00300000U

§ HOST_DMA_CHCTL0_CH5_I2C0

#define HOST_DMA_CHCTL0_CH5_I2C0   0x00400000U

§ HOST_DMA_CHCTL0_CH5_I2C1

#define HOST_DMA_CHCTL0_CH5_I2C1   0x00500000U

§ HOST_DMA_CHCTL0_CH5_SDMMC

#define HOST_DMA_CHCTL0_CH5_SDMMC   0x00600000U

§ HOST_DMA_CHCTL0_CH5_SDIO

#define HOST_DMA_CHCTL0_CH5_SDIO   0x00700000U

§ HOST_DMA_CHCTL0_CH5_MCAN

#define HOST_DMA_CHCTL0_CH5_MCAN   0x00800000U

§ HOST_DMA_CHCTL0_CH5_ADC

#define HOST_DMA_CHCTL0_CH5_ADC   0x00900000U

§ HOST_DMA_CHCTL0_CH5_PDM

#define HOST_DMA_CHCTL0_CH5_PDM   0x00A00000U

§ HOST_DMA_CHCTL0_CH5_HIF

#define HOST_DMA_CHCTL0_CH5_HIF   0x00B00000U

§ HOST_DMA_CHCTL0_CH5_UART2

#define HOST_DMA_CHCTL0_CH5_UART2   0x00C00000U

§ HOST_DMA_CHCTL0_CH6_W

#define HOST_DMA_CHCTL0_CH6_W   4U

§ HOST_DMA_CHCTL0_CH6_M

#define HOST_DMA_CHCTL0_CH6_M   0x0F000000U

§ HOST_DMA_CHCTL0_CH6_S

#define HOST_DMA_CHCTL0_CH6_S   24U

§ HOST_DMA_CHCTL0_CH6_UART0

#define HOST_DMA_CHCTL0_CH6_UART0   0x00000000U

§ HOST_DMA_CHCTL0_CH6_UART1

#define HOST_DMA_CHCTL0_CH6_UART1   0x01000000U

§ HOST_DMA_CHCTL0_CH6_SPIO

#define HOST_DMA_CHCTL0_CH6_SPIO   0x02000000U

§ HOST_DMA_CHCTL0_CH6_SPI1

#define HOST_DMA_CHCTL0_CH6_SPI1   0x03000000U

§ HOST_DMA_CHCTL0_CH6_I2C0

#define HOST_DMA_CHCTL0_CH6_I2C0   0x04000000U

§ HOST_DMA_CHCTL0_CH6_I2C1

#define HOST_DMA_CHCTL0_CH6_I2C1   0x05000000U

§ HOST_DMA_CHCTL0_CH6_SDMMC

#define HOST_DMA_CHCTL0_CH6_SDMMC   0x06000000U

§ HOST_DMA_CHCTL0_CH6_SDIO

#define HOST_DMA_CHCTL0_CH6_SDIO   0x07000000U

§ HOST_DMA_CHCTL0_CH6_MCAN

#define HOST_DMA_CHCTL0_CH6_MCAN   0x08000000U

§ HOST_DMA_CHCTL0_CH6_ADC

#define HOST_DMA_CHCTL0_CH6_ADC   0x09000000U

§ HOST_DMA_CHCTL0_CH6_PDM

#define HOST_DMA_CHCTL0_CH6_PDM   0x0A000000U

§ HOST_DMA_CHCTL0_CH6_HIF

#define HOST_DMA_CHCTL0_CH6_HIF   0x0B000000U

§ HOST_DMA_CHCTL0_CH6_UART2

#define HOST_DMA_CHCTL0_CH6_UART2   0x0C000000U

§ HOST_DMA_CHCTL0_CH7_W

#define HOST_DMA_CHCTL0_CH7_W   4U

§ HOST_DMA_CHCTL0_CH7_M

#define HOST_DMA_CHCTL0_CH7_M   0xF0000000U

§ HOST_DMA_CHCTL0_CH7_S

#define HOST_DMA_CHCTL0_CH7_S   28U

§ HOST_DMA_CHCTL0_CH7_UART0

#define HOST_DMA_CHCTL0_CH7_UART0   0x00000000U

§ HOST_DMA_CHCTL0_CH7_UART1

#define HOST_DMA_CHCTL0_CH7_UART1   0x10000000U

§ HOST_DMA_CHCTL0_CH7_SPIO

#define HOST_DMA_CHCTL0_CH7_SPIO   0x20000000U

§ HOST_DMA_CHCTL0_CH7_SPI1

#define HOST_DMA_CHCTL0_CH7_SPI1   0x30000000U

§ HOST_DMA_CHCTL0_CH7_I2C0

#define HOST_DMA_CHCTL0_CH7_I2C0   0x40000000U

§ HOST_DMA_CHCTL0_CH7_I2C1

#define HOST_DMA_CHCTL0_CH7_I2C1   0x50000000U

§ HOST_DMA_CHCTL0_CH7_SDMMC

#define HOST_DMA_CHCTL0_CH7_SDMMC   0x60000000U

§ HOST_DMA_CHCTL0_CH7_SDIO

#define HOST_DMA_CHCTL0_CH7_SDIO   0x70000000U

§ HOST_DMA_CHCTL0_CH7_MCAN

#define HOST_DMA_CHCTL0_CH7_MCAN   0x80000000U

§ HOST_DMA_CHCTL0_CH7_ADC

#define HOST_DMA_CHCTL0_CH7_ADC   0x90000000U

§ HOST_DMA_CHCTL0_CH7_PDM

#define HOST_DMA_CHCTL0_CH7_PDM   0xA0000000U

§ HOST_DMA_CHCTL0_CH7_HIF

#define HOST_DMA_CHCTL0_CH7_HIF   0xB0000000U

§ HOST_DMA_CHCTL0_CH7_UART2

#define HOST_DMA_CHCTL0_CH7_UART2   0xC0000000U

§ HOST_DMA_CHCTL1_CH8_W

#define HOST_DMA_CHCTL1_CH8_W   4U

§ HOST_DMA_CHCTL1_CH8_M

#define HOST_DMA_CHCTL1_CH8_M   0x0000000FU

§ HOST_DMA_CHCTL1_CH8_S

#define HOST_DMA_CHCTL1_CH8_S   0U

§ HOST_DMA_CHCTL1_CH8_UART0

#define HOST_DMA_CHCTL1_CH8_UART0   0x00000000U

§ HOST_DMA_CHCTL1_CH8_UART1

#define HOST_DMA_CHCTL1_CH8_UART1   0x00000001U

§ HOST_DMA_CHCTL1_CH8_SPIO

#define HOST_DMA_CHCTL1_CH8_SPIO   0x00000002U

§ HOST_DMA_CHCTL1_CH8_SPI1

#define HOST_DMA_CHCTL1_CH8_SPI1   0x00000003U

§ HOST_DMA_CHCTL1_CH8_I2C0

#define HOST_DMA_CHCTL1_CH8_I2C0   0x00000004U

§ HOST_DMA_CHCTL1_CH8_I2C1

#define HOST_DMA_CHCTL1_CH8_I2C1   0x00000005U

§ HOST_DMA_CHCTL1_CH8_SDMMC

#define HOST_DMA_CHCTL1_CH8_SDMMC   0x00000006U

§ HOST_DMA_CHCTL1_CH8_SDIO

#define HOST_DMA_CHCTL1_CH8_SDIO   0x00000007U

§ HOST_DMA_CHCTL1_CH8_MCAN

#define HOST_DMA_CHCTL1_CH8_MCAN   0x00000008U

§ HOST_DMA_CHCTL1_CH8_ADC

#define HOST_DMA_CHCTL1_CH8_ADC   0x00000009U

§ HOST_DMA_CHCTL1_CH8_PDM

#define HOST_DMA_CHCTL1_CH8_PDM   0x0000000AU

§ HOST_DMA_CHCTL1_CH8_HIF

#define HOST_DMA_CHCTL1_CH8_HIF   0x0000000BU

§ HOST_DMA_CHCTL1_CH8_UART2

#define HOST_DMA_CHCTL1_CH8_UART2   0x0000000CU

§ HOST_DMA_CHCTL1_CH9_W

#define HOST_DMA_CHCTL1_CH9_W   4U

§ HOST_DMA_CHCTL1_CH9_M

#define HOST_DMA_CHCTL1_CH9_M   0x000000F0U

§ HOST_DMA_CHCTL1_CH9_S

#define HOST_DMA_CHCTL1_CH9_S   4U

§ HOST_DMA_CHCTL1_CH9_UART0

#define HOST_DMA_CHCTL1_CH9_UART0   0x00000000U

§ HOST_DMA_CHCTL1_CH9_UART1

#define HOST_DMA_CHCTL1_CH9_UART1   0x00000010U

§ HOST_DMA_CHCTL1_CH9_SPIO

#define HOST_DMA_CHCTL1_CH9_SPIO   0x00000020U

§ HOST_DMA_CHCTL1_CH9_SPI1

#define HOST_DMA_CHCTL1_CH9_SPI1   0x00000030U

§ HOST_DMA_CHCTL1_CH9_I2C0

#define HOST_DMA_CHCTL1_CH9_I2C0   0x00000040U

§ HOST_DMA_CHCTL1_CH9_I2C1

#define HOST_DMA_CHCTL1_CH9_I2C1   0x00000050U

§ HOST_DMA_CHCTL1_CH9_SDMMC

#define HOST_DMA_CHCTL1_CH9_SDMMC   0x00000060U

§ HOST_DMA_CHCTL1_CH9_SDIO

#define HOST_DMA_CHCTL1_CH9_SDIO   0x00000070U

§ HOST_DMA_CHCTL1_CH9_MCAN

#define HOST_DMA_CHCTL1_CH9_MCAN   0x00000080U

§ HOST_DMA_CHCTL1_CH9_ADC

#define HOST_DMA_CHCTL1_CH9_ADC   0x00000090U

§ HOST_DMA_CHCTL1_CH9_PDM

#define HOST_DMA_CHCTL1_CH9_PDM   0x000000A0U

§ HOST_DMA_CHCTL1_CH9_HIF

#define HOST_DMA_CHCTL1_CH9_HIF   0x000000B0U

§ HOST_DMA_CHCTL1_CH9_UART2

#define HOST_DMA_CHCTL1_CH9_UART2   0x000000C0U

§ HOST_DMA_CHCTL1_CH10_W

#define HOST_DMA_CHCTL1_CH10_W   4U

§ HOST_DMA_CHCTL1_CH10_M

#define HOST_DMA_CHCTL1_CH10_M   0x00000F00U

§ HOST_DMA_CHCTL1_CH10_S

#define HOST_DMA_CHCTL1_CH10_S   8U

§ HOST_DMA_CHCTL1_CH10_UART0

#define HOST_DMA_CHCTL1_CH10_UART0   0x00000000U

§ HOST_DMA_CHCTL1_CH10_UART1

#define HOST_DMA_CHCTL1_CH10_UART1   0x00000100U

§ HOST_DMA_CHCTL1_CH10_SPIO

#define HOST_DMA_CHCTL1_CH10_SPIO   0x00000200U

§ HOST_DMA_CHCTL1_CH10_SPI1

#define HOST_DMA_CHCTL1_CH10_SPI1   0x00000300U

§ HOST_DMA_CHCTL1_CH10_I2C0

#define HOST_DMA_CHCTL1_CH10_I2C0   0x00000400U

§ HOST_DMA_CHCTL1_CH10_I2C1

#define HOST_DMA_CHCTL1_CH10_I2C1   0x00000500U

§ HOST_DMA_CHCTL1_CH10_SDMMC

#define HOST_DMA_CHCTL1_CH10_SDMMC   0x00000600U

§ HOST_DMA_CHCTL1_CH10_SDIO

#define HOST_DMA_CHCTL1_CH10_SDIO   0x00000700U

§ HOST_DMA_CHCTL1_CH10_MCAN

#define HOST_DMA_CHCTL1_CH10_MCAN   0x00000800U

§ HOST_DMA_CHCTL1_CH10_ADC

#define HOST_DMA_CHCTL1_CH10_ADC   0x00000900U

§ HOST_DMA_CHCTL1_CH10_PDM

#define HOST_DMA_CHCTL1_CH10_PDM   0x00000A00U

§ HOST_DMA_CHCTL1_CH10_HIF

#define HOST_DMA_CHCTL1_CH10_HIF   0x00000B00U

§ HOST_DMA_CHCTL1_CH10_UART2

#define HOST_DMA_CHCTL1_CH10_UART2   0x00000C00U

§ HOST_DMA_CHCTL1_CH11_W

#define HOST_DMA_CHCTL1_CH11_W   4U

§ HOST_DMA_CHCTL1_CH11_M

#define HOST_DMA_CHCTL1_CH11_M   0x0000F000U

§ HOST_DMA_CHCTL1_CH11_S

#define HOST_DMA_CHCTL1_CH11_S   12U

§ HOST_DMA_CHCTL1_CH11_UART0

#define HOST_DMA_CHCTL1_CH11_UART0   0x00000000U

§ HOST_DMA_CHCTL1_CH11_UART1

#define HOST_DMA_CHCTL1_CH11_UART1   0x00001000U

§ HOST_DMA_CHCTL1_CH11_SPIO

#define HOST_DMA_CHCTL1_CH11_SPIO   0x00002000U

§ HOST_DMA_CHCTL1_CH11_SPI1

#define HOST_DMA_CHCTL1_CH11_SPI1   0x00003000U

§ HOST_DMA_CHCTL1_CH11_I2C0

#define HOST_DMA_CHCTL1_CH11_I2C0   0x00004000U

§ HOST_DMA_CHCTL1_CH11_I2C1

#define HOST_DMA_CHCTL1_CH11_I2C1   0x00005000U

§ HOST_DMA_CHCTL1_CH11_SDMMC

#define HOST_DMA_CHCTL1_CH11_SDMMC   0x00006000U

§ HOST_DMA_CHCTL1_CH11_SDIO

#define HOST_DMA_CHCTL1_CH11_SDIO   0x00007000U

§ HOST_DMA_CHCTL1_CH11_MCAN

#define HOST_DMA_CHCTL1_CH11_MCAN   0x00008000U

§ HOST_DMA_CHCTL1_CH11_ADC

#define HOST_DMA_CHCTL1_CH11_ADC   0x00009000U

§ HOST_DMA_CHCTL1_CH11_PDM

#define HOST_DMA_CHCTL1_CH11_PDM   0x0000A000U

§ HOST_DMA_CHCTL1_CH11_HIF

#define HOST_DMA_CHCTL1_CH11_HIF   0x0000B000U

§ HOST_DMA_CHCTL1_CH11_UART2

#define HOST_DMA_CHCTL1_CH11_UART2   0x0000C000U

§ HOST_DMA_CHCTL1_CH12_W

#define HOST_DMA_CHCTL1_CH12_W   4U

§ HOST_DMA_CHCTL1_CH12_M

#define HOST_DMA_CHCTL1_CH12_M   0x000F0000U

§ HOST_DMA_CHCTL1_CH12_S

#define HOST_DMA_CHCTL1_CH12_S   16U

§ HOST_DMA_CHCTL1_CH12_UART0

#define HOST_DMA_CHCTL1_CH12_UART0   0x00000000U

§ HOST_DMA_CHCTL1_CH12_UART1

#define HOST_DMA_CHCTL1_CH12_UART1   0x00010000U

§ HOST_DMA_CHCTL1_CH12_SPIO

#define HOST_DMA_CHCTL1_CH12_SPIO   0x00020000U

§ HOST_DMA_CHCTL1_CH12_SPI1

#define HOST_DMA_CHCTL1_CH12_SPI1   0x00030000U

§ HOST_DMA_CHCTL1_CH12_I2C0

#define HOST_DMA_CHCTL1_CH12_I2C0   0x00040000U

§ HOST_DMA_CHCTL1_CH12_I2C1

#define HOST_DMA_CHCTL1_CH12_I2C1   0x00050000U

§ HOST_DMA_CHCTL1_CH12_SDMMC

#define HOST_DMA_CHCTL1_CH12_SDMMC   0x00060000U

§ HOST_DMA_CHCTL1_CH12_SDIO

#define HOST_DMA_CHCTL1_CH12_SDIO   0x00070000U

§ HOST_DMA_CHCTL1_CH12_MCAN

#define HOST_DMA_CHCTL1_CH12_MCAN   0x00080000U

§ HOST_DMA_CHCTL1_CH12_ADC

#define HOST_DMA_CHCTL1_CH12_ADC   0x00090000U

§ HOST_DMA_CHCTL1_CH12_PDM

#define HOST_DMA_CHCTL1_CH12_PDM   0x000A0000U

§ HOST_DMA_CHCTL1_CH12_HIF

#define HOST_DMA_CHCTL1_CH12_HIF   0x000B0000U

§ HOST_DMA_CHCTL1_CH12_UART2

#define HOST_DMA_CHCTL1_CH12_UART2   0x000C0000U

§ HOST_DMA_CHCTL1_CH13_W

#define HOST_DMA_CHCTL1_CH13_W   4U

§ HOST_DMA_CHCTL1_CH13_M

#define HOST_DMA_CHCTL1_CH13_M   0x00F00000U

§ HOST_DMA_CHCTL1_CH13_S

#define HOST_DMA_CHCTL1_CH13_S   20U

§ HOST_DMA_CHCTL1_CH13_UART0

#define HOST_DMA_CHCTL1_CH13_UART0   0x00000000U

§ HOST_DMA_CHCTL1_CH13_UART1

#define HOST_DMA_CHCTL1_CH13_UART1   0x00100000U

§ HOST_DMA_CHCTL1_CH13_SPIO

#define HOST_DMA_CHCTL1_CH13_SPIO   0x00200000U

§ HOST_DMA_CHCTL1_CH13_SPI1

#define HOST_DMA_CHCTL1_CH13_SPI1   0x00300000U

§ HOST_DMA_CHCTL1_CH13_I2C0

#define HOST_DMA_CHCTL1_CH13_I2C0   0x00400000U

§ HOST_DMA_CHCTL1_CH13_I2C1

#define HOST_DMA_CHCTL1_CH13_I2C1   0x00500000U

§ HOST_DMA_CHCTL1_CH13_SDMMC

#define HOST_DMA_CHCTL1_CH13_SDMMC   0x00600000U

§ HOST_DMA_CHCTL1_CH13_SDIO

#define HOST_DMA_CHCTL1_CH13_SDIO   0x00700000U

§ HOST_DMA_CHCTL1_CH13_MCAN

#define HOST_DMA_CHCTL1_CH13_MCAN   0x00800000U

§ HOST_DMA_CHCTL1_CH13_ADC

#define HOST_DMA_CHCTL1_CH13_ADC   0x00900000U

§ HOST_DMA_CHCTL1_CH13_PDM

#define HOST_DMA_CHCTL1_CH13_PDM   0x00A00000U

§ HOST_DMA_CHCTL1_CH13_HIF

#define HOST_DMA_CHCTL1_CH13_HIF   0x00B00000U

§ HOST_DMA_CHCTL1_CH13_UART2

#define HOST_DMA_CHCTL1_CH13_UART2   0x00C00000U

§ HOST_DMA_PRIOCFG_PRIOEN

#define HOST_DMA_PRIOCFG_PRIOEN   0x00000001U

§ HOST_DMA_PRIOCFG_PRIOEN_M

#define HOST_DMA_PRIOCFG_PRIOEN_M   0x00000001U

§ HOST_DMA_PRIOCFG_PRIOEN_S

#define HOST_DMA_PRIOCFG_PRIOEN_S   0U

§ HOST_DMA_PRIOCFG_CH1ST_W

#define HOST_DMA_PRIOCFG_CH1ST_W   4U

§ HOST_DMA_PRIOCFG_CH1ST_M

#define HOST_DMA_PRIOCFG_CH1ST_M   0x00000F00U

§ HOST_DMA_PRIOCFG_CH1ST_S

#define HOST_DMA_PRIOCFG_CH1ST_S   8U

§ HOST_DMA_PRIOCFG_CH2ND_W

#define HOST_DMA_PRIOCFG_CH2ND_W   4U

§ HOST_DMA_PRIOCFG_CH2ND_M

#define HOST_DMA_PRIOCFG_CH2ND_M   0x000F0000U

§ HOST_DMA_PRIOCFG_CH2ND_S

#define HOST_DMA_PRIOCFG_CH2ND_S   16U

§ HOST_DMA_PRIOCFG_MAXBLOCKS_W

#define HOST_DMA_PRIOCFG_MAXBLOCKS_W   5U

§ HOST_DMA_PRIOCFG_MAXBLOCKS_M

#define HOST_DMA_PRIOCFG_MAXBLOCKS_M   0x1F000000U

§ HOST_DMA_PRIOCFG_MAXBLOCKS_S

#define HOST_DMA_PRIOCFG_MAXBLOCKS_S   24U

§ HOST_DMA_CH0STA_HWEVENT_W

#define HOST_DMA_CH0STA_HWEVENT_W   3U

§ HOST_DMA_CH0STA_HWEVENT_M

#define HOST_DMA_CH0STA_HWEVENT_M   0x00000007U

Referenced by DMAGetChannelStatus().

§ HOST_DMA_CH0STA_HWEVENT_S

#define HOST_DMA_CH0STA_HWEVENT_S   0U

Referenced by DMAGetChannelStatus().

§ HOST_DMA_CH0STA_FSMSTATE_W

#define HOST_DMA_CH0STA_FSMSTATE_W   4U

§ HOST_DMA_CH0STA_FSMSTATE_M

#define HOST_DMA_CH0STA_FSMSTATE_M   0x00000F00U

§ HOST_DMA_CH0STA_FSMSTATE_S

#define HOST_DMA_CH0STA_FSMSTATE_S   8U

§ HOST_DMA_CH0STA_RUN

#define HOST_DMA_CH0STA_RUN   0x00010000U

§ HOST_DMA_CH0STA_RUN_M

#define HOST_DMA_CH0STA_RUN_M   0x00010000U

§ HOST_DMA_CH0STA_RUN_S

#define HOST_DMA_CH0STA_RUN_S   16U

§ HOST_DMA_CH0TIPTR_IPTR_W

#define HOST_DMA_CH0TIPTR_IPTR_W   32U

§ HOST_DMA_CH0TIPTR_IPTR_M

#define HOST_DMA_CH0TIPTR_IPTR_M   0xFFFFFFFFU

Referenced by DMAStartTransaction().

§ HOST_DMA_CH0TIPTR_IPTR_S

#define HOST_DMA_CH0TIPTR_IPTR_S   0U

Referenced by DMAStartTransaction().

§ HOST_DMA_CH0OPTR_OPTR_W

#define HOST_DMA_CH0OPTR_OPTR_W   32U

§ HOST_DMA_CH0OPTR_OPTR_M

#define HOST_DMA_CH0OPTR_OPTR_M   0xFFFFFFFFU

Referenced by DMAStartTransaction().

§ HOST_DMA_CH0OPTR_OPTR_S

#define HOST_DMA_CH0OPTR_OPTR_S   0U

Referenced by DMAStartTransaction().

§ HOST_DMA_CH0TCTL_TRANSB_W

#define HOST_DMA_CH0TCTL_TRANSB_W   14U

§ HOST_DMA_CH0TCTL_TRANSB_M

#define HOST_DMA_CH0TCTL_TRANSB_M   0x00003FFFU

Referenced by DMAStartTransaction().

§ HOST_DMA_CH0TCTL_TRANSB_S

#define HOST_DMA_CH0TCTL_TRANSB_S   0U

Referenced by DMAStartTransaction().

§ HOST_DMA_CH0TCTL_BURSTREQ

#define HOST_DMA_CH0TCTL_BURSTREQ   0x00010000U

Referenced by DMAStartTransaction().

§ HOST_DMA_CH0TCTL_BURSTREQ_M

#define HOST_DMA_CH0TCTL_BURSTREQ_M   0x00010000U

§ HOST_DMA_CH0TCTL_BURSTREQ_S

#define HOST_DMA_CH0TCTL_BURSTREQ_S   16U

§ HOST_DMA_CH0TCTL_SPARE

#define HOST_DMA_CH0TCTL_SPARE   0x00020000U

§ HOST_DMA_CH0TCTL_SPARE_M

#define HOST_DMA_CH0TCTL_SPARE_M   0x00020000U

§ HOST_DMA_CH0TCTL_SPARE_S

#define HOST_DMA_CH0TCTL_SPARE_S   17U

§ HOST_DMA_CH0TCTL_ENDIANESS_W

#define HOST_DMA_CH0TCTL_ENDIANESS_W   2U

§ HOST_DMA_CH0TCTL_ENDIANESS_M

#define HOST_DMA_CH0TCTL_ENDIANESS_M   0x03000000U

§ HOST_DMA_CH0TCTL_ENDIANESS_S

#define HOST_DMA_CH0TCTL_ENDIANESS_S   24U

§ HOST_DMA_CH0TCTL2_CMD_W

#define HOST_DMA_CH0TCTL2_CMD_W   3U

§ HOST_DMA_CH0TCTL2_CMD_M

#define HOST_DMA_CH0TCTL2_CMD_M   0x00000007U

Referenced by DMAStartTransaction().

§ HOST_DMA_CH0TCTL2_CMD_S

#define HOST_DMA_CH0TCTL2_CMD_S   0U

Referenced by DMAStartTransaction().

§ HOST_DMA_CH0TSTA_STA

#define HOST_DMA_CH0TSTA_STA   0x00000001U

§ HOST_DMA_CH0TSTA_STA_M

#define HOST_DMA_CH0TSTA_STA_M   0x00000001U

§ HOST_DMA_CH0TSTA_STA_S

#define HOST_DMA_CH0TSTA_STA_S   0U

§ HOST_DMA_CH0TSTA_OFFSET_W

#define HOST_DMA_CH0TSTA_OFFSET_W   8U

§ HOST_DMA_CH0TSTA_OFFSET_M

#define HOST_DMA_CH0TSTA_OFFSET_M   0x0000FF00U

§ HOST_DMA_CH0TSTA_OFFSET_S

#define HOST_DMA_CH0TSTA_OFFSET_S   8U

§ HOST_DMA_CH0TSTA_REMAINB_W

#define HOST_DMA_CH0TSTA_REMAINB_W   14U

§ HOST_DMA_CH0TSTA_REMAINB_M

#define HOST_DMA_CH0TSTA_REMAINB_M   0x3FFF0000U

§ HOST_DMA_CH0TSTA_REMAINB_S

#define HOST_DMA_CH0TSTA_REMAINB_S   16U

§ HOST_DMA_CH0JCTL_WORDSIZE_W

#define HOST_DMA_CH0JCTL_WORDSIZE_W   2U

§ HOST_DMA_CH0JCTL_WORDSIZE_M

#define HOST_DMA_CH0JCTL_WORDSIZE_M   0x00000003U

Referenced by DMAConfigureChannel().

§ HOST_DMA_CH0JCTL_WORDSIZE_S

#define HOST_DMA_CH0JCTL_WORDSIZE_S   0U

Referenced by DMAConfigureChannel().

§ HOST_DMA_CH0JCTL_BLKSIZE_W

#define HOST_DMA_CH0JCTL_BLKSIZE_W   6U

§ HOST_DMA_CH0JCTL_BLKSIZE_M

#define HOST_DMA_CH0JCTL_BLKSIZE_M   0x003F0000U

Referenced by DMAConfigureChannel().

§ HOST_DMA_CH0JCTL_BLKSIZE_S

#define HOST_DMA_CH0JCTL_BLKSIZE_S   16U

Referenced by DMAConfigureChannel().

§ HOST_DMA_CH0JCTL_BLKMODESRC

#define HOST_DMA_CH0JCTL_BLKMODESRC   0x01000000U

§ HOST_DMA_CH0JCTL_BLKMODESRC_M

#define HOST_DMA_CH0JCTL_BLKMODESRC_M   0x01000000U

§ HOST_DMA_CH0JCTL_BLKMODESRC_S

#define HOST_DMA_CH0JCTL_BLKMODESRC_S   24U

§ HOST_DMA_CH0JCTL_BLKMODEDST

#define HOST_DMA_CH0JCTL_BLKMODEDST   0x02000000U

§ HOST_DMA_CH0JCTL_BLKMODEDST_M

#define HOST_DMA_CH0JCTL_BLKMODEDST_M   0x02000000U

§ HOST_DMA_CH0JCTL_BLKMODEDST_S

#define HOST_DMA_CH0JCTL_BLKMODEDST_S   25U

§ HOST_DMA_CH0JCTL_DMASIGBPS

#define HOST_DMA_CH0JCTL_DMASIGBPS   0x04000000U

§ HOST_DMA_CH0JCTL_DMASIGBPS_M

#define HOST_DMA_CH0JCTL_DMASIGBPS_M   0x04000000U

§ HOST_DMA_CH0JCTL_DMASIGBPS_S

#define HOST_DMA_CH0JCTL_DMASIGBPS_S   26U

§ HOST_DMA_CH0JCTL_FIFOMODS

#define HOST_DMA_CH0JCTL_FIFOMODS   0x08000000U

§ HOST_DMA_CH0JCTL_FIFOMODS_M

#define HOST_DMA_CH0JCTL_FIFOMODS_M   0x08000000U

§ HOST_DMA_CH0JCTL_FIFOMODS_S

#define HOST_DMA_CH0JCTL_FIFOMODS_S   27U

§ HOST_DMA_CH0JCTL_FIFOMODD

#define HOST_DMA_CH0JCTL_FIFOMODD   0x10000000U

Referenced by DMADisableDestinationFifoMode(), and DMAEnableDestinationFifoMode().

§ HOST_DMA_CH0JCTL_FIFOMODD_M

#define HOST_DMA_CH0JCTL_FIFOMODD_M   0x10000000U

§ HOST_DMA_CH0JCTL_FIFOMODD_S

#define HOST_DMA_CH0JCTL_FIFOMODD_S   28U

§ HOST_DMA_CH0JCTL_SRCDSTCFG

#define HOST_DMA_CH0JCTL_SRCDSTCFG   0x20000000U

§ HOST_DMA_CH0JCTL_SRCDSTCFG_M

#define HOST_DMA_CH0JCTL_SRCDSTCFG_M   0x20000000U

Referenced by DMAGetChannelDirection().

§ HOST_DMA_CH0JCTL_SRCDSTCFG_S

#define HOST_DMA_CH0JCTL_SRCDSTCFG_S   29U

§ HOST_DMA_CH0JCTL_ENCLR

#define HOST_DMA_CH0JCTL_ENCLR   0x40000000U

§ HOST_DMA_CH0JCTL_ENCLR_M

#define HOST_DMA_CH0JCTL_ENCLR_M   0x40000000U

§ HOST_DMA_CH0JCTL_ENCLR_S

#define HOST_DMA_CH0JCTL_ENCLR_S   30U

§ HOST_DMA_CH1STA_HWEVENT_W

#define HOST_DMA_CH1STA_HWEVENT_W   3U

§ HOST_DMA_CH1STA_HWEVENT_M

#define HOST_DMA_CH1STA_HWEVENT_M   0x00000007U

§ HOST_DMA_CH1STA_HWEVENT_S

#define HOST_DMA_CH1STA_HWEVENT_S   0U

§ HOST_DMA_CH1STA_FSMSTATE_W

#define HOST_DMA_CH1STA_FSMSTATE_W   4U

§ HOST_DMA_CH1STA_FSMSTATE_M

#define HOST_DMA_CH1STA_FSMSTATE_M   0x00000F00U

§ HOST_DMA_CH1STA_FSMSTATE_S

#define HOST_DMA_CH1STA_FSMSTATE_S   8U

§ HOST_DMA_CH1STA_RUN

#define HOST_DMA_CH1STA_RUN   0x00010000U

§ HOST_DMA_CH1STA_RUN_M

#define HOST_DMA_CH1STA_RUN_M   0x00010000U

§ HOST_DMA_CH1STA_RUN_S

#define HOST_DMA_CH1STA_RUN_S   16U

§ HOST_DMA_CH1TIPTR_IPTR_W

#define HOST_DMA_CH1TIPTR_IPTR_W   32U

§ HOST_DMA_CH1TIPTR_IPTR_M

#define HOST_DMA_CH1TIPTR_IPTR_M   0xFFFFFFFFU

§ HOST_DMA_CH1TIPTR_IPTR_S

#define HOST_DMA_CH1TIPTR_IPTR_S   0U

§ HOST_DMA_CH1TOPTR_OPTR_W

#define HOST_DMA_CH1TOPTR_OPTR_W   32U

§ HOST_DMA_CH1TOPTR_OPTR_M

#define HOST_DMA_CH1TOPTR_OPTR_M   0xFFFFFFFFU

§ HOST_DMA_CH1TOPTR_OPTR_S

#define HOST_DMA_CH1TOPTR_OPTR_S   0U

§ HOST_DMA_CH1TCTL_TRANSB_W

#define HOST_DMA_CH1TCTL_TRANSB_W   14U

§ HOST_DMA_CH1TCTL_TRANSB_M

#define HOST_DMA_CH1TCTL_TRANSB_M   0x00003FFFU

§ HOST_DMA_CH1TCTL_TRANSB_S

#define HOST_DMA_CH1TCTL_TRANSB_S   0U

§ HOST_DMA_CH1TCTL_BURSTREQ

#define HOST_DMA_CH1TCTL_BURSTREQ   0x00010000U

§ HOST_DMA_CH1TCTL_BURSTREQ_M

#define HOST_DMA_CH1TCTL_BURSTREQ_M   0x00010000U

§ HOST_DMA_CH1TCTL_BURSTREQ_S

#define HOST_DMA_CH1TCTL_BURSTREQ_S   16U

§ HOST_DMA_CH1TCTL_SPARE

#define HOST_DMA_CH1TCTL_SPARE   0x00020000U

§ HOST_DMA_CH1TCTL_SPARE_M

#define HOST_DMA_CH1TCTL_SPARE_M   0x00020000U

§ HOST_DMA_CH1TCTL_SPARE_S

#define HOST_DMA_CH1TCTL_SPARE_S   17U

§ HOST_DMA_CH1TCTL_ENDIANESS_W

#define HOST_DMA_CH1TCTL_ENDIANESS_W   2U

§ HOST_DMA_CH1TCTL_ENDIANESS_M

#define HOST_DMA_CH1TCTL_ENDIANESS_M   0x03000000U

§ HOST_DMA_CH1TCTL_ENDIANESS_S

#define HOST_DMA_CH1TCTL_ENDIANESS_S   24U

§ HOST_DMA_CH1TCTRL2_CMD_W

#define HOST_DMA_CH1TCTRL2_CMD_W   3U

§ HOST_DMA_CH1TCTRL2_CMD_M

#define HOST_DMA_CH1TCTRL2_CMD_M   0x00000007U

§ HOST_DMA_CH1TCTRL2_CMD_S

#define HOST_DMA_CH1TCTRL2_CMD_S   0U

§ HOST_DMA_CH1TSTA_STA

#define HOST_DMA_CH1TSTA_STA   0x00000001U

§ HOST_DMA_CH1TSTA_STA_M

#define HOST_DMA_CH1TSTA_STA_M   0x00000001U

§ HOST_DMA_CH1TSTA_STA_S

#define HOST_DMA_CH1TSTA_STA_S   0U

§ HOST_DMA_CH1TSTA_OFFSET_W

#define HOST_DMA_CH1TSTA_OFFSET_W   8U

§ HOST_DMA_CH1TSTA_OFFSET_M

#define HOST_DMA_CH1TSTA_OFFSET_M   0x0000FF00U

§ HOST_DMA_CH1TSTA_OFFSET_S

#define HOST_DMA_CH1TSTA_OFFSET_S   8U

§ HOST_DMA_CH1TSTA_REMAINB_W

#define HOST_DMA_CH1TSTA_REMAINB_W   14U

§ HOST_DMA_CH1TSTA_REMAINB_M

#define HOST_DMA_CH1TSTA_REMAINB_M   0x3FFF0000U

§ HOST_DMA_CH1TSTA_REMAINB_S

#define HOST_DMA_CH1TSTA_REMAINB_S   16U

§ HOST_DMA_CH1JCTL_WORDSIZE_W

#define HOST_DMA_CH1JCTL_WORDSIZE_W   2U

§ HOST_DMA_CH1JCTL_WORDSIZE_M

#define HOST_DMA_CH1JCTL_WORDSIZE_M   0x00000003U

§ HOST_DMA_CH1JCTL_WORDSIZE_S

#define HOST_DMA_CH1JCTL_WORDSIZE_S   0U

§ HOST_DMA_CH1JCTL_BLKSIZE_W

#define HOST_DMA_CH1JCTL_BLKSIZE_W   6U

§ HOST_DMA_CH1JCTL_BLKSIZE_M

#define HOST_DMA_CH1JCTL_BLKSIZE_M   0x003F0000U

§ HOST_DMA_CH1JCTL_BLKSIZE_S

#define HOST_DMA_CH1JCTL_BLKSIZE_S   16U

§ HOST_DMA_CH1JCTL_BLKMODESRC

#define HOST_DMA_CH1JCTL_BLKMODESRC   0x01000000U

§ HOST_DMA_CH1JCTL_BLKMODESRC_M

#define HOST_DMA_CH1JCTL_BLKMODESRC_M   0x01000000U

§ HOST_DMA_CH1JCTL_BLKMODESRC_S

#define HOST_DMA_CH1JCTL_BLKMODESRC_S   24U

§ HOST_DMA_CH1JCTL_BLKMODEDST

#define HOST_DMA_CH1JCTL_BLKMODEDST   0x02000000U

§ HOST_DMA_CH1JCTL_BLKMODEDST_M

#define HOST_DMA_CH1JCTL_BLKMODEDST_M   0x02000000U

§ HOST_DMA_CH1JCTL_BLKMODEDST_S

#define HOST_DMA_CH1JCTL_BLKMODEDST_S   25U

§ HOST_DMA_CH1JCTL_DMASIGBPS

#define HOST_DMA_CH1JCTL_DMASIGBPS   0x04000000U

§ HOST_DMA_CH1JCTL_DMASIGBPS_M

#define HOST_DMA_CH1JCTL_DMASIGBPS_M   0x04000000U

§ HOST_DMA_CH1JCTL_DMASIGBPS_S

#define HOST_DMA_CH1JCTL_DMASIGBPS_S   26U

§ HOST_DMA_CH1JCTL_FIFOMODS

#define HOST_DMA_CH1JCTL_FIFOMODS   0x08000000U

§ HOST_DMA_CH1JCTL_FIFOMODS_M

#define HOST_DMA_CH1JCTL_FIFOMODS_M   0x08000000U

§ HOST_DMA_CH1JCTL_FIFOMODS_S

#define HOST_DMA_CH1JCTL_FIFOMODS_S   27U

§ HOST_DMA_CH1JCTL_FIFOMODD

#define HOST_DMA_CH1JCTL_FIFOMODD   0x10000000U

§ HOST_DMA_CH1JCTL_FIFOMODD_M

#define HOST_DMA_CH1JCTL_FIFOMODD_M   0x10000000U

§ HOST_DMA_CH1JCTL_FIFOMODD_S

#define HOST_DMA_CH1JCTL_FIFOMODD_S   28U

§ HOST_DMA_CH1JCTL_SRCDSTCFG

#define HOST_DMA_CH1JCTL_SRCDSTCFG   0x20000000U

§ HOST_DMA_CH1JCTL_SRCDSTCFG_M

#define HOST_DMA_CH1JCTL_SRCDSTCFG_M   0x20000000U

§ HOST_DMA_CH1JCTL_SRCDSTCFG_S

#define HOST_DMA_CH1JCTL_SRCDSTCFG_S   29U

§ HOST_DMA_CH1JCTL_ENCLR

#define HOST_DMA_CH1JCTL_ENCLR   0x40000000U

§ HOST_DMA_CH1JCTL_ENCLR_M

#define HOST_DMA_CH1JCTL_ENCLR_M   0x40000000U

§ HOST_DMA_CH1JCTL_ENCLR_S

#define HOST_DMA_CH1JCTL_ENCLR_S   30U

§ HOST_DMA_CH2STA_HWEVENT_W

#define HOST_DMA_CH2STA_HWEVENT_W   3U

§ HOST_DMA_CH2STA_HWEVENT_M

#define HOST_DMA_CH2STA_HWEVENT_M   0x00000007U

§ HOST_DMA_CH2STA_HWEVENT_S

#define HOST_DMA_CH2STA_HWEVENT_S   0U

§ HOST_DMA_CH2STA_FSMSTATE_W

#define HOST_DMA_CH2STA_FSMSTATE_W   4U

§ HOST_DMA_CH2STA_FSMSTATE_M

#define HOST_DMA_CH2STA_FSMSTATE_M   0x00000F00U

§ HOST_DMA_CH2STA_FSMSTATE_S

#define HOST_DMA_CH2STA_FSMSTATE_S   8U

§ HOST_DMA_CH2STA_RUN

#define HOST_DMA_CH2STA_RUN   0x00010000U

§ HOST_DMA_CH2STA_RUN_M

#define HOST_DMA_CH2STA_RUN_M   0x00010000U

§ HOST_DMA_CH2STA_RUN_S

#define HOST_DMA_CH2STA_RUN_S   16U

§ HOST_DMA_CH2TIPTR_IPTR_W

#define HOST_DMA_CH2TIPTR_IPTR_W   32U

§ HOST_DMA_CH2TIPTR_IPTR_M

#define HOST_DMA_CH2TIPTR_IPTR_M   0xFFFFFFFFU

§ HOST_DMA_CH2TIPTR_IPTR_S

#define HOST_DMA_CH2TIPTR_IPTR_S   0U

§ HOST_DMA_CH2TOPTR_OPTR_W

#define HOST_DMA_CH2TOPTR_OPTR_W   32U

§ HOST_DMA_CH2TOPTR_OPTR_M

#define HOST_DMA_CH2TOPTR_OPTR_M   0xFFFFFFFFU

§ HOST_DMA_CH2TOPTR_OPTR_S

#define HOST_DMA_CH2TOPTR_OPTR_S   0U

§ HOST_DMA_CH2TCTL_TRANSB_W

#define HOST_DMA_CH2TCTL_TRANSB_W   14U

§ HOST_DMA_CH2TCTL_TRANSB_M

#define HOST_DMA_CH2TCTL_TRANSB_M   0x00003FFFU

§ HOST_DMA_CH2TCTL_TRANSB_S

#define HOST_DMA_CH2TCTL_TRANSB_S   0U

§ HOST_DMA_CH2TCTL_BURSTREQ

#define HOST_DMA_CH2TCTL_BURSTREQ   0x00010000U

§ HOST_DMA_CH2TCTL_BURSTREQ_M

#define HOST_DMA_CH2TCTL_BURSTREQ_M   0x00010000U

§ HOST_DMA_CH2TCTL_BURSTREQ_S

#define HOST_DMA_CH2TCTL_BURSTREQ_S   16U

§ HOST_DMA_CH2TCTL_SPARE

#define HOST_DMA_CH2TCTL_SPARE   0x00020000U

§ HOST_DMA_CH2TCTL_SPARE_M

#define HOST_DMA_CH2TCTL_SPARE_M   0x00020000U

§ HOST_DMA_CH2TCTL_SPARE_S

#define HOST_DMA_CH2TCTL_SPARE_S   17U

§ HOST_DMA_CH2TCTL_ENDIANESS_W

#define HOST_DMA_CH2TCTL_ENDIANESS_W   2U

§ HOST_DMA_CH2TCTL_ENDIANESS_M

#define HOST_DMA_CH2TCTL_ENDIANESS_M   0x03000000U

§ HOST_DMA_CH2TCTL_ENDIANESS_S

#define HOST_DMA_CH2TCTL_ENDIANESS_S   24U

§ HOST_DMA_CH2TCTL2_CMD_W

#define HOST_DMA_CH2TCTL2_CMD_W   3U

§ HOST_DMA_CH2TCTL2_CMD_M

#define HOST_DMA_CH2TCTL2_CMD_M   0x00000007U

§ HOST_DMA_CH2TCTL2_CMD_S

#define HOST_DMA_CH2TCTL2_CMD_S   0U

§ HOST_DMA_CH2TSTA_STA

#define HOST_DMA_CH2TSTA_STA   0x00000001U

§ HOST_DMA_CH2TSTA_STA_M

#define HOST_DMA_CH2TSTA_STA_M   0x00000001U

§ HOST_DMA_CH2TSTA_STA_S

#define HOST_DMA_CH2TSTA_STA_S   0U

§ HOST_DMA_CH2TSTA_OFFSET_W

#define HOST_DMA_CH2TSTA_OFFSET_W   8U

§ HOST_DMA_CH2TSTA_OFFSET_M

#define HOST_DMA_CH2TSTA_OFFSET_M   0x0000FF00U

§ HOST_DMA_CH2TSTA_OFFSET_S

#define HOST_DMA_CH2TSTA_OFFSET_S   8U

§ HOST_DMA_CH2TSTA_REMAINB_W

#define HOST_DMA_CH2TSTA_REMAINB_W   14U

§ HOST_DMA_CH2TSTA_REMAINB_M

#define HOST_DMA_CH2TSTA_REMAINB_M   0x3FFF0000U

§ HOST_DMA_CH2TSTA_REMAINB_S

#define HOST_DMA_CH2TSTA_REMAINB_S   16U

§ HOST_DMA_CH2JCTL_WORDSIZE_W

#define HOST_DMA_CH2JCTL_WORDSIZE_W   2U

§ HOST_DMA_CH2JCTL_WORDSIZE_M

#define HOST_DMA_CH2JCTL_WORDSIZE_M   0x00000003U

§ HOST_DMA_CH2JCTL_WORDSIZE_S

#define HOST_DMA_CH2JCTL_WORDSIZE_S   0U

§ HOST_DMA_CH2JCTL_BLKSIZE_W

#define HOST_DMA_CH2JCTL_BLKSIZE_W   6U

§ HOST_DMA_CH2JCTL_BLKSIZE_M

#define HOST_DMA_CH2JCTL_BLKSIZE_M   0x003F0000U

§ HOST_DMA_CH2JCTL_BLKSIZE_S

#define HOST_DMA_CH2JCTL_BLKSIZE_S   16U

§ HOST_DMA_CH2JCTL_DMASIGBPS

#define HOST_DMA_CH2JCTL_DMASIGBPS   0x04000000U

§ HOST_DMA_CH2JCTL_DMASIGBPS_M

#define HOST_DMA_CH2JCTL_DMASIGBPS_M   0x04000000U

§ HOST_DMA_CH2JCTL_DMASIGBPS_S

#define HOST_DMA_CH2JCTL_DMASIGBPS_S   26U

§ HOST_DMA_CH2JCTL_FIFOMODS

#define HOST_DMA_CH2JCTL_FIFOMODS   0x08000000U

§ HOST_DMA_CH2JCTL_FIFOMODS_M

#define HOST_DMA_CH2JCTL_FIFOMODS_M   0x08000000U

§ HOST_DMA_CH2JCTL_FIFOMODS_S

#define HOST_DMA_CH2JCTL_FIFOMODS_S   27U

§ HOST_DMA_CH2JCTL_FIFOMODD

#define HOST_DMA_CH2JCTL_FIFOMODD   0x10000000U

§ HOST_DMA_CH2JCTL_FIFOMODD_M

#define HOST_DMA_CH2JCTL_FIFOMODD_M   0x10000000U

§ HOST_DMA_CH2JCTL_FIFOMODD_S

#define HOST_DMA_CH2JCTL_FIFOMODD_S   28U

§ HOST_DMA_CH2JCTL_SRCDSTCFG

#define HOST_DMA_CH2JCTL_SRCDSTCFG   0x20000000U

§ HOST_DMA_CH2JCTL_SRCDSTCFG_M

#define HOST_DMA_CH2JCTL_SRCDSTCFG_M   0x20000000U

§ HOST_DMA_CH2JCTL_SRCDSTCFG_S

#define HOST_DMA_CH2JCTL_SRCDSTCFG_S   29U

§ HOST_DMA_CH2JCTL_ENCLR

#define HOST_DMA_CH2JCTL_ENCLR   0x40000000U

§ HOST_DMA_CH2JCTL_ENCLR_M

#define HOST_DMA_CH2JCTL_ENCLR_M   0x40000000U

§ HOST_DMA_CH2JCTL_ENCLR_S

#define HOST_DMA_CH2JCTL_ENCLR_S   30U

§ HOST_DMA_CH3STA_HWEVENT_W

#define HOST_DMA_CH3STA_HWEVENT_W   3U

§ HOST_DMA_CH3STA_HWEVENT_M

#define HOST_DMA_CH3STA_HWEVENT_M   0x00000007U

§ HOST_DMA_CH3STA_HWEVENT_S

#define HOST_DMA_CH3STA_HWEVENT_S   0U

§ HOST_DMA_CH3STA_FSMSTATE_W

#define HOST_DMA_CH3STA_FSMSTATE_W   4U

§ HOST_DMA_CH3STA_FSMSTATE_M

#define HOST_DMA_CH3STA_FSMSTATE_M   0x00000F00U

§ HOST_DMA_CH3STA_FSMSTATE_S

#define HOST_DMA_CH3STA_FSMSTATE_S   8U

§ HOST_DMA_CH3STA_RUN

#define HOST_DMA_CH3STA_RUN   0x00010000U

§ HOST_DMA_CH3STA_RUN_M

#define HOST_DMA_CH3STA_RUN_M   0x00010000U

§ HOST_DMA_CH3STA_RUN_S

#define HOST_DMA_CH3STA_RUN_S   16U

§ HOST_DMA_CH3TIPTR_IPTR_W

#define HOST_DMA_CH3TIPTR_IPTR_W   32U

§ HOST_DMA_CH3TIPTR_IPTR_M

#define HOST_DMA_CH3TIPTR_IPTR_M   0xFFFFFFFFU

§ HOST_DMA_CH3TIPTR_IPTR_S

#define HOST_DMA_CH3TIPTR_IPTR_S   0U

§ HOST_DMA_CH3TOPTR_OPTR_W

#define HOST_DMA_CH3TOPTR_OPTR_W   32U

§ HOST_DMA_CH3TOPTR_OPTR_M

#define HOST_DMA_CH3TOPTR_OPTR_M   0xFFFFFFFFU

§ HOST_DMA_CH3TOPTR_OPTR_S

#define HOST_DMA_CH3TOPTR_OPTR_S   0U

§ HOST_DMA_CH3TCTL_TRANSB_W

#define HOST_DMA_CH3TCTL_TRANSB_W   14U

§ HOST_DMA_CH3TCTL_TRANSB_M

#define HOST_DMA_CH3TCTL_TRANSB_M   0x00003FFFU

§ HOST_DMA_CH3TCTL_TRANSB_S

#define HOST_DMA_CH3TCTL_TRANSB_S   0U

§ HOST_DMA_CH3TCTL_BURSTREQ

#define HOST_DMA_CH3TCTL_BURSTREQ   0x00010000U

§ HOST_DMA_CH3TCTL_BURSTREQ_M

#define HOST_DMA_CH3TCTL_BURSTREQ_M   0x00010000U

§ HOST_DMA_CH3TCTL_BURSTREQ_S

#define HOST_DMA_CH3TCTL_BURSTREQ_S   16U

§ HOST_DMA_CH3TCTL_SPARE

#define HOST_DMA_CH3TCTL_SPARE   0x00020000U

§ HOST_DMA_CH3TCTL_SPARE_M

#define HOST_DMA_CH3TCTL_SPARE_M   0x00020000U

§ HOST_DMA_CH3TCTL_SPARE_S

#define HOST_DMA_CH3TCTL_SPARE_S   17U

§ HOST_DMA_CH3TCTL_ENDIANESS_W

#define HOST_DMA_CH3TCTL_ENDIANESS_W   2U

§ HOST_DMA_CH3TCTL_ENDIANESS_M

#define HOST_DMA_CH3TCTL_ENDIANESS_M   0x03000000U

§ HOST_DMA_CH3TCTL_ENDIANESS_S

#define HOST_DMA_CH3TCTL_ENDIANESS_S   24U

§ HOST_DMA_CH3TCTL2_CMD_W

#define HOST_DMA_CH3TCTL2_CMD_W   3U

§ HOST_DMA_CH3TCTL2_CMD_M

#define HOST_DMA_CH3TCTL2_CMD_M   0x00000007U

§ HOST_DMA_CH3TCTL2_CMD_S

#define HOST_DMA_CH3TCTL2_CMD_S   0U

§ HOST_DMA_CH3TSTA_STA

#define HOST_DMA_CH3TSTA_STA   0x00000001U

§ HOST_DMA_CH3TSTA_STA_M

#define HOST_DMA_CH3TSTA_STA_M   0x00000001U

§ HOST_DMA_CH3TSTA_STA_S

#define HOST_DMA_CH3TSTA_STA_S   0U

§ HOST_DMA_CH3TSTA_OFFSET_W

#define HOST_DMA_CH3TSTA_OFFSET_W   8U

§ HOST_DMA_CH3TSTA_OFFSET_M

#define HOST_DMA_CH3TSTA_OFFSET_M   0x0000FF00U

§ HOST_DMA_CH3TSTA_OFFSET_S

#define HOST_DMA_CH3TSTA_OFFSET_S   8U

§ HOST_DMA_CH3TSTA_REMAINB_W

#define HOST_DMA_CH3TSTA_REMAINB_W   14U

§ HOST_DMA_CH3TSTA_REMAINB_M

#define HOST_DMA_CH3TSTA_REMAINB_M   0x3FFF0000U

§ HOST_DMA_CH3TSTA_REMAINB_S

#define HOST_DMA_CH3TSTA_REMAINB_S   16U

§ HOST_DMA_CH3JCTL_WORDSIZE_W

#define HOST_DMA_CH3JCTL_WORDSIZE_W   2U

§ HOST_DMA_CH3JCTL_WORDSIZE_M

#define HOST_DMA_CH3JCTL_WORDSIZE_M   0x00000003U

§ HOST_DMA_CH3JCTL_WORDSIZE_S

#define HOST_DMA_CH3JCTL_WORDSIZE_S   0U

§ HOST_DMA_CH3JCTL_BLKSIZE_W

#define HOST_DMA_CH3JCTL_BLKSIZE_W   6U

§ HOST_DMA_CH3JCTL_BLKSIZE_M

#define HOST_DMA_CH3JCTL_BLKSIZE_M   0x003F0000U

§ HOST_DMA_CH3JCTL_BLKSIZE_S

#define HOST_DMA_CH3JCTL_BLKSIZE_S   16U

§ HOST_DMA_CH3JCTL_DMASIGBPS

#define HOST_DMA_CH3JCTL_DMASIGBPS   0x04000000U

§ HOST_DMA_CH3JCTL_DMASIGBPS_M

#define HOST_DMA_CH3JCTL_DMASIGBPS_M   0x04000000U

§ HOST_DMA_CH3JCTL_DMASIGBPS_S

#define HOST_DMA_CH3JCTL_DMASIGBPS_S   26U

§ HOST_DMA_CH3JCTL_FIFOMODS

#define HOST_DMA_CH3JCTL_FIFOMODS   0x08000000U

§ HOST_DMA_CH3JCTL_FIFOMODS_M

#define HOST_DMA_CH3JCTL_FIFOMODS_M   0x08000000U

§ HOST_DMA_CH3JCTL_FIFOMODS_S

#define HOST_DMA_CH3JCTL_FIFOMODS_S   27U

§ HOST_DMA_CH3JCTL_FIFOMODD

#define HOST_DMA_CH3JCTL_FIFOMODD   0x10000000U

§ HOST_DMA_CH3JCTL_FIFOMODD_M

#define HOST_DMA_CH3JCTL_FIFOMODD_M   0x10000000U

§ HOST_DMA_CH3JCTL_FIFOMODD_S

#define HOST_DMA_CH3JCTL_FIFOMODD_S   28U

§ HOST_DMA_CH3JCTL_SRCDSTCFG

#define HOST_DMA_CH3JCTL_SRCDSTCFG   0x20000000U

§ HOST_DMA_CH3JCTL_SRCDSTCFG_M

#define HOST_DMA_CH3JCTL_SRCDSTCFG_M   0x20000000U

§ HOST_DMA_CH3JCTL_SRCDSTCFG_S

#define HOST_DMA_CH3JCTL_SRCDSTCFG_S   29U

§ HOST_DMA_CH3JCTL_ENCLR

#define HOST_DMA_CH3JCTL_ENCLR   0x40000000U

§ HOST_DMA_CH3JCTL_ENCLR_M

#define HOST_DMA_CH3JCTL_ENCLR_M   0x40000000U

§ HOST_DMA_CH3JCTL_ENCLR_S

#define HOST_DMA_CH3JCTL_ENCLR_S   30U

§ HOST_DMA_CH4STA_HWEVENT_W

#define HOST_DMA_CH4STA_HWEVENT_W   3U

§ HOST_DMA_CH4STA_HWEVENT_M

#define HOST_DMA_CH4STA_HWEVENT_M   0x00000007U

§ HOST_DMA_CH4STA_HWEVENT_S

#define HOST_DMA_CH4STA_HWEVENT_S   0U

§ HOST_DMA_CH4STA_FSMSTATE_W

#define HOST_DMA_CH4STA_FSMSTATE_W   4U

§ HOST_DMA_CH4STA_FSMSTATE_M

#define HOST_DMA_CH4STA_FSMSTATE_M   0x00000F00U

§ HOST_DMA_CH4STA_FSMSTATE_S

#define HOST_DMA_CH4STA_FSMSTATE_S   8U

§ HOST_DMA_CH4STA_RUN

#define HOST_DMA_CH4STA_RUN   0x00010000U

§ HOST_DMA_CH4STA_RUN_M

#define HOST_DMA_CH4STA_RUN_M   0x00010000U

§ HOST_DMA_CH4STA_RUN_S

#define HOST_DMA_CH4STA_RUN_S   16U

§ HOST_DMA_CH4TIPTR_INPTR_W

#define HOST_DMA_CH4TIPTR_INPTR_W   32U

§ HOST_DMA_CH4TIPTR_INPTR_M

#define HOST_DMA_CH4TIPTR_INPTR_M   0xFFFFFFFFU

§ HOST_DMA_CH4TIPTR_INPTR_S

#define HOST_DMA_CH4TIPTR_INPTR_S   0U

§ HOST_DMA_CH4TOPTR_OPTR_W

#define HOST_DMA_CH4TOPTR_OPTR_W   32U

§ HOST_DMA_CH4TOPTR_OPTR_M

#define HOST_DMA_CH4TOPTR_OPTR_M   0xFFFFFFFFU

§ HOST_DMA_CH4TOPTR_OPTR_S

#define HOST_DMA_CH4TOPTR_OPTR_S   0U

§ HOST_DMA_CH4TCTL_TRANSB_W

#define HOST_DMA_CH4TCTL_TRANSB_W   14U

§ HOST_DMA_CH4TCTL_TRANSB_M

#define HOST_DMA_CH4TCTL_TRANSB_M   0x00003FFFU

§ HOST_DMA_CH4TCTL_TRANSB_S

#define HOST_DMA_CH4TCTL_TRANSB_S   0U

§ HOST_DMA_CH4TCTL_BURSTREQ

#define HOST_DMA_CH4TCTL_BURSTREQ   0x00010000U

§ HOST_DMA_CH4TCTL_BURSTREQ_M

#define HOST_DMA_CH4TCTL_BURSTREQ_M   0x00010000U

§ HOST_DMA_CH4TCTL_BURSTREQ_S

#define HOST_DMA_CH4TCTL_BURSTREQ_S   16U

§ HOST_DMA_CH4TCTL_SPARE

#define HOST_DMA_CH4TCTL_SPARE   0x00020000U

§ HOST_DMA_CH4TCTL_SPARE_M

#define HOST_DMA_CH4TCTL_SPARE_M   0x00020000U

§ HOST_DMA_CH4TCTL_SPARE_S

#define HOST_DMA_CH4TCTL_SPARE_S   17U

§ HOST_DMA_CH4TCTL_ENDIANESS_W

#define HOST_DMA_CH4TCTL_ENDIANESS_W   2U

§ HOST_DMA_CH4TCTL_ENDIANESS_M

#define HOST_DMA_CH4TCTL_ENDIANESS_M   0x03000000U

§ HOST_DMA_CH4TCTL_ENDIANESS_S

#define HOST_DMA_CH4TCTL_ENDIANESS_S   24U

§ HOST_DMA_CH4TCTL2_CMD_W

#define HOST_DMA_CH4TCTL2_CMD_W   3U

§ HOST_DMA_CH4TCTL2_CMD_M

#define HOST_DMA_CH4TCTL2_CMD_M   0x00000007U

§ HOST_DMA_CH4TCTL2_CMD_S

#define HOST_DMA_CH4TCTL2_CMD_S   0U

§ HOST_DMA_CH4TSTA_STA

#define HOST_DMA_CH4TSTA_STA   0x00000001U

§ HOST_DMA_CH4TSTA_STA_M

#define HOST_DMA_CH4TSTA_STA_M   0x00000001U

§ HOST_DMA_CH4TSTA_STA_S

#define HOST_DMA_CH4TSTA_STA_S   0U

§ HOST_DMA_CH4TSTA_OFFSET_W

#define HOST_DMA_CH4TSTA_OFFSET_W   8U

§ HOST_DMA_CH4TSTA_OFFSET_M

#define HOST_DMA_CH4TSTA_OFFSET_M   0x0000FF00U

§ HOST_DMA_CH4TSTA_OFFSET_S

#define HOST_DMA_CH4TSTA_OFFSET_S   8U

§ HOST_DMA_CH4TSTA_REMAINB_W

#define HOST_DMA_CH4TSTA_REMAINB_W   14U

§ HOST_DMA_CH4TSTA_REMAINB_M

#define HOST_DMA_CH4TSTA_REMAINB_M   0x3FFF0000U

§ HOST_DMA_CH4TSTA_REMAINB_S

#define HOST_DMA_CH4TSTA_REMAINB_S   16U

§ HOST_DMA_CH4JCTL_WORDSIZE_W

#define HOST_DMA_CH4JCTL_WORDSIZE_W   2U

§ HOST_DMA_CH4JCTL_WORDSIZE_M

#define HOST_DMA_CH4JCTL_WORDSIZE_M   0x00000003U

§ HOST_DMA_CH4JCTL_WORDSIZE_S

#define HOST_DMA_CH4JCTL_WORDSIZE_S   0U

§ HOST_DMA_CH4JCTL_BLKSIZE_W

#define HOST_DMA_CH4JCTL_BLKSIZE_W   6U

§ HOST_DMA_CH4JCTL_BLKSIZE_M

#define HOST_DMA_CH4JCTL_BLKSIZE_M   0x003F0000U

§ HOST_DMA_CH4JCTL_BLKSIZE_S

#define HOST_DMA_CH4JCTL_BLKSIZE_S   16U

§ HOST_DMA_CH4JCTL_DMASIGBPS

#define HOST_DMA_CH4JCTL_DMASIGBPS   0x04000000U

§ HOST_DMA_CH4JCTL_DMASIGBPS_M

#define HOST_DMA_CH4JCTL_DMASIGBPS_M   0x04000000U

§ HOST_DMA_CH4JCTL_DMASIGBPS_S

#define HOST_DMA_CH4JCTL_DMASIGBPS_S   26U

§ HOST_DMA_CH4JCTL_FIFOMODS

#define HOST_DMA_CH4JCTL_FIFOMODS   0x08000000U

§ HOST_DMA_CH4JCTL_FIFOMODS_M

#define HOST_DMA_CH4JCTL_FIFOMODS_M   0x08000000U

§ HOST_DMA_CH4JCTL_FIFOMODS_S

#define HOST_DMA_CH4JCTL_FIFOMODS_S   27U

§ HOST_DMA_CH4JCTL_FIFOMODD

#define HOST_DMA_CH4JCTL_FIFOMODD   0x10000000U

§ HOST_DMA_CH4JCTL_FIFOMODD_M

#define HOST_DMA_CH4JCTL_FIFOMODD_M   0x10000000U

§ HOST_DMA_CH4JCTL_FIFOMODD_S

#define HOST_DMA_CH4JCTL_FIFOMODD_S   28U

§ HOST_DMA_CH4JCTL_SRCDSTCFG

#define HOST_DMA_CH4JCTL_SRCDSTCFG   0x20000000U

§ HOST_DMA_CH4JCTL_SRCDSTCFG_M

#define HOST_DMA_CH4JCTL_SRCDSTCFG_M   0x20000000U

§ HOST_DMA_CH4JCTL_SRCDSTCFG_S

#define HOST_DMA_CH4JCTL_SRCDSTCFG_S   29U

§ HOST_DMA_CH4JCTL_ENCLR

#define HOST_DMA_CH4JCTL_ENCLR   0x40000000U

§ HOST_DMA_CH4JCTL_ENCLR_M

#define HOST_DMA_CH4JCTL_ENCLR_M   0x40000000U

§ HOST_DMA_CH4JCTL_ENCLR_S

#define HOST_DMA_CH4JCTL_ENCLR_S   30U

§ HOST_DMA_CH5STA_HWEVENT_W

#define HOST_DMA_CH5STA_HWEVENT_W   3U

§ HOST_DMA_CH5STA_HWEVENT_M

#define HOST_DMA_CH5STA_HWEVENT_M   0x00000007U

§ HOST_DMA_CH5STA_HWEVENT_S

#define HOST_DMA_CH5STA_HWEVENT_S   0U

§ HOST_DMA_CH5STA_FSMSTATE_W

#define HOST_DMA_CH5STA_FSMSTATE_W   4U

§ HOST_DMA_CH5STA_FSMSTATE_M

#define HOST_DMA_CH5STA_FSMSTATE_M   0x00000F00U

§ HOST_DMA_CH5STA_FSMSTATE_S

#define HOST_DMA_CH5STA_FSMSTATE_S   8U

§ HOST_DMA_CH5STA_RUN

#define HOST_DMA_CH5STA_RUN   0x00010000U

§ HOST_DMA_CH5STA_RUN_M

#define HOST_DMA_CH5STA_RUN_M   0x00010000U

§ HOST_DMA_CH5STA_RUN_S

#define HOST_DMA_CH5STA_RUN_S   16U

§ HOST_DMA_CH5TIPTR_IPTR_W

#define HOST_DMA_CH5TIPTR_IPTR_W   32U

§ HOST_DMA_CH5TIPTR_IPTR_M

#define HOST_DMA_CH5TIPTR_IPTR_M   0xFFFFFFFFU

§ HOST_DMA_CH5TIPTR_IPTR_S

#define HOST_DMA_CH5TIPTR_IPTR_S   0U

§ HOST_DMA_CH5TOPTR_OPTR_W

#define HOST_DMA_CH5TOPTR_OPTR_W   32U

§ HOST_DMA_CH5TOPTR_OPTR_M

#define HOST_DMA_CH5TOPTR_OPTR_M   0xFFFFFFFFU

§ HOST_DMA_CH5TOPTR_OPTR_S

#define HOST_DMA_CH5TOPTR_OPTR_S   0U

§ HOST_DMA_CH5TCTL_TRANSB_W

#define HOST_DMA_CH5TCTL_TRANSB_W   14U

§ HOST_DMA_CH5TCTL_TRANSB_M

#define HOST_DMA_CH5TCTL_TRANSB_M   0x00003FFFU

§ HOST_DMA_CH5TCTL_TRANSB_S

#define HOST_DMA_CH5TCTL_TRANSB_S   0U

§ HOST_DMA_CH5TCTL_BURSTREQ

#define HOST_DMA_CH5TCTL_BURSTREQ   0x00010000U

§ HOST_DMA_CH5TCTL_BURSTREQ_M

#define HOST_DMA_CH5TCTL_BURSTREQ_M   0x00010000U

§ HOST_DMA_CH5TCTL_BURSTREQ_S

#define HOST_DMA_CH5TCTL_BURSTREQ_S   16U

§ HOST_DMA_CH5TCTL_SPARE

#define HOST_DMA_CH5TCTL_SPARE   0x00020000U

§ HOST_DMA_CH5TCTL_SPARE_M

#define HOST_DMA_CH5TCTL_SPARE_M   0x00020000U

§ HOST_DMA_CH5TCTL_SPARE_S

#define HOST_DMA_CH5TCTL_SPARE_S   17U

§ HOST_DMA_CH5TCTL_ENDIANESS_W

#define HOST_DMA_CH5TCTL_ENDIANESS_W   2U

§ HOST_DMA_CH5TCTL_ENDIANESS_M

#define HOST_DMA_CH5TCTL_ENDIANESS_M   0x03000000U

§ HOST_DMA_CH5TCTL_ENDIANESS_S

#define HOST_DMA_CH5TCTL_ENDIANESS_S   24U

§ HOST_DMA_CH5TCTL2_CMD_W

#define HOST_DMA_CH5TCTL2_CMD_W   3U

§ HOST_DMA_CH5TCTL2_CMD_M

#define HOST_DMA_CH5TCTL2_CMD_M   0x00000007U

§ HOST_DMA_CH5TCTL2_CMD_S

#define HOST_DMA_CH5TCTL2_CMD_S   0U

§ HOST_DMA_CH5TSTA_STA

#define HOST_DMA_CH5TSTA_STA   0x00000001U

§ HOST_DMA_CH5TSTA_STA_M

#define HOST_DMA_CH5TSTA_STA_M   0x00000001U

§ HOST_DMA_CH5TSTA_STA_S

#define HOST_DMA_CH5TSTA_STA_S   0U

§ HOST_DMA_CH5TSTA_OFFSET_W

#define HOST_DMA_CH5TSTA_OFFSET_W   8U

§ HOST_DMA_CH5TSTA_OFFSET_M

#define HOST_DMA_CH5TSTA_OFFSET_M   0x0000FF00U

§ HOST_DMA_CH5TSTA_OFFSET_S

#define HOST_DMA_CH5TSTA_OFFSET_S   8U

§ HOST_DMA_CH5TSTA_REMAINB_W

#define HOST_DMA_CH5TSTA_REMAINB_W   14U

§ HOST_DMA_CH5TSTA_REMAINB_M

#define HOST_DMA_CH5TSTA_REMAINB_M   0x3FFF0000U

§ HOST_DMA_CH5TSTA_REMAINB_S

#define HOST_DMA_CH5TSTA_REMAINB_S   16U

§ HOST_DMA_CH5JCTL_WORDSIZE_W

#define HOST_DMA_CH5JCTL_WORDSIZE_W   2U

§ HOST_DMA_CH5JCTL_WORDSIZE_M

#define HOST_DMA_CH5JCTL_WORDSIZE_M   0x00000003U

§ HOST_DMA_CH5JCTL_WORDSIZE_S

#define HOST_DMA_CH5JCTL_WORDSIZE_S   0U

§ HOST_DMA_CH5JCTL_BLKSIZE_W

#define HOST_DMA_CH5JCTL_BLKSIZE_W   6U

§ HOST_DMA_CH5JCTL_BLKSIZE_M

#define HOST_DMA_CH5JCTL_BLKSIZE_M   0x003F0000U

§ HOST_DMA_CH5JCTL_BLKSIZE_S

#define HOST_DMA_CH5JCTL_BLKSIZE_S   16U

§ HOST_DMA_CH5JCTL_DMASIGBPS

#define HOST_DMA_CH5JCTL_DMASIGBPS   0x04000000U

§ HOST_DMA_CH5JCTL_DMASIGBPS_M

#define HOST_DMA_CH5JCTL_DMASIGBPS_M   0x04000000U

§ HOST_DMA_CH5JCTL_DMASIGBPS_S

#define HOST_DMA_CH5JCTL_DMASIGBPS_S   26U

§ HOST_DMA_CH5JCTL_FIFOMODS

#define HOST_DMA_CH5JCTL_FIFOMODS   0x08000000U

§ HOST_DMA_CH5JCTL_FIFOMODS_M

#define HOST_DMA_CH5JCTL_FIFOMODS_M   0x08000000U

§ HOST_DMA_CH5JCTL_FIFOMODS_S

#define HOST_DMA_CH5JCTL_FIFOMODS_S   27U

§ HOST_DMA_CH5JCTL_FIFOMODD

#define HOST_DMA_CH5JCTL_FIFOMODD   0x10000000U

§ HOST_DMA_CH5JCTL_FIFOMODD_M

#define HOST_DMA_CH5JCTL_FIFOMODD_M   0x10000000U

§ HOST_DMA_CH5JCTL_FIFOMODD_S

#define HOST_DMA_CH5JCTL_FIFOMODD_S   28U

§ HOST_DMA_CH5JCTL_SRCDSTCFG

#define HOST_DMA_CH5JCTL_SRCDSTCFG   0x20000000U

§ HOST_DMA_CH5JCTL_SRCDSTCFG_M

#define HOST_DMA_CH5JCTL_SRCDSTCFG_M   0x20000000U

§ HOST_DMA_CH5JCTL_SRCDSTCFG_S

#define HOST_DMA_CH5JCTL_SRCDSTCFG_S   29U

§ HOST_DMA_CH5JCTL_ENCLR

#define HOST_DMA_CH5JCTL_ENCLR   0x40000000U

§ HOST_DMA_CH5JCTL_ENCLR_M

#define HOST_DMA_CH5JCTL_ENCLR_M   0x40000000U

§ HOST_DMA_CH5JCTL_ENCLR_S

#define HOST_DMA_CH5JCTL_ENCLR_S   30U

§ HOST_DMA_CH6STA_HWEVENT_W

#define HOST_DMA_CH6STA_HWEVENT_W   3U

§ HOST_DMA_CH6STA_HWEVENT_M

#define HOST_DMA_CH6STA_HWEVENT_M   0x00000007U

§ HOST_DMA_CH6STA_HWEVENT_S

#define HOST_DMA_CH6STA_HWEVENT_S   0U

§ HOST_DMA_CH6STA_FSMSTATE_W

#define HOST_DMA_CH6STA_FSMSTATE_W   4U

§ HOST_DMA_CH6STA_FSMSTATE_M

#define HOST_DMA_CH6STA_FSMSTATE_M   0x00000F00U

§ HOST_DMA_CH6STA_FSMSTATE_S

#define HOST_DMA_CH6STA_FSMSTATE_S   8U

§ HOST_DMA_CH6STA_RUN

#define HOST_DMA_CH6STA_RUN   0x00010000U

§ HOST_DMA_CH6STA_RUN_M

#define HOST_DMA_CH6STA_RUN_M   0x00010000U

§ HOST_DMA_CH6STA_RUN_S

#define HOST_DMA_CH6STA_RUN_S   16U

§ HOST_DMA_CH6TIPTR_IPTR_W

#define HOST_DMA_CH6TIPTR_IPTR_W   32U

§ HOST_DMA_CH6TIPTR_IPTR_M

#define HOST_DMA_CH6TIPTR_IPTR_M   0xFFFFFFFFU

§ HOST_DMA_CH6TIPTR_IPTR_S

#define HOST_DMA_CH6TIPTR_IPTR_S   0U

§ HOST_DMA_CH6TOPTR_OPTR_W

#define HOST_DMA_CH6TOPTR_OPTR_W   32U

§ HOST_DMA_CH6TOPTR_OPTR_M

#define HOST_DMA_CH6TOPTR_OPTR_M   0xFFFFFFFFU

§ HOST_DMA_CH6TOPTR_OPTR_S

#define HOST_DMA_CH6TOPTR_OPTR_S   0U

§ HOST_DMA_CH6TCTL_TRANSB_W

#define HOST_DMA_CH6TCTL_TRANSB_W   14U

§ HOST_DMA_CH6TCTL_TRANSB_M

#define HOST_DMA_CH6TCTL_TRANSB_M   0x00003FFFU

§ HOST_DMA_CH6TCTL_TRANSB_S

#define HOST_DMA_CH6TCTL_TRANSB_S   0U

§ HOST_DMA_CH6TCTL_BURSTREQ

#define HOST_DMA_CH6TCTL_BURSTREQ   0x00010000U

§ HOST_DMA_CH6TCTL_BURSTREQ_M

#define HOST_DMA_CH6TCTL_BURSTREQ_M   0x00010000U

§ HOST_DMA_CH6TCTL_BURSTREQ_S

#define HOST_DMA_CH6TCTL_BURSTREQ_S   16U

§ HOST_DMA_CH6TCTL_SPARE

#define HOST_DMA_CH6TCTL_SPARE   0x00020000U

§ HOST_DMA_CH6TCTL_SPARE_M

#define HOST_DMA_CH6TCTL_SPARE_M   0x00020000U

§ HOST_DMA_CH6TCTL_SPARE_S

#define HOST_DMA_CH6TCTL_SPARE_S   17U

§ HOST_DMA_CH6TCTL_ENDIANESS_W

#define HOST_DMA_CH6TCTL_ENDIANESS_W   2U

§ HOST_DMA_CH6TCTL_ENDIANESS_M

#define HOST_DMA_CH6TCTL_ENDIANESS_M   0x03000000U

§ HOST_DMA_CH6TCTL_ENDIANESS_S

#define HOST_DMA_CH6TCTL_ENDIANESS_S   24U

§ HOST_DMA_CH6TCTL2_CMD_W

#define HOST_DMA_CH6TCTL2_CMD_W   3U

§ HOST_DMA_CH6TCTL2_CMD_M

#define HOST_DMA_CH6TCTL2_CMD_M   0x00000007U

§ HOST_DMA_CH6TCTL2_CMD_S

#define HOST_DMA_CH6TCTL2_CMD_S   0U

§ HOST_DMA_CH6TSTA_STA

#define HOST_DMA_CH6TSTA_STA   0x00000001U

§ HOST_DMA_CH6TSTA_STA_M

#define HOST_DMA_CH6TSTA_STA_M   0x00000001U

§ HOST_DMA_CH6TSTA_STA_S

#define HOST_DMA_CH6TSTA_STA_S   0U

§ HOST_DMA_CH6TSTA_WORDOFFSET_W

#define HOST_DMA_CH6TSTA_WORDOFFSET_W   8U

§ HOST_DMA_CH6TSTA_WORDOFFSET_M

#define HOST_DMA_CH6TSTA_WORDOFFSET_M   0x0000FF00U

§ HOST_DMA_CH6TSTA_WORDOFFSET_S

#define HOST_DMA_CH6TSTA_WORDOFFSET_S   8U

§ HOST_DMA_CH6TSTA_REMAINB_W

#define HOST_DMA_CH6TSTA_REMAINB_W   14U

§ HOST_DMA_CH6TSTA_REMAINB_M

#define HOST_DMA_CH6TSTA_REMAINB_M   0x3FFF0000U

§ HOST_DMA_CH6TSTA_REMAINB_S

#define HOST_DMA_CH6TSTA_REMAINB_S   16U

§ HOST_DMA_CH6JCTL_WORDSIZE_W

#define HOST_DMA_CH6JCTL_WORDSIZE_W   2U

§ HOST_DMA_CH6JCTL_WORDSIZE_M

#define HOST_DMA_CH6JCTL_WORDSIZE_M   0x00000003U

§ HOST_DMA_CH6JCTL_WORDSIZE_S

#define HOST_DMA_CH6JCTL_WORDSIZE_S   0U

§ HOST_DMA_CH6JCTL_BLKSIZE_W

#define HOST_DMA_CH6JCTL_BLKSIZE_W   6U

§ HOST_DMA_CH6JCTL_BLKSIZE_M

#define HOST_DMA_CH6JCTL_BLKSIZE_M   0x003F0000U

§ HOST_DMA_CH6JCTL_BLKSIZE_S

#define HOST_DMA_CH6JCTL_BLKSIZE_S   16U

§ HOST_DMA_CH6JCTL_DMASIGBPS

#define HOST_DMA_CH6JCTL_DMASIGBPS   0x04000000U

§ HOST_DMA_CH6JCTL_DMASIGBPS_M

#define HOST_DMA_CH6JCTL_DMASIGBPS_M   0x04000000U

§ HOST_DMA_CH6JCTL_DMASIGBPS_S

#define HOST_DMA_CH6JCTL_DMASIGBPS_S   26U

§ HOST_DMA_CH6JCTL_FIFOMODS

#define HOST_DMA_CH6JCTL_FIFOMODS   0x08000000U

§ HOST_DMA_CH6JCTL_FIFOMODS_M

#define HOST_DMA_CH6JCTL_FIFOMODS_M   0x08000000U

§ HOST_DMA_CH6JCTL_FIFOMODS_S

#define HOST_DMA_CH6JCTL_FIFOMODS_S   27U

§ HOST_DMA_CH6JCTL_FIFOMODD

#define HOST_DMA_CH6JCTL_FIFOMODD   0x10000000U

§ HOST_DMA_CH6JCTL_FIFOMODD_M

#define HOST_DMA_CH6JCTL_FIFOMODD_M   0x10000000U

§ HOST_DMA_CH6JCTL_FIFOMODD_S

#define HOST_DMA_CH6JCTL_FIFOMODD_S   28U

§ HOST_DMA_CH6JCTL_SRCDSTCFG

#define HOST_DMA_CH6JCTL_SRCDSTCFG   0x20000000U

§ HOST_DMA_CH6JCTL_SRCDSTCFG_M

#define HOST_DMA_CH6JCTL_SRCDSTCFG_M   0x20000000U

§ HOST_DMA_CH6JCTL_SRCDSTCFG_S

#define HOST_DMA_CH6JCTL_SRCDSTCFG_S   29U

§ HOST_DMA_CH6JCTL_ENCLR

#define HOST_DMA_CH6JCTL_ENCLR   0x40000000U

§ HOST_DMA_CH6JCTL_ENCLR_M

#define HOST_DMA_CH6JCTL_ENCLR_M   0x40000000U

§ HOST_DMA_CH6JCTL_ENCLR_S

#define HOST_DMA_CH6JCTL_ENCLR_S   30U

§ HOST_DMA_CH7STA_HWEVENT_W

#define HOST_DMA_CH7STA_HWEVENT_W   3U

§ HOST_DMA_CH7STA_HWEVENT_M

#define HOST_DMA_CH7STA_HWEVENT_M   0x00000007U

§ HOST_DMA_CH7STA_HWEVENT_S

#define HOST_DMA_CH7STA_HWEVENT_S   0U

§ HOST_DMA_CH7STA_FSMSTATE_W

#define HOST_DMA_CH7STA_FSMSTATE_W   4U

§ HOST_DMA_CH7STA_FSMSTATE_M

#define HOST_DMA_CH7STA_FSMSTATE_M   0x00000F00U

§ HOST_DMA_CH7STA_FSMSTATE_S

#define HOST_DMA_CH7STA_FSMSTATE_S   8U

§ HOST_DMA_CH7STA_RUN

#define HOST_DMA_CH7STA_RUN   0x00010000U

§ HOST_DMA_CH7STA_RUN_M

#define HOST_DMA_CH7STA_RUN_M   0x00010000U

§ HOST_DMA_CH7STA_RUN_S

#define HOST_DMA_CH7STA_RUN_S   16U

§ HOST_DMA_CH7TIPTR_IPTR_W

#define HOST_DMA_CH7TIPTR_IPTR_W   32U

§ HOST_DMA_CH7TIPTR_IPTR_M

#define HOST_DMA_CH7TIPTR_IPTR_M   0xFFFFFFFFU

§ HOST_DMA_CH7TIPTR_IPTR_S

#define HOST_DMA_CH7TIPTR_IPTR_S   0U

§ HOST_DMA_CH7TOPTR_OPTR_W

#define HOST_DMA_CH7TOPTR_OPTR_W   32U

§ HOST_DMA_CH7TOPTR_OPTR_M

#define HOST_DMA_CH7TOPTR_OPTR_M   0xFFFFFFFFU

§ HOST_DMA_CH7TOPTR_OPTR_S

#define HOST_DMA_CH7TOPTR_OPTR_S   0U

§ HOST_DMA_CH7TCTL_TRANSB_W

#define HOST_DMA_CH7TCTL_TRANSB_W   14U

§ HOST_DMA_CH7TCTL_TRANSB_M

#define HOST_DMA_CH7TCTL_TRANSB_M   0x00003FFFU

§ HOST_DMA_CH7TCTL_TRANSB_S

#define HOST_DMA_CH7TCTL_TRANSB_S   0U

§ HOST_DMA_CH7TCTL_BURSTREQ

#define HOST_DMA_CH7TCTL_BURSTREQ   0x00010000U

§ HOST_DMA_CH7TCTL_BURSTREQ_M

#define HOST_DMA_CH7TCTL_BURSTREQ_M   0x00010000U

§ HOST_DMA_CH7TCTL_BURSTREQ_S

#define HOST_DMA_CH7TCTL_BURSTREQ_S   16U

§ HOST_DMA_CH7TCTL_SPARE

#define HOST_DMA_CH7TCTL_SPARE   0x00020000U

§ HOST_DMA_CH7TCTL_SPARE_M

#define HOST_DMA_CH7TCTL_SPARE_M   0x00020000U

§ HOST_DMA_CH7TCTL_SPARE_S

#define HOST_DMA_CH7TCTL_SPARE_S   17U

§ HOST_DMA_CH7TCTL_ENDIANESS_W

#define HOST_DMA_CH7TCTL_ENDIANESS_W   2U

§ HOST_DMA_CH7TCTL_ENDIANESS_M

#define HOST_DMA_CH7TCTL_ENDIANESS_M   0x03000000U

§ HOST_DMA_CH7TCTL_ENDIANESS_S

#define HOST_DMA_CH7TCTL_ENDIANESS_S   24U

§ HOST_DMA_CH7TCTL2_CMD_W

#define HOST_DMA_CH7TCTL2_CMD_W   3U

§ HOST_DMA_CH7TCTL2_CMD_M

#define HOST_DMA_CH7TCTL2_CMD_M   0x00000007U

§ HOST_DMA_CH7TCTL2_CMD_S

#define HOST_DMA_CH7TCTL2_CMD_S   0U

§ HOST_DMA_CH7TSTA_STA

#define HOST_DMA_CH7TSTA_STA   0x00000001U

§ HOST_DMA_CH7TSTA_STA_M

#define HOST_DMA_CH7TSTA_STA_M   0x00000001U

§ HOST_DMA_CH7TSTA_STA_S

#define HOST_DMA_CH7TSTA_STA_S   0U

§ HOST_DMA_CH7TSTA_OFFSET_W

#define HOST_DMA_CH7TSTA_OFFSET_W   8U

§ HOST_DMA_CH7TSTA_OFFSET_M

#define HOST_DMA_CH7TSTA_OFFSET_M   0x0000FF00U

§ HOST_DMA_CH7TSTA_OFFSET_S

#define HOST_DMA_CH7TSTA_OFFSET_S   8U

§ HOST_DMA_CH7TSTA_REMAINB_W

#define HOST_DMA_CH7TSTA_REMAINB_W   14U

§ HOST_DMA_CH7TSTA_REMAINB_M

#define HOST_DMA_CH7TSTA_REMAINB_M   0x3FFF0000U

§ HOST_DMA_CH7TSTA_REMAINB_S

#define HOST_DMA_CH7TSTA_REMAINB_S   16U

§ HOST_DMA_CH7JCTL_WORDSIZE_W

#define HOST_DMA_CH7JCTL_WORDSIZE_W   2U

§ HOST_DMA_CH7JCTL_WORDSIZE_M

#define HOST_DMA_CH7JCTL_WORDSIZE_M   0x00000003U

§ HOST_DMA_CH7JCTL_WORDSIZE_S

#define HOST_DMA_CH7JCTL_WORDSIZE_S   0U

§ HOST_DMA_CH7JCTL_BLKSIZE_W

#define HOST_DMA_CH7JCTL_BLKSIZE_W   6U

§ HOST_DMA_CH7JCTL_BLKSIZE_M

#define HOST_DMA_CH7JCTL_BLKSIZE_M   0x003F0000U

§ HOST_DMA_CH7JCTL_BLKSIZE_S

#define HOST_DMA_CH7JCTL_BLKSIZE_S   16U

§ HOST_DMA_CH7JCTL_DMASIGBPS

#define HOST_DMA_CH7JCTL_DMASIGBPS   0x04000000U

§ HOST_DMA_CH7JCTL_DMASIGBPS_M

#define HOST_DMA_CH7JCTL_DMASIGBPS_M   0x04000000U

§ HOST_DMA_CH7JCTL_DMASIGBPS_S

#define HOST_DMA_CH7JCTL_DMASIGBPS_S   26U

§ HOST_DMA_CH7JCTL_FIFOMODS

#define HOST_DMA_CH7JCTL_FIFOMODS   0x08000000U

§ HOST_DMA_CH7JCTL_FIFOMODS_M

#define HOST_DMA_CH7JCTL_FIFOMODS_M   0x08000000U

§ HOST_DMA_CH7JCTL_FIFOMODS_S

#define HOST_DMA_CH7JCTL_FIFOMODS_S   27U

§ HOST_DMA_CH7JCTL_FIFOMODD

#define HOST_DMA_CH7JCTL_FIFOMODD   0x10000000U

§ HOST_DMA_CH7JCTL_FIFOMODD_M

#define HOST_DMA_CH7JCTL_FIFOMODD_M   0x10000000U

§ HOST_DMA_CH7JCTL_FIFOMODD_S

#define HOST_DMA_CH7JCTL_FIFOMODD_S   28U

§ HOST_DMA_CH7JCTL_SRCDSTCFG

#define HOST_DMA_CH7JCTL_SRCDSTCFG   0x20000000U

§ HOST_DMA_CH7JCTL_SRCDSTCFG_M

#define HOST_DMA_CH7JCTL_SRCDSTCFG_M   0x20000000U

§ HOST_DMA_CH7JCTL_SRCDSTCFG_S

#define HOST_DMA_CH7JCTL_SRCDSTCFG_S   29U

§ HOST_DMA_CH7JCTL_ENCLR

#define HOST_DMA_CH7JCTL_ENCLR   0x40000000U

§ HOST_DMA_CH7JCTL_ENCLR_M

#define HOST_DMA_CH7JCTL_ENCLR_M   0x40000000U

§ HOST_DMA_CH7JCTL_ENCLR_S

#define HOST_DMA_CH7JCTL_ENCLR_S   30U

§ HOST_DMA_CH8STA_HWEVENT_W

#define HOST_DMA_CH8STA_HWEVENT_W   3U

§ HOST_DMA_CH8STA_HWEVENT_M

#define HOST_DMA_CH8STA_HWEVENT_M   0x00000007U

§ HOST_DMA_CH8STA_HWEVENT_S

#define HOST_DMA_CH8STA_HWEVENT_S   0U

§ HOST_DMA_CH8STA_FSMSTATE_W

#define HOST_DMA_CH8STA_FSMSTATE_W   4U

§ HOST_DMA_CH8STA_FSMSTATE_M

#define HOST_DMA_CH8STA_FSMSTATE_M   0x00000F00U

§ HOST_DMA_CH8STA_FSMSTATE_S

#define HOST_DMA_CH8STA_FSMSTATE_S   8U

§ HOST_DMA_CH8STA_RUN

#define HOST_DMA_CH8STA_RUN   0x00010000U

§ HOST_DMA_CH8STA_RUN_M

#define HOST_DMA_CH8STA_RUN_M   0x00010000U

§ HOST_DMA_CH8STA_RUN_S

#define HOST_DMA_CH8STA_RUN_S   16U

§ HOST_DMA_CH8TIPTR_IPTR_W

#define HOST_DMA_CH8TIPTR_IPTR_W   32U

§ HOST_DMA_CH8TIPTR_IPTR_M

#define HOST_DMA_CH8TIPTR_IPTR_M   0xFFFFFFFFU

§ HOST_DMA_CH8TIPTR_IPTR_S

#define HOST_DMA_CH8TIPTR_IPTR_S   0U

§ HOST_DMA_CH8TOPTR_OPTR_W

#define HOST_DMA_CH8TOPTR_OPTR_W   32U

§ HOST_DMA_CH8TOPTR_OPTR_M

#define HOST_DMA_CH8TOPTR_OPTR_M   0xFFFFFFFFU

§ HOST_DMA_CH8TOPTR_OPTR_S

#define HOST_DMA_CH8TOPTR_OPTR_S   0U

§ HOST_DMA_CH8TCTL_TRANSB_W

#define HOST_DMA_CH8TCTL_TRANSB_W   14U

§ HOST_DMA_CH8TCTL_TRANSB_M

#define HOST_DMA_CH8TCTL_TRANSB_M   0x00003FFFU

§ HOST_DMA_CH8TCTL_TRANSB_S

#define HOST_DMA_CH8TCTL_TRANSB_S   0U

§ HOST_DMA_CH8TCTL_BURSTREQ

#define HOST_DMA_CH8TCTL_BURSTREQ   0x00010000U

§ HOST_DMA_CH8TCTL_BURSTREQ_M

#define HOST_DMA_CH8TCTL_BURSTREQ_M   0x00010000U

§ HOST_DMA_CH8TCTL_BURSTREQ_S

#define HOST_DMA_CH8TCTL_BURSTREQ_S   16U

§ HOST_DMA_CH8TCTL_SPARE

#define HOST_DMA_CH8TCTL_SPARE   0x00020000U

§ HOST_DMA_CH8TCTL_SPARE_M

#define HOST_DMA_CH8TCTL_SPARE_M   0x00020000U

§ HOST_DMA_CH8TCTL_SPARE_S

#define HOST_DMA_CH8TCTL_SPARE_S   17U

§ HOST_DMA_CH8TCTL_ENDIANESS_W

#define HOST_DMA_CH8TCTL_ENDIANESS_W   2U

§ HOST_DMA_CH8TCTL_ENDIANESS_M

#define HOST_DMA_CH8TCTL_ENDIANESS_M   0x03000000U

§ HOST_DMA_CH8TCTL_ENDIANESS_S

#define HOST_DMA_CH8TCTL_ENDIANESS_S   24U

§ HOST_DMA_CH8TCTL2_CMD_W

#define HOST_DMA_CH8TCTL2_CMD_W   3U

§ HOST_DMA_CH8TCTL2_CMD_M

#define HOST_DMA_CH8TCTL2_CMD_M   0x00000007U

§ HOST_DMA_CH8TCTL2_CMD_S

#define HOST_DMA_CH8TCTL2_CMD_S   0U

§ HOST_DMA_CH8TSTA_STA

#define HOST_DMA_CH8TSTA_STA   0x00000001U

§ HOST_DMA_CH8TSTA_STA_M

#define HOST_DMA_CH8TSTA_STA_M   0x00000001U

§ HOST_DMA_CH8TSTA_STA_S

#define HOST_DMA_CH8TSTA_STA_S   0U

§ HOST_DMA_CH8TSTA_OFFSET_W

#define HOST_DMA_CH8TSTA_OFFSET_W   8U

§ HOST_DMA_CH8TSTA_OFFSET_M

#define HOST_DMA_CH8TSTA_OFFSET_M   0x0000FF00U

§ HOST_DMA_CH8TSTA_OFFSET_S

#define HOST_DMA_CH8TSTA_OFFSET_S   8U

§ HOST_DMA_CH8TSTA_REMAINB_W

#define HOST_DMA_CH8TSTA_REMAINB_W   14U

§ HOST_DMA_CH8TSTA_REMAINB_M

#define HOST_DMA_CH8TSTA_REMAINB_M   0x3FFF0000U

§ HOST_DMA_CH8TSTA_REMAINB_S

#define HOST_DMA_CH8TSTA_REMAINB_S   16U

§ HOST_DMA_CH8JCTL_WORDSIZE_W

#define HOST_DMA_CH8JCTL_WORDSIZE_W   2U

§ HOST_DMA_CH8JCTL_WORDSIZE_M

#define HOST_DMA_CH8JCTL_WORDSIZE_M   0x00000003U

§ HOST_DMA_CH8JCTL_WORDSIZE_S

#define HOST_DMA_CH8JCTL_WORDSIZE_S   0U

§ HOST_DMA_CH8JCTL_BLKSIZE_W

#define HOST_DMA_CH8JCTL_BLKSIZE_W   6U

§ HOST_DMA_CH8JCTL_BLKSIZE_M

#define HOST_DMA_CH8JCTL_BLKSIZE_M   0x003F0000U

§ HOST_DMA_CH8JCTL_BLKSIZE_S

#define HOST_DMA_CH8JCTL_BLKSIZE_S   16U

§ HOST_DMA_CH8JCTL_DMASIGBPS

#define HOST_DMA_CH8JCTL_DMASIGBPS   0x04000000U

§ HOST_DMA_CH8JCTL_DMASIGBPS_M

#define HOST_DMA_CH8JCTL_DMASIGBPS_M   0x04000000U

§ HOST_DMA_CH8JCTL_DMASIGBPS_S

#define HOST_DMA_CH8JCTL_DMASIGBPS_S   26U

§ HOST_DMA_CH8JCTL_FIFOMODS

#define HOST_DMA_CH8JCTL_FIFOMODS   0x08000000U

§ HOST_DMA_CH8JCTL_FIFOMODS_M

#define HOST_DMA_CH8JCTL_FIFOMODS_M   0x08000000U

§ HOST_DMA_CH8JCTL_FIFOMODS_S

#define HOST_DMA_CH8JCTL_FIFOMODS_S   27U

§ HOST_DMA_CH8JCTL_FIFOMODD

#define HOST_DMA_CH8JCTL_FIFOMODD   0x10000000U

§ HOST_DMA_CH8JCTL_FIFOMODD_M

#define HOST_DMA_CH8JCTL_FIFOMODD_M   0x10000000U

§ HOST_DMA_CH8JCTL_FIFOMODD_S

#define HOST_DMA_CH8JCTL_FIFOMODD_S   28U

§ HOST_DMA_CH8JCTL_SRCDSTCFG

#define HOST_DMA_CH8JCTL_SRCDSTCFG   0x20000000U

§ HOST_DMA_CH8JCTL_SRCDSTCFG_M

#define HOST_DMA_CH8JCTL_SRCDSTCFG_M   0x20000000U

§ HOST_DMA_CH8JCTL_SRCDSTCFG_S

#define HOST_DMA_CH8JCTL_SRCDSTCFG_S   29U

§ HOST_DMA_CH8JCTL_ENCLR

#define HOST_DMA_CH8JCTL_ENCLR   0x40000000U

§ HOST_DMA_CH8JCTL_ENCLR_M

#define HOST_DMA_CH8JCTL_ENCLR_M   0x40000000U

§ HOST_DMA_CH8JCTL_ENCLR_S

#define HOST_DMA_CH8JCTL_ENCLR_S   30U

§ HOST_DMA_CH9STA_HWEVENT_W

#define HOST_DMA_CH9STA_HWEVENT_W   3U

§ HOST_DMA_CH9STA_HWEVENT_M

#define HOST_DMA_CH9STA_HWEVENT_M   0x00000007U

§ HOST_DMA_CH9STA_HWEVENT_S

#define HOST_DMA_CH9STA_HWEVENT_S   0U

§ HOST_DMA_CH9STA_FSMSTATE_W

#define HOST_DMA_CH9STA_FSMSTATE_W   4U

§ HOST_DMA_CH9STA_FSMSTATE_M

#define HOST_DMA_CH9STA_FSMSTATE_M   0x00000F00U

§ HOST_DMA_CH9STA_FSMSTATE_S

#define HOST_DMA_CH9STA_FSMSTATE_S   8U

§ HOST_DMA_CH9STA_RUN

#define HOST_DMA_CH9STA_RUN   0x00010000U

§ HOST_DMA_CH9STA_RUN_M

#define HOST_DMA_CH9STA_RUN_M   0x00010000U

§ HOST_DMA_CH9STA_RUN_S

#define HOST_DMA_CH9STA_RUN_S   16U

§ HOST_DMA_CH9TIPTR_IPTR_W

#define HOST_DMA_CH9TIPTR_IPTR_W   32U

§ HOST_DMA_CH9TIPTR_IPTR_M

#define HOST_DMA_CH9TIPTR_IPTR_M   0xFFFFFFFFU

§ HOST_DMA_CH9TIPTR_IPTR_S

#define HOST_DMA_CH9TIPTR_IPTR_S   0U

§ HOST_DMA_CH9TOPTR_OPTR_W

#define HOST_DMA_CH9TOPTR_OPTR_W   32U

§ HOST_DMA_CH9TOPTR_OPTR_M

#define HOST_DMA_CH9TOPTR_OPTR_M   0xFFFFFFFFU

§ HOST_DMA_CH9TOPTR_OPTR_S

#define HOST_DMA_CH9TOPTR_OPTR_S   0U

§ HOST_DMA_CH9TCTL_TRANSB_W

#define HOST_DMA_CH9TCTL_TRANSB_W   14U

§ HOST_DMA_CH9TCTL_TRANSB_M

#define HOST_DMA_CH9TCTL_TRANSB_M   0x00003FFFU

§ HOST_DMA_CH9TCTL_TRANSB_S

#define HOST_DMA_CH9TCTL_TRANSB_S   0U

§ HOST_DMA_CH9TCTL_BURSTREQ

#define HOST_DMA_CH9TCTL_BURSTREQ   0x00010000U

§ HOST_DMA_CH9TCTL_BURSTREQ_M

#define HOST_DMA_CH9TCTL_BURSTREQ_M   0x00010000U

§ HOST_DMA_CH9TCTL_BURSTREQ_S

#define HOST_DMA_CH9TCTL_BURSTREQ_S   16U

§ HOST_DMA_CH9TCTL_SPARE

#define HOST_DMA_CH9TCTL_SPARE   0x00020000U

§ HOST_DMA_CH9TCTL_SPARE_M

#define HOST_DMA_CH9TCTL_SPARE_M   0x00020000U

§ HOST_DMA_CH9TCTL_SPARE_S

#define HOST_DMA_CH9TCTL_SPARE_S   17U

§ HOST_DMA_CH9TCTL_ENDIANESS_W

#define HOST_DMA_CH9TCTL_ENDIANESS_W   2U

§ HOST_DMA_CH9TCTL_ENDIANESS_M

#define HOST_DMA_CH9TCTL_ENDIANESS_M   0x03000000U

§ HOST_DMA_CH9TCTL_ENDIANESS_S

#define HOST_DMA_CH9TCTL_ENDIANESS_S   24U

§ HOST_DMA_CH9TCTL2_CMD_W

#define HOST_DMA_CH9TCTL2_CMD_W   3U

§ HOST_DMA_CH9TCTL2_CMD_M

#define HOST_DMA_CH9TCTL2_CMD_M   0x00000007U

§ HOST_DMA_CH9TCTL2_CMD_S

#define HOST_DMA_CH9TCTL2_CMD_S   0U

§ HOST_DMA_CH9TSTA_STA

#define HOST_DMA_CH9TSTA_STA   0x00000001U

§ HOST_DMA_CH9TSTA_STA_M

#define HOST_DMA_CH9TSTA_STA_M   0x00000001U

§ HOST_DMA_CH9TSTA_STA_S

#define HOST_DMA_CH9TSTA_STA_S   0U

§ HOST_DMA_CH9TSTA_OFFSET_W

#define HOST_DMA_CH9TSTA_OFFSET_W   8U

§ HOST_DMA_CH9TSTA_OFFSET_M

#define HOST_DMA_CH9TSTA_OFFSET_M   0x0000FF00U

§ HOST_DMA_CH9TSTA_OFFSET_S

#define HOST_DMA_CH9TSTA_OFFSET_S   8U

§ HOST_DMA_CH9TSTA_REMAINB_W

#define HOST_DMA_CH9TSTA_REMAINB_W   14U

§ HOST_DMA_CH9TSTA_REMAINB_M

#define HOST_DMA_CH9TSTA_REMAINB_M   0x3FFF0000U

§ HOST_DMA_CH9TSTA_REMAINB_S

#define HOST_DMA_CH9TSTA_REMAINB_S   16U

§ HOST_DMA_CH9JCTL_WORDSIZE_W

#define HOST_DMA_CH9JCTL_WORDSIZE_W   2U

§ HOST_DMA_CH9JCTL_WORDSIZE_M

#define HOST_DMA_CH9JCTL_WORDSIZE_M   0x00000003U

§ HOST_DMA_CH9JCTL_WORDSIZE_S

#define HOST_DMA_CH9JCTL_WORDSIZE_S   0U

§ HOST_DMA_CH9JCTL_BLKSIZE_W

#define HOST_DMA_CH9JCTL_BLKSIZE_W   6U

§ HOST_DMA_CH9JCTL_BLKSIZE_M

#define HOST_DMA_CH9JCTL_BLKSIZE_M   0x003F0000U

§ HOST_DMA_CH9JCTL_BLKSIZE_S

#define HOST_DMA_CH9JCTL_BLKSIZE_S   16U

§ HOST_DMA_CH9JCTL_DMASIGBPS

#define HOST_DMA_CH9JCTL_DMASIGBPS   0x04000000U

§ HOST_DMA_CH9JCTL_DMASIGBPS_M

#define HOST_DMA_CH9JCTL_DMASIGBPS_M   0x04000000U

§ HOST_DMA_CH9JCTL_DMASIGBPS_S

#define HOST_DMA_CH9JCTL_DMASIGBPS_S   26U

§ HOST_DMA_CH9JCTL_FIFOMODS

#define HOST_DMA_CH9JCTL_FIFOMODS   0x08000000U

§ HOST_DMA_CH9JCTL_FIFOMODS_M

#define HOST_DMA_CH9JCTL_FIFOMODS_M   0x08000000U

§ HOST_DMA_CH9JCTL_FIFOMODS_S

#define HOST_DMA_CH9JCTL_FIFOMODS_S   27U

§ HOST_DMA_CH9JCTL_FIFOMODD

#define HOST_DMA_CH9JCTL_FIFOMODD   0x10000000U

§ HOST_DMA_CH9JCTL_FIFOMODD_M

#define HOST_DMA_CH9JCTL_FIFOMODD_M   0x10000000U

§ HOST_DMA_CH9JCTL_FIFOMODD_S

#define HOST_DMA_CH9JCTL_FIFOMODD_S   28U

§ HOST_DMA_CH9JCTL_SRCDSTCFG

#define HOST_DMA_CH9JCTL_SRCDSTCFG   0x20000000U

§ HOST_DMA_CH9JCTL_SRCDSTCFG_M

#define HOST_DMA_CH9JCTL_SRCDSTCFG_M   0x20000000U

§ HOST_DMA_CH9JCTL_SRCDSTCFG_S

#define HOST_DMA_CH9JCTL_SRCDSTCFG_S   29U

§ HOST_DMA_CH9JCTL_ENCLR

#define HOST_DMA_CH9JCTL_ENCLR   0x40000000U

§ HOST_DMA_CH9JCTL_ENCLR_M

#define HOST_DMA_CH9JCTL_ENCLR_M   0x40000000U

§ HOST_DMA_CH9JCTL_ENCLR_S

#define HOST_DMA_CH9JCTL_ENCLR_S   30U

§ HOST_DMA_CH10STA_HWEVENT_W

#define HOST_DMA_CH10STA_HWEVENT_W   3U

§ HOST_DMA_CH10STA_HWEVENT_M

#define HOST_DMA_CH10STA_HWEVENT_M   0x00000007U

§ HOST_DMA_CH10STA_HWEVENT_S

#define HOST_DMA_CH10STA_HWEVENT_S   0U

§ HOST_DMA_CH10STA_FSMSTATE_W

#define HOST_DMA_CH10STA_FSMSTATE_W   4U

§ HOST_DMA_CH10STA_FSMSTATE_M

#define HOST_DMA_CH10STA_FSMSTATE_M   0x00000F00U

§ HOST_DMA_CH10STA_FSMSTATE_S

#define HOST_DMA_CH10STA_FSMSTATE_S   8U

§ HOST_DMA_CH10STA_RUN

#define HOST_DMA_CH10STA_RUN   0x00010000U

§ HOST_DMA_CH10STA_RUN_M

#define HOST_DMA_CH10STA_RUN_M   0x00010000U

§ HOST_DMA_CH10STA_RUN_S

#define HOST_DMA_CH10STA_RUN_S   16U

§ HOST_DMA_CH10TIPTR_IPTR_W

#define HOST_DMA_CH10TIPTR_IPTR_W   32U

§ HOST_DMA_CH10TIPTR_IPTR_M

#define HOST_DMA_CH10TIPTR_IPTR_M   0xFFFFFFFFU

§ HOST_DMA_CH10TIPTR_IPTR_S

#define HOST_DMA_CH10TIPTR_IPTR_S   0U

§ HOST_DMA_CH10TOPTR_OPTR_W

#define HOST_DMA_CH10TOPTR_OPTR_W   32U

§ HOST_DMA_CH10TOPTR_OPTR_M

#define HOST_DMA_CH10TOPTR_OPTR_M   0xFFFFFFFFU

§ HOST_DMA_CH10TOPTR_OPTR_S

#define HOST_DMA_CH10TOPTR_OPTR_S   0U

§ HOST_DMA_CH10TCTL_TRANSB_W

#define HOST_DMA_CH10TCTL_TRANSB_W   14U

§ HOST_DMA_CH10TCTL_TRANSB_M

#define HOST_DMA_CH10TCTL_TRANSB_M   0x00003FFFU

§ HOST_DMA_CH10TCTL_TRANSB_S

#define HOST_DMA_CH10TCTL_TRANSB_S   0U

§ HOST_DMA_CH10TCTL_BURSTREQ

#define HOST_DMA_CH10TCTL_BURSTREQ   0x00010000U

§ HOST_DMA_CH10TCTL_BURSTREQ_M

#define HOST_DMA_CH10TCTL_BURSTREQ_M   0x00010000U

§ HOST_DMA_CH10TCTL_BURSTREQ_S

#define HOST_DMA_CH10TCTL_BURSTREQ_S   16U

§ HOST_DMA_CH10TCTL_SPARE

#define HOST_DMA_CH10TCTL_SPARE   0x00020000U

§ HOST_DMA_CH10TCTL_SPARE_M

#define HOST_DMA_CH10TCTL_SPARE_M   0x00020000U

§ HOST_DMA_CH10TCTL_SPARE_S

#define HOST_DMA_CH10TCTL_SPARE_S   17U

§ HOST_DMA_CH10TCTL_ENDIANESS_W

#define HOST_DMA_CH10TCTL_ENDIANESS_W   2U

§ HOST_DMA_CH10TCTL_ENDIANESS_M

#define HOST_DMA_CH10TCTL_ENDIANESS_M   0x03000000U

§ HOST_DMA_CH10TCTL_ENDIANESS_S

#define HOST_DMA_CH10TCTL_ENDIANESS_S   24U

§ HOST_DMA_CH10TCTL2_CMD_W

#define HOST_DMA_CH10TCTL2_CMD_W   3U

§ HOST_DMA_CH10TCTL2_CMD_M

#define HOST_DMA_CH10TCTL2_CMD_M   0x00000007U

§ HOST_DMA_CH10TCTL2_CMD_S

#define HOST_DMA_CH10TCTL2_CMD_S   0U

§ HOST_DMA_CH10TSTA_STA

#define HOST_DMA_CH10TSTA_STA   0x00000001U

§ HOST_DMA_CH10TSTA_STA_M

#define HOST_DMA_CH10TSTA_STA_M   0x00000001U

§ HOST_DMA_CH10TSTA_STA_S

#define HOST_DMA_CH10TSTA_STA_S   0U

§ HOST_DMA_CH10TSTA_OFFSET_W

#define HOST_DMA_CH10TSTA_OFFSET_W   8U

§ HOST_DMA_CH10TSTA_OFFSET_M

#define HOST_DMA_CH10TSTA_OFFSET_M   0x0000FF00U

§ HOST_DMA_CH10TSTA_OFFSET_S

#define HOST_DMA_CH10TSTA_OFFSET_S   8U

§ HOST_DMA_CH10TSTA_REMAINB_W

#define HOST_DMA_CH10TSTA_REMAINB_W   14U

§ HOST_DMA_CH10TSTA_REMAINB_M

#define HOST_DMA_CH10TSTA_REMAINB_M   0x3FFF0000U

§ HOST_DMA_CH10TSTA_REMAINB_S

#define HOST_DMA_CH10TSTA_REMAINB_S   16U

§ HOST_DMA_CH10JCTL_WORDSIZE_W

#define HOST_DMA_CH10JCTL_WORDSIZE_W   2U

§ HOST_DMA_CH10JCTL_WORDSIZE_M

#define HOST_DMA_CH10JCTL_WORDSIZE_M   0x00000003U

§ HOST_DMA_CH10JCTL_WORDSIZE_S

#define HOST_DMA_CH10JCTL_WORDSIZE_S   0U

§ HOST_DMA_CH10JCTL_BLKSIZE_W

#define HOST_DMA_CH10JCTL_BLKSIZE_W   8U

§ HOST_DMA_CH10JCTL_BLKSIZE_M

#define HOST_DMA_CH10JCTL_BLKSIZE_M   0x00FF0000U

§ HOST_DMA_CH10JCTL_BLKSIZE_S

#define HOST_DMA_CH10JCTL_BLKSIZE_S   16U

§ HOST_DMA_CH10JCTL_DMASIGBPS

#define HOST_DMA_CH10JCTL_DMASIGBPS   0x04000000U

§ HOST_DMA_CH10JCTL_DMASIGBPS_M

#define HOST_DMA_CH10JCTL_DMASIGBPS_M   0x04000000U

§ HOST_DMA_CH10JCTL_DMASIGBPS_S

#define HOST_DMA_CH10JCTL_DMASIGBPS_S   26U

§ HOST_DMA_CH10JCTL_FIFOMODS

#define HOST_DMA_CH10JCTL_FIFOMODS   0x08000000U

§ HOST_DMA_CH10JCTL_FIFOMODS_M

#define HOST_DMA_CH10JCTL_FIFOMODS_M   0x08000000U

§ HOST_DMA_CH10JCTL_FIFOMODS_S

#define HOST_DMA_CH10JCTL_FIFOMODS_S   27U

§ HOST_DMA_CH10JCTL_FIFOMODD

#define HOST_DMA_CH10JCTL_FIFOMODD   0x10000000U

§ HOST_DMA_CH10JCTL_FIFOMODD_M

#define HOST_DMA_CH10JCTL_FIFOMODD_M   0x10000000U

§ HOST_DMA_CH10JCTL_FIFOMODD_S

#define HOST_DMA_CH10JCTL_FIFOMODD_S   28U

§ HOST_DMA_CH10JCTL_SRCDSTCFG

#define HOST_DMA_CH10JCTL_SRCDSTCFG   0x20000000U

§ HOST_DMA_CH10JCTL_SRCDSTCFG_M

#define HOST_DMA_CH10JCTL_SRCDSTCFG_M   0x20000000U

§ HOST_DMA_CH10JCTL_SRCDSTCFG_S

#define HOST_DMA_CH10JCTL_SRCDSTCFG_S   29U

§ HOST_DMA_CH10JCTL_ENCLR

#define HOST_DMA_CH10JCTL_ENCLR   0x40000000U

§ HOST_DMA_CH10JCTL_ENCLR_M

#define HOST_DMA_CH10JCTL_ENCLR_M   0x40000000U

§ HOST_DMA_CH10JCTL_ENCLR_S

#define HOST_DMA_CH10JCTL_ENCLR_S   30U

§ HOST_DMA_CH11STA_HWEVENT_W

#define HOST_DMA_CH11STA_HWEVENT_W   3U

§ HOST_DMA_CH11STA_HWEVENT_M

#define HOST_DMA_CH11STA_HWEVENT_M   0x00000007U

§ HOST_DMA_CH11STA_HWEVENT_S

#define HOST_DMA_CH11STA_HWEVENT_S   0U

§ HOST_DMA_CH11STA_FSMSTATE_W

#define HOST_DMA_CH11STA_FSMSTATE_W   4U

§ HOST_DMA_CH11STA_FSMSTATE_M

#define HOST_DMA_CH11STA_FSMSTATE_M   0x00000F00U

§ HOST_DMA_CH11STA_FSMSTATE_S

#define HOST_DMA_CH11STA_FSMSTATE_S   8U

§ HOST_DMA_CH11STA_RUN

#define HOST_DMA_CH11STA_RUN   0x00010000U

§ HOST_DMA_CH11STA_RUN_M

#define HOST_DMA_CH11STA_RUN_M   0x00010000U

§ HOST_DMA_CH11STA_RUN_S

#define HOST_DMA_CH11STA_RUN_S   16U

§ HOST_DMA_CH11TIPTR_IPTR_W

#define HOST_DMA_CH11TIPTR_IPTR_W   32U

§ HOST_DMA_CH11TIPTR_IPTR_M

#define HOST_DMA_CH11TIPTR_IPTR_M   0xFFFFFFFFU

§ HOST_DMA_CH11TIPTR_IPTR_S

#define HOST_DMA_CH11TIPTR_IPTR_S   0U

§ HOST_DMA_CH11TOPTR_OPTR_W

#define HOST_DMA_CH11TOPTR_OPTR_W   32U

§ HOST_DMA_CH11TOPTR_OPTR_M

#define HOST_DMA_CH11TOPTR_OPTR_M   0xFFFFFFFFU

§ HOST_DMA_CH11TOPTR_OPTR_S

#define HOST_DMA_CH11TOPTR_OPTR_S   0U

§ HOST_DMA_CH11TCTL_TRANSB_W

#define HOST_DMA_CH11TCTL_TRANSB_W   14U

§ HOST_DMA_CH11TCTL_TRANSB_M

#define HOST_DMA_CH11TCTL_TRANSB_M   0x00003FFFU

§ HOST_DMA_CH11TCTL_TRANSB_S

#define HOST_DMA_CH11TCTL_TRANSB_S   0U

§ HOST_DMA_CH11TCTL_BURSTREQ

#define HOST_DMA_CH11TCTL_BURSTREQ   0x00010000U

§ HOST_DMA_CH11TCTL_BURSTREQ_M

#define HOST_DMA_CH11TCTL_BURSTREQ_M   0x00010000U

§ HOST_DMA_CH11TCTL_BURSTREQ_S

#define HOST_DMA_CH11TCTL_BURSTREQ_S   16U

§ HOST_DMA_CH11TCTL_SPARE

#define HOST_DMA_CH11TCTL_SPARE   0x00020000U

§ HOST_DMA_CH11TCTL_SPARE_M

#define HOST_DMA_CH11TCTL_SPARE_M   0x00020000U

§ HOST_DMA_CH11TCTL_SPARE_S

#define HOST_DMA_CH11TCTL_SPARE_S   17U

§ HOST_DMA_CH11TCTL_ENDIANESS_W

#define HOST_DMA_CH11TCTL_ENDIANESS_W   2U

§ HOST_DMA_CH11TCTL_ENDIANESS_M

#define HOST_DMA_CH11TCTL_ENDIANESS_M   0x03000000U

§ HOST_DMA_CH11TCTL_ENDIANESS_S

#define HOST_DMA_CH11TCTL_ENDIANESS_S   24U

§ HOST_DMA_CH11TCTL2_CMD_W

#define HOST_DMA_CH11TCTL2_CMD_W   3U

§ HOST_DMA_CH11TCTL2_CMD_M

#define HOST_DMA_CH11TCTL2_CMD_M   0x00000007U

§ HOST_DMA_CH11TCTL2_CMD_S

#define HOST_DMA_CH11TCTL2_CMD_S   0U

§ HOST_DMA_CH11TSTA_STA

#define HOST_DMA_CH11TSTA_STA   0x00000001U

§ HOST_DMA_CH11TSTA_STA_M

#define HOST_DMA_CH11TSTA_STA_M   0x00000001U

§ HOST_DMA_CH11TSTA_STA_S

#define HOST_DMA_CH11TSTA_STA_S   0U

§ HOST_DMA_CH11TSTA_OFFSET_W

#define HOST_DMA_CH11TSTA_OFFSET_W   8U

§ HOST_DMA_CH11TSTA_OFFSET_M

#define HOST_DMA_CH11TSTA_OFFSET_M   0x0000FF00U

§ HOST_DMA_CH11TSTA_OFFSET_S

#define HOST_DMA_CH11TSTA_OFFSET_S   8U

§ HOST_DMA_CH11TSTA_REMAINB_W

#define HOST_DMA_CH11TSTA_REMAINB_W   14U

§ HOST_DMA_CH11TSTA_REMAINB_M

#define HOST_DMA_CH11TSTA_REMAINB_M   0x3FFF0000U

§ HOST_DMA_CH11TSTA_REMAINB_S

#define HOST_DMA_CH11TSTA_REMAINB_S   16U

§ HOST_DMA_CH11JCTL_WORDSIZE_W

#define HOST_DMA_CH11JCTL_WORDSIZE_W   2U

§ HOST_DMA_CH11JCTL_WORDSIZE_M

#define HOST_DMA_CH11JCTL_WORDSIZE_M   0x00000003U

§ HOST_DMA_CH11JCTL_WORDSIZE_S

#define HOST_DMA_CH11JCTL_WORDSIZE_S   0U

§ HOST_DMA_CH11JCTL_BLKSIZE_W

#define HOST_DMA_CH11JCTL_BLKSIZE_W   6U

§ HOST_DMA_CH11JCTL_BLKSIZE_M

#define HOST_DMA_CH11JCTL_BLKSIZE_M   0x003F0000U

§ HOST_DMA_CH11JCTL_BLKSIZE_S

#define HOST_DMA_CH11JCTL_BLKSIZE_S   16U

§ HOST_DMA_CH11JCTL_DMASIGBPS

#define HOST_DMA_CH11JCTL_DMASIGBPS   0x04000000U

§ HOST_DMA_CH11JCTL_DMASIGBPS_M

#define HOST_DMA_CH11JCTL_DMASIGBPS_M   0x04000000U

§ HOST_DMA_CH11JCTL_DMASIGBPS_S

#define HOST_DMA_CH11JCTL_DMASIGBPS_S   26U

§ HOST_DMA_CH11JCTL_FIFOMODS

#define HOST_DMA_CH11JCTL_FIFOMODS   0x08000000U

§ HOST_DMA_CH11JCTL_FIFOMODS_M

#define HOST_DMA_CH11JCTL_FIFOMODS_M   0x08000000U

§ HOST_DMA_CH11JCTL_FIFOMODS_S

#define HOST_DMA_CH11JCTL_FIFOMODS_S   27U

§ HOST_DMA_CH11JCTL_FIFOMODD

#define HOST_DMA_CH11JCTL_FIFOMODD   0x10000000U

§ HOST_DMA_CH11JCTL_FIFOMODD_M

#define HOST_DMA_CH11JCTL_FIFOMODD_M   0x10000000U

§ HOST_DMA_CH11JCTL_FIFOMODD_S

#define HOST_DMA_CH11JCTL_FIFOMODD_S   28U

§ HOST_DMA_CH11JCTL_SRCDSTCFG

#define HOST_DMA_CH11JCTL_SRCDSTCFG   0x20000000U

§ HOST_DMA_CH11JCTL_SRCDSTCFG_M

#define HOST_DMA_CH11JCTL_SRCDSTCFG_M   0x20000000U

§ HOST_DMA_CH11JCTL_SRCDSTCFG_S

#define HOST_DMA_CH11JCTL_SRCDSTCFG_S   29U

§ HOST_DMA_CH11JCTL_ENCLR

#define HOST_DMA_CH11JCTL_ENCLR   0x40000000U

§ HOST_DMA_CH11JCTL_ENCLR_M

#define HOST_DMA_CH11JCTL_ENCLR_M   0x40000000U

§ HOST_DMA_CH11JCTL_ENCLR_S

#define HOST_DMA_CH11JCTL_ENCLR_S   30U

§ HOST_DMA_CH12STA_HWEVENT_W

#define HOST_DMA_CH12STA_HWEVENT_W   3U

§ HOST_DMA_CH12STA_HWEVENT_M

#define HOST_DMA_CH12STA_HWEVENT_M   0x00000007U

§ HOST_DMA_CH12STA_HWEVENT_S

#define HOST_DMA_CH12STA_HWEVENT_S   0U

§ HOST_DMA_CH12STA_FSMSTATE_W

#define HOST_DMA_CH12STA_FSMSTATE_W   4U

§ HOST_DMA_CH12STA_FSMSTATE_M

#define HOST_DMA_CH12STA_FSMSTATE_M   0x00000F00U

§ HOST_DMA_CH12STA_FSMSTATE_S

#define HOST_DMA_CH12STA_FSMSTATE_S   8U

§ HOST_DMA_CH12STA_RUN

#define HOST_DMA_CH12STA_RUN   0x00010000U

§ HOST_DMA_CH12STA_RUN_M

#define HOST_DMA_CH12STA_RUN_M   0x00010000U

§ HOST_DMA_CH12STA_RUN_S

#define HOST_DMA_CH12STA_RUN_S   16U

§ HOST_DMA_CH12TIPTR_IPTR_W

#define HOST_DMA_CH12TIPTR_IPTR_W   32U

§ HOST_DMA_CH12TIPTR_IPTR_M

#define HOST_DMA_CH12TIPTR_IPTR_M   0xFFFFFFFFU

§ HOST_DMA_CH12TIPTR_IPTR_S

#define HOST_DMA_CH12TIPTR_IPTR_S   0U

§ HOST_DMA_CH12TOPTR_OPTR_W

#define HOST_DMA_CH12TOPTR_OPTR_W   32U

§ HOST_DMA_CH12TOPTR_OPTR_M

#define HOST_DMA_CH12TOPTR_OPTR_M   0xFFFFFFFFU

§ HOST_DMA_CH12TOPTR_OPTR_S

#define HOST_DMA_CH12TOPTR_OPTR_S   0U

§ HOST_DMA_CH12TCTL_TRANSB_W

#define HOST_DMA_CH12TCTL_TRANSB_W   14U

§ HOST_DMA_CH12TCTL_TRANSB_M

#define HOST_DMA_CH12TCTL_TRANSB_M   0x00003FFFU

§ HOST_DMA_CH12TCTL_TRANSB_S

#define HOST_DMA_CH12TCTL_TRANSB_S   0U

§ HOST_DMA_CH12TCTL_BURSTREQ

#define HOST_DMA_CH12TCTL_BURSTREQ   0x00010000U

§ HOST_DMA_CH12TCTL_BURSTREQ_M

#define HOST_DMA_CH12TCTL_BURSTREQ_M   0x00010000U

§ HOST_DMA_CH12TCTL_BURSTREQ_S

#define HOST_DMA_CH12TCTL_BURSTREQ_S   16U

§ HOST_DMA_CH12TCTL_SPARE

#define HOST_DMA_CH12TCTL_SPARE   0x00020000U

§ HOST_DMA_CH12TCTL_SPARE_M

#define HOST_DMA_CH12TCTL_SPARE_M   0x00020000U

§ HOST_DMA_CH12TCTL_SPARE_S

#define HOST_DMA_CH12TCTL_SPARE_S   17U

§ HOST_DMA_CH12TCTL_ENDIANESS_W

#define HOST_DMA_CH12TCTL_ENDIANESS_W   2U

§ HOST_DMA_CH12TCTL_ENDIANESS_M

#define HOST_DMA_CH12TCTL_ENDIANESS_M   0x03000000U

§ HOST_DMA_CH12TCTL_ENDIANESS_S

#define HOST_DMA_CH12TCTL_ENDIANESS_S   24U

§ HOST_DMA_CH12TCTL2_CMD_W

#define HOST_DMA_CH12TCTL2_CMD_W   3U

§ HOST_DMA_CH12TCTL2_CMD_M

#define HOST_DMA_CH12TCTL2_CMD_M   0x00000007U

§ HOST_DMA_CH12TCTL2_CMD_S

#define HOST_DMA_CH12TCTL2_CMD_S   0U

§ HOST_DMA_CH12TSTA_STA

#define HOST_DMA_CH12TSTA_STA   0x00000001U

§ HOST_DMA_CH12TSTA_STA_M

#define HOST_DMA_CH12TSTA_STA_M   0x00000001U

§ HOST_DMA_CH12TSTA_STA_S

#define HOST_DMA_CH12TSTA_STA_S   0U

§ HOST_DMA_CH12TSTA_OFFSET_W

#define HOST_DMA_CH12TSTA_OFFSET_W   8U

§ HOST_DMA_CH12TSTA_OFFSET_M

#define HOST_DMA_CH12TSTA_OFFSET_M   0x0000FF00U

§ HOST_DMA_CH12TSTA_OFFSET_S

#define HOST_DMA_CH12TSTA_OFFSET_S   8U

§ HOST_DMA_CH12TSTA_REMAINB_W

#define HOST_DMA_CH12TSTA_REMAINB_W   14U

§ HOST_DMA_CH12TSTA_REMAINB_M

#define HOST_DMA_CH12TSTA_REMAINB_M   0x3FFF0000U

§ HOST_DMA_CH12TSTA_REMAINB_S

#define HOST_DMA_CH12TSTA_REMAINB_S   16U

§ HOST_DMA_CH12JCTL_WORDSIZE_W

#define HOST_DMA_CH12JCTL_WORDSIZE_W   2U

§ HOST_DMA_CH12JCTL_WORDSIZE_M

#define HOST_DMA_CH12JCTL_WORDSIZE_M   0x00000003U

§ HOST_DMA_CH12JCTL_WORDSIZE_S

#define HOST_DMA_CH12JCTL_WORDSIZE_S   0U

§ HOST_DMA_CH12JCTL_BLKSIZE_W

#define HOST_DMA_CH12JCTL_BLKSIZE_W   6U

§ HOST_DMA_CH12JCTL_BLKSIZE_M

#define HOST_DMA_CH12JCTL_BLKSIZE_M   0x003F0000U

§ HOST_DMA_CH12JCTL_BLKSIZE_S

#define HOST_DMA_CH12JCTL_BLKSIZE_S   16U

§ HOST_DMA_CH12JCTL_DMASIGBPS

#define HOST_DMA_CH12JCTL_DMASIGBPS   0x04000000U

§ HOST_DMA_CH12JCTL_DMASIGBPS_M

#define HOST_DMA_CH12JCTL_DMASIGBPS_M   0x04000000U

§ HOST_DMA_CH12JCTL_DMASIGBPS_S

#define HOST_DMA_CH12JCTL_DMASIGBPS_S   26U

§ HOST_DMA_CH12JCTL_FIFOMODS

#define HOST_DMA_CH12JCTL_FIFOMODS   0x08000000U

§ HOST_DMA_CH12JCTL_FIFOMODS_M

#define HOST_DMA_CH12JCTL_FIFOMODS_M   0x08000000U

§ HOST_DMA_CH12JCTL_FIFOMODS_S

#define HOST_DMA_CH12JCTL_FIFOMODS_S   27U

§ HOST_DMA_CH12JCTL_FIFOMODD

#define HOST_DMA_CH12JCTL_FIFOMODD   0x10000000U

§ HOST_DMA_CH12JCTL_FIFOMODD_M

#define HOST_DMA_CH12JCTL_FIFOMODD_M   0x10000000U

§ HOST_DMA_CH12JCTL_FIFOMODD_S

#define HOST_DMA_CH12JCTL_FIFOMODD_S   28U

§ HOST_DMA_CH12JCTL_SRCDSTCFG

#define HOST_DMA_CH12JCTL_SRCDSTCFG   0x20000000U

§ HOST_DMA_CH12JCTL_SRCDSTCFG_M

#define HOST_DMA_CH12JCTL_SRCDSTCFG_M   0x20000000U

§ HOST_DMA_CH12JCTL_SRCDSTCFG_S

#define HOST_DMA_CH12JCTL_SRCDSTCFG_S   29U

§ HOST_DMA_CH12JCTL_ENCLR

#define HOST_DMA_CH12JCTL_ENCLR   0x40000000U

§ HOST_DMA_CH12JCTL_ENCLR_M

#define HOST_DMA_CH12JCTL_ENCLR_M   0x40000000U

§ HOST_DMA_CH12JCTL_ENCLR_S

#define HOST_DMA_CH12JCTL_ENCLR_S   30U

§ HOST_DMA_CH13STA_HWEVENT_W

#define HOST_DMA_CH13STA_HWEVENT_W   3U

§ HOST_DMA_CH13STA_HWEVENT_M

#define HOST_DMA_CH13STA_HWEVENT_M   0x00000007U

§ HOST_DMA_CH13STA_HWEVENT_S

#define HOST_DMA_CH13STA_HWEVENT_S   0U

§ HOST_DMA_CH13STA_FSMSTATE_W

#define HOST_DMA_CH13STA_FSMSTATE_W   4U

§ HOST_DMA_CH13STA_FSMSTATE_M

#define HOST_DMA_CH13STA_FSMSTATE_M   0x00000F00U

§ HOST_DMA_CH13STA_FSMSTATE_S

#define HOST_DMA_CH13STA_FSMSTATE_S   8U

§ HOST_DMA_CH13STA_RUN

#define HOST_DMA_CH13STA_RUN   0x00010000U

§ HOST_DMA_CH13STA_RUN_M

#define HOST_DMA_CH13STA_RUN_M   0x00010000U

§ HOST_DMA_CH13STA_RUN_S

#define HOST_DMA_CH13STA_RUN_S   16U

§ HOST_DMA_CH13TIPTR_IPTR_W

#define HOST_DMA_CH13TIPTR_IPTR_W   32U

§ HOST_DMA_CH13TIPTR_IPTR_M

#define HOST_DMA_CH13TIPTR_IPTR_M   0xFFFFFFFFU

§ HOST_DMA_CH13TIPTR_IPTR_S

#define HOST_DMA_CH13TIPTR_IPTR_S   0U

§ HOST_DMA_CH13TOPTR_OPTR_W

#define HOST_DMA_CH13TOPTR_OPTR_W   32U

§ HOST_DMA_CH13TOPTR_OPTR_M

#define HOST_DMA_CH13TOPTR_OPTR_M   0xFFFFFFFFU

§ HOST_DMA_CH13TOPTR_OPTR_S

#define HOST_DMA_CH13TOPTR_OPTR_S   0U

§ HOST_DMA_CH13TCTL_TRANSB_W

#define HOST_DMA_CH13TCTL_TRANSB_W   14U

§ HOST_DMA_CH13TCTL_TRANSB_M

#define HOST_DMA_CH13TCTL_TRANSB_M   0x00003FFFU

§ HOST_DMA_CH13TCTL_TRANSB_S

#define HOST_DMA_CH13TCTL_TRANSB_S   0U

§ HOST_DMA_CH13TCTL_BURSTREQ

#define HOST_DMA_CH13TCTL_BURSTREQ   0x00010000U

§ HOST_DMA_CH13TCTL_BURSTREQ_M

#define HOST_DMA_CH13TCTL_BURSTREQ_M   0x00010000U

§ HOST_DMA_CH13TCTL_BURSTREQ_S

#define HOST_DMA_CH13TCTL_BURSTREQ_S   16U

§ HOST_DMA_CH13TCTL_SPARE

#define HOST_DMA_CH13TCTL_SPARE   0x00020000U

§ HOST_DMA_CH13TCTL_SPARE_M

#define HOST_DMA_CH13TCTL_SPARE_M   0x00020000U

§ HOST_DMA_CH13TCTL_SPARE_S

#define HOST_DMA_CH13TCTL_SPARE_S   17U

§ HOST_DMA_CH13TCTL_ENDIANESS_W

#define HOST_DMA_CH13TCTL_ENDIANESS_W   2U

§ HOST_DMA_CH13TCTL_ENDIANESS_M

#define HOST_DMA_CH13TCTL_ENDIANESS_M   0x03000000U

§ HOST_DMA_CH13TCTL_ENDIANESS_S

#define HOST_DMA_CH13TCTL_ENDIANESS_S   24U

§ HOST_DMA_CH13TCTL2_CMD_W

#define HOST_DMA_CH13TCTL2_CMD_W   3U

§ HOST_DMA_CH13TCTL2_CMD_M

#define HOST_DMA_CH13TCTL2_CMD_M   0x00000007U

§ HOST_DMA_CH13TCTL2_CMD_S

#define HOST_DMA_CH13TCTL2_CMD_S   0U

§ HOST_DMA_CH13TSTA_STA

#define HOST_DMA_CH13TSTA_STA   0x00000001U

§ HOST_DMA_CH13TSTA_STA_M

#define HOST_DMA_CH13TSTA_STA_M   0x00000001U

§ HOST_DMA_CH13TSTA_STA_S

#define HOST_DMA_CH13TSTA_STA_S   0U

§ HOST_DMA_CH13TSTA_OFFSET_W

#define HOST_DMA_CH13TSTA_OFFSET_W   8U

§ HOST_DMA_CH13TSTA_OFFSET_M

#define HOST_DMA_CH13TSTA_OFFSET_M   0x0000FF00U

§ HOST_DMA_CH13TSTA_OFFSET_S

#define HOST_DMA_CH13TSTA_OFFSET_S   8U

§ HOST_DMA_CH13TSTA_REMAINB_W

#define HOST_DMA_CH13TSTA_REMAINB_W   14U

§ HOST_DMA_CH13TSTA_REMAINB_M

#define HOST_DMA_CH13TSTA_REMAINB_M   0x3FFF0000U

§ HOST_DMA_CH13TSTA_REMAINB_S

#define HOST_DMA_CH13TSTA_REMAINB_S   16U

§ HOST_DMA_CH13JCTL_WORDSIZE_W

#define HOST_DMA_CH13JCTL_WORDSIZE_W   2U

§ HOST_DMA_CH13JCTL_WORDSIZE_M

#define HOST_DMA_CH13JCTL_WORDSIZE_M   0x00000003U

§ HOST_DMA_CH13JCTL_WORDSIZE_S

#define HOST_DMA_CH13JCTL_WORDSIZE_S   0U

§ HOST_DMA_CH13JCTL_BLKSIZE_W

#define HOST_DMA_CH13JCTL_BLKSIZE_W   6U

§ HOST_DMA_CH13JCTL_BLKSIZE_M

#define HOST_DMA_CH13JCTL_BLKSIZE_M   0x003F0000U

§ HOST_DMA_CH13JCTL_BLKSIZE_S

#define HOST_DMA_CH13JCTL_BLKSIZE_S   16U

§ HOST_DMA_CH13JCTL_DMASIGBPS

#define HOST_DMA_CH13JCTL_DMASIGBPS   0x04000000U

§ HOST_DMA_CH13JCTL_DMASIGBPS_M

#define HOST_DMA_CH13JCTL_DMASIGBPS_M   0x04000000U

§ HOST_DMA_CH13JCTL_DMASIGBPS_S

#define HOST_DMA_CH13JCTL_DMASIGBPS_S   26U

§ HOST_DMA_CH13JCTL_FIFOMODS

#define HOST_DMA_CH13JCTL_FIFOMODS   0x08000000U

§ HOST_DMA_CH13JCTL_FIFOMODS_M

#define HOST_DMA_CH13JCTL_FIFOMODS_M   0x08000000U

§ HOST_DMA_CH13JCTL_FIFOMODS_S

#define HOST_DMA_CH13JCTL_FIFOMODS_S   27U

§ HOST_DMA_CH13JCTL_FIFOMODD

#define HOST_DMA_CH13JCTL_FIFOMODD   0x10000000U

§ HOST_DMA_CH13JCTL_FIFOMODD_M

#define HOST_DMA_CH13JCTL_FIFOMODD_M   0x10000000U

§ HOST_DMA_CH13JCTL_FIFOMODD_S

#define HOST_DMA_CH13JCTL_FIFOMODD_S   28U

§ HOST_DMA_CH13JCTL_SRCDSTCFG

#define HOST_DMA_CH13JCTL_SRCDSTCFG   0x20000000U

§ HOST_DMA_CH13JCTL_SRCDSTCFG_M

#define HOST_DMA_CH13JCTL_SRCDSTCFG_M   0x20000000U

§ HOST_DMA_CH13JCTL_SRCDSTCFG_S

#define HOST_DMA_CH13JCTL_SRCDSTCFG_S   29U

§ HOST_DMA_CH13JCTL_ENCLR

#define HOST_DMA_CH13JCTL_ENCLR   0x40000000U

§ HOST_DMA_CH13JCTL_ENCLR_M

#define HOST_DMA_CH13JCTL_ENCLR_M   0x40000000U

§ HOST_DMA_CH13JCTL_ENCLR_S

#define HOST_DMA_CH13JCTL_ENCLR_S   30U