CC35xxDriverLibrary
hw_hif.h
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1 /******************************************************************************
2 * Filename: hw_hif.h
3 *
4 * Description: Defines and prototypes for the HIF peripheral.
5 *
6 * Copyright (c) 2023-2025, Texas Instruments Incorporated
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36 #ifndef __HW_HIF_H__
37 #define __HW_HIF_H__
38 /*-------------------------------------------------------------------------------
39 
40 This section defines the register offsets of the HIF component
41 
42 --------------------------------------------------------------------------------- */
43 
44 //INTERCONNECT WRITE FIFO
45 #define HIF_O_ICWRFIFO 0x00000000U
46 
47 //INTERCONNECT READ FIFO
48 #define HIF_O_ICRDFIFO 0x00000010U
49 
50 //MODE
51 #define HIF_O_MOD 0x00000024U
52 
53 //HIF FIFO Status
54 #define HIF_O_FIFOSTA 0x0000002CU
55 
56 //UNDERFLOW
57 #define HIF_O_UNDER 0x00000030U
58 
59 //OVERFLOW
60 #define HIF_O_OVER 0x00000034U
61 
62 //RESET
63 #define HIF_O_RST 0x00000038U
64 
65 //FSM STATUS
66 #define HIF_O_FSMSTA 0x0000003CU
67 
68 //HIF FIFO Threshold Status
69 #define HIF_O_FIFOTH 0x00000040U
70 
71 //IRQ
72 #define HIF_O_IRQ 0x00000044U
73 
74 //IRQ MASK Config
75 #define HIF_O_IM 0x00000048U
76 
77 //NAB READY
78 #define HIF_O_NABRDY 0x0000004CU
79 
80 //CORE
81 #define HIF_O_CR 0x00000050U
82 
83 //RX AON
84 #define HIF_O_RXAON 0x00000054U
85 
86 //RX STATUS LATCH
87 #define HIF_O_RXSTALAT 0x00000058U
88 
89 //NAB HINT STATUS
90 #define HIF_O_NABHNTSTA 0x0000005CU
91 
92 //NAB
93 #define HIF_O_NAB 0x00000060U
94 
95 //HINT BIT MASK
96 #define HIF_O_HNTBM 0x00000064U
97 
98 //HINT BIT MASK CLEAR
99 #define HIF_O_HNTBMCLR 0x00000068U
100 
101 //HINT STATUS CLEAR
102 #define HIF_O_HNTSTACLR 0x0000006CU
103 
104 //NAB HINT
105 #define HIF_O_NABHNT 0x00000070U
106 
107 //NAB HINT CLEAR
108 #define HIF_O_NABHNTCLR 0x00000074U
109 
110 
111 
112 /*-----------------------------------REGISTER------------------------------------
113  Register name: ICWRFIFO
114  Offset name: HIF_O_ICWRFIFO
115  Relative address: 0x0
116  Description: INTERCONNECT WRITE FIFO
117 
118  Host interface FIFO
119  Default Value: NA
120 
121  Field: WORD
122  From..to bits: 0...31
123  DefaultValue: NA
124  Access type: write-only
125  Description: WORD
126 
127  write opt
128 
129  IC to NAB write word
130 
131 */
132 #define HIF_ICWRFIFO_WORD_W 32U
133 #define HIF_ICWRFIFO_WORD_M 0xFFFFFFFFU
134 #define HIF_ICWRFIFO_WORD_S 0U
135 
136 
137 /*-----------------------------------REGISTER------------------------------------
138  Register name: ICRDFIFO
139  Offset name: HIF_O_ICRDFIFO
140  Relative address: 0x10
141  Description: INTERCONNECT READ FIFO
142 
143  Host interface FIFO
144  Default Value: 0xEEEEEEEE
145 
146  Field: WORD
147  From..to bits: 0...31
148  DefaultValue: 0xEEEEEEEE
149  Access type: read-only
150  Description: WORD
151 
152  read clear
153 
154  NAB to IC read word
155 
156 */
157 #define HIF_ICRDFIFO_WORD_W 32U
158 #define HIF_ICRDFIFO_WORD_M 0xFFFFFFFFU
159 #define HIF_ICRDFIFO_WORD_S 0U
160 
161 
162 /*-----------------------------------REGISTER------------------------------------
163  Register name: MOD
164  Offset name: HIF_O_MOD
165  Relative address: 0x24
166  Description: MODE
167 
168  HIF Mode Configuration
169  Default Value: NA
170 
171  Field: CFG
172  From..to bits: 0...1
173  DefaultValue: NA
174  Access type: read-write
175  Description: CONFIG
176 
177  "00" - Direct Access WR
178  "01" - DMA WR
179  "10" - Direct Access RD
180  "11" - DMA RD
181 
182 */
183 #define HIF_MOD_CFG_W 2U
184 #define HIF_MOD_CFG_M 0x00000003U
185 #define HIF_MOD_CFG_S 0U
186 
187 
188 /*-----------------------------------REGISTER------------------------------------
189  Register name: FIFOSTA
190  Offset name: HIF_O_FIFOSTA
191  Relative address: 0x2C
192  Description: HIF FIFO Status
193  Default Value: 0x00000001
194 
195  Field: RDPTR
196  From..to bits: 0...4
197  DefaultValue: 0x1
198  Access type: read-only
199  Description: READ POINTER
200 
201 */
202 #define HIF_FIFOSTA_RDPTR_W 5U
203 #define HIF_FIFOSTA_RDPTR_M 0x0000001FU
204 #define HIF_FIFOSTA_RDPTR_S 0U
205 /*
206 
207  Field: WRPTR
208  From..to bits: 8...12
209  DefaultValue: 0x0
210  Access type: read-only
211  Description: WRITE POINTER
212 
213 */
214 #define HIF_FIFOSTA_WRPTR_W 5U
215 #define HIF_FIFOSTA_WRPTR_M 0x00001F00U
216 #define HIF_FIFOSTA_WRPTR_S 8U
217 /*
218 
219  Field: EMP
220  From..to bits: 20...20
221  DefaultValue: 0x0
222  Access type: read-only
223  Description: EMPTY
224 
225 */
226 #define HIF_FIFOSTA_EMP 0x00100000U
227 #define HIF_FIFOSTA_EMP_M 0x00100000U
228 #define HIF_FIFOSTA_EMP_S 20U
229 /*
230 
231  Field: FULL
232  From..to bits: 21...21
233  DefaultValue: 0x0
234  Access type: read-only
235  Description: FULL
236 
237 */
238 #define HIF_FIFOSTA_FULL 0x00200000U
239 #define HIF_FIFOSTA_FULL_M 0x00200000U
240 #define HIF_FIFOSTA_FULL_S 21U
241 
242 
243 /*-----------------------------------REGISTER------------------------------------
244  Register name: UNDER
245  Offset name: HIF_O_UNDER
246  Relative address: 0x30
247  Description: UNDERFLOW
248 
249  clear on read.
250  H/W latch underflow and s/w clears it by reading.
251  Default Value: NA
252 
253  Field: STA
254  From..to bits: 0...0
255  DefaultValue: NA
256  Access type: read-only
257  Description: STATUS
258 
259  read clear
260 
261  FIFO Underflow - RD when FIFO is empty.
262 
263 */
264 #define HIF_UNDER_STA 0x00000001U
265 #define HIF_UNDER_STA_M 0x00000001U
266 #define HIF_UNDER_STA_S 0U
267 
268 
269 /*-----------------------------------REGISTER------------------------------------
270  Register name: OVER
271  Offset name: HIF_O_OVER
272  Relative address: 0x34
273  Description: OVERFLOW
274 
275  clear on read.
276  H/W latch overflow and s/w clears it by reading.
277  Default Value: NA
278 
279  Field: STA
280  From..to bits: 0...0
281  DefaultValue: NA
282  Access type: read-only
283  Description: STATUS
284 
285  read clear
286 
287  FIFO Overflow - WR when FIFO is full.
288 
289 */
290 #define HIF_OVER_STA 0x00000001U
291 #define HIF_OVER_STA_M 0x00000001U
292 #define HIF_OVER_STA_S 0U
293 
294 
295 /*-----------------------------------REGISTER------------------------------------
296  Register name: RST
297  Offset name: HIF_O_RST
298  Relative address: 0x38
299  Description: RESET
300 
301  HIF FIFO set RESET
302  Default Value: NA
303 
304  Field: FIFO
305  From..to bits: 0...0
306  DefaultValue: NA
307  Access type: write-only
308  Description: FIFO
309 
310  write clear
311 
312  Setting this bit clears the FIFO Controls.
313 
314 */
315 #define HIF_RST_FIFO 0x00000001U
316 #define HIF_RST_FIFO_M 0x00000001U
317 #define HIF_RST_FIFO_S 0U
318 
319 
320 /*-----------------------------------REGISTER------------------------------------
321  Register name: FSMSTA
322  Offset name: HIF_O_FSMSTA
323  Relative address: 0x3C
324  Description: FSM STATUS
325  Default Value: NA
326 
327  Field: HANDLER
328  From..to bits: 0...2
329  DefaultValue: NA
330  Access type: read-only
331  Description: HANDLER
332 
333  IDLE = 3'b000
334  DMA_BL_WR = 3'b101
335  DMA_HOLD_WR = 3'b110
336  DIRECT_ACCESS_WR = 3'b111
337  NAB_WR = 3'b001
338  DMA_BL_RD = 3'b010
339  DIRECT_ACCESS_RD = 3'b011 ;
340 
341 */
342 #define HIF_FSMSTA_HANDLER_W 3U
343 #define HIF_FSMSTA_HANDLER_M 0x00000007U
344 #define HIF_FSMSTA_HANDLER_S 0U
345 /*
346 
347  Field: WRNAB
348  From..to bits: 8...10
349  DefaultValue: NA
350  Access type: read-only
351  Description: WRITE NAB
352 
353 */
354 #define HIF_FSMSTA_WRNAB_W 3U
355 #define HIF_FSMSTA_WRNAB_M 0x00000700U
356 #define HIF_FSMSTA_WRNAB_S 8U
357 /*
358 
359  Field: RDNAB
360  From..to bits: 16...18
361  DefaultValue: NA
362  Access type: read-only
363  Description: READ NAB
364 
365 */
366 #define HIF_FSMSTA_RDNAB_W 3U
367 #define HIF_FSMSTA_RDNAB_M 0x00070000U
368 #define HIF_FSMSTA_RDNAB_S 16U
369 
370 
371 /*-----------------------------------REGISTER------------------------------------
372  Register name: FIFOTH
373  Offset name: HIF_O_FIFOTH
374  Relative address: 0x40
375  Description: HIF FIFO Threshold Status
376  Default Value: 0x0000000F
377 
378  Field: THR
379  From..to bits: 0...3
380  DefaultValue: 0xF
381  Access type: read-write
382  Description: THRESHOLD
383 
384  Sets the HIF threshold:
385  for TX (DMA to NAB)-
386  0 - if there is room for 1 word the req to DMA will be send
387  ...
388  15 - if there is room for 16 words the req to DMA will be send
389 
390  for RX (NAB to DMA)-
391  0 - if FIFO is occupied by at lest 1 word, the req to DMA will be send
392  ...
393  15 - if FIFO is occupied by at lest 16 word, the req to DMA will be send
394 
395 */
396 #define HIF_FIFOTH_THR_W 4U
397 #define HIF_FIFOTH_THR_M 0x0000000FU
398 #define HIF_FIFOTH_THR_S 0U
399 /*
400 
401  Field: WRTHRNTHIT
402  From..to bits: 8...8
403  DefaultValue: 0x0
404  Access type: read-only
405  Description: WRITE THRESHOLD NOT HIT
406 
407  indication if the write threshold not hit
408 
409 */
410 #define HIF_FIFOTH_WRTHRNTHIT 0x00000100U
411 #define HIF_FIFOTH_WRTHRNTHIT_M 0x00000100U
412 #define HIF_FIFOTH_WRTHRNTHIT_S 8U
413 /*
414 
415  Field: RDTHRHIT
416  From..to bits: 9...9
417  DefaultValue: 0x0
418  Access type: read-only
419  Description: READ THRESHOLD HIT
420 
421  indication if the read threshold hit
422 
423 */
424 #define HIF_FIFOTH_RDTHRHIT 0x00000200U
425 #define HIF_FIFOTH_RDTHRHIT_M 0x00000200U
426 #define HIF_FIFOTH_RDTHRHIT_S 9U
427 /*
428 
429  Field: SZAVAIL
430  From..to bits: 16...20
431  DefaultValue: 0x0
432  Access type: read-only
433  Description: SIZE AVAILABLE
434 
435  indication of free space left at FIFO
436  0 - FIFO full
437  1 - 1 word can be written
438  ...
439  16 - 16 words can be written
440 
441 */
442 #define HIF_FIFOTH_SZAVAIL_W 5U
443 #define HIF_FIFOTH_SZAVAIL_M 0x001F0000U
444 #define HIF_FIFOTH_SZAVAIL_S 16U
445 /*
446 
447  Field: SZOCC
448  From..to bits: 24...28
449  DefaultValue: 0x0
450  Access type: read-only
451  Description: SIZE OCCUPIED
452 
453  indication of how many words have been written to FIFO
454  0 - nothing was written
455  1 - 1 word have been written
456  ...
457  16 - 16 words have been written
458 
459 */
460 #define HIF_FIFOTH_SZOCC_W 5U
461 #define HIF_FIFOTH_SZOCC_M 0x1F000000U
462 #define HIF_FIFOTH_SZOCC_S 24U
463 
464 
465 /*-----------------------------------REGISTER------------------------------------
466  Register name: IRQ
467  Offset name: HIF_O_IRQ
468  Relative address: 0x44
469  Description: IRQ
470  Default Value: 0x00000001
471 
472  Field: RIS
473  From..to bits: 0...5
474  DefaultValue: 0x1
475  Access type: read-only
476  Description: RIS
477 
478  read clear
479 
480  bit[0] - empty
481  bit[1] - full
482  bit[2] - underflow
483  bit[3] - overflow
484  bit[4] - not empty with direct access read
485  bit[5] - nab data receive done
486 
487 */
488 #define HIF_IRQ_RIS_W 6U
489 #define HIF_IRQ_RIS_M 0x0000003FU
490 #define HIF_IRQ_RIS_S 0U
491 
492 
493 /*-----------------------------------REGISTER------------------------------------
494  Register name: IM
495  Offset name: HIF_O_IM
496  Relative address: 0x48
497  Description: IRQ MASK Config
498  Default Value: 0x0000003F
499 
500  Field: EVTBM
501  From..to bits: 0...5
502  DefaultValue: 0x3F
503  Access type: read-write
504  Description: EVENT BIT MASK
505 
506  '1' - Mask
507  '0' - Do Not Mask
508 
509  bit[0] - empty
510  bit[1] - full
511  bit[2] - underflow
512  bit[3] - overflow
513  bit[4] - not empty with direct access read
514  bit[5] - nab data receive done
515 
516 */
517 #define HIF_IM_EVTBM_W 6U
518 #define HIF_IM_EVTBM_M 0x0000003FU
519 #define HIF_IM_EVTBM_S 0U
520 /*
521 
522  Field: STA
523  From..to bits: 6...11
524  DefaultValue: 0x0
525  Access type: read-only
526  Description: STATUS
527 
528  bit[0] - empty
529  bit[1] - full
530  bit[2] - underflow
531  bit[3] - overflow
532  bit[4] - not empty with direct access read
533  bit[5] - nab data receive done
534 
535 */
536 #define HIF_IM_STA_W 6U
537 #define HIF_IM_STA_M 0x00000FC0U
538 #define HIF_IM_STA_S 6U
539 
540 
541 /*-----------------------------------REGISTER------------------------------------
542  Register name: NABRDY
543  Offset name: HIF_O_NABRDY
544  Relative address: 0x4C
545  Description: NAB READY
546 
547  HIF Mode Configuration
548  Default Value: NA
549 
550  Field: TORCV
551  From..to bits: 0...0
552  DefaultValue: NA
553  Access type: read-only
554  Description: TO RECEIVE
555 
556  indication when NAB is ready to receive data
557 
558 */
559 #define HIF_NABRDY_TORCV 0x00000001U
560 #define HIF_NABRDY_TORCV_M 0x00000001U
561 #define HIF_NABRDY_TORCV_S 0U
562 /*
563 
564  Field: RCVDONE
565  From..to bits: 1...1
566  DefaultValue: NA
567  Access type: read-only
568  Description: RECEIVE DONE
569 
570  indication when NAB data recieve done
571 
572 */
573 #define HIF_NABRDY_RCVDONE 0x00000002U
574 #define HIF_NABRDY_RCVDONE_M 0x00000002U
575 #define HIF_NABRDY_RCVDONE_S 1U
576 /*
577 
578  Field: RCVDONEM2MIDL
579  From..to bits: 2...2
580  DefaultValue: NA
581  Access type: read-only
582  Description: RECEIVE DONE AND M2M IDLE
583 
584  indication when NAB data recieve done and M2M FSM IDLE
585 
586 */
587 #define HIF_NABRDY_RCVDONEM2MIDL 0x00000004U
588 #define HIF_NABRDY_RCVDONEM2MIDL_M 0x00000004U
589 #define HIF_NABRDY_RCVDONEM2MIDL_S 2U
590 /*
591 
592  Field: FIFONEMPT
593  From..to bits: 3...3
594  DefaultValue: NA
595  Access type: read-only
596  Description: NAB HOST FIFO NOT EMPTY
597 
598  indication when NAB FIFO not empty
599 
600 */
601 #define HIF_NABRDY_FIFONEMPT 0x00000008U
602 #define HIF_NABRDY_FIFONEMPT_M 0x00000008U
603 #define HIF_NABRDY_FIFONEMPT_S 3U
604 
605 
606 /*-----------------------------------REGISTER------------------------------------
607  Register name: CR
608  Offset name: HIF_O_CR
609  Relative address: 0x50
610  Description: CORE
611 
612  HIF Mode Configuration
613  Default Value: NA
614 
615  Field: TMSTMP
616  From..to bits: 0...31
617  DefaultValue: NA
618  Access type: read-only
619  Description: TIMESTAMP
620 
621 */
622 #define HIF_CR_TMSTMP_W 32U
623 #define HIF_CR_TMSTMP_M 0xFFFFFFFFU
624 #define HIF_CR_TMSTMP_S 0U
625 
626 
627 /*-----------------------------------REGISTER------------------------------------
628  Register name: RXAON
629  Offset name: HIF_O_RXAON
630  Relative address: 0x54
631  Description: RX AON
632  Default Value: 0x00000000
633 
634  Field: STA
635  From..to bits: 0...31
636  DefaultValue: 0x0
637  Access type: read-only
638  Description: STATUS
639 
640  read clear
641 
642 
643  This is not a regular clear-on-read register.
644  A fresh status value from Rx sub system is being latch upon reading the register.
645  The objective is for the device to have the last value the host has read
646 
647 */
648 #define HIF_RXAON_STA_W 32U
649 #define HIF_RXAON_STA_M 0xFFFFFFFFU
650 #define HIF_RXAON_STA_S 0U
651 
652 
653 /*-----------------------------------REGISTER------------------------------------
654  Register name: RXSTALAT
655  Offset name: HIF_O_RXSTALAT
656  Relative address: 0x58
657  Description: RX STATUS LATCH
658  Default Value: 0x00000000
659 
660  Field: VAL
661  From..to bits: 0...31
662  DefaultValue: 0x0
663  Access type: read-only
664  Description: VALUE
665 
666  Reflects the Rx status word current value (dynamic Read).
667  and automatically latch the value in RX_STATUS_LATCH_LATCHED.
668 
669  Usage: SDIO Wrapper reads this location and send the read value toward the host.
670 
671  For bit field description refer to RX_STATUS_LATCH.
672 
673  This register is valid only in BSD_BYPASS=1 (Osprey).
674 
675 */
676 #define HIF_RXSTALAT_VAL_W 32U
677 #define HIF_RXSTALAT_VAL_M 0xFFFFFFFFU
678 #define HIF_RXSTALAT_VAL_S 0U
679 
680 
681 /*-----------------------------------REGISTER------------------------------------
682  Register name: NABHNTSTA
683  Offset name: HIF_O_NABHNTSTA
684  Relative address: 0x5C
685  Description: NAB HINT STATUS
686  Default Value: NA
687 
688  Field: BMVAL
689  From..to bits: 0...31
690  DefaultValue: NA
691  Access type: read-only
692  Description: BIT MASK VALUE
693 
694  Host interrupt status read register. non-intrusive read. Post mask (masked).
695 
696 */
697 #define HIF_NABHNTSTA_BMVAL_W 32U
698 #define HIF_NABHNTSTA_BMVAL_M 0xFFFFFFFFU
699 #define HIF_NABHNTSTA_BMVAL_S 0U
700 
701 
702 /*-----------------------------------REGISTER------------------------------------
703  Register name: NAB
704  Offset name: HIF_O_NAB
705  Relative address: 0x60
706  Description: NAB
707  Default Value: NA
708 
709  Field: BMVAL
710  From..to bits: 0...31
711  DefaultValue: NA
712  Access type: read-only
713  Description: BIT MASK VALUE
714 
715  Read mask bitmap.
716 
717  Mask bit legend:
718  '0' - do not mask the interrupt.
719  '1' - Mask the related interrupt.
720 
721 */
722 #define HIF_NAB_BMVAL_W 32U
723 #define HIF_NAB_BMVAL_M 0xFFFFFFFFU
724 #define HIF_NAB_BMVAL_S 0U
725 
726 
727 /*-----------------------------------REGISTER------------------------------------
728  Register name: HNTBM
729  Offset name: HIF_O_HNTBM
730  Relative address: 0x64
731  Description: HINT BIT MASK
732  Default Value: NA
733 
734  Field: VAL
735  From..to bits: 0...31
736  DefaultValue: NA
737  Access type: write-only
738  Description: VALUE
739 
740  write clear
741 
742  Host interrupt mask register set
743  Writing to this register will set to '1' the related interrupt mask bit.
744 
745  Mask bit legend:
746  '0' - do not mask the interrupt.
747  '1' - Mask the related interrupt.
748 
749 */
750 #define HIF_HNTBM_VAL_W 32U
751 #define HIF_HNTBM_VAL_M 0xFFFFFFFFU
752 #define HIF_HNTBM_VAL_S 0U
753 
754 
755 /*-----------------------------------REGISTER------------------------------------
756  Register name: HNTBMCLR
757  Offset name: HIF_O_HNTBMCLR
758  Relative address: 0x68
759  Description: HINT BIT MASK CLEAR
760  Default Value: NA
761 
762  Field: VAL
763  From..to bits: 0...31
764  DefaultValue: NA
765  Access type: write-only
766  Description: VALUE
767 
768  write clear
769 
770  Host interrupt mask register clear
771  Writing to this register will clear the related interrupt mask bit.
772 
773  Mask bit legend:
774  '0' - do not mask the interrupt.
775  '1' - Mask the related interrupt.
776 
777 */
778 #define HIF_HNTBMCLR_VAL_W 32U
779 #define HIF_HNTBMCLR_VAL_M 0xFFFFFFFFU
780 #define HIF_HNTBMCLR_VAL_S 0U
781 
782 
783 /*-----------------------------------REGISTER------------------------------------
784  Register name: HNTSTACLR
785  Offset name: HIF_O_HNTSTACLR
786  Relative address: 0x6C
787  Description: HINT STATUS CLEAR
788  Default Value: NA
789 
790  Field: STA
791  From..to bits: 0...31
792  DefaultValue: NA
793  Access type: read-only
794  Description: STATUS
795 
796  read clear
797 
798  Host interrupt status clear-on-read register
799  Clears all bits of upon read.
800  Usage: host reads the IRQ register which is automatically getting cleared by H/W
801  Osprey Note: The endianness correction and word-size correction are done in SDIO(WSPI) H/W.
802 
803 */
804 #define HIF_HNTSTACLR_STA_W 32U
805 #define HIF_HNTSTACLR_STA_M 0xFFFFFFFFU
806 #define HIF_HNTSTACLR_STA_S 0U
807 
808 
809 /*-----------------------------------REGISTER------------------------------------
810  Register name: NABHNT
811  Offset name: HIF_O_NABHNT
812  Relative address: 0x70
813  Description: NAB HINT
814  Default Value: NA
815 
816  Field: SET
817  From..to bits: 0...31
818  DefaultValue: NA
819  Access type: write-only
820  Description: SET
821 
822  write clear register
823 
824  Host interrupt set register
825 
826 */
827 #define HIF_NABHNT_SET_W 32U
828 #define HIF_NABHNT_SET_M 0xFFFFFFFFU
829 #define HIF_NABHNT_SET_S 0U
830 
831 
832 /*-----------------------------------REGISTER------------------------------------
833  Register name: NABHNTCLR
834  Offset name: HIF_O_NABHNTCLR
835  Relative address: 0x74
836  Description: NAB HINT CLEAR
837  Default Value: NA
838 
839  Field: SET
840  From..to bits: 0...31
841  DefaultValue: NA
842  Access type: write-only
843  Description: SET
844 
845  write clear register
846 
847  Host interrupt clear register
848 
849 
850 */
851 #define HIF_NABHNTCLR_SET_W 32U
852 #define HIF_NABHNTCLR_SET_M 0xFFFFFFFFU
853 #define HIF_NABHNTCLR_SET_S 0U
854 
855 #endif /* __HW_HIF_H__*/