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CC35xxDriverLibrary
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Go to the source code of this file.
| #define GPTIMER_O_DESC 0x00000000U |
| #define GPTIMER_O_DESCEX 0x00000004U |
| #define GPTIMER_O_STARTCFG 0x00000008U |
| #define GPTIMER_O_CTL 0x0000000CU |
| #define GPTIMER_O_OUTCTL 0x00000010U |
| #define GPTIMER_O_CNTR 0x00000014U |
| #define GPTIMER_O_PRECFG 0x00000018U |
| #define GPTIMER_O_PREEVENT 0x0000001CU |
| #define GPTIMER_O_CHFILT 0x00000020U |
| #define GPTIMER_O_FAULT 0x00000024U |
| #define GPTIMER_O_PARK 0x00000028U |
| #define GPTIMER_O_DBDLY 0x0000002CU |
| #define GPTIMER_O_DBCTL 0x00000030U |
| #define GPTIMER_O_QDECSTAT 0x00000034U |
| #define GPTIMER_O_IRGEN 0x00000038U |
| #define GPTIMER_O_DMA 0x0000003CU |
| #define GPTIMER_O_DMARW 0x00000040U |
| #define GPTIMER_O_ADCTRG 0x00000044U |
| #define GPTIMER_O_IOCTL 0x00000048U |
| #define GPTIMER_O_IMASK 0x00000068U |
| #define GPTIMER_O_RIS 0x0000006CU |
| #define GPTIMER_O_MIS 0x00000070U |
| #define GPTIMER_O_ISET 0x00000074U |
| #define GPTIMER_O_ICLR 0x00000078U |
| #define GPTIMER_O_IMSET 0x0000007CU |
| #define GPTIMER_O_IMCLR 0x00000080U |
| #define GPTIMER_O_EMU 0x00000084U |
| #define GPTIMER_O_C0CFG 0x000000C0U |
| #define GPTIMER_O_C1CFG 0x000000C4U |
| #define GPTIMER_O_C2CFG 0x000000C8U |
| #define GPTIMER_O_C3CFG 0x000000CCU |
| #define GPTIMER_O_PTGT 0x000000FCU |
| #define GPTIMER_O_PC0CC 0x00000100U |
| #define GPTIMER_O_PC1CC 0x00000104U |
| #define GPTIMER_O_PC2CC 0x00000108U |
| #define GPTIMER_O_PC3CC 0x0000010CU |
| #define GPTIMER_O_TGT 0x0000013CU |
| #define GPTIMER_O_C0CC 0x00000140U |
| #define GPTIMER_O_C1CC 0x00000144U |
| #define GPTIMER_O_C2CC 0x00000148U |
| #define GPTIMER_O_C3CC 0x0000014CU |
| #define GPTIMER_O_PTGTNC 0x0000017CU |
| #define GPTIMER_O_PC0CCNC 0x00000180U |
| #define GPTIMER_O_PC1CCNC 0x00000184U |
| #define GPTIMER_O_PC2CCNC 0x00000188U |
| #define GPTIMER_O_PC3CCNC 0x0000018CU |
| #define GPTIMER_O_TGTNC 0x000001BCU |
| #define GPTIMER_O_C0CCNC 0x000001C0U |
| #define GPTIMER_O_C1CCNC 0x000001C4U |
| #define GPTIMER_O_C2CCNC 0x000001C8U |
| #define GPTIMER_O_C3CCNC 0x000001CCU |
| #define GPTIMER_O_CLKCFG 0x00001000U |
| #define GPTIMER_DESC_MINREV_W 4U |
| #define GPTIMER_DESC_MINREV_M 0x0000000FU |
| #define GPTIMER_DESC_MINREV_S 0U |
| #define GPTIMER_DESC_MAJREV_W 4U |
| #define GPTIMER_DESC_MAJREV_M 0x000000F0U |
| #define GPTIMER_DESC_MAJREV_S 4U |
| #define GPTIMER_DESC_INSTIDX_W 4U |
| #define GPTIMER_DESC_INSTIDX_M 0x00000F00U |
| #define GPTIMER_DESC_INSTIDX_S 8U |
| #define GPTIMER_DESC_STDIPOFF_W 4U |
| #define GPTIMER_DESC_STDIPOFF_M 0x0000F000U |
| #define GPTIMER_DESC_STDIPOFF_S 12U |
| #define GPTIMER_DESC_MODID_W 16U |
| #define GPTIMER_DESC_MODID_M 0xFFFF0000U |
| #define GPTIMER_DESC_MODID_S 16U |
| #define GPTIMER_DESCEX_NCH_W 4U |
| #define GPTIMER_DESCEX_NCH_M 0x0000000FU |
| #define GPTIMER_DESCEX_NCH_S 0U |
| #define GPTIMER_DESCEX_CNTRW_W 2U |
| #define GPTIMER_DESCEX_CNTRW_M 0x00000030U |
| #define GPTIMER_DESCEX_CNTRW_S 4U |
| #define GPTIMER_DESCEX_CNTRW_CNTR16 0x00000000U |
| #define GPTIMER_DESCEX_CNTRW_CNTR24 0x00000010U |
| #define GPTIMER_DESCEX_CNTRW_CNTR32 0x00000020U |
| #define GPTIMER_DESCEX_CNTRW_RESERVED 0x00000030U |
| #define GPTIMER_DESCEX_HINT 0x00000040U |
| #define GPTIMER_DESCEX_HINT_M 0x00000040U |
| #define GPTIMER_DESCEX_HINT_S 6U |
| #define GPTIMER_DESCEX_HDMA 0x00000080U |
| #define GPTIMER_DESCEX_HDMA_M 0x00000080U |
| #define GPTIMER_DESCEX_HDMA_S 7U |
| #define GPTIMER_DESCEX_CIFS_W 4U |
| #define GPTIMER_DESCEX_CIFS_M 0x00000F00U |
| #define GPTIMER_DESCEX_CIFS_S 8U |
| #define GPTIMER_DESCEX_HCIF 0x00001000U |
| #define GPTIMER_DESCEX_HCIF_M 0x00001000U |
| #define GPTIMER_DESCEX_HCIF_S 12U |
| #define GPTIMER_DESCEX_HQDEC 0x00002000U |
| #define GPTIMER_DESCEX_HQDEC_M 0x00002000U |
| #define GPTIMER_DESCEX_HQDEC_S 13U |
| #define GPTIMER_DESCEX_PREW_W 4U |
| #define GPTIMER_DESCEX_PREW_M 0x0003C000U |
| #define GPTIMER_DESCEX_PREW_S 14U |
| #define GPTIMER_DESCEX_HDBF 0x00040000U |
| #define GPTIMER_DESCEX_HDBF_M 0x00040000U |
| #define GPTIMER_DESCEX_HDBF_S 18U |
| #define GPTIMER_DESCEX_HIR 0x00080000U |
| #define GPTIMER_DESCEX_HIR_M 0x00080000U |
| #define GPTIMER_DESCEX_HIR_S 19U |
| #define GPTIMER_STARTCFG_LGPT0_W 2U |
| #define GPTIMER_STARTCFG_LGPT0_M 0x00000003U |
| #define GPTIMER_STARTCFG_LGPT0_S 0U |
| #define GPTIMER_STARTCFG_LGPT0_EV_SYNC 0x00000000U |
| #define GPTIMER_CTL_MODE_W 3U |
| #define GPTIMER_CTL_MODE_M 0x00000007U |
| #define GPTIMER_CTL_MODE_S 0U |
| #define GPTIMER_CTL_MODE_DIS 0x00000000U |
| #define GPTIMER_CTL_MODE_UP_ONCE 0x00000001U |
| #define GPTIMER_CTL_MODE_UP_PER 0x00000002U |
| #define GPTIMER_CTL_MODE_UPDWN_PER 0x00000003U |
| #define GPTIMER_CTL_MODE_QDEC 0x00000004U |
| #define GPTIMER_CTL_MODE_SYNC_UP_ONCE 0x00000005U |
| #define GPTIMER_CTL_MODE_SYNC_UP_PER 0x00000006U |
| #define GPTIMER_CTL_MODE_SYNC_UPDWN_PER 0x00000007U |
| #define GPTIMER_CTL_CMPDIR_W 2U |
| #define GPTIMER_CTL_CMPDIR_M 0x00000018U |
| #define GPTIMER_CTL_CMPDIR_S 3U |
| #define GPTIMER_CTL_CMPDIR_BOTH 0x00000000U |
| #define GPTIMER_CTL_CMPDIR_UP 0x00000008U |
| #define GPTIMER_CTL_CMPDIR_DOWN 0x00000010U |
| #define GPTIMER_CTL_CMPDIR_RESERVED 0x00000018U |
| #define GPTIMER_CTL_INTP 0x00000020U |
| #define GPTIMER_CTL_INTP_M 0x00000020U |
| #define GPTIMER_CTL_INTP_S 5U |
| #define GPTIMER_CTL_INTP_EARLY 0x00000000U |
| #define GPTIMER_CTL_INTP_LATE 0x00000020U |
| #define GPTIMER_CTL_C0RST 0x00000100U |
| #define GPTIMER_CTL_C0RST_M 0x00000100U |
| #define GPTIMER_CTL_C0RST_S 8U |
| #define GPTIMER_CTL_C0RST_NOEFF 0x00000000U |
| #define GPTIMER_CTL_C0RST_RST 0x00000100U |
| #define GPTIMER_CTL_C1RST 0x00000200U |
| #define GPTIMER_CTL_C1RST_M 0x00000200U |
| #define GPTIMER_CTL_C1RST_S 9U |
| #define GPTIMER_CTL_C1RST_NOEFF 0x00000000U |
| #define GPTIMER_CTL_C1RST_RST 0x00000200U |
| #define GPTIMER_CTL_C2RST 0x00000400U |
| #define GPTIMER_CTL_C2RST_M 0x00000400U |
| #define GPTIMER_CTL_C2RST_S 10U |
| #define GPTIMER_CTL_C2RST_NOEFF 0x00000000U |
| #define GPTIMER_CTL_C2RST_RST 0x00000400U |
| #define GPTIMER_CTL_C3RST 0x00000800U |
| #define GPTIMER_CTL_C3RST_M 0x00000800U |
| #define GPTIMER_CTL_C3RST_S 11U |
| #define GPTIMER_CTL_C3RST_NOEFF 0x00000000U |
| #define GPTIMER_CTL_C3RST_RST 0x00000800U |
| #define GPTIMER_OUTCTL_CLROUT0 0x00000001U |
| #define GPTIMER_OUTCTL_CLROUT0_M 0x00000001U |
| #define GPTIMER_OUTCTL_CLROUT0_S 0U |
| #define GPTIMER_OUTCTL_SETOUT0 0x00000002U |
| #define GPTIMER_OUTCTL_SETOUT0_M 0x00000002U |
| #define GPTIMER_OUTCTL_SETOUT0_S 1U |
| #define GPTIMER_OUTCTL_CLROUT1 0x00000004U |
| #define GPTIMER_OUTCTL_CLROUT1_M 0x00000004U |
| #define GPTIMER_OUTCTL_CLROUT1_S 2U |
| #define GPTIMER_OUTCTL_SETOUT1 0x00000008U |
| #define GPTIMER_OUTCTL_SETOUT1_M 0x00000008U |
| #define GPTIMER_OUTCTL_SETOUT1_S 3U |
| #define GPTIMER_OUTCTL_CLROUT2 0x00000010U |
| #define GPTIMER_OUTCTL_CLROUT2_M 0x00000010U |
| #define GPTIMER_OUTCTL_CLROUT2_S 4U |
| #define GPTIMER_OUTCTL_SETOUT2 0x00000020U |
| #define GPTIMER_OUTCTL_SETOUT2_M 0x00000020U |
| #define GPTIMER_OUTCTL_SETOUT2_S 5U |
| #define GPTIMER_OUTCTL_CLROUT3 0x00000040U |
| #define GPTIMER_OUTCTL_CLROUT3_M 0x00000040U |
| #define GPTIMER_OUTCTL_CLROUT3_S 6U |
| #define GPTIMER_OUTCTL_SETOUT3 0x00000080U |
| #define GPTIMER_OUTCTL_SETOUT3_M 0x00000080U |
| #define GPTIMER_OUTCTL_SETOUT3_S 7U |
| #define GPTIMER_CNTR_VAL_W 32U |
| #define GPTIMER_CNTR_VAL_M 0xFFFFFFFFU |
| #define GPTIMER_CNTR_VAL_S 0U |
| #define GPTIMER_PRECFG_TICKSRC_W 2U |
| #define GPTIMER_PRECFG_TICKSRC_M 0x00000003U |
| #define GPTIMER_PRECFG_TICKSRC_S 0U |
| #define GPTIMER_PRECFG_TICKSRC_CLK 0x00000000U |
| #define GPTIMER_PRECFG_TICKSRC_RISE_TICK 0x00000001U |
| #define GPTIMER_PRECFG_TICKSRC_FALL_TICK 0x00000002U |
| #define GPTIMER_PRECFG_TICKSRC_BOTH_TICK 0x00000003U |
| #define GPTIMER_PRECFG_TICKDIV_W 8U |
| #define GPTIMER_PRECFG_TICKDIV_M 0x0000FF00U |
| #define GPTIMER_PRECFG_TICKDIV_S 8U |
| #define GPTIMER_PREEVENT_VAL_W 8U |
| #define GPTIMER_PREEVENT_VAL_M 0x000000FFU |
| #define GPTIMER_PREEVENT_VAL_S 0U |
| #define GPTIMER_CHFILT_MODE_W 2U |
| #define GPTIMER_CHFILT_MODE_M 0x00000003U |
| #define GPTIMER_CHFILT_MODE_S 0U |
| #define GPTIMER_CHFILT_MODE_BYPASS 0x00000000U |
| #define GPTIMER_CHFILT_MODE_CLK 0x00000001U |
| #define GPTIMER_CHFILT_MODE_TICKSRC 0x00000002U |
| #define GPTIMER_CHFILT_MODE_TIMERCLK 0x00000003U |
| #define GPTIMER_CHFILT_LOAD_W 8U |
| #define GPTIMER_CHFILT_LOAD_M 0x0000FF00U |
| #define GPTIMER_CHFILT_LOAD_S 8U |
| #define GPTIMER_FAULT_CTL_W 2U |
| #define GPTIMER_FAULT_CTL_M 0x00000003U |
| #define GPTIMER_FAULT_CTL_S 0U |
| #define GPTIMER_FAULT_CTL_DIS 0x00000000U |
| #define GPTIMER_FAULT_CTL_IMMEDIATE 0x00000001U |
| #define GPTIMER_FAULT_CTL_ZERCOND 0x00000002U |
| #define GPTIMER_FAULT_CTL_IRQ 0x00000003U |
| #define GPTIMER_FAULT_RES_W 30U |
| #define GPTIMER_FAULT_RES_M 0xFFFFFFFCU |
| #define GPTIMER_FAULT_RES_S 2U |
| #define GPTIMER_PARK_CTL_W 2U |
| #define GPTIMER_PARK_CTL_M 0x00000003U |
| #define GPTIMER_PARK_CTL_S 0U |
| #define GPTIMER_PARK_CTL_DIS 0x00000000U |
| #define GPTIMER_PARK_CTL_FAULT 0x00000001U |
| #define GPTIMER_PARK_CTL_DEBUG 0x00000002U |
| #define GPTIMER_PARK_CTL_BOTH 0x00000003U |
| #define GPTIMER_PARK_IOPS0 0x00000004U |
| #define GPTIMER_PARK_IOPS0_M 0x00000004U |
| #define GPTIMER_PARK_IOPS0_S 2U |
| #define GPTIMER_PARK_IOPS0_HIGH 0x00000004U |
| #define GPTIMER_PARK_IOPS0_LOW 0x00000000U |
| #define GPTIMER_PARK_IOCPS0 0x00000008U |
| #define GPTIMER_PARK_IOCPS0_M 0x00000008U |
| #define GPTIMER_PARK_IOCPS0_S 3U |
| #define GPTIMER_PARK_IOCPS0_LOW 0x00000000U |
| #define GPTIMER_PARK_IOCPS0_HIGH 0x00000008U |
| #define GPTIMER_PARK_IOPS1 0x00000010U |
| #define GPTIMER_PARK_IOPS1_M 0x00000010U |
| #define GPTIMER_PARK_IOPS1_S 4U |
| #define GPTIMER_PARK_IOPS1_LOW 0x00000000U |
| #define GPTIMER_PARK_IOPS1_HIGH 0x00000010U |
| #define GPTIMER_PARK_IOCPS1 0x00000020U |
| #define GPTIMER_PARK_IOCPS1_M 0x00000020U |
| #define GPTIMER_PARK_IOCPS1_S 5U |
| #define GPTIMER_PARK_IOCPS1_LOW 0x00000000U |
| #define GPTIMER_PARK_IOCPS1_HIGH 0x00000020U |
| #define GPTIMER_PARK_IOPS2 0x00000040U |
| #define GPTIMER_PARK_IOPS2_M 0x00000040U |
| #define GPTIMER_PARK_IOPS2_S 6U |
| #define GPTIMER_PARK_IOPS2_LOW 0x00000000U |
| #define GPTIMER_PARK_IOPS2_HIGH 0x00000040U |
| #define GPTIMER_PARK_IOCPS2 0x00000080U |
| #define GPTIMER_PARK_IOCPS2_M 0x00000080U |
| #define GPTIMER_PARK_IOCPS2_S 7U |
| #define GPTIMER_PARK_IOCPS2_LOW 0x00000000U |
| #define GPTIMER_PARK_IOCPS2_HIGH 0x00000080U |
| #define GPTIMER_PARK_IOPS3 0x00000100U |
| #define GPTIMER_PARK_IOPS3_M 0x00000100U |
| #define GPTIMER_PARK_IOPS3_S 8U |
| #define GPTIMER_PARK_IOPS3_LOW 0x00000000U |
| #define GPTIMER_PARK_IOPS3_HIGH 0x00000100U |
| #define GPTIMER_PARK_IOCPS3 0x00000200U |
| #define GPTIMER_PARK_IOCPS3_M 0x00000200U |
| #define GPTIMER_PARK_IOCPS3_S 9U |
| #define GPTIMER_PARK_IOCPS3_LOW 0x00000000U |
| #define GPTIMER_PARK_IOCPS3_HIGH 0x00000200U |
| #define GPTIMER_DBDLY_RISEDLY_W 12U |
| #define GPTIMER_DBDLY_RISEDLY_M 0x00000FFFU |
| #define GPTIMER_DBDLY_RISEDLY_S 0U |
| #define GPTIMER_DBDLY_FALLDLY_W 12U |
| #define GPTIMER_DBDLY_FALLDLY_M 0x0FFF0000U |
| #define GPTIMER_DBDLY_FALLDLY_S 16U |
| #define GPTIMER_DBCTL_IO0 0x00000001U |
| #define GPTIMER_DBCTL_IO0_M 0x00000001U |
| #define GPTIMER_DBCTL_IO0_S 0U |
| #define GPTIMER_DBCTL_IO0_DIS 0x00000000U |
| #define GPTIMER_DBCTL_IO0_EN 0x00000001U |
| #define GPTIMER_DBCTL_IO1 0x00000002U |
| #define GPTIMER_DBCTL_IO1_M 0x00000002U |
| #define GPTIMER_DBCTL_IO1_S 1U |
| #define GPTIMER_DBCTL_IO1_DIS 0x00000000U |
| #define GPTIMER_DBCTL_IO1_EN 0x00000002U |
| #define GPTIMER_DBCTL_IO2 0x00000004U |
| #define GPTIMER_DBCTL_IO2_M 0x00000004U |
| #define GPTIMER_DBCTL_IO2_S 2U |
| #define GPTIMER_DBCTL_IO2_DIS 0x00000000U |
| #define GPTIMER_DBCTL_IO2_EN 0x00000004U |
| #define GPTIMER_DBCTL_IO3 0x00000008U |
| #define GPTIMER_DBCTL_IO3_M 0x00000008U |
| #define GPTIMER_DBCTL_IO3_S 3U |
| #define GPTIMER_DBCTL_IO3_DIS 0x00000000U |
| #define GPTIMER_DBCTL_IO3_EN 0x00000008U |
| #define GPTIMER_QDECSTAT_QDIR 0x00000001U |
| #define GPTIMER_QDECSTAT_QDIR_M 0x00000001U |
| #define GPTIMER_QDECSTAT_QDIR_S 0U |
| #define GPTIMER_QDECSTAT_QDIR_UP 0x00000000U |
| #define GPTIMER_QDECSTAT_QDIR_DOWN 0x00000001U |
| #define GPTIMER_QDECSTAT_DBLTRANS 0x00000002U |
| #define GPTIMER_QDECSTAT_DBLTRANS_M 0x00000002U |
| #define GPTIMER_QDECSTAT_DBLTRANS_S 1U |
| #define GPTIMER_QDECSTAT_DBLTRANS_NONE 0x00000000U |
| #define GPTIMER_QDECSTAT_DBLTRANS_DBL 0x00000002U |
| #define GPTIMER_IRGEN_CTL 0x00000001U |
| #define GPTIMER_IRGEN_CTL_M 0x00000001U |
| #define GPTIMER_IRGEN_CTL_S 0U |
| #define GPTIMER_IRGEN_CTL_DIS 0x00000000U |
| #define GPTIMER_IRGEN_CTL_EN 0x00000001U |
| #define GPTIMER_DMA_REQ_W 3U |
| #define GPTIMER_DMA_REQ_M 0x00000007U |
| #define GPTIMER_DMA_REQ_S 0U |
| #define GPTIMER_DMA_REQ_DIS 0x00000000U |
| #define GPTIMER_DMA_REQ_FAULT 0x00000003U |
| #define GPTIMER_DMA_REQ_TGT 0x00000001U |
| #define GPTIMER_DMA_REQ_ZERO 0x00000002U |
| #define GPTIMER_DMA_REQ_C0CC 0x00000004U |
| #define GPTIMER_DMA_REQ_C1CC 0x00000005U |
| #define GPTIMER_DMA_REQ_C2CC 0x00000006U |
| #define GPTIMER_DMA_REQ_C3CC 0x00000007U |
| #define GPTIMER_DMA_ADDRESS_W 7U |
| #define GPTIMER_DMA_ADDRESS_M 0x00007F00U |
| #define GPTIMER_DMA_ADDRESS_S 8U |
| #define GPTIMER_DMA_RWC_W 4U |
| #define GPTIMER_DMA_RWC_M 0x000F0000U |
| #define GPTIMER_DMA_RWC_S 16U |
| #define GPTIMER_DMARW_VAL_W 32U |
| #define GPTIMER_DMARW_VAL_M 0xFFFFFFFFU |
| #define GPTIMER_DMARW_VAL_S 0U |
| #define GPTIMER_ADCTRG_SRC_W 3U |
| #define GPTIMER_ADCTRG_SRC_M 0x00000007U |
| #define GPTIMER_ADCTRG_SRC_S 0U |
| #define GPTIMER_ADCTRG_SRC_DIS 0x00000000U |
| #define GPTIMER_ADCTRG_SRC_FAULT 0x00000003U |
| #define GPTIMER_ADCTRG_SRC_TGT 0x00000001U |
| #define GPTIMER_ADCTRG_SRC_ZERO 0x00000002U |
| #define GPTIMER_ADCTRG_SRC_C0CC 0x00000004U |
| #define GPTIMER_ADCTRG_SRC_C1CC 0x00000005U |
| #define GPTIMER_ADCTRG_SRC_C2CC 0x00000006U |
| #define GPTIMER_ADCTRG_SRC_C3CC 0x00000007U |
| #define GPTIMER_IOCTL_OUT0_W 2U |
| #define GPTIMER_IOCTL_OUT0_M 0x00000003U |
| #define GPTIMER_IOCTL_OUT0_S 0U |
| #define GPTIMER_IOCTL_OUT0_NRM 0x00000000U |
| #define GPTIMER_IOCTL_OUT0_LOW 0x00000001U |
| #define GPTIMER_IOCTL_OUT0_HIGH 0x00000002U |
| #define GPTIMER_IOCTL_OUT0_INV 0x00000003U |
| #define GPTIMER_IOCTL_COUT0_W 2U |
| #define GPTIMER_IOCTL_COUT0_M 0x0000000CU |
| #define GPTIMER_IOCTL_COUT0_S 2U |
| #define GPTIMER_IOCTL_COUT0_NRM 0x00000000U |
| #define GPTIMER_IOCTL_COUT0_LOW 0x00000004U |
| #define GPTIMER_IOCTL_COUT0_HIGH 0x00000008U |
| #define GPTIMER_IOCTL_COUT0_INV 0x0000000CU |
| #define GPTIMER_IOCTL_OUT1_W 2U |
| #define GPTIMER_IOCTL_OUT1_M 0x00000030U |
| #define GPTIMER_IOCTL_OUT1_S 4U |
| #define GPTIMER_IOCTL_OUT1_NRM 0x00000000U |
| #define GPTIMER_IOCTL_OUT1_LOW 0x00000010U |
| #define GPTIMER_IOCTL_OUT1_HIGH 0x00000020U |
| #define GPTIMER_IOCTL_OUT1_INV 0x00000030U |
| #define GPTIMER_IOCTL_COUT1_W 2U |
| #define GPTIMER_IOCTL_COUT1_M 0x000000C0U |
| #define GPTIMER_IOCTL_COUT1_S 6U |
| #define GPTIMER_IOCTL_COUT1_NRM 0x00000000U |
| #define GPTIMER_IOCTL_COUT1_LOW 0x00000040U |
| #define GPTIMER_IOCTL_COUT1_HIGH 0x00000080U |
| #define GPTIMER_IOCTL_COUT1_INV 0x000000C0U |
| #define GPTIMER_IOCTL_OUT2_W 2U |
| #define GPTIMER_IOCTL_OUT2_M 0x00000300U |
| #define GPTIMER_IOCTL_OUT2_S 8U |
| #define GPTIMER_IOCTL_OUT2_NRM 0x00000000U |
| #define GPTIMER_IOCTL_OUT2_LOW 0x00000100U |
| #define GPTIMER_IOCTL_OUT2_HIGH 0x00000200U |
| #define GPTIMER_IOCTL_OUT2_INV 0x00000300U |
| #define GPTIMER_IOCTL_COUT2_W 2U |
| #define GPTIMER_IOCTL_COUT2_M 0x00000C00U |
| #define GPTIMER_IOCTL_COUT2_S 10U |
| #define GPTIMER_IOCTL_COUT2_NRM 0x00000000U |
| #define GPTIMER_IOCTL_COUT2_LOW 0x00000400U |
| #define GPTIMER_IOCTL_COUT2_HIGH 0x00000800U |
| #define GPTIMER_IOCTL_COUT2_INV 0x00000C00U |
| #define GPTIMER_IOCTL_OUT3_W 2U |
| #define GPTIMER_IOCTL_OUT3_M 0x00003000U |
| #define GPTIMER_IOCTL_OUT3_S 12U |
| #define GPTIMER_IOCTL_OUT3_NRM 0x00000000U |
| #define GPTIMER_IOCTL_OUT3_LOW 0x00001000U |
| #define GPTIMER_IOCTL_OUT3_HIGH 0x00002000U |
| #define GPTIMER_IOCTL_OUT3_INV 0x00003000U |
| #define GPTIMER_IOCTL_COUT3_W 2U |
| #define GPTIMER_IOCTL_COUT3_M 0x0000C000U |
| #define GPTIMER_IOCTL_COUT3_S 14U |
| #define GPTIMER_IOCTL_COUT3_NRM 0x00000000U |
| #define GPTIMER_IOCTL_COUT3_LOW 0x00004000U |
| #define GPTIMER_IOCTL_COUT3_HIGH 0x00008000U |
| #define GPTIMER_IOCTL_COUT3_INV 0x0000C000U |
| #define GPTIMER_IMASK_TGT 0x00000001U |
| #define GPTIMER_IMASK_TGT_M 0x00000001U |
| #define GPTIMER_IMASK_TGT_S 0U |
| #define GPTIMER_IMASK_TGT_DIS 0x00000000U |
| #define GPTIMER_IMASK_TGT_EN 0x00000001U |
| #define GPTIMER_IMASK_ZERO 0x00000002U |
| #define GPTIMER_IMASK_ZERO_M 0x00000002U |
| #define GPTIMER_IMASK_ZERO_S 1U |
| #define GPTIMER_IMASK_ZERO_DIS 0x00000000U |
| #define GPTIMER_IMASK_ZERO_EN 0x00000002U |
| #define GPTIMER_IMASK_DBLTRANS 0x00000004U |
| #define GPTIMER_IMASK_DBLTRANS_M 0x00000004U |
| #define GPTIMER_IMASK_DBLTRANS_S 2U |
| #define GPTIMER_IMASK_DBLTRANS_DIS 0x00000000U |
| #define GPTIMER_IMASK_DBLTRANS_EN 0x00000004U |
| #define GPTIMER_IMASK_CNTRCHNG 0x00000008U |
| #define GPTIMER_IMASK_CNTRCHNG_M 0x00000008U |
| #define GPTIMER_IMASK_CNTRCHNG_S 3U |
| #define GPTIMER_IMASK_CNTRCHNG_DIS 0x00000000U |
| #define GPTIMER_IMASK_CNTRCHNG_EN 0x00000008U |
| #define GPTIMER_IMASK_DIRCHNG 0x00000010U |
| #define GPTIMER_IMASK_DIRCHNG_M 0x00000010U |
| #define GPTIMER_IMASK_DIRCHNG_S 4U |
| #define GPTIMER_IMASK_DIRCHNG_DIS 0x00000000U |
| #define GPTIMER_IMASK_DIRCHNG_EN 0x00000010U |
| #define GPTIMER_IMASK_IDX 0x00000020U |
| #define GPTIMER_IMASK_IDX_M 0x00000020U |
| #define GPTIMER_IMASK_IDX_S 5U |
| #define GPTIMER_IMASK_IDX_DIS 0x00000000U |
| #define GPTIMER_IMASK_IDX_EN 0x00000020U |
| #define GPTIMER_IMASK_FAULT 0x00000040U |
| #define GPTIMER_IMASK_FAULT_M 0x00000040U |
| #define GPTIMER_IMASK_FAULT_S 6U |
| #define GPTIMER_IMASK_FAULT_DIS 0x00000000U |
| #define GPTIMER_IMASK_FAULT_EN 0x00000040U |
| #define GPTIMER_IMASK_C0CC 0x00000100U |
| #define GPTIMER_IMASK_C0CC_M 0x00000100U |
| #define GPTIMER_IMASK_C0CC_S 8U |
| #define GPTIMER_IMASK_C0CC_DIS 0x00000000U |
| #define GPTIMER_IMASK_C0CC_EN 0x00000100U |
| #define GPTIMER_IMASK_C1CC 0x00000200U |
| #define GPTIMER_IMASK_C1CC_M 0x00000200U |
| #define GPTIMER_IMASK_C1CC_S 9U |
| #define GPTIMER_IMASK_C1CC_DIS 0x00000000U |
| #define GPTIMER_IMASK_C1CC_EN 0x00000200U |
| #define GPTIMER_IMASK_C2CC 0x00000400U |
| #define GPTIMER_IMASK_C2CC_M 0x00000400U |
| #define GPTIMER_IMASK_C2CC_S 10U |
| #define GPTIMER_IMASK_C2CC_DIS 0x00000000U |
| #define GPTIMER_IMASK_C2CC_EN 0x00000400U |
| #define GPTIMER_IMASK_C3CC 0x00000800U |
| #define GPTIMER_IMASK_C3CC_M 0x00000800U |
| #define GPTIMER_IMASK_C3CC_S 11U |
| #define GPTIMER_IMASK_C3CC_DIS 0x00000000U |
| #define GPTIMER_IMASK_C3CC_EN 0x00000800U |
| #define GPTIMER_RIS_TGT 0x00000001U |
| #define GPTIMER_RIS_TGT_M 0x00000001U |
| #define GPTIMER_RIS_TGT_S 0U |
| #define GPTIMER_RIS_TGT_CLR 0x00000000U |
| #define GPTIMER_RIS_TGT_SET 0x00000001U |
| #define GPTIMER_RIS_ZERO 0x00000002U |
| #define GPTIMER_RIS_ZERO_M 0x00000002U |
| #define GPTIMER_RIS_ZERO_S 1U |
| #define GPTIMER_RIS_ZERO_CLR 0x00000000U |
| #define GPTIMER_RIS_ZERO_SET 0x00000002U |
| #define GPTIMER_RIS_DBLTRANS 0x00000004U |
| #define GPTIMER_RIS_DBLTRANS_M 0x00000004U |
| #define GPTIMER_RIS_DBLTRANS_S 2U |
| #define GPTIMER_RIS_DBLTRANS_CLR 0x00000000U |
| #define GPTIMER_RIS_DBLTRANS_SET 0x00000004U |
| #define GPTIMER_RIS_CNTRCHNG 0x00000008U |
| #define GPTIMER_RIS_CNTRCHNG_M 0x00000008U |
| #define GPTIMER_RIS_CNTRCHNG_S 3U |
| #define GPTIMER_RIS_CNTRCHNG_CLR 0x00000000U |
| #define GPTIMER_RIS_CNTRCHNG_SET 0x00000008U |
| #define GPTIMER_RIS_DIRCHNG 0x00000010U |
| #define GPTIMER_RIS_DIRCHNG_M 0x00000010U |
| #define GPTIMER_RIS_DIRCHNG_S 4U |
| #define GPTIMER_RIS_DIRCHNG_CLR 0x00000000U |
| #define GPTIMER_RIS_DIRCHNG_SET 0x00000010U |
| #define GPTIMER_RIS_IDX 0x00000020U |
| #define GPTIMER_RIS_IDX_M 0x00000020U |
| #define GPTIMER_RIS_IDX_S 5U |
| #define GPTIMER_RIS_IDX_CLR 0x00000000U |
| #define GPTIMER_RIS_IDX_SET 0x00000020U |
| #define GPTIMER_RIS_FAULT 0x00000040U |
| #define GPTIMER_RIS_FAULT_M 0x00000040U |
| #define GPTIMER_RIS_FAULT_S 6U |
| #define GPTIMER_RIS_FAULT_CLR 0x00000000U |
| #define GPTIMER_RIS_FAULT_SET 0x00000040U |
| #define GPTIMER_RIS_C0CC 0x00000100U |
| #define GPTIMER_RIS_C0CC_M 0x00000100U |
| #define GPTIMER_RIS_C0CC_S 8U |
| #define GPTIMER_RIS_C0CC_CLR 0x00000000U |
| #define GPTIMER_RIS_C0CC_SET 0x00000100U |
| #define GPTIMER_RIS_C1CC 0x00000200U |
| #define GPTIMER_RIS_C1CC_M 0x00000200U |
| #define GPTIMER_RIS_C1CC_S 9U |
| #define GPTIMER_RIS_C1CC_CLR 0x00000000U |
| #define GPTIMER_RIS_C1CC_SET 0x00000200U |
| #define GPTIMER_RIS_C2CC 0x00000400U |
| #define GPTIMER_RIS_C2CC_M 0x00000400U |
| #define GPTIMER_RIS_C2CC_S 10U |
| #define GPTIMER_RIS_C2CC_CLR 0x00000000U |
| #define GPTIMER_RIS_C2CC_SET 0x00000400U |
| #define GPTIMER_RIS_C3CC 0x00000800U |
| #define GPTIMER_RIS_C3CC_M 0x00000800U |
| #define GPTIMER_RIS_C3CC_S 11U |
| #define GPTIMER_RIS_C3CC_DIS 0x00000000U |
| #define GPTIMER_RIS_C3CC_EN 0x00000800U |
| #define GPTIMER_MIS_TGT 0x00000001U |
| #define GPTIMER_MIS_TGT_M 0x00000001U |
| #define GPTIMER_MIS_TGT_S 0U |
| #define GPTIMER_MIS_TGT_CLR 0x00000000U |
| #define GPTIMER_MIS_TGT_SET 0x00000001U |
| #define GPTIMER_MIS_ZERO 0x00000002U |
| #define GPTIMER_MIS_ZERO_M 0x00000002U |
| #define GPTIMER_MIS_ZERO_S 1U |
| #define GPTIMER_MIS_ZERO_CLR 0x00000000U |
| #define GPTIMER_MIS_ZERO_SET 0x00000002U |
| #define GPTIMER_MIS_DBLTRANS 0x00000004U |
| #define GPTIMER_MIS_DBLTRANS_M 0x00000004U |
| #define GPTIMER_MIS_DBLTRANS_S 2U |
| #define GPTIMER_MIS_DBLTRANS_CLR 0x00000000U |
| #define GPTIMER_MIS_DBLTRANS_SET 0x00000004U |
| #define GPTIMER_MIS_CNTRCHNG 0x00000008U |
| #define GPTIMER_MIS_CNTRCHNG_M 0x00000008U |
| #define GPTIMER_MIS_CNTRCHNG_S 3U |
| #define GPTIMER_MIS_CNTRCHNG_CLR 0x00000000U |
| #define GPTIMER_MIS_CNTRCHNG_SET 0x00000008U |
| #define GPTIMER_MIS_DIRCHNG 0x00000010U |
| #define GPTIMER_MIS_DIRCHNG_M 0x00000010U |
| #define GPTIMER_MIS_DIRCHNG_S 4U |
| #define GPTIMER_MIS_DIRCHNG_CLR 0x00000000U |
| #define GPTIMER_MIS_DIRCHNG_SET 0x00000010U |
| #define GPTIMER_MIS_IDX 0x00000020U |
| #define GPTIMER_MIS_IDX_M 0x00000020U |
| #define GPTIMER_MIS_IDX_S 5U |
| #define GPTIMER_MIS_IDX_CLR 0x00000000U |
| #define GPTIMER_MIS_IDX_SET 0x00000020U |
| #define GPTIMER_MIS_FAULT 0x00000040U |
| #define GPTIMER_MIS_FAULT_M 0x00000040U |
| #define GPTIMER_MIS_FAULT_S 6U |
| #define GPTIMER_MIS_FAULT_CLR 0x00000000U |
| #define GPTIMER_MIS_FAULT_SET 0x00000040U |
| #define GPTIMER_MIS_C0CC 0x00000100U |
| #define GPTIMER_MIS_C0CC_M 0x00000100U |
| #define GPTIMER_MIS_C0CC_S 8U |
| #define GPTIMER_MIS_C0CC_CLR 0x00000000U |
| #define GPTIMER_MIS_C0CC_SET 0x00000100U |
| #define GPTIMER_MIS_C1CC 0x00000200U |
| #define GPTIMER_MIS_C1CC_M 0x00000200U |
| #define GPTIMER_MIS_C1CC_S 9U |
| #define GPTIMER_MIS_C1CC_CLR 0x00000000U |
| #define GPTIMER_MIS_C1CC_SET 0x00000200U |
| #define GPTIMER_MIS_C2CC 0x00000400U |
| #define GPTIMER_MIS_C2CC_M 0x00000400U |
| #define GPTIMER_MIS_C2CC_S 10U |
| #define GPTIMER_MIS_C2CC_CLR 0x00000000U |
| #define GPTIMER_MIS_C2CC_SET 0x00000400U |
| #define GPTIMER_MIS_C3CC 0x00000800U |
| #define GPTIMER_MIS_C3CC_M 0x00000800U |
| #define GPTIMER_MIS_C3CC_S 11U |
| #define GPTIMER_MIS_C3CC_CLR 0x00000000U |
| #define GPTIMER_MIS_C3CC_SET 0x00000800U |
| #define GPTIMER_ISET_TGT 0x00000001U |
| #define GPTIMER_ISET_TGT_M 0x00000001U |
| #define GPTIMER_ISET_TGT_S 0U |
| #define GPTIMER_ISET_TGT_NO_EFFECT 0x00000000U |
| #define GPTIMER_ISET_TGT_SET 0x00000001U |
| #define GPTIMER_ISET_ZERO 0x00000002U |
| #define GPTIMER_ISET_ZERO_M 0x00000002U |
| #define GPTIMER_ISET_ZERO_S 1U |
| #define GPTIMER_ISET_ZERO_NO_EFFECT 0x00000000U |
| #define GPTIMER_ISET_ZERO_SET 0x00000002U |
| #define GPTIMER_ISET_DBLTRANS 0x00000004U |
| #define GPTIMER_ISET_DBLTRANS_M 0x00000004U |
| #define GPTIMER_ISET_DBLTRANS_S 2U |
| #define GPTIMER_ISET_DBLTRANS_NO_EFFECT 0x00000000U |
| #define GPTIMER_ISET_DBLTRANS_SET 0x00000004U |
| #define GPTIMER_ISET_CNTRCHNG 0x00000008U |
| #define GPTIMER_ISET_CNTRCHNG_M 0x00000008U |
| #define GPTIMER_ISET_CNTRCHNG_S 3U |
| #define GPTIMER_ISET_CNTRCHNG_NO_EFFECT 0x00000000U |
| #define GPTIMER_ISET_CNTRCHNG_SET 0x00000008U |
| #define GPTIMER_ISET_DIRCHNG 0x00000010U |
| #define GPTIMER_ISET_DIRCHNG_M 0x00000010U |
| #define GPTIMER_ISET_DIRCHNG_S 4U |
| #define GPTIMER_ISET_DIRCHNG_NO_EFFECT 0x00000000U |
| #define GPTIMER_ISET_DIRCHNG_SET 0x00000010U |
| #define GPTIMER_ISET_IDX 0x00000020U |
| #define GPTIMER_ISET_IDX_M 0x00000020U |
| #define GPTIMER_ISET_IDX_S 5U |
| #define GPTIMER_ISET_IDX_NO_EFFECT 0x00000000U |
| #define GPTIMER_ISET_IDX_SET 0x00000020U |
| #define GPTIMER_ISET_FAULT 0x00000040U |
| #define GPTIMER_ISET_FAULT_M 0x00000040U |
| #define GPTIMER_ISET_FAULT_S 6U |
| #define GPTIMER_ISET_FAULT_NO_EFFECT 0x00000000U |
| #define GPTIMER_ISET_FAULT_SET 0x00000040U |
| #define GPTIMER_ISET_C0CC 0x00000100U |
| #define GPTIMER_ISET_C0CC_M 0x00000100U |
| #define GPTIMER_ISET_C0CC_S 8U |
| #define GPTIMER_ISET_C0CC_NO_EFFECT 0x00000000U |
| #define GPTIMER_ISET_C0CC_SET 0x00000100U |
| #define GPTIMER_ISET_C1CC 0x00000200U |
| #define GPTIMER_ISET_C1CC_M 0x00000200U |
| #define GPTIMER_ISET_C1CC_S 9U |
| #define GPTIMER_ISET_C1CC_NO_EFFECT 0x00000000U |
| #define GPTIMER_ISET_C1CC_SET 0x00000200U |
| #define GPTIMER_ISET_C2CC 0x00000400U |
| #define GPTIMER_ISET_C2CC_M 0x00000400U |
| #define GPTIMER_ISET_C2CC_S 10U |
| #define GPTIMER_ISET_C2CC_NO_EFFECT 0x00000000U |
| #define GPTIMER_ISET_C2CC_SET 0x00000400U |
| #define GPTIMER_ISET_C3CC 0x00000800U |
| #define GPTIMER_ISET_C3CC_M 0x00000800U |
| #define GPTIMER_ISET_C3CC_S 11U |
| #define GPTIMER_ISET_C3CC_NO_EFFECT 0x00000000U |
| #define GPTIMER_ISET_C3CC_SET 0x00000800U |
| #define GPTIMER_ICLR_TGT 0x00000001U |
| #define GPTIMER_ICLR_TGT_M 0x00000001U |
| #define GPTIMER_ICLR_TGT_S 0U |
| #define GPTIMER_ICLR_TGT_NO_EFFECT 0x00000000U |
| #define GPTIMER_ICLR_TGT_CLR 0x00000001U |
| #define GPTIMER_ICLR_ZERO 0x00000002U |
| #define GPTIMER_ICLR_ZERO_M 0x00000002U |
| #define GPTIMER_ICLR_ZERO_S 1U |
| #define GPTIMER_ICLR_ZERO_NO_EFFECT 0x00000000U |
| #define GPTIMER_ICLR_ZERO_CLR 0x00000002U |
| #define GPTIMER_ICLR_DBLTRANS 0x00000004U |
| #define GPTIMER_ICLR_DBLTRANS_M 0x00000004U |
| #define GPTIMER_ICLR_DBLTRANS_S 2U |
| #define GPTIMER_ICLR_DBLTRANS_NO_EFFECT 0x00000000U |
| #define GPTIMER_ICLR_DBLTRANS_CLR 0x00000004U |
| #define GPTIMER_ICLR_CNTRCHNG 0x00000008U |
| #define GPTIMER_ICLR_CNTRCHNG_M 0x00000008U |
| #define GPTIMER_ICLR_CNTRCHNG_S 3U |
| #define GPTIMER_ICLR_CNTRCHNG_NO_EFFECT 0x00000000U |
| #define GPTIMER_ICLR_CNTRCHNG_CLR 0x00000008U |
| #define GPTIMER_ICLR_DIRCHNG 0x00000010U |
| #define GPTIMER_ICLR_DIRCHNG_M 0x00000010U |
| #define GPTIMER_ICLR_DIRCHNG_S 4U |
| #define GPTIMER_ICLR_DIRCHNG_NO_EFFECT 0x00000000U |
| #define GPTIMER_ICLR_DIRCHNG_CLR 0x00000010U |
| #define GPTIMER_ICLR_IDX 0x00000020U |
| #define GPTIMER_ICLR_IDX_M 0x00000020U |
| #define GPTIMER_ICLR_IDX_S 5U |
| #define GPTIMER_ICLR_IDX_NO_EFFECT 0x00000000U |
| #define GPTIMER_ICLR_IDX_CLR 0x00000020U |
| #define GPTIMER_ICLR_FAULT 0x00000040U |
| #define GPTIMER_ICLR_FAULT_M 0x00000040U |
| #define GPTIMER_ICLR_FAULT_S 6U |
| #define GPTIMER_ICLR_FAULT_NO_EFFECT 0x00000000U |
| #define GPTIMER_ICLR_FAULT_CLR 0x00000040U |
| #define GPTIMER_ICLR_C0CC 0x00000100U |
| #define GPTIMER_ICLR_C0CC_M 0x00000100U |
| #define GPTIMER_ICLR_C0CC_S 8U |
| #define GPTIMER_ICLR_C0CC_NO_EFFECT 0x00000000U |
| #define GPTIMER_ICLR_C0CC_CLR 0x00000100U |
| #define GPTIMER_ICLR_C1CC 0x00000200U |
| #define GPTIMER_ICLR_C1CC_M 0x00000200U |
| #define GPTIMER_ICLR_C1CC_S 9U |
| #define GPTIMER_ICLR_C1CC_NO_EFFECT 0x00000000U |
| #define GPTIMER_ICLR_C1CC_CLR 0x00000200U |
| #define GPTIMER_ICLR_C2CC 0x00000400U |
| #define GPTIMER_ICLR_C2CC_M 0x00000400U |
| #define GPTIMER_ICLR_C2CC_S 10U |
| #define GPTIMER_ICLR_C2CC_NO_EFFECT 0x00000000U |
| #define GPTIMER_ICLR_C2CC_CLR 0x00000400U |
| #define GPTIMER_ICLR_C3CC 0x00000800U |
| #define GPTIMER_ICLR_C3CC_M 0x00000800U |
| #define GPTIMER_ICLR_C3CC_S 11U |
| #define GPTIMER_ICLR_C3CC_NO_EFFECT 0x00000000U |
| #define GPTIMER_ICLR_C3CC_CLR 0x00000800U |
| #define GPTIMER_IMSET_TGT 0x00000001U |
| #define GPTIMER_IMSET_TGT_M 0x00000001U |
| #define GPTIMER_IMSET_TGT_S 0U |
| #define GPTIMER_IMSET_TGT_NO_EFFECT 0x00000000U |
| #define GPTIMER_IMSET_TGT_SET 0x00000001U |
| #define GPTIMER_IMSET_ZERO 0x00000002U |
| #define GPTIMER_IMSET_ZERO_M 0x00000002U |
| #define GPTIMER_IMSET_ZERO_S 1U |
| #define GPTIMER_IMSET_ZERO_NO_EFFECT 0x00000000U |
| #define GPTIMER_IMSET_ZERO_SET 0x00000002U |
| #define GPTIMER_IMSET_DBLTRANS 0x00000004U |
| #define GPTIMER_IMSET_DBLTRANS_M 0x00000004U |
| #define GPTIMER_IMSET_DBLTRANS_S 2U |
| #define GPTIMER_IMSET_DBLTRANS_NO_EFFECT 0x00000000U |
| #define GPTIMER_IMSET_DBLTRANS_SET 0x00000004U |
| #define GPTIMER_IMSET_CNTRCHNG 0x00000008U |
| #define GPTIMER_IMSET_CNTRCHNG_M 0x00000008U |
| #define GPTIMER_IMSET_CNTRCHNG_S 3U |
| #define GPTIMER_IMSET_CNTRCHNG_NO_EFFECT 0x00000000U |
| #define GPTIMER_IMSET_CNTRCHNG_SET 0x00000008U |
| #define GPTIMER_IMSET_DIRCHNG 0x00000010U |
| #define GPTIMER_IMSET_DIRCHNG_M 0x00000010U |
| #define GPTIMER_IMSET_DIRCHNG_S 4U |
| #define GPTIMER_IMSET_DIRCHNG_NO_EFFECT 0x00000000U |
| #define GPTIMER_IMSET_DIRCHNG_SET 0x00000010U |
| #define GPTIMER_IMSET_IDX 0x00000020U |
| #define GPTIMER_IMSET_IDX_M 0x00000020U |
| #define GPTIMER_IMSET_IDX_S 5U |
| #define GPTIMER_IMSET_IDX_NO_EFFECT 0x00000000U |
| #define GPTIMER_IMSET_IDX_SET 0x00000020U |
| #define GPTIMER_IMSET_FAULT 0x00000040U |
| #define GPTIMER_IMSET_FAULT_M 0x00000040U |
| #define GPTIMER_IMSET_FAULT_S 6U |
| #define GPTIMER_IMSET_FAULT_NO_EFFECT 0x00000000U |
| #define GPTIMER_IMSET_FAULT_SET 0x00000040U |
| #define GPTIMER_IMSET_C0CC 0x00000100U |
| #define GPTIMER_IMSET_C0CC_M 0x00000100U |
| #define GPTIMER_IMSET_C0CC_S 8U |
| #define GPTIMER_IMSET_C0CC_NO_EFFECT 0x00000000U |
| #define GPTIMER_IMSET_C0CC_SET 0x00000100U |
| #define GPTIMER_IMSET_C1CC 0x00000200U |
| #define GPTIMER_IMSET_C1CC_M 0x00000200U |
| #define GPTIMER_IMSET_C1CC_S 9U |
| #define GPTIMER_IMSET_C1CC_NO_EFFECT 0x00000000U |
| #define GPTIMER_IMSET_C1CC_SET 0x00000200U |
| #define GPTIMER_IMSET_C2CC 0x00000400U |
| #define GPTIMER_IMSET_C2CC_M 0x00000400U |
| #define GPTIMER_IMSET_C2CC_S 10U |
| #define GPTIMER_IMSET_C2CC_NO_EFFECT 0x00000000U |
| #define GPTIMER_IMSET_C2CC_SET 0x00000400U |
| #define GPTIMER_IMSET_C3CC 0x00000800U |
| #define GPTIMER_IMSET_C3CC_M 0x00000800U |
| #define GPTIMER_IMSET_C3CC_S 11U |
| #define GPTIMER_IMSET_C3CC_NO_EFFECT 0x00000000U |
| #define GPTIMER_IMSET_C3CC_SET 0x00000800U |
| #define GPTIMER_IMCLR_TGT 0x00000001U |
| #define GPTIMER_IMCLR_TGT_M 0x00000001U |
| #define GPTIMER_IMCLR_TGT_S 0U |
| #define GPTIMER_IMCLR_TGT_NO_EFFECT 0x00000000U |
| #define GPTIMER_IMCLR_TGT_CLR 0x00000001U |
| #define GPTIMER_IMCLR_ZERO 0x00000002U |
| #define GPTIMER_IMCLR_ZERO_M 0x00000002U |
| #define GPTIMER_IMCLR_ZERO_S 1U |
| #define GPTIMER_IMCLR_ZERO_NO_EFFECT 0x00000000U |
| #define GPTIMER_IMCLR_ZERO_CLR 0x00000002U |
| #define GPTIMER_IMCLR_DBLTRANS 0x00000004U |
| #define GPTIMER_IMCLR_DBLTRANS_M 0x00000004U |
| #define GPTIMER_IMCLR_DBLTRANS_S 2U |
| #define GPTIMER_IMCLR_DBLTRANS_NO_EFFECT 0x00000000U |
| #define GPTIMER_IMCLR_DBLTRANS_CLR 0x00000004U |
| #define GPTIMER_IMCLR_CNTRCHNG 0x00000008U |
| #define GPTIMER_IMCLR_CNTRCHNG_M 0x00000008U |
| #define GPTIMER_IMCLR_CNTRCHNG_S 3U |
| #define GPTIMER_IMCLR_CNTRCHNG_NO_EFFECT 0x00000000U |
| #define GPTIMER_IMCLR_CNTRCHNG_CLR 0x00000008U |
| #define GPTIMER_IMCLR_DIRCHNG 0x00000010U |
| #define GPTIMER_IMCLR_DIRCHNG_M 0x00000010U |
| #define GPTIMER_IMCLR_DIRCHNG_S 4U |
| #define GPTIMER_IMCLR_DIRCHNG_NO_EFFECT 0x00000000U |
| #define GPTIMER_IMCLR_DIRCHNG_CLR 0x00000010U |
| #define GPTIMER_IMCLR_IDX 0x00000020U |
| #define GPTIMER_IMCLR_IDX_M 0x00000020U |
| #define GPTIMER_IMCLR_IDX_S 5U |
| #define GPTIMER_IMCLR_IDX_NO_EFFECT 0x00000000U |
| #define GPTIMER_IMCLR_IDX_CLR 0x00000020U |
| #define GPTIMER_IMCLR_FAULT 0x00000040U |
| #define GPTIMER_IMCLR_FAULT_M 0x00000040U |
| #define GPTIMER_IMCLR_FAULT_S 6U |
| #define GPTIMER_IMCLR_FAULT_NO_EFFECT 0x00000000U |
| #define GPTIMER_IMCLR_FAULT_CLR 0x00000040U |
| #define GPTIMER_IMCLR_C0CC 0x00000100U |
| #define GPTIMER_IMCLR_C0CC_M 0x00000100U |
| #define GPTIMER_IMCLR_C0CC_S 8U |
| #define GPTIMER_IMCLR_C0CC_NO_EFFECT 0x00000000U |
| #define GPTIMER_IMCLR_C0CC_CLR 0x00000100U |
| #define GPTIMER_IMCLR_C1CC 0x00000200U |
| #define GPTIMER_IMCLR_C1CC_M 0x00000200U |
| #define GPTIMER_IMCLR_C1CC_S 9U |
| #define GPTIMER_IMCLR_C1CC_NO_EFFECT 0x00000000U |
| #define GPTIMER_IMCLR_C1CC_CLR 0x00000200U |
| #define GPTIMER_IMCLR_C2CC 0x00000400U |
| #define GPTIMER_IMCLR_C2CC_M 0x00000400U |
| #define GPTIMER_IMCLR_C2CC_S 10U |
| #define GPTIMER_IMCLR_C2CC_NO_EFFECT 0x00000000U |
| #define GPTIMER_IMCLR_C2CC_CLR 0x00000400U |
| #define GPTIMER_IMCLR_C3CC 0x00000800U |
| #define GPTIMER_IMCLR_C3CC_M 0x00000800U |
| #define GPTIMER_IMCLR_C3CC_S 11U |
| #define GPTIMER_IMCLR_C3CC_NO_EFFECT 0x00000000U |
| #define GPTIMER_IMCLR_C3CC_CLR 0x00000800U |
| #define GPTIMER_EMU_HALT 0x00000001U |
| #define GPTIMER_EMU_HALT_M 0x00000001U |
| #define GPTIMER_EMU_HALT_S 0U |
| #define GPTIMER_EMU_HALT_DIS 0x00000000U |
| #define GPTIMER_EMU_HALT_EN 0x00000001U |
| #define GPTIMER_EMU_CTL 0x00000002U |
| #define GPTIMER_EMU_CTL_M 0x00000002U |
| #define GPTIMER_EMU_CTL_S 1U |
| #define GPTIMER_EMU_CTL_IMMEDIATE 0x00000000U |
| #define GPTIMER_EMU_CTL_ZERCOND 0x00000002U |
| #define GPTIMER_C0CFG_CCACT_W 4U |
| #define GPTIMER_C0CFG_CCACT_M 0x0000000FU |
| #define GPTIMER_C0CFG_CCACT_S 0U |
| #define GPTIMER_C0CFG_CCACT_DIS 0x00000000U |
| #define GPTIMER_C0CFG_CCACT_SET_ON_CAPT_DIS 0x00000001U |
| #define GPTIMER_C0CFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000AU |
| #define GPTIMER_C0CFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000BU |
| #define GPTIMER_C0CFG_CCACT_CLR_ON_CMP 0x0000000CU |
| #define GPTIMER_C0CFG_CCACT_SET_ON_CMP 0x0000000DU |
| #define GPTIMER_C0CFG_CCACT_TGL_ON_CMP 0x0000000EU |
| #define GPTIMER_C0CFG_CCACT_PULSE_ON_CMP 0x0000000FU |
| #define GPTIMER_C0CFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002U |
| #define GPTIMER_C0CFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003U |
| #define GPTIMER_C0CFG_CCACT_CLR_ON_CMP_DIS 0x00000004U |
| #define GPTIMER_C0CFG_CCACT_SET_ON_CMP_DIS 0x00000005U |
| #define GPTIMER_C0CFG_CCACT_TGL_ON_CMP_DIS 0x00000006U |
| #define GPTIMER_C0CFG_CCACT_PULSE_ON_CMP_DIS 0x00000007U |
| #define GPTIMER_C0CFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008U |
| #define GPTIMER_C0CFG_CCACT_SET_ON_CAPT 0x00000009U |
| #define GPTIMER_C0CFG_EDGE_W 2U |
| #define GPTIMER_C0CFG_EDGE_M 0x00000030U |
| #define GPTIMER_C0CFG_EDGE_S 4U |
| #define GPTIMER_C0CFG_EDGE_NONE 0x00000000U |
| #define GPTIMER_C0CFG_EDGE_RISE 0x00000010U |
| #define GPTIMER_C0CFG_EDGE_FALL 0x00000020U |
| #define GPTIMER_C0CFG_EDGE_BOTH 0x00000030U |
| #define GPTIMER_C0CFG_INPUT 0x00000040U |
| #define GPTIMER_C0CFG_INPUT_M 0x00000040U |
| #define GPTIMER_C0CFG_INPUT_S 6U |
| #define GPTIMER_C0CFG_INPUT_EV 0x00000000U |
| #define GPTIMER_C0CFG_INPUT_IO 0x00000040U |
| #define GPTIMER_C0CFG_OUT0 0x00000100U |
| #define GPTIMER_C0CFG_OUT0_M 0x00000100U |
| #define GPTIMER_C0CFG_OUT0_S 8U |
| #define GPTIMER_C0CFG_OUT0_DIS 0x00000000U |
| #define GPTIMER_C0CFG_OUT0_EN 0x00000100U |
| #define GPTIMER_C0CFG_OUT1 0x00000200U |
| #define GPTIMER_C0CFG_OUT1_M 0x00000200U |
| #define GPTIMER_C0CFG_OUT1_S 9U |
| #define GPTIMER_C0CFG_OUT1_DIS 0x00000000U |
| #define GPTIMER_C0CFG_OUT1_EN 0x00000200U |
| #define GPTIMER_C0CFG_OUT2 0x00000400U |
| #define GPTIMER_C0CFG_OUT2_M 0x00000400U |
| #define GPTIMER_C0CFG_OUT2_S 10U |
| #define GPTIMER_C0CFG_OUT2_DIS 0x00000000U |
| #define GPTIMER_C0CFG_OUT2_EN 0x00000400U |
| #define GPTIMER_C0CFG_OUT3 0x00000800U |
| #define GPTIMER_C0CFG_OUT3_M 0x00000800U |
| #define GPTIMER_C0CFG_OUT3_S 11U |
| #define GPTIMER_C0CFG_OUT3_DIS 0x00000000U |
| #define GPTIMER_C0CFG_OUT3_EN 0x00000800U |
| #define GPTIMER_C1CFG_CCACT_W 4U |
| #define GPTIMER_C1CFG_CCACT_M 0x0000000FU |
| #define GPTIMER_C1CFG_CCACT_S 0U |
| #define GPTIMER_C1CFG_CCACT_DIS 0x00000000U |
| #define GPTIMER_C1CFG_CCACT_SET_ON_CAPT_DIS 0x00000001U |
| #define GPTIMER_C1CFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000AU |
| #define GPTIMER_C1CFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000BU |
| #define GPTIMER_C1CFG_CCACT_CLR_ON_CMP 0x0000000CU |
| #define GPTIMER_C1CFG_CCACT_SET_ON_CMP 0x0000000DU |
| #define GPTIMER_C1CFG_CCACT_TGL_ON_CMP 0x0000000EU |
| #define GPTIMER_C1CFG_CCACT_PULSE_ON_CMP 0x0000000FU |
| #define GPTIMER_C1CFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002U |
| #define GPTIMER_C1CFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003U |
| #define GPTIMER_C1CFG_CCACT_CLR_ON_CMP_DIS 0x00000004U |
| #define GPTIMER_C1CFG_CCACT_SET_ON_CMP_DIS 0x00000005U |
| #define GPTIMER_C1CFG_CCACT_TGL_ON_CMP_DIS 0x00000006U |
| #define GPTIMER_C1CFG_CCACT_PULSE_ON_CMP_DIS 0x00000007U |
| #define GPTIMER_C1CFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008U |
| #define GPTIMER_C1CFG_CCACT_SET_ON_CAPT 0x00000009U |
| #define GPTIMER_C1CFG_EDGE_W 2U |
| #define GPTIMER_C1CFG_EDGE_M 0x00000030U |
| #define GPTIMER_C1CFG_EDGE_S 4U |
| #define GPTIMER_C1CFG_EDGE_NONE 0x00000000U |
| #define GPTIMER_C1CFG_EDGE_RISE 0x00000010U |
| #define GPTIMER_C1CFG_EDGE_FALL 0x00000020U |
| #define GPTIMER_C1CFG_EDGE_BOTH 0x00000030U |
| #define GPTIMER_C1CFG_INPUT 0x00000040U |
| #define GPTIMER_C1CFG_INPUT_M 0x00000040U |
| #define GPTIMER_C1CFG_INPUT_S 6U |
| #define GPTIMER_C1CFG_INPUT_EV 0x00000000U |
| #define GPTIMER_C1CFG_INPUT_IO 0x00000040U |
| #define GPTIMER_C1CFG_OUT0 0x00000100U |
| #define GPTIMER_C1CFG_OUT0_M 0x00000100U |
| #define GPTIMER_C1CFG_OUT0_S 8U |
| #define GPTIMER_C1CFG_OUT0_DIS 0x00000000U |
| #define GPTIMER_C1CFG_OUT0_EN 0x00000100U |
| #define GPTIMER_C1CFG_OUT1 0x00000200U |
| #define GPTIMER_C1CFG_OUT1_M 0x00000200U |
| #define GPTIMER_C1CFG_OUT1_S 9U |
| #define GPTIMER_C1CFG_OUT1_DIS 0x00000000U |
| #define GPTIMER_C1CFG_OUT1_EN 0x00000200U |
| #define GPTIMER_C1CFG_OUT2 0x00000400U |
| #define GPTIMER_C1CFG_OUT2_M 0x00000400U |
| #define GPTIMER_C1CFG_OUT2_S 10U |
| #define GPTIMER_C1CFG_OUT2_DIS 0x00000000U |
| #define GPTIMER_C1CFG_OUT2_EN 0x00000400U |
| #define GPTIMER_C1CFG_OUT3 0x00000800U |
| #define GPTIMER_C1CFG_OUT3_M 0x00000800U |
| #define GPTIMER_C1CFG_OUT3_S 11U |
| #define GPTIMER_C1CFG_OUT3_DIS 0x00000000U |
| #define GPTIMER_C1CFG_OUT3_EN 0x00000800U |
| #define GPTIMER_C2CFG_CCACT_W 4U |
| #define GPTIMER_C2CFG_CCACT_M 0x0000000FU |
| #define GPTIMER_C2CFG_CCACT_S 0U |
| #define GPTIMER_C2CFG_CCACT_DIS 0x00000000U |
| #define GPTIMER_C2CFG_CCACT_SET_ON_CAPT_DIS 0x00000001U |
| #define GPTIMER_C2CFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000AU |
| #define GPTIMER_C2CFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000BU |
| #define GPTIMER_C2CFG_CCACT_CLR_ON_CMP 0x0000000CU |
| #define GPTIMER_C2CFG_CCACT_SET_ON_CMP 0x0000000DU |
| #define GPTIMER_C2CFG_CCACT_TGL_ON_CMP 0x0000000EU |
| #define GPTIMER_C2CFG_CCACT_PULSE_ON_CMP 0x0000000FU |
| #define GPTIMER_C2CFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002U |
| #define GPTIMER_C2CFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003U |
| #define GPTIMER_C2CFG_CCACT_CLR_ON_CMP_DIS 0x00000004U |
| #define GPTIMER_C2CFG_CCACT_SET_ON_CMP_DIS 0x00000005U |
| #define GPTIMER_C2CFG_CCACT_TGL_ON_CMP_DIS 0x00000006U |
| #define GPTIMER_C2CFG_CCACT_PULSE_ON_CMP_DIS 0x00000007U |
| #define GPTIMER_C2CFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008U |
| #define GPTIMER_C2CFG_CCACT_SET_ON_CAPT 0x00000009U |
| #define GPTIMER_C2CFG_EDGE_W 2U |
| #define GPTIMER_C2CFG_EDGE_M 0x00000030U |
| #define GPTIMER_C2CFG_EDGE_S 4U |
| #define GPTIMER_C2CFG_EDGE_NONE 0x00000000U |
| #define GPTIMER_C2CFG_EDGE_RISE 0x00000010U |
| #define GPTIMER_C2CFG_EDGE_FALL 0x00000020U |
| #define GPTIMER_C2CFG_EDGE_BOTH 0x00000030U |
| #define GPTIMER_C2CFG_INPUT 0x00000040U |
| #define GPTIMER_C2CFG_INPUT_M 0x00000040U |
| #define GPTIMER_C2CFG_INPUT_S 6U |
| #define GPTIMER_C2CFG_INPUT_EV 0x00000000U |
| #define GPTIMER_C2CFG_INPUT_IO 0x00000040U |
| #define GPTIMER_C2CFG_OUT0 0x00000100U |
| #define GPTIMER_C2CFG_OUT0_M 0x00000100U |
| #define GPTIMER_C2CFG_OUT0_S 8U |
| #define GPTIMER_C2CFG_OUT0_DIS 0x00000000U |
| #define GPTIMER_C2CFG_OUT0_EN 0x00000100U |
| #define GPTIMER_C2CFG_OUT1 0x00000200U |
| #define GPTIMER_C2CFG_OUT1_M 0x00000200U |
| #define GPTIMER_C2CFG_OUT1_S 9U |
| #define GPTIMER_C2CFG_OUT1_DIS 0x00000000U |
| #define GPTIMER_C2CFG_OUT1_EN 0x00000200U |
| #define GPTIMER_C2CFG_OUT2 0x00000400U |
| #define GPTIMER_C2CFG_OUT2_M 0x00000400U |
| #define GPTIMER_C2CFG_OUT2_S 10U |
| #define GPTIMER_C2CFG_OUT2_DIS 0x00000000U |
| #define GPTIMER_C2CFG_OUT2_EN 0x00000400U |
| #define GPTIMER_C2CFG_OUT3 0x00000800U |
| #define GPTIMER_C2CFG_OUT3_M 0x00000800U |
| #define GPTIMER_C2CFG_OUT3_S 11U |
| #define GPTIMER_C2CFG_OUT3_DIS 0x00000000U |
| #define GPTIMER_C2CFG_OUT3_EN 0x00000800U |
| #define GPTIMER_C3CFG_CCACT_W 4U |
| #define GPTIMER_C3CFG_CCACT_M 0x0000000FU |
| #define GPTIMER_C3CFG_CCACT_S 0U |
| #define GPTIMER_C3CFG_CCACT_DIS 0x00000000U |
| #define GPTIMER_C3CFG_CCACT_SET_ON_CAPT_DIS 0x00000001U |
| #define GPTIMER_C3CFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000AU |
| #define GPTIMER_C3CFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000BU |
| #define GPTIMER_C3CFG_CCACT_CLR_ON_CMP 0x0000000CU |
| #define GPTIMER_C3CFG_CCACT_SET_ON_CMP 0x0000000DU |
| #define GPTIMER_C3CFG_CCACT_TGL_ON_CMP 0x0000000EU |
| #define GPTIMER_C3CFG_CCACT_PULSE_ON_CMP 0x0000000FU |
| #define GPTIMER_C3CFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002U |
| #define GPTIMER_C3CFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003U |
| #define GPTIMER_C3CFG_CCACT_CLR_ON_CMP_DIS 0x00000004U |
| #define GPTIMER_C3CFG_CCACT_SET_ON_CMP_DIS 0x00000005U |
| #define GPTIMER_C3CFG_CCACT_TGL_ON_CMP_DIS 0x00000006U |
| #define GPTIMER_C3CFG_CCACT_PULSE_ON_CMP_DIS 0x00000007U |
| #define GPTIMER_C3CFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008U |
| #define GPTIMER_C3CFG_CCACT_SET_ON_CAPT 0x00000009U |
| #define GPTIMER_C3CFG_EDGE_W 2U |
| #define GPTIMER_C3CFG_EDGE_M 0x00000030U |
| #define GPTIMER_C3CFG_EDGE_S 4U |
| #define GPTIMER_C3CFG_EDGE_NONE 0x00000000U |
| #define GPTIMER_C3CFG_EDGE_RISE 0x00000010U |
| #define GPTIMER_C3CFG_EDGE_FALL 0x00000020U |
| #define GPTIMER_C3CFG_EDGE_BOTH 0x00000030U |
| #define GPTIMER_C3CFG_INPUT 0x00000040U |
| #define GPTIMER_C3CFG_INPUT_M 0x00000040U |
| #define GPTIMER_C3CFG_INPUT_S 6U |
| #define GPTIMER_C3CFG_INPUT_EV 0x00000000U |
| #define GPTIMER_C3CFG_INPUT_IO 0x00000040U |
| #define GPTIMER_C3CFG_OUT0 0x00000100U |
| #define GPTIMER_C3CFG_OUT0_M 0x00000100U |
| #define GPTIMER_C3CFG_OUT0_S 8U |
| #define GPTIMER_C3CFG_OUT0_DIS 0x00000000U |
| #define GPTIMER_C3CFG_OUT0_EN 0x00000100U |
| #define GPTIMER_C3CFG_OUT1 0x00000200U |
| #define GPTIMER_C3CFG_OUT1_M 0x00000200U |
| #define GPTIMER_C3CFG_OUT1_S 9U |
| #define GPTIMER_C3CFG_OUT1_DIS 0x00000000U |
| #define GPTIMER_C3CFG_OUT1_EN 0x00000200U |
| #define GPTIMER_C3CFG_OUT2 0x00000400U |
| #define GPTIMER_C3CFG_OUT2_M 0x00000400U |
| #define GPTIMER_C3CFG_OUT2_S 10U |
| #define GPTIMER_C3CFG_OUT2_DIS 0x00000000U |
| #define GPTIMER_C3CFG_OUT2_EN 0x00000400U |
| #define GPTIMER_C3CFG_OUT3 0x00000800U |
| #define GPTIMER_C3CFG_OUT3_M 0x00000800U |
| #define GPTIMER_C3CFG_OUT3_S 11U |
| #define GPTIMER_C3CFG_OUT3_DIS 0x00000000U |
| #define GPTIMER_C3CFG_OUT3_EN 0x00000800U |
| #define GPTIMER_PTGT_VAL_W 32U |
| #define GPTIMER_PTGT_VAL_M 0xFFFFFFFFU |
| #define GPTIMER_PTGT_VAL_S 0U |
| #define GPTIMER_PC0CC_VAL_W 32U |
| #define GPTIMER_PC0CC_VAL_M 0xFFFFFFFFU |
| #define GPTIMER_PC0CC_VAL_S 0U |
| #define GPTIMER_PC1CC_VAL_W 32U |
| #define GPTIMER_PC1CC_VAL_M 0xFFFFFFFFU |
| #define GPTIMER_PC1CC_VAL_S 0U |
| #define GPTIMER_PC2CC_VAL_W 32U |
| #define GPTIMER_PC2CC_VAL_M 0xFFFFFFFFU |
| #define GPTIMER_PC2CC_VAL_S 0U |
| #define GPTIMER_PC3CC_VAL_W 32U |
| #define GPTIMER_PC3CC_VAL_M 0xFFFFFFFFU |
| #define GPTIMER_PC3CC_VAL_S 0U |
| #define GPTIMER_TGT_VAL_W 32U |
| #define GPTIMER_TGT_VAL_M 0xFFFFFFFFU |
| #define GPTIMER_TGT_VAL_S 0U |
| #define GPTIMER_C0CC_VAL_W 32U |
| #define GPTIMER_C0CC_VAL_M 0xFFFFFFFFU |
| #define GPTIMER_C0CC_VAL_S 0U |
| #define GPTIMER_C1CC_VAL_W 32U |
| #define GPTIMER_C1CC_VAL_M 0xFFFFFFFFU |
| #define GPTIMER_C1CC_VAL_S 0U |
| #define GPTIMER_C2CC_VAL_W 32U |
| #define GPTIMER_C2CC_VAL_M 0xFFFFFFFFU |
| #define GPTIMER_C2CC_VAL_S 0U |
| #define GPTIMER_C3CC_VAL_W 32U |
| #define GPTIMER_C3CC_VAL_M 0xFFFFFFFFU |
| #define GPTIMER_C3CC_VAL_S 0U |
| #define GPTIMER_PTGTNC_VAL_W 32U |
| #define GPTIMER_PTGTNC_VAL_M 0xFFFFFFFFU |
| #define GPTIMER_PTGTNC_VAL_S 0U |
| #define GPTIMER_PC0CCNC_VAL_W 32U |
| #define GPTIMER_PC0CCNC_VAL_M 0xFFFFFFFFU |
| #define GPTIMER_PC0CCNC_VAL_S 0U |
| #define GPTIMER_PC1CCNC_VAL_W 32U |
| #define GPTIMER_PC1CCNC_VAL_M 0xFFFFFFFFU |
| #define GPTIMER_PC1CCNC_VAL_S 0U |
| #define GPTIMER_PC2CCNC_VAL_W 32U |
| #define GPTIMER_PC2CCNC_VAL_M 0xFFFFFFFFU |
| #define GPTIMER_PC2CCNC_VAL_S 0U |
| #define GPTIMER_PC3CCNC_VAL_W 32U |
| #define GPTIMER_PC3CCNC_VAL_M 0xFFFFFFFFU |
| #define GPTIMER_PC3CCNC_VAL_S 0U |
| #define GPTIMER_TGTNC_VAL_W 32U |
| #define GPTIMER_TGTNC_VAL_M 0xFFFFFFFFU |
| #define GPTIMER_TGTNC_VAL_S 0U |
| #define GPTIMER_C0CCNC_VAL_W 32U |
| #define GPTIMER_C0CCNC_VAL_M 0xFFFFFFFFU |
| #define GPTIMER_C0CCNC_VAL_S 0U |
| #define GPTIMER_C1CCNC_VAL_W 32U |
| #define GPTIMER_C1CCNC_VAL_M 0xFFFFFFFFU |
| #define GPTIMER_C1CCNC_VAL_S 0U |
| #define GPTIMER_C2CCNC_VAL_W 32U |
| #define GPTIMER_C2CCNC_VAL_M 0xFFFFFFFFU |
| #define GPTIMER_C2CCNC_VAL_S 0U |
| #define GPTIMER_C3CCNC_VAL_W 32U |
| #define GPTIMER_C3CCNC_VAL_M 0xFFFFFFFFU |
| #define GPTIMER_C3CCNC_VAL_S 0U |
| #define GPTIMER_CLKCFG_ENABLE 0x00000001U |
| #define GPTIMER_CLKCFG_ENABLE_M 0x00000001U |
| #define GPTIMER_CLKCFG_ENABLE_S 0U |