dma.h

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/******************************************************************************
 *  Filename:       dma.h
 *
 *  Description:    Defines and prototypes for the DMA peripheral.
 *
 *  Copyright (c) 2022-2025 Texas Instruments Incorporated
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1) Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *  2) Redistributions in binary form must reproduce the above copyright notice,
 *     this list of conditions and the following disclaimer in the documentation
 *     and/or other materials provided with the distribution.
 *
 *  3) Neither the name of the copyright holder nor the names of its
 *     contributors may be used to endorse or promote products derived from this
 *     software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************/

#ifndef __DMA_H__
#define __DMA_H__

//*****************************************************************************
//
//
//*****************************************************************************

#include "../inc/hw_types.h"
#include "../inc/hw_memmap.h"
#include "../inc/hw_host_dma.h"
#include "../inc/hw_soc_aaon.h"
#include "../inc/hw_soc_aon.h"
#include "debug.h"

//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C" {
#endif

#define DMA_NUM_CHANNELS            12
#define DMA_CH_OFFSET               0x1000
#define DMA_CHCTL_FIELD_WIDTH       HOST_DMA_CHCTL0_CH0_W
#define DMA_CHCTRL_NUMBER_OF_FIELDS (32 / DMA_CHCTL_FIELD_WIDTH)

//*****************************************************************************
//
// Configuration values that can be passed to DMAConfigureChannel() as the config parameter
//
//*****************************************************************************
#define DMA_CONFIG_SRC_PTR_WRAP       HOST_DMA_CH0JCTL_BLKMODESRC
#define DMA_CONFIG_DST_PTR_WRAP       HOST_DMA_CH0JCTL_BLKMODEDST
#define DMA_CONFIG_FORCE_REQ          HOST_DMA_CH0JCTL_DMASIGBPS
#define DMA_CONFIG_SRC_PTR_FIFO       HOST_DMA_CH0JCTL_FIFOMODS
#define DMA_CONFIG_DST_PTR_FIFO       HOST_DMA_CH0JCTL_FIFOMODD
#define DMA_CONFIG_RX                 0x00000000U
#define DMA_CONFIG_TX                 HOST_DMA_CH0JCTL_SRCDSTCFG
#define DMA_CONFIG_CLEAR_AT_JOB_START HOST_DMA_CH0JCTL_ENCLR
#define DMA_CONFIG_ALLOWED_MASK                                                                           \
    (DMA_CONFIG_SRC_PTR_WRAP | DMA_CONFIG_DST_PTR_WRAP | DMA_CONFIG_FORCE_REQ | DMA_CONFIG_SRC_PTR_FIFO | \
     DMA_CONFIG_DST_PTR_FIFO | DMA_CONFIG_TX | DMA_CONFIG_CLEAR_AT_JOB_START)

//*****************************************************************************
//
// Word size values that can be passed to DMAConfigureChannel() as the wordSize parameter
//
//*****************************************************************************
#define DMA_WORD_SIZE_1B 2
#define DMA_WORD_SIZE_2B 1
#define DMA_WORD_SIZE_4B 0

//*****************************************************************************
//
// Enumerations
//
//*****************************************************************************
// DMA peripheral mapping (source:
// https://confluence.itg.ti.com/display/WNG/Host+DMA#HostDMA-HostDMAAppendix1-Channelsallocation)
typedef enum
{
    DMA_PERIPH_UARTLIN_0 = 0,  
    DMA_PERIPH_UARTLIN_1 = 1,  
    DMA_PERIPH_SPI_0     = 2,  
    DMA_PERIPH_SPI_1     = 3,  
    DMA_PERIPH_I2C_0     = 4,  
    DMA_PERIPH_I2C_1     = 5,  
    DMA_PERIPH_SDMMC     = 6,  
    DMA_PERIPH_SDIO      = 7,  
    DMA_PERIPH_MCAN      = 8,  
    DMA_PERIPH_ADC       = 9,  
    DMA_PERIPH_PDM       = 10, 
    DMA_PERIPH_HIF       = 11, 
    DMA_PERIPH_UARTLIN_2 = 12, 
    DMA_NUM_PERIPHS      = 13  
} DMAPeripheral;

// TODO: Update to use DOC release defines when available (LPRFXXWARE-747)
typedef enum
{
    DMA_HW_EVT_NO_EVENT   = 0, 
    DMA_HW_EVT_TRANS_DONE = 1, 
    DMA_HW_EVT_ABORTED    = 2, 
    DMA_HW_EVT_EXC        = 4  
} DMAChannelStatus;

typedef enum
{
    DMA_CMD_RUN   = 1,
    DMA_CMD_ABORT = 2,
    DMA_CMD_INIT  = 4
} DMACommand;

//*****************************************************************************
//
// Functions
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
extern void DMAInitChannel(uint32_t channel, DMAPeripheral peripheral);

//*****************************************************************************
//
//
//*****************************************************************************
extern void DMAConfigureChannel(uint32_t channel, uint8_t blockSize, uint8_t wordSize, uint32_t config);

//*****************************************************************************
//
//
//*****************************************************************************
extern void DMAStartTransaction(uint32_t channel,
                                const uint32_t *srcStartAddr,
                                uint32_t *dstStartAddr,
                                uint16_t transLenByte,
                                bool remainingBytesBurst);

//*****************************************************************************
//
//
//*****************************************************************************
extern uint32_t DMAGetChannelStatus(uint32_t channel);

//*****************************************************************************
//
//
//*****************************************************************************
extern uint32_t DMAGetChannelDirection(uint32_t channel);

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void DMAEnableInt(uint32_t channelMask)
{
    // Enable the specified interrupts.
    HWREG(SOC_AAON_BASE + SOC_AAON_O_DMASIMASK) |= channelMask;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void DMADisableInt(uint32_t channelMask)
{
    // Disable the specified interrupts.
    HWREG(SOC_AAON_BASE + SOC_AAON_O_DMASIMASK) &= ~(channelMask);
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void DMAClearInt(uint32_t channelMask)
{
    // Clear the requested interrupt sources
    HWREG(SOC_AAON_BASE + SOC_AAON_O_DMASICLR) = channelMask;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE uint32_t DMAIntStatus(bool masked)
{
    // Return either the masked interrupt status or the raw interrupt status as
    // requested.
    if (masked)
    {
        return (HWREG(SOC_AAON_BASE + SOC_AAON_O_DMASMIS));
    }
    else
    {
        return (HWREG(SOC_AAON_BASE + SOC_AAON_O_DMASICLR));
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void DMAConfigureChannelFlags(uint32_t channel, uint32_t config)
{
    // Check arguments
    ASSERT(channel < DMA_NUM_CHANNELS);
    // Check allowed flags and not allowed flags
    ASSERT((~(DMA_CONFIG_ALLOWED_MASK)&config) == 0);

    uint32_t regOffset = channel * DMA_CH_OFFSET;
    uint32_t configReg = HWREG(HOST_DMA_TGT_BASE + HOST_DMA_O_CH0JCTL + regOffset);

    // Clear flags
    configReg &= ~DMA_CONFIG_ALLOWED_MASK;

    // Incorporate flags to configuration value
    configReg |= config;

    // Write configuration to hardware
    HWREG(HOST_DMA_TGT_BASE + HOST_DMA_O_CH0JCTL + regOffset) = configReg;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void DMAEnableDestinationFifoMode(uint32_t channel)
{
    // Check arguments
    ASSERT(channel < DMA_NUM_CHANNELS);

    uint32_t regOffset = channel * DMA_CH_OFFSET;

    HWREG(HOST_DMA_TGT_BASE + HOST_DMA_O_CH0JCTL + regOffset) |= HOST_DMA_CH0JCTL_FIFOMODD;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void DMADisableDestinationFifoMode(uint32_t channel)
{
    // Check arguments
    ASSERT(channel < DMA_NUM_CHANNELS);

    uint32_t regOffset = channel * DMA_CH_OFFSET;

    HWREG(HOST_DMA_TGT_BASE + HOST_DMA_O_CH0JCTL + regOffset) &= ~HOST_DMA_CH0JCTL_FIFOMODD;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE uint32_t DMAGetChannelPeripheral(uint32_t channel)
{
    uint32_t regOffset;
    uint32_t shiftValue;
    uint32_t channelReg;
    uint32_t peripheral;

    // Calculate register offset (0/4) based on the channel number
    regOffset = (channel / DMA_CHCTRL_NUMBER_OF_FIELDS) * sizeof(uint32_t);

    // Read register containing channel configuration
    channelReg = HWREG(HOST_DMA_TGT_BASE + HOST_DMA_O_CHCTL0 + regOffset);

    // Calculate bitfield position based on the channel number
    shiftValue = (channel % DMA_CHCTRL_NUMBER_OF_FIELDS) * DMA_CHCTL_FIELD_WIDTH;

    // Extract the peripheral
    peripheral = (channelReg & (HOST_DMA_CHCTL0_CH0_M << shiftValue)) >> shiftValue;

    return peripheral;
}

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif

//*****************************************************************************
//
//
//*****************************************************************************

#endif // __DMA_H__