UART2WFF3 Hardware attributes. More...

#include <UART2WFF3.h>

Data Fields
UART2_BASE_HWATTRS uint32_t	txDmaChannel

uint32_t	rxDmaChannel

int32_t	txPinMux

int32_t	rxPinMux

int32_t	ctsPinMux

int32_t	rtsPinMux

UART2WFF3_CodingScheme	codingScheme

uint8_t	irLPClkDivider

uint8_t	powerID

bool	concatenateFIFO

Detailed Description

UART2WFF3 Hardware attributes.

The baseAddr and intNum fields are used by driverlib APIs and therefore must be populated by driverlib macro definitions. These definitions are found under the device family in:

inc/hw_memmap.h
inc/hw_ints.h
driverlib/uart.h

intPriority is the UART peripheral's interrupt priority. This value is passed unmodified to HwiP_construct().

The WiFi F3 devices use three priority bits. That means ~0 has the same effect as (7 << 5).

Setting the priority to 0 is not supported by this driver. HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver.

A sample structure is shown below:

const UART2WFF3_HWAttrs UART2WFF3_hwAttrs[] = {
    {
         .baseAddr           = UARTLIN0_BASE,
         .intNum             = INT_SP_UART_0,
         .intPriority        = (~0),
         .rxPin              = CONFIG_GPIO_UART2_0_RX,
         .txPin              = CONFIG_GPIO_UART2_0_TX,
         .ctsPin             = GPIO_INVALID_INDEX,
         .rtsPin             = GPIO_INVALID_INDEX,
         .flowControl        = UART2_FLOWCTRL_NONE,
         .txPinMux           = 5,
         .rxPinMux           = 3,
         .ctsPinMux          = GPIO_MUX_GPIO_INTERNAL,
         .rtsPinMux          = GPIO_MUX_GPIO_INTERNAL,
         .rxDmaChannel       = 0,
         .txDmaChannel       = 1,
         .codingScheme       = UART2WFF3_CODING_UART,
         .concatenateFIFO    = false,
    },
};

To enable flow control, the .ctsPin and/or .rtsPin must be assigned. In addition, .flowControl must be set to UART2_FLOWCTRL_HARDWARE.

Field Documentation

§ txDmaChannel

UART2_BASE_HWATTRS uint32_t UART2WFF3_HWAttrs::txDmaChannel

DMA TX channel number

§ rxDmaChannel

uint32_t UART2WFF3_HWAttrs::rxDmaChannel

DMA RX channel number

§ txPinMux

int32_t UART2WFF3_HWAttrs::txPinMux

TX PIN mux value

§ rxPinMux

int32_t UART2WFF3_HWAttrs::rxPinMux

RX PIN mux value

§ ctsPinMux

int32_t UART2WFF3_HWAttrs::ctsPinMux

CTS PIN mux value for flow control

§ rtsPinMux

int32_t UART2WFF3_HWAttrs::rtsPinMux

RTS PIN mux value for flow control

§ codingScheme

UART2WFF3_CodingScheme UART2WFF3_HWAttrs::codingScheme

UART TXD/RXD encoding/decoding scheme

§ irLPClkDivider

uint8_t UART2WFF3_HWAttrs::irLPClkDivider

Clock divider for IR Low-Power mode

§ powerID

uint8_t UART2WFF3_HWAttrs::powerID

Power driver ID for this UART instance

§ concatenateFIFO

bool UART2WFF3_HWAttrs::concatenateFIFO

Concatenate RX and TX FIFO if write-only

The documentation for this struct was generated from the following file:

UART2WFF3.h

Data Fields