#include <SDWFF3.h>

Data Fields
uint32_t	baseAddr

uint32_t	intNum

uint32_t	intPriority

PowerWFF3_Resource	powerID

uint32_t	DmaChannel

uint8_t	clkPin

uint8_t	clkPinMux

uint8_t	cmdPin

uint8_t	cmdPinMux

uint8_t	data0Pin

uint8_t	data0PinMux

uint8_t	data1Pin

uint8_t	data1PinMux

uint8_t	data2Pin

uint8_t	data2PinMux

uint8_t	data3Pin

uint8_t	data3PinMux

uint8_t	cdPin

uint8_t	cdPinMux

uint8_t	wpPin

uint8_t	wpPinMux

uint8_t	powPin

uint8_t	powPinMux

uint32_t	numData

uint32_t	divClk

bool	cdEnable

bool	cdPolHigh

bool	wpEnable

bool	wpPolHigh

bool	powEnable

bool	powerOffInSleep

Field Documentation

§ baseAddr

uint32_t SDWFF3_HwAttrs::baseAddr

SD HW register base address

§ intNum

uint32_t SDWFF3_HwAttrs::intNum

Interrupt number for HWip driver

§ intPriority

uint32_t SDWFF3_HwAttrs::intPriority

Interrupt priority for HWip driver

§ powerID

PowerWFF3_Resource SDWFF3_HwAttrs::powerID

Peripheral ID for power driver

§ DmaChannel

uint32_t SDWFF3_HwAttrs::DmaChannel

DMA channel for SD

§ clkPin

uint8_t SDWFF3_HwAttrs::clkPin

GPIO number for clock I/F

§ clkPinMux

uint8_t SDWFF3_HwAttrs::clkPinMux

GPIO mode number for clock I/F

§ cmdPin

uint8_t SDWFF3_HwAttrs::cmdPin

GPIO number for command I/F

§ cmdPinMux

uint8_t SDWFF3_HwAttrs::cmdPinMux

GPIO mode number for command I/F

§ data0Pin

uint8_t SDWFF3_HwAttrs::data0Pin

GPIO number for data 0 I/F

§ data0PinMux

uint8_t SDWFF3_HwAttrs::data0PinMux

GPIO mode number for data 0 I/F

§ data1Pin

uint8_t SDWFF3_HwAttrs::data1Pin

GPIO number for data 1 I/F

§ data1PinMux

uint8_t SDWFF3_HwAttrs::data1PinMux

GPIO mode number for data 1 I/F

§ data2Pin

uint8_t SDWFF3_HwAttrs::data2Pin

GPIO number for data 2 I/F

§ data2PinMux

uint8_t SDWFF3_HwAttrs::data2PinMux

GPIO mode number for data 2 I/F

§ data3Pin

uint8_t SDWFF3_HwAttrs::data3Pin

GPIO number for data 3 I/F

§ data3PinMux

uint8_t SDWFF3_HwAttrs::data3PinMux

GPIO mode number for data 3 I/F

§ cdPin

uint8_t SDWFF3_HwAttrs::cdPin

GPIO number for card detect I/F

§ cdPinMux

uint8_t SDWFF3_HwAttrs::cdPinMux

GPIO mode number for card detect I/F

§ wpPin

uint8_t SDWFF3_HwAttrs::wpPin

GPIO number for write protect I/F

§ wpPinMux

uint8_t SDWFF3_HwAttrs::wpPinMux

GPIO mode number write protect I/F

§ powPin

uint8_t SDWFF3_HwAttrs::powPin

GPIO number for HW power supply I/F

§ powPinMux

uint8_t SDWFF3_HwAttrs::powPinMux

GPIO mode number for HW power supply I/F

§ numData

uint32_t SDWFF3_HwAttrs::numData

Number of data lines

§ divClk

uint32_t SDWFF3_HwAttrs::divClk

Card clock divider

§ cdEnable

bool SDWFF3_HwAttrs::cdEnable

Card detect enable

§ cdPolHigh

bool SDWFF3_HwAttrs::cdPolHigh

Is Card detect polarity high

§ wpEnable

bool SDWFF3_HwAttrs::wpEnable

Write protect enable

§ wpPolHigh

bool SDWFF3_HwAttrs::wpPolHigh

Is Write protect polarity high

§ powEnable

bool SDWFF3_HwAttrs::powEnable

HW power supply enable

§ powerOffInSleep

bool SDWFF3_HwAttrs::powerOffInSleep

Card power off when host sleep

The documentation for this struct was generated from the following file:

SDWFF3.h

Data Fields