SOC_DEBUGSS

This section provides information on the SOC_DEBUGSS Module Instance within this product. Each of the registers within the Module Instance is described separately below.

SOC_DEBUGSS Registers Mapping Summary

:SOC_DEBUGSS Common Register Mapping Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset
CFGAPDEVID	RO	32	0bxxxx xxxx xxxx xxxx xxxx xxxx x010 1111	0x0000 0000
CFGAPDEVUC	RO	32	0x0000 0000	0x0000 0004
DBGSSVER	RO	32	0x4000 0098	0x0000 0008
RESERVED	RW	32	0x0000 0000	0x0000 000C
CFGAPBOOT	RO	32	0x0000 0000	0x0000 0010
CFGAPLCST	RO	32	0x0000 0000	0x0000 0014
DFTEN	RW	32	0x0000 0000	0x0000 0018
RSTREQ	RW	32	0x0000 0000	0x0000 001C
CFGAPUDID0	RO	32	0x0000 0000	0x0000 0028
CFGAPUDID1	RO	32	0x0000 0000	0x0000 002C
CFGAPIDR	RO	32	0x102E 0001	0x0000 00FC
PWRAPDP0	RW	32	0x0000 0000	0x0000 0100
PWRAPDP1	RW	32	0x0000 0000	0x0000 0104
PWRAPDP2	RW	32	0x0000 0000	0x0000 0108
PWRAPDP3	RW	32	0x0000 0000	0x0000 010C
PWRAPIDR	RO	32	0x002E 0002	0x0000 01FC
SECAPTXD	RW	32	0x0000 0000	0x0000 0200
SECAPTXCTL	RW	32	0x0000 0000	0x0000 0204
SECAPRXD	RO	32	0x0000 0000	0x0000 0208
RXCTL	RW	32	0x0000 0000	0x0000 020C
SECAPIDR	RO	32	0x002E 0000	0x0000 02FC
ETAPSEL	RW	32	0xXXXX XXFF	0x0000 0300
ETAPCAPCTL	RO	32	0x0000 0007	0x0000 0304
ETAPSTARD	RO	32	0x0000 0000	0x0000 0308
ETAPDMNCTL	RW	32	0xXXXX XXXX	0x0000 030C
ETAPIDR	RO	32	0x002E 0003	0x0000 03FC

SOC_DEBUGSS Instances Register Mapping Summary

SOC_DEBUGSS Register Descriptions

:SOC_DEBUGSS Common Register Descriptions

:SOC_DEBUGSS:CFGAPDEVID

Address offset	0x0000 0000
Description	CFGAP Device ID. The device identification register allows the manufacturer, part number, and version of a component to be determined. This is the same 32-bit value obtained via the IDCODE instruction in the optional ICEPickM Scan module and is determined by tie-offs at DebugSS boundary.
Type	RO

Bits	Field Name	Description	Type	Reset
31:28	VER	Revision of the device. This field should change each time that the logic or mask set of the device is revised.	RO	0xX
27:12	PARTNUM	Identifies the part	RO	0xXXXX
11:1	MAN	TI's JEDEC bank and company code, which is 00000010111b	RO	0bxxx xx01 0111
0	ALWAYSONE	The value 1 in bit 0 of a JTAG IDCODE means that a 32-bit scan register exists. This is replicated here for completeness.	RO	1

:SOC_DEBUGSS:CFGAPDEVUC

Address offset	0x0000 0004
Description	CFGAP Device User Code. The Device Usercode register is used in conjunction with the Device Identification Register to provide extended device information. This is the same 32-bit value obtained via the USERCODE instruction in the optional ICEPickM Scan module and is determined by tie-offs at DebugSS boundary.
Type	RO

Bits	Field Name	Description			Type	Reset
31:0	USERCODE	The Device Usercode register is used in conjunction with the Device Identification Register to provide extended device information. This is the same 32-bit value obtained via the USERCODE instruction in the optional ICEPickM Scan module and is determined by tie-offs at DebugSS boundary.			RO	0x0000 0000

:SOC_DEBUGSS:DBGSSVER

Address offset	0x0000 0008
Description	CFGAP DEBUGSS Version. The DebugSS Configuration Register provides information on the configuration of this particular instance of the subsystem.
Type	RO

Bits	Field Name	Description	Type	Reset
31:28	REVMAJ	Indicates the major revision of this Subsystem instance.	RO	0x4
27:24	REVMIN	Indicates the minor revision of this Subsystem instance. Currently 0000b	RO	0x0
23:8	RESERVED	RESERVED space write will be ignored and read will result in zeroes	RO	0x0000
7	PWRAP	A value of '1' indicates this subsystem instance contains a Power-AP module	RO	1
6	SYSTEMAP	A value of '1' indicates this subsystem instance contains an AHB-AP module for system bus mastering	RO	0
5	APBAP	A value of '1' indicates this subsystem instance contains an ABP-AP for accessing system level debug components	RO	0
4	SECAP	A value of '1' indicates this subsystem instance contains a Secure AP	RO	1
3	ETAP	A value of '1' indicates this subsystem instance contains an EnergyTrace AP	RO	1
2	ICEPICKM	A value of '1' indicates this subsystem instance contains an ICEPickM Scan module for extended scan support	RO	0
1	TRIG	A value of '1' indicates this subsystem instance contains Cross Trigger submodule	RO	0
0	TRACE	A value of '1' indicates this subsystem instance contains a Trace submodule	RO	0

:SOC_DEBUGSS:RESERVED

Address offset	0x0000 000C
Description	RESERVED space write will be ignored and read will result in zeroes
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	RESERVED32				RW	0x0000 0000

:SOC_DEBUGSS:CFGAPBOOT

Address offset	0x0000 0010
Description	CFGAP Boot Diag. This register provides feedback on the boot process
Type	RO

Bits	Field Name	Description			Type	Reset
31:0	CFGAPBOOT_VALUE	This register provides feedback on the boot process [3:0] PG_Version [5:3] Metal_Version [8:6] Memory Stacking [11:9] Package type [13:12] Temperature [17:14] Device PartNumber [18] Disable 5GHz [19] Disable 6GHz [20] Disable BLE [21] Disable BLE M0+ [22] Disable CAN FD [25:23] Boot ROM Version (FMU) [26] Launch pad Mode [28:27] SDIO Product ID [31:29] TI Fuse ROM Structure Version			RO	0x0000 0000

:SOC_DEBUGSS:CFGAPLCST

Address offset	0x0000 0014
Description	CFGAP Life-cycle. Indicates the current device lifecycle state
Type	RO

Bits	Field Name	Description			Type	Reset
31:0	CFGAPLCST_VALUE	Life cycle state [3:0] PG_Version [5:3] Metal_Version [8:6] Memory Stacking [11:9] Package type [13:12] Temperature [17:14] Device PartNumber [18] Disable 5GHz [19] Disable 6GHz [20] Disable BLE [21] Disable BLE M0+ [22] Disable CAN FD [25:23] Boot ROM Version (FMU) [26] Launch pad Mode [28:27] SDIO Product ID [31:29] TI Fuse ROM Structure Version			RO	0x0000 0000

:SOC_DEBUGSS:DFTEN

Address offset	0x0000 0018
Description	DFT Enable. This bit can be configured to enable multiplexing of JTAG signals on device pins.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	RESERVED	RESERVED	RO	0x0000 0000
0	MEM_DFTEN	This bit can be configured to enable multiplexing of JTAG signals on device pins. Pin #2 --> TCK ;Pin #3 --> TMS ; Pin #10 --> TDI ; Pin #15 --> TDO. Refer to pinout_iomux.xls for more information.	RW	0

:SOC_DEBUGSS:RSTREQ

Address offset	0x0000 001C
Description	Reset Request. This bit can be configured to request reset.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	RESERVED	RESERVED	RO	0x0000 0000
0	MEM_RSTREQ	This bit can be configured to request device reset	WO	0

:SOC_DEBUGSS:CFGAPUDID0

Address offset	0x0000 0028
Description	CFGAP Unique Device 0. Used to provide a unique device ID/token for security authentication of tester and tools. Unique device ID is 64bit value and this register reads lower 32 bits.
Type	RO

Bits	Field Name	Description			Type	Reset
31:0	VAL	Used to provide a unique divide ID/token for security authentication of tester and tools			RO	0x0000 0000

:SOC_DEBUGSS:CFGAPUDID1

Address offset	0x0000 002C
Description	CFGAP Unique Device 1. Used to provide a unique device ID/token for security authentication of tester and tools. Unique device ID is 64bit value and this register reads upper 32 bits.
Type	RO

Bits	Field Name	Description			Type	Reset
31:0	VAL	Used to provide a unique devide ID/token for security authentication of tester and tools			RO	0x0000 0000

:SOC_DEBUGSS:CFGAPIDR

Address offset	0x0000 00FC
Description	CFGAP Identification Register. AP Identification Register. The AP identification register allows tools to determine the manufacturer and the type of AP.
Type	RO

Bits	Field Name	Description	Type	Reset
31:28	CFGAPIDR_REVISION	Component Revision. Indicates the revision of this AP instance. Currently 0001b	RO	0x1
27:17	CFGAPIDR_JEPIDS	Manufacturer JEP106 ID. The concatenated JEP106 ID and continuation ID for TI. This is 00000010111b.	RO	0x017
16	CFGAPIDR_APCLASS	AP Class. 0 indicates that this AP is not a bridge to a memory interconnect (not a Memory Access Port).	RO	0
15:8	RESERVED_CFGAPIDR	reserved.	RO	0x00
7:4	CFGAPIDR_APVAR	AP Variant. There is only one variant for this AP Type and it is 0.	RO	0x0
3:0	CFGAPIDR_APTYPE	The AP Type Register. TI Subsystem Config APs have a type of 0001b	RO	0x1

:SOC_DEBUGSS:PWRAPDP0

Address offset	0x0000 0100
Description	Sub-Domain PREC Register This register provides an interface for debug tooling to obtain status and override the power, reset and execution state of debug targets in dynamically controlled sub-domains.
Type	RW

Bits	Field Name	Description	Type	Reset
31	RESERVED		RO	0
30	RESERVED		RO	0
29	RESERVED		RO	0
28	RESERVED		RO	0
27	RESERVED		RO	0
26	RESERVED		RO	0
25	RESERVED		RO	0
24	RESERVED		RO	0
23	RESERVED	Used to indicate that the domain entered retention since the bit is cleared. Not supported in MX.	RO	0
22	PWRAPDP0_WSOCCPU_RESETOCCURED	Input from CPU-SS. Used by debug tools. A sticky bit Indicate that a reset to WSOC MCU has happened since last time tools checked. Cleared on write by the tool.	RW	0
21	PWRAPDP0_WSOCCPU_POWERLOSS	Input from PRCM. Used by debug tools. A sticky bit Indicate that a power loss to CORE has happened since last time tools checked. Cleared on write by the tool.	RW	0
20	RESERVED		RO	0
19	PWRAPDP0_DEBUGPOWER	Used to indicate power state of debug logic in the associated domain. 0 -> Debug logic is off. 1 -> Debug logic is powered.	RO	0
18	PWRAPDP0_WSOCCPU_UNNATURALRESET	input from PRCM. "1" indicate that WSOC MCU (SYSRSTn) reset is extended.	RO	0
17	PWRAPDP0_WSOCCPU_INRESET_RELEASEWIR	Input from PRCM. "1" indicates WSOC MCU is in reset. Setting this bit shall release the extended SYSRSTn to WSOc MCU.	RW	0
16:14	PWRAPDP0_WSOCCPU_RESETCONTROL	Following are the field values with their description. 000 -> Normal Operation; 001 -> Wait in Reset (Reset Ext); 010 -> Block Reset; 100- > Reset Req.	RW	0x0
13	PWRAPDP0_DEBUGENABLE	Defines operating mode of debug logic in Cortex. Not used in MX.	RW	0
12:11	PWRAPDP0_DEBUGMODE	Used to define debug properties. Not used in MX.	RW	0x0
10	PWRAPDP0_WSOCCPU_DEBUGATTENTION	Input from CPU-SS. "1" indicate that WSOC MCU is halted and in debug mode.	RO	0
9	RESERVED		RO	0
8	RESERVED		RO	0
7	PWRAPDP0_WSOCCPU_POWERDOWNDESIRED	Input from ELP. Indicates that CORE domain can be shutdown.	RO	0
6	RESERVED		RO	0
5	PWRAPDP0_WSOCCPU_POWER	Input from PRCM. "1" indicates CORE domain is powered.	RO	0
4	PWRAPDP0_WSOCCPU_CLOCKDOWNDESIRED	"1" indicated that WSOC MCU is clocked artificially.	RO	0
3	PWRAPDP0_WSOCCPU_FORCEACTIVE	Provides debug override of the default state of the CORE P.D power and clock.	RW	0
2	PWRAPDP0_WSOCCPU_CLOCKSTATE	Input from CPU-SS. "1" indicated that WSOC MCU is clocked by it's functional clock.	RO	0
1	PWRAPDP0_WSOCCPU_CORESACCESSABLE	Input from DSSM. Indicate that WSOC MCU Power-AP overrides are writable.	RO	0
0	PWRAPDP0_WSOCCPU_COREPRESENT	1 indicates that WSOC MCU is present in this Osprey device.	RO	0

:SOC_DEBUGSS:PWRAPDP1

Address offset	0x0000 0104
Description	Sub-Domain PREC Register This register provides an interface for debug tooling to obtain status and override the power, reset and execution state of debug targets in dynamically controlled sub-domains.
Type	RW

Bits	Field Name	Description	Type	Reset
31	RESERVED		RO	0
30	RESERVED		RO	0
29	RESERVED		RO	0
28	RESERVED		RO	0
27	RESERVED		RO	0
26	RESERVED		RO	0
25	RESERVED		RO	0
24	RESERVED		RO	0
23	RESERVED	Used to indicate that the domain entered retention since the bit is cleared. Not supported in MX.	RO	0
22	PWRAPDP1_WPHYCPU_RESETOCCURED	Input from CPU-SS. Used by debug tools. A sticky bit Indicate that a reset to WPHY MCU has happened since last time tools checked. Cleared on write by the tool.	RW	0
21	PWRAPDP1_WPHYCPU_POWERLOSS	Input from PRCM. Used by debug tools. A sticky bit Indicate that a power loss to CORE has happened since last time tools checked. Cleared on write by the tool.	RW	0
20	RESERVED		RO	0
19	PWRAPDP1_DEBUGPOWER	Used to indicate power state of debug logic in the associated domain. 0 -> Debug logic is off. 1 -> Debug logic is powered.	RO	0
18	RESERVED		RO	0
17	PWRAPDP1_WPHYCPU_INRESET	Input from PRCM. "1" indicates WPHY MCU is in reset.	RO	0
16:14	PWRAPDP1_WPHYCPU_RESETCONTROL	Following are the field values with their description. 000 -> Normal Operation; 001 -> Wait in Reset (Reset Ext); 010 -> Block Reset; 100- > Reset Req.	RW	0x0
13	PWRAPDP1_DEBUGENABLE	Defines operating mode of debug logic in Cortex. Not used in MX.	RW	0
12:11	PWRAPDP1_DEBUGMODE	Used to define debug properties. Not used in MX.	RW	0x0
10	PWRAPDP1_WPHYCPU_DEBUGATTENTION	Input from CPU-SS. "1" indicate that WPHY MCU is halted and in debug mode.	RO	0
9	RESERVED		RO	0
8	RESERVED		RO	0
7	PWRAPDP1_WPHYCPU_POWERDOWNDESIRED	Input from ELP. Indicates that CORE domain can be shutdown.	RO	0
6	RESERVED		RO	0
5	PWRAPDP1_WPHYCPU_POWER	Input from PRCM. "1" indicates CORE domain is powered.	RO	0
4	PWRAPDP1_WPHYCPU_CLOCKDOWNDESIRED	Input from ?. "1" indicated that WPHY MCU is clocked artificially.	RO	0
3	PWRAPDP1_WPHYCPU_FORCEACTIVE	Provides debug override of the default state of the CORE P.D power and clock.	RW	0
2	PWRAPDP1_WPHYCPU_CLOCKSTATE	Input from CPU-SS. "1" indicated that WPHY MCU is clocked by it's functional clock.	RO	0
1	PWRAPDP1_WPHYCPU_CORESACCESSABLE	Input from DSSM. Indicate that WSOC MCU, WPHY and LRF MCU (CORE domain cores) Power-AP overrides are writable.	RO	0
0	PWRAPDP1_WPHYCPU_COREPRESENT	1 indicates that WPHY MCU is present in this Osprey device.	RO	0

:SOC_DEBUGSS:PWRAPDP2

Address offset	0x0000 0108
Description	Sub-Domain PREC Register This register provides an interface for debug tooling to obtain status and override the power, reset and execution state of debug targets in dynamically controlled sub-domains.
Type	RW

Bits	Field Name	Description	Type	Reset
31	RESERVED		RO	0
30	RESERVED		RO	0
29	RESERVED		RO	0
28	RESERVED		RO	0
27	RESERVED		RO	0
26	RESERVED		RO	0
25	RESERVED		RO	0
24	RESERVED		RO	0
23	RESERVED	Used to indicate that the domain entered retention since the bit is cleared. Not supported in MX.	RO	0
22	PWRAPDP2_LRFCPU_RESETOCCURED	Input from CPU-SS. Used by debug tools. A sticky bit Indicate that a reset to LRF MCU has happened since last time tools checked. Cleared on write by the tool.	RW	0
21	PWRAPDP2_LRFCPU_POWERLOSS	Input from PRCM. Used by debug tools. A sticky bit Indicate that a power loss to CORE has happened since last time tools checked. Cleared on write by the tool.	RW	0
20	RESERVED		RO	0
19	PWRAPDP2_DEBUGPOWER	Used to indicate power state of debug logic in the associated domain. 0 -> Debug logic is off. 1 -> Debug logic is powered.	RO	0
18	RESERVED		RO	0
17	PWRAPDP2_LRFCPU_INRESET	Input from PRCM. "1" indicates LRF MCU is in reset.	RO	0
16:14	PWRAPDP2_LRFCPU_RESETCONTROL	Following are the field values with their description. 000 -> Normal Operation; 001 -> Wait in Reset (Reset Ext); 010 -> Block Reset; 100- > Reset Req.	RW	0x0
13	PWRAPDP2_DEBUGENABLE	Defines operating mode of debug logic in Cortex. Not used in MX.	RW	0
12:11	PWRAPDP2_DEBUGMODE	Used to define debug properties. Not used in MX.	RW	0x0
10	PWRAPDP2_LRFCPU_DEBUGATTENTION	Input from CPU-SS. "1" indicate that LRF MCU is halted and in debug mode.	RO	0
9	RESERVED		RO	0
8	RESERVED		RO	0
7	PWRAPDP2_LRFCPU_POWERDOWNDESIRED	Input from ELP. Indicates that CORE domain can be shutdown.	RO	0
6	RESERVED		RO	0
5	PWRAPDP2_LRFCPU_POWER	Input from PRCM. "1" indicates CORE domain is powered.	RO	0
4	PWRAPDP2_LRFCPU_CLOCKDOWNDESIRED	Input from ?. "1" indicated that LRF MCU is clocked artificially.	RO	0
3	PWRAPDP2_LRFCPU_FORCEACTIVE	Provides debug override of the default state of the CORE P.D power and clock.	RW	0
2	PWRAPDP2_LRFCPU_CLOCKSTATE	Input from CPU-SS. "1" indicated that LRF MCU is clocked by it's functional clock.	RO	0
1	PWRAPDP2_LRFCPU_CORESACCESSABLE	Input from DSSM. Indicate that WSOC MCU, WPHY and LRF MCU (CORE domain cores) Power-AP overrides are writable.	RO	0
0	PWRAPDP2_LRFCPU_COREPRESENT	1 indicates that LRF MCU is present in this Osprey device.	RO	0

:SOC_DEBUGSS:PWRAPDP3

Address offset	0x0000 010C
Description	Sub-Domain PREC Register This register provides an interface for debug tooling to obtain status and override the power, reset and execution state of debug targets in dynamically controlled sub-domains.
Type	RW

Bits	Field Name	Description	Type	Reset
31	RESERVED		RO	0
30	RESERVED		RO	0
29	RESERVED		RO	0
28	RESERVED		RO	0
27	RESERVED		RO	0
26	RESERVED		RO	0
25	RESERVED		RO	0
24	RESERVED		RO	0
23	RESERVED	Used to indicate that the domain entered retention since the bit is cleared. Not supported in MX.	RO	0
22	PWRAPDP3_APPCPU_RESETOCCURED	Input from CPU-SS. Used by debug tools. A sticky bit Indicate that a reset to APP MCU has happened since last time tools checked. Cleared on write by the tool.	RW	0
21	PWRAPDP3_APPCPU_POWERLOSS	Input from PRCM. Used by debug tools. A sticky bit Indicate that a power loss to HOST has happened since last time tools checked. Cleared on write by the tool.	RW	0
20	RESERVED		RO	0
19	PWRAPDP3_DEBUGPOWER	Used to indicate power state of debug logic in the associated domain. 0 -> Debug logic is off. 1 -> Debug logic is powered.	RO	0
18	PWRAPDP3_APPCPU_UNNATURALRESET	input from PRCM. "1" indicate that APPCPU (SYSRSTn) reset is extended.	RO	0
17	PWRAPDP3_APPCPU_INRESET_RELEASEWIR	Input from PRCM. "1" indicates APP MCU is in reset.	RO	0
16:14	PWRAPDP3_APPCPU_RESETCONTROL	Following are the field values with their description. 000 -> Normal Operation; 001 -> Wait in Reset (Reset Ext); 010 -> Block Reset; 100- > Reset Req.	RW	0x0
13	PWRAPDP3_DEBUGENABLE	Defines operating mode of debug logic in Cortex. Not used in MX.	RW	0
12:11	PWRAPDP3_DEBUGMODE	Used to define debug properties. Not used in MX.	RW	0x0
10	PWRAPDP3_APPCPU_DEBUGATTENTION	Input from CPU-SS. "1" indicate that APP MCU is halted and in debug mode.	RO	0
9	RESERVED		RO	0
8	RESERVED		RO	0
7	PWRAPDP3_APPCPU_POWERDOWNDESIRED	Input from ?. Indicates that HOST domain can be shutdown.	RO	0
6	RESERVED		RO	0
5	PWRAPDP3_HOST_POWER	Input from PRCM. "1" indicates HOST domain is powered.	RO	0
4	PWRAPDP3_APPCPU_CLOCKDOWNDESIRED	Input from ?. "1" indicated that APP MCU is clocked artificially.	RO	0
3	PWRAPDP3_APPCPU_FORCEACTIVE	Provides debug override of the default state of the HOST P.D power and clock.	RW	0
2	PWRAPDP3_APPCPU_CLOCKSTATE	Input from CPU-SS. "1" indicated that APP MCU is clocked by it's functional clock.	RO	0
1	PWRAPDP3_APPCPU_CORESACCESSABLE	Input from DSSM. Indicate that HOST Power-AP overrides are writable.	RO	0
0	PWRAPDP3_APPCPU_COREPRESENT	1 indicates that APP MCU is present in this Osprey device.	RO	0

:SOC_DEBUGSS:PWRAPIDR

Address offset	0x0000 01FC
Description	PWEAP Identification Register. The AP identification register allows tools to determine the manufacturer and the type of AP.
Type	RO

Bits	Field Name	Description	Type	Reset
31:28	PWRAPIDR_REVISION	Component Revision. Indicates the revision of this AP instance. Currently 0000b	RO	0x0
27:17	PWRAPIDR_JEPIDS	Manufacturer JEP106 ID. The concatenated JEP106 ID and continuation ID for TI. This is 00000010111b.	RO	0x017
16	PWRAPIDR_APCLASS	AP Class. 0 indicates that this is AP is not a bridge to a memory interconnect (not a Memory Access Port).	RO	0
15:8	RESERVED_PWRAPIDR	RESERVED.	RO	0x00
7:4	PWRAPIDR_APVAR	AP Variant. There is only one variant for this AP Type and it is 0.	RO	0x0
3:0	PWRAPIDR_APTYPE	The AP Type Register. TI Subsystem Config APs have a type of 0001b	RO	0x2

:SOC_DEBUGSS:SECAPTXD

Address offset	0x0000 0200
Description	Transmit Data Register. This register is used to pass data to the system security logic.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	SECAPTXD_VALUE	Transmit Data Register. This register is used to pass data to the system security logic.			RW	0x0000 0000

:SOC_DEBUGSS:SECAPTXCTL

Address offset	0x0000 0204
Description	Transmit Control Register. This register provides the handshake for the TX Data Register and can also be used to pass control data to the system security logic.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	SECAPTXCTL_TXCONTROL	Device specific control information from the system security logic	RW	0x0000 0000
0	SECAPTXCTL_TXDATAVAIL	Transmit Data Available. Set automatically when the TX data Register is written Cleared automatically when the system debug logic indicates it has accepted the TX data	RO	0

:SOC_DEBUGSS:SECAPRXD

Address offset	0x0000 0208
Description	Receive Data Register. This register is used to pass data from the system security logic.
Type	RO

Bits	Field Name	Description			Type	Reset
31:0	SECAPRXD_VALUE	Receive Data Register. This register is used to pass data from the system security logic.			RO	0x0000 0000

:SOC_DEBUGSS:RXCTL

Address offset	0x0000 020C
Description	Receive Control Register. This register provides the handshake for the RX Data Register and can also be used to pass control data from the system security logic.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	RXCTL_RXCONTROL	Device specific control information from the system security logic	RW	0x0000 0000
0	RXCTL_RXDATAVAIL	Set automatically when the system security logic indicates that RX Data Register is valid. Cleared automatically when the RX data Register is read.	RO	0

:SOC_DEBUGSS:SECAPIDR

Address offset	0x0000 02FC
Description	AP Identification Register. The AP identification register allows tools to determine the manufacturer and the type of AP.
Type	RO

Bits	Field Name	Description	Type	Reset
31:28	SECAPIDR_REVISION	Component Revision. Indicates the revision of this AP instance.	RO	0x0
27:17	SECAPIDR_JEPIDS	Manufacturer JEP106 ID. The concatenated JEP106 ID and continuation ID for TI. This is 00000010111b.	RO	0x017
16	SECAPIDR_APCLASS	AP Class. 0 indicates that this AP is not a bridge to a memory interconnect (not a Memory Access Port).	RO	0
15:8	RESERVED_SECAPIDR	reserved.	RO	0x00
7:4	SECAPIDR_APVAR	AP Variant. There is only one variant for this AP Type and it is 0.	RO	0x0
3:0	SECAPIDR_APTYPE	The AP Type Register.	RO	0x0

:SOC_DEBUGSS:ETAPSEL

Address offset	0x0000 0300
Description	ETAP Register Selector. Has a bit associated with each 32-bit Status Bitfield in the status array. Bit 0 corresponds to Status Bitfield 0. At reset all available Status Bitfields are selected. After writing this bitfield STATREAD will return the value of the status bitfield with the lowest selected index.
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	RESERVED	Reads to this field return zero, writes to this field are ignored.	RO	0xXX XXXX
7:0	ETAPSEL_VALUE	Has a bit associated with each 32-bit Status Bitfield in the status array. Bit 0 corresponds to Status Bitfield 0. At reset all available Status Bitfields are selected. After writing this bitfield [ETAPSTARD.*] will return the value of the status bitfield with the lowest selected index. Attempting to select an unimplemented register will not set the associated bit.	RW	0xFF

:SOC_DEBUGSS:ETAPCAPCTL

Address offset	0x0000 0304
Description	ETAP Capability Control. This register can be used to read out the capability parameters of EnergyTrace and allows controlling the function.
Type	RO

Bits	Field Name	Description	Type	Reset
31:8	RESERVED	reserved	RO	0x00 0000
7:0	ETAPCAPCTL_NUMREGS	Indicates the number of available 32bit register containing EnergyTrace data. Actual registers is NUMREGS + 1.	RO	0x07

:SOC_DEBUGSS:ETAPSTARD

Address offset	0x0000 0308
Description	ETAP Status Read. Returns the value of the EnergyTrace++ status bitfields. After writing the [ETAPSEL.] bitfield, this register will return the value of the first available status bitfield. Subsequent reads will return the remaining bitfields as selected with [ETAPSEL.].
Type	RO

Bits	Field Name	Description			Type	Reset
31:0	ETAPSTARD_FLAGS	Returns the value of the EnergyTrace++ status bitfields. After writing the [ETAPSEL.] bitfield, this register will return the value of the first available status bitfield. Subsequent reads will return the remaining bitfields as selected with [ETAPSEL.].			RO	0x0000 0000

:SOC_DEBUGSS:ETAPDMNCTL

Address offset	0x0000 030C
Description	ETAP Domain Control. Controls which async domains are included in the async handshake sequence for data capture.
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	RESERVED	reserved	RO	0xXX XXXX
7:0	ETAPDMNCTL_DOMAININCLUDE	Each bit in this bitfield is associated with one of the 16 async domain controls (req/ack) supported by the ET-AP 0 = The domain is not included in the handshake request 1 = The domain is included in the handshake request Osprey MDB, all 8 ET status buses are synchronous, this register will read all zeroes and writes will be ignored. The mapping of domains to specific ET data sources is in device specific documentation	RW	0xXX

:SOC_DEBUGSS:ETAPIDR

Address offset	0x0000 03FC
Description	ETAP Identification Register. AP Identification Register. The AP identification register allows tools to determine the manufacturer and the type of AP.
Type	RO

Bits	Field Name	Description	Type	Reset
31:28	ETAPIDR_REVISION	Component Revision. Indicates the revision of this AP instance. Currently 0000b	RO	0x0
27:17	ETAPIDR_JEPIDS	Manufacturer JEP106 ID. The concatenated JEP106 ID and continuation ID for TI. This is 00000010111b.	RO	0x017
16	ETAPIDR_APCLASS	AP Class. 0 indicates that this is AP is not a bridge to a memory interconnect (not a Memory Access Port).	RO	0
15:8	RESERVED_ETAPIDR	reserved	RO	0x00
7:4	ETAPIDR_APVAR	AP Variant. There is only one variant for this AP Type and it is 0.	RO	0x0
3:0	ETAPIDR_APTYPE	The AP Type Register.	RO	0x3