SOC_AON

This section provides information on the SOC_AON Module Instance within this product. Each of the registers within the Module Instance is described separately below.

SOC_AON Registers. This component include soc_aon register, event manager regisers, security registers and more. INTERNAL NOTE- [Confluence][https://confluence.itg.ti.com/display/WNG/Security+AON+Module-Mx]

SOC_AON Registers Mapping Summary

:SOC_AON Common Register Mapping Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset
M3EVTCTL1	RW	32	0x0000 0000	0x0000 0000
M3IRQCTL2	RW	32	0x0000 0000	0x0000 0004
M3EVTCTL3	RW	32	0x0000 0000	0x0000 0008
SPEVTCTL	RW	32	0x0000 0000	0x0000 000C
TMEVTCTL	RW	32	0x0000 0000	0x0000 0010
GPT0EVTCTL0	RW	32	0x0000 0000	0x0000 0014
GPT1EVTCTL0	RW	32	0x0000 0000	0x0000 0018
DB0M33CLR	RW	32	0x0000 0000	0x0000 001C
DB0M33SET	RW	32	0x0000 0000	0x0000 0020
DB0M33LOCK	RW	32	0x0000 0000	0x0000 0024
DB1M33CLR	RW	32	0x0000 0000	0x0000 0028
DB1M33SET	RW	32	0x0000 0000	0x0000 002C
DB1M33LOCK	RW	32	0x0000 0000	0x0000 0030
DB4M33CLR	RW	32	0x0000 0000	0x0000 0034
DB4M33SET	RW	32	0x0000 0000	0x0000 0038
DB4M33LOCK	RW	32	0x0000 0000	0x0000 003C
DB5M33CLR	RW	32	0x0000 0000	0x0000 0040
DB5M33SET	RW	32	0x0000 0000	0x0000 0044
DB5M33LOCK	RW	32	0x0000 0000	0x0000 0048
CMEMSTART	RW	32	0x0800 0000	0x0000 004C
CMEMEND	RW	32	0x0FFF FFFF	0x0000 0050
DMEMSTART	RW	32	0x2800 0000	0x0000 0054
DMEMEND	RW	32	0x2FFF FFFF	0x0000 0058
TCMSTART	RW	32	0x2000 0000	0x0000 0064
TCMEND	RW	32	0x27FF FFFF	0x0000 0068
GPIOEVTS0	RW	32	0x0000 0000	0x0000 007C
GPIOEVTS1	RW	32	0x0000 0000	0x0000 0080
MEMSSCTL0	RW	32	0x0000 0000	0x0000 0084
MEMSSCTL1	RW	32	0x0000 0000	0x0000 0088
SPARE0	RW	32	0x0000 0000	0x0000 0090
VTORS	RW	32	0x0000 0000	0x0000 009C
VTORNS	RW	32	0x0000 0000	0x0000 00A0
CPULOCKS	RW	32	0x0000 0000	0x0000 00A8
HOSTLOCKS	RW	32	0x0000 0000	0x0000 00AC
HOSTBOOT	RW	32	0x0000 0000	0x0000 00B0
SECCFG	RW	32	0x0000 0000	0x0000 00B4
DBSIMASK	RW	32	0x0000 0000	0x0000 00B8
DBSISET	RW	32	0x0000 0000	0x0000 00BC
DBSICLR	RW	32	0x0000 0000	0x0000 00C0
DBSIMSET	RW	32	0x0000 0000	0x0000 00C4
DBSIMCLR	RW	32	0x0000 0000	0x0000 00C8
DBSRIS	RW	32	0x0000 0000	0x0000 00CC
DBSMIS	RW	32	0x0000 0000	0x0000 00D0
ERRSIMASK	RW	32	0x0000 0000	0x0000 00D4
ERRSISET	RW	32	0x0000 0000	0x0000 00D8
ERRSICLR	RW	32	0x0000 0000	0x0000 00DC
ERRSIMSET	RW	32	0x0000 0000	0x0000 00E0
ERRSIMCLR	RW	32	0x0000 0000	0x0000 00E4
ERRSRIS	RW	32	0x0000 0000	0x0000 00E8
ERRSMIS	RW	32	0x0000 0000	0x0000 00EC
GPT0EVTCTL1	RW	32	0x0000 0000	0x0000 00F0
GPT1EVTCTL1	RW	32	0x0000 0000	0x0000 00F4
ESMSTACST	RW	32	0x0000 0000	0x0000 0104
MEMSSCFG	RW	32	0x0000 0000	0x0000 010C
GPIOMIS0S	RW	32	0x0000 0000	0x0000 0138
GPIOMIS1S	RW	32	0x0000 0000	0x0000 013C
GPIOFNC0S	RW	32	0x0000 0000	0x0000 0140
GPIOFNC1S	RW	32	0x0000 0000	0x0000 0144
SPARE10	RW	32	0x0000 0000	0x0000 0148
ESM1VAL2ND	RW	32	0x0000 0000	0x0000 014C
ESM2VAL2ND	RW	32	0x0000 0000	0x0000 0150
ESM1STA2ND	RW	32	0x0000 0000	0x0000 0154
ESM2STA2ND	RW	32	0x0000 0000	0x0000 0158
FWCFGHOST	RW	32	0x0000 0001	0x0000 015C
FWCFGDMA	RW	32	0x0000 0001	0x0000 0160
FWCFGFPRPH	RW	32	0x0000 0001	0x0000 0164
FWCFGM33	RW	32	0x0000 0001	0x0000 0168
FWCFGMEMSS	RW	32	0x0000 0001	0x0000 016C
FWIOGENSEL	RW	32	0x0000 0000	0x0000 0170
FWPRCMHOST	RW	32	0x0000 0000	0x0000 0174
FWPRCMSPAD	RW	32	0x0000 0000	0x0000 0178
FWPRCMCMN	RW	32	0x0000 0000	0x0000 017C
FWCKM	RW	32	0x0000 0000	0x0000 0180
FWSOCIC	RW	32	0x0000 0000	0x0000 0184
FWAONM33S	RW	32	0x0000 0000	0x0000 0188
FWAONM33NS	RW	32	0x0000 0000	0x0000 018C
FWAAONM33S	RW	32	0x0000 0000	0x0000 0190
FWAAONM33NS	RW	32	0x0000 0000	0x0000 0194
FWCMNRTC	RW	32	0x0000 0000	0x0000 0198
FWMEMSS0	RW	32	0x0000 0000	0x0000 019C
FWMEMSS1	RW	32	0x0000 0000	0x0000 01A0
FWMEMSS2	RW	32	0x0000 0000	0x0000 01A4
FWHOSTAON	RW	32	0x0000 0000	0x0000 01A8
FWHIF	RW	32	0x0000 0000	0x0000 01B0
FWHOST0	RW	32	0x0000 0000	0x0000 01B4
FWHOST1	RW	32	0x0000 0000	0x0000 01B8
FWHOST2	RW	32	0x0000 0000	0x0000 01BC
FWHOST3	RW	32	0x0000 0000	0x0000 01C0
FWHOST4	RW	32	0x0000 0000	0x0000 01C4
FWHOST5	RW	32	0x0000 0000	0x0000 01C8
FWHOST6	RW	32	0x0400 0000	0x0000 01CC
FWHOST7	RW	32	0x0400 0000	0x0000 01D0
FWHOST8	RW	32	0x0000 0000	0x0000 01D4
FWHOST9	RW	32	0x0000 0000	0x0000 01D8
FWHOST10	RW	32	0x0000 0000	0x0000 01DC
FWHOST11	RW	32	0x0000 0000	0x0000 01E0
FWXIPOSPI	RW	32	0x0000 0000	0x0000 01E4
FWXIPINDAC	RW	32	0x0000 0000	0x0000 01E8
FWXIPGEN	RW	32	0x0000 0000	0x0000 01EC
FWXIPUDMAS	RW	32	0x0000 0000	0x0000 01F0
FWXIPUDMANS	RW	32	0x0000 0000	0x0000 01F4
FWOTFDE0	RW	32	0x0000 0000	0x0000 01F8
FWOTFDE1	RW	32	0x0000 0000	0x0000 01FC
FWOTFDE2	RW	32	0x0000 0000	0x0000 0200
FWOTFDE3	RW	32	0x0000 0000	0x0000 0204
FWDMAGEN	RW	32	0x0000 0000	0x0000 0208
FWDMA0	RW	32	0x0000 0000	0x0000 020C
FWDMA1	RW	32	0x0000 0000	0x0000 0210
FWDMA2	RW	32	0x0000 0000	0x0000 0214
FWDMA3	RW	32	0x0000 0000	0x0000 0218
FWDMA4	RW	32	0x0000 0000	0x0000 021C
FWDMA5	RW	32	0x0000 0000	0x0000 0220
FWDMA6	RW	32	0x0000 0000	0x0000 0224
FWDMA7	RW	32	0x0000 0000	0x0000 0228
FWDMA8	RW	32	0x0000 0000	0x0000 022C
FWDMA9	RW	32	0x0000 0000	0x0000 0230
FWDMA10	RW	32	0x0000 0000	0x0000 0234
FWDMA11	RW	32	0x0000 0000	0x0000 0238
FWHSMEIPNS	RW	32	0x0000 0000	0x0000 023C
FWHSMEIPS	RW	32	0x0000 0000	0x0000 0240
FWHSMWRAPNS	RW	32	0x0000 0000	0x0000 0244
FWHSMWRAPS	RW	32	0x0000 0000	0x0000 0248
FWHSMDBG	RW	32	0x0000 0000	0x0000 024C
FWI2C0	RW	32	0x0000 0000	0x0000 0250
FWI2C1	RW	32	0x0000 0000	0x0000 0254
FWSPSPI0	RW	32	0x0000 0000	0x0000 0258
FWSPSPI1	RW	32	0x0000 0000	0x0000 025C
FWSPUART0	RW	32	0x0000 0000	0x0000 0260
FWSPUART1	RW	32	0x0000 0000	0x0000 0264
FWSPGPT0	RW	32	0x0000 0000	0x0000 0268
FWSPGPT1	RW	32	0x0000 0000	0x0000 026C
FWSPI2S	RW	32	0x0000 0000	0x0000 0270
FWPDM	RW	32	0x0000 0000	0x0000 0274
FWSPCAN	RW	32	0x0000 0000	0x0000 0278
FWSPADC	RW	32	0x0000 0000	0x0000 027C
FWSPSDMMC	RW	32	0x0000 0000	0x0000 0280
FWSPSDIO	RW	32	0x0000 0000	0x0000 0284
FWSPUART2	RW	32	0x0000 0000	0x0000 0288
UDMANSCTL	RW	32	0x0000 0000	0x0000 028C
FWIOPAD0	RW	32	0x0000 0000	0x0000 0290
FWIOPAD1	RW	32	0x0000 0000	0x0000 0294
FWIOPAD2	RW	32	0x0000 0000	0x0000 0298
FWIOPAD3	RW	32	0x0000 0000	0x0000 029C
FWIOPAD4	RW	32	0x0000 0000	0x0000 02A0
FWIOPAD5	RW	32	0x0000 0000	0x0000 02A4
FWIOPAD6	RW	32	0x0000 0000	0x0000 02A8
FWIOPAD7	RW	32	0x0000 0000	0x0000 02AC
FWIOPAD8	RW	32	0x0000 0000	0x0000 02B0
FWIOPAD9	RW	32	0x0000 0000	0x0000 02B4
FWIOPAD10	RW	32	0x0000 0000	0x0000 02B8
FWIOPAD11	RW	32	0x0000 0000	0x0000 02BC
FWIOPAD12	RW	32	0x0000 0000	0x0000 02C0
FWIOPAD13	RW	32	0x0000 0000	0x0000 02C4
FWIOPAD14	RW	32	0x0000 0000	0x0000 02C8
FWIOPAD15	RW	32	0x0000 0000	0x0000 02CC
FWIOPAD16	RW	32	0x0000 0000	0x0000 02D0
FWIOPAD17	RW	32	0x0000 0000	0x0000 02D4
FWIOPAD18	RW	32	0x0000 0000	0x0000 02D8
FWIOPAD19	RW	32	0x0000 0000	0x0000 02DC
FWIOPAD20	RW	32	0x0000 0000	0x0000 02E0
FWIOPAD21	RW	32	0x0000 0000	0x0000 02E4
FWIOPAD22	RW	32	0x0000 0000	0x0000 02E8
FWIOPAD23	RW	32	0x0000 0000	0x0000 02EC
FWIOPAD24	RW	32	0x0000 0000	0x0000 02F0
FWIOPAD25	RW	32	0x0000 0000	0x0000 02F4
FWIOPAD26	RW	32	0x0000 0000	0x0000 02F8
FWIOPAD27	RW	32	0x0000 0000	0x0000 02FC
FWIOPAD28	RW	32	0x0000 0000	0x0000 0300
FWIOPAD29	RW	32	0x0000 0000	0x0000 0304
FWIOPAD30	RW	32	0x0000 0000	0x0000 0308
FWIOPAD31	RW	32	0x0000 0000	0x0000 030C
FWIOPAD32	RW	32	0x0000 0000	0x0000 0310
FWIOPAD33	RW	32	0x0000 0000	0x0000 0314
FWIOPAD34	RW	32	0x0000 0000	0x0000 0318
FWIOPAD35	RW	32	0x0000 0000	0x0000 031C
FWIOPAD36	RW	32	0x0000 0000	0x0000 0320
FWIOPAD37	RW	32	0x0000 0000	0x0000 0324
FWIOPAD38	RW	32	0x0000 0000	0x0000 0328
FWIOPAD39	RW	32	0x0000 0000	0x0000 032C
FWIOPAD40	RW	32	0x0000 0000	0x0000 0330
FWIOPAD41	RW	32	0x0000 0000	0x0000 0334
FWIOPAD42	RW	32	0x0000 0000	0x0000 0338
FWIOPAD43	RW	32	0x0000 0000	0x0000 033C
FWIOPAD44	RW	32	0x0000 0000	0x0000 0340
FWIOPAD45	RW	32	0x0000 0000	0x0000 0344
FWIOPAD46	RW	32	0x0000 0000	0x0000 0348
FWIOPAD47	RW	32	0x0000 0000	0x0000 034C
FWIOPAD48	RW	32	0x0000 0000	0x0000 0350
FWDMA12	RW	32	0x0000 0000	0x0000 0354
FWDMA13	RW	32	0x0000 0000	0x0000 0358
SECGK_FIREWALL_CONFIG_SPARE0_0	RW	32	0x0000 0000	0x0000 035C
USECSTB	RW	32	0x0000 0F4F	0x0000 1000
DB2M33CLR	RW	32	0x0000 0000	0x0000 1004
DB2M33SET	RW	32	0x0000 0000	0x0000 1008
DB2M33LOCK	RW	32	0x0000 0000	0x0000 100C
DB3M33CLR	RW	32	0x0000 0000	0x0000 1010
DB3M33SET	RW	32	0x0000 0000	0x0000 1014
DB3M33LOCK	RW	32	0x0000 0000	0x0000 1018
DB6M33CLR	RW	32	0x0000 0000	0x0000 101C
DB6M33SET	RW	32	0x0000 0000	0x0000 1020
DB6M33LOCK	RW	32	0x0000 0000	0x0000 1024
DB7M33CLR	RW	32	0x0000 0000	0x0000 1028
DB7M33SET	RW	32	0x0000 0000	0x0000 102C
DB7M33LOCK	RW	32	0x0000 0000	0x0000 1030
NON_GPIOEVTS0	RW	32	0x0000 0000	0x0000 1044
NON_GPIOEVTS1	RW	32	0x0000 0000	0x0000 1048
DBM33NS0	RW	32	0x0000 0000	0x0000 1054
DBNSISET	RW	32	0x0000 0000	0x0000 1058
DBNSICLR	RW	32	0x0000 0000	0x0000 105C
DBNSIMSET	RW	32	0x0000 0000	0x0000 1060
DBNSIMCLR	RW	32	0x0000 0000	0x0000 1064
DBNSRIS	RW	32	0x0000 0000	0x0000 1068
DBNSMIS	RW	32	0x0000 0000	0x0000 106C
NON_GPIOMIS0S	RW	32	0x0000 0000	0x0000 1070
NON_GPIOMIS1S	RW	32	0x0000 0000	0x0000 1074
NON_GPIOFNC0S	RW	32	0x0000 0000	0x0000 1078
NON_GPIOFNC1S	RW	32	0x0000 0000	0x0000 107C
SPARE20	RW	32	0x0000 0000	0x0000 1080
FUSE	RW	32	0x0000 0000	0x0000 2004
ESM1CFG	RW	32	0x0000 0101	0x0000 2048
ESM1EN1	RW	32	0x0000 0000	0x0000 204C
ESM1EN2	RW	32	0x0000 0000	0x0000 2050
ESM1EN3	RW	32	0x0000 0000	0x0000 2054
ESM1EN4	RW	32	0x0000 0000	0x0000 2058
ESM1EN5	RW	32	0x0000 0000	0x0000 205C
ESM2EN1	RW	32	0x0000 0000	0x0000 2060
ESM2EN2	RW	32	0x0000 0000	0x0000 2064
ESM2EN3	RW	32	0x0000 0000	0x0000 2068
ESM2EN4	RW	32	0x0000 0000	0x0000 206C
ESM2EN5	RW	32	0x0000 0000	0x0000 2070
ESM2CFG	RW	32	0x0000 0101	0x0000 2074
DBGSSDSSM	RW	32	0x0007 0001	0x0000 20A4
ESM3CFG	RW	32	0x0000 0101	0x0000 20B4
ESM3EN1	RW	32	0x0000 0000	0x0000 20B8
ESM3EN2	RW	32	0x0000 0000	0x0000 20BC
ESM3EN3	RW	32	0x0000 0000	0x0000 20C0
ESM3EN4	RW	32	0x0000 0000	0x0000 20C4
ESM3EN5	RW	32	0x0000 0000	0x0000 20C8
SOC_AON_FUSE_LINE0	RW	32	0x0000 0000	0x0000 20CC
SOC_AON_FUSE_LINE1	RW	32	0x0000 0000	0x0000 20D0
SOC_AON_FUSE_LINE2	RW	32	0x0000 0000	0x0000 20D4
SECGV_SOC_AON_FUSE_LINE3	RW	32	0x0000 0000	0x0000 20D8
SECGV_SOC_AON_FUSE_LINE4	RW	32	0x0000 0000	0x0000 20DC
SECGV_SOC_AON_FUSE_LINE5	RW	32	0x0000 0000	0x0000 20E0
SECGV_SOC_AON_FUSE_LINE6	RW	32	0x0000 0000	0x0000 20E4
SOC_AON_FUSE_LINE7	RW	32	0x0000 0000	0x0000 20E8
SOC_AON_FUSE_LINE8	RO	32	0x0000 0000	0x0000 20EC
FUSECTL	RW	32	0x0000 0002	0x0000 2100
COREMEMCTL	RW	32	0x0000 0000	0x0000 2104
COREGPCTL	RW	32	0x0000 0001	0x0000 2108
MEMSSGPCTL	RW	32	0x0000 0000	0x0000 210C
BLEFUSECTL	RW	32	0x0000 0000	0x0000 2110
SPARE4	RW	32	0x0000 0000	0x0000 2118
ESM4CFG	RW	32	0x0000 0101	0x0000 211C
ESM4EN1	RW	32	0x0000 0000	0x0000 2120
ESM4EN2	RW	32	0x0000 0000	0x0000 2124
ESM4EN3	RW	32	0x0000 0000	0x0000 2128
ESM4EN4	RW	32	0x0000 0000	0x0000 212C
ESM4EN5	RW	32	0x0000 0000	0x0000 2130
MEMPROT	RW	32	0x0000 0000	0x0000 2140
VTORCFG	RW	32	0x0000 0000	0x0000 2144
ROMJUMPCTL	RW	32	0x0000 0000	0x0000 2148
CRAMPROT1	RW	32	0x0000 0000	0x0000 214C
CRAMPROT0	RW	32	0x0000 0000	0x0000 2150
DRAMPROT1	RW	32	0x0000 0000	0x0000 2154
DRAMPROT0	RW	32	0x0000 0100	0x0000 2158
PRAMPROT0	RW	32	0x0000 0100	0x0000 215C
STRONGPAT	RW	32	0x0000 0000	0x0000 2160
UDS0	RW	32	0x0000 0000	0x0000 2164
UDS1	RW	32	0x0000 0000	0x0000 2168
UDS2	RW	32	0x0000 0000	0x0000 216C
UDS3	RW	32	0x0000 0000	0x0000 2170
DBGBUS	RW	32	0x0000 0008	0x0000 2174
DEBUGSS	RW	32	0x0000 0000	0x0000 217C
CPEPROT1	RW	32	0x0031 8001	0x0000 2180
CPEPROT0	RW	32	0x0000 0100	0x0000 2184
FUSESHIFT	RW	32	0x0000 0000	0x0000 2188
SECROM	RW	32	0x0000 0000	0x0000 218C
SECUDS	RW	32	0x0000 0000	0x0000 2190
PHYPROT1	RW	32	0x0000 0000	0x0000 2198
PHYPROT0	RW	32	0x0000 0100	0x0000 219C
ESMDIS	RW	32	0x0000 0100	0x0000 21A0
SPARE50	RW	32	0x0000 0000	0x0000 21A4
TOPDBG	RW	32	0x0000 0000	0x0000 21A8
DB0M3CLR	RW	32	0x0000 0000	0x0000 2370
DB0M3SET	RW	32	0x0000 0000	0x0000 2374
DB0M3LOCK	RW	32	0x0000 0000	0x0000 2378
DB1M3CLR	RW	32	0x0000 0000	0x0000 237C
DB1M3SET	RW	32	0x0000 0000	0x0000 2380
DB1M3LOCK	RW	32	0x0000 0000	0x0000 2384
DB2M3CLR	RW	32	0x0000 0000	0x0000 2388
DB2M3SET	RW	32	0x0000 0000	0x0000 238C
DB2M3LOCK	RW	32	0x0000 0000	0x0000 2390
DB3M3CLR	RW	32	0x0000 0000	0x0000 2394
DB3M3SET	RW	32	0x0000 0000	0x0000 2398
DB3M3LOCK	RW	32	0x0000 0000	0x0000 239C
DB4M3CLR	RW	32	0x0000 0000	0x0000 23A0
DB4M3SET	RW	32	0x0000 0000	0x0000 23A4
DB4M3LOCK	RW	32	0x0000 0000	0x0000 23A8
DB5M3CLR	RW	32	0x0000 0000	0x0000 23AC
DB5M3SET	RW	32	0x0000 0000	0x0000 23B0
DB5M3LOCK	RW	32	0x0000 0000	0x0000 23B4
DB6M3CLR	RW	32	0x0000 0000	0x0000 23B8
DB6M3SET	RW	32	0x0000 0000	0x0000 23BC
DB6M3LOCK	RW	32	0x0000 0000	0x0000 23C0
DB7M3CLR	RW	32	0x0000 0000	0x0000 23C4
DB7M3SET	RW	32	0x0000 0000	0x0000 23C8
DB7M3LOCK	RW	32	0x0000 0000	0x0000 23CC
M3GPIOEVT0	RW	32	0x0000 0000	0x0000 23D0
M3GPIOEVT1	RW	32	0x0000 0000	0x0000 23D4
FUSELOCK	RW	32	0x0000 0000	0x0000 23E8
ROMBOOT	RW	32	0x0000 0000	0x0000 23EC
SOCBOOT	RW	32	0x0000 0000	0x0000 23FC
ELEVATED	RW	32	0x0000 0000	0x0000 2400
M3TCM	RW	32	0x0000 0000	0x0000 2408
HSMCFG	RW	32	0x0000 0006	0x0000 240C
ESM5CFG	RW	32	0x0000 0101	0x0000 2410
ESM5EN1	RW	32	0x0000 0000	0x0000 2414
ESM5EN2	RW	32	0x0000 0000	0x0000 2418
ESM5EN3	RW	32	0x0000 0000	0x0000 241C
ESM5EN4	RW	32	0x0000 0000	0x0000 2420
ESM5EN5	RW	32	0x0000 0000	0x0000 2424
ESM1VAL1ST	RW	32	0x0000 0000	0x0000 2428
ESM2VAL1ST	RW	32	0x0000 0000	0x0000 242C
ESM3VAL1ST	RW	32	0x0000 0000	0x0000 2430
ESM4VAL1ST	RW	32	0x0000 0000	0x0000 2434
ESM5VAL1ST	RW	32	0x0000 0000	0x0000 2438
DBM3IMASK	RW	32	0x0000 0000	0x0000 2450
DBM3ISET	RW	32	0x0000 0000	0x0000 2454
DBM3ICLR	RW	32	0x0000 0000	0x0000 2458
DBM3IMSET	RW	32	0x0000 0000	0x0000 245C
DBM3IMCLR	RW	32	0x0000 0000	0x0000 2460
DBM3RIS	RW	32	0x0000 0000	0x0000 2464
DBM3MIS	RW	32	0x0000 0000	0x0000 2468
HOSTCRTX	RW	32	0x0000 0000	0x0000 2680
FWCFGSOC	RW	32	0x0000 0001	0x0000 2684
FWCOEX	RW	32	0x0000 0000	0x0000 2688
FWPRCM	RW	32	0x0000 0000	0x0000 268C
FWFUSE	RW	32	0x0000 0000	0x0000 2690
FWGPADC	RW	32	0x0000 0000	0x0000 2694
FWDBGSS	RW	32	0x0000 0000	0x0000 2698
FWAONM3	RW	32	0x0000 0000	0x0000 269C
FWOCLA	RW	32	0x0000 0000	0x0000 26A0
FWCORE	RW	32	0x0000 0000	0x0000 26A4
FWAAONM3	RW	32	0x0000 0000	0x0000 26A8
FWXIPCFG	RW	32	0x0000 0000	0x0000 26AC
FWOTFLCK	RW	32	0x0000 0000	0x0000 26B0
FWOTFNLCK	RW	32	0x0000 0000	0x0000 26B4
FWCOREAON	RW	32	0x0000 0000	0x0000 2808
SECGA_FIREWALL_CONFIG_SPARE0_1	RW	32	0x0000 0000	0x0000 287C
SOCSTA	RW	32	0x0000 0000	0x0000 2898
LCCFG	RW	32	0x0000 0000	0x0000 289C
ESM1STA	RW	32	0x0000 0000	0x0000 28A0
ESM2STA	RW	32	0x0000 0000	0x0000 28A4
ESM1STA1ST	RW	32	0x0000 0000	0x0000 28A8
ESM2STA1ST	RW	32	0x0000 0000	0x0000 28AC
ESM3STA1ST	RW	32	0x0000 0000	0x0000 28B0
ESM4STA1ST	RW	32	0x0000 0000	0x0000 28B4
ESM5STA1ST	RW	32	0x0000 0000	0x0000 28B8
SECGSERR	RW	32	0x0000 0000	0x0000 2908
DRAMCTL	RW	32	0x0000 0100	0x0000 290C
CONNSTPCTL	RW	32	0x0000 0100	0x0000 2910
ESMSTATI	RW	32	0x0000 0000	0x0000 2914
M3GPIOMIS0	RW	32	0x0000 0000	0x0000 2918
M3GPIOMIS1	RW	32	0x0000 0000	0x0000 291C
M3GPIOFNC0	RW	32	0x0000 0000	0x0000 2920
M3GPIOFNC1	RW	32	0x0000 0000	0x0000 2924
DBGBUS_OUT_SEL	RW	32	0x0000 0008	0x0000 2928
CPUWAIT	RW	32	0x0000 0000	0x0000 292C
SPARE60	RW	32	0x0000 0000	0x0000 2930
SECSTA	RW	32	0x0000 0000	0x0000 2934
ESM3VAL2ND	RW	32	0x0000 0000	0x0000 2938
ESM4VAL2ND	RW	32	0x0000 0000	0x0000 293C
ESM5VAL2ND	RW	32	0x0000 0000	0x0000 2940
ESM3STA	RW	32	0x0000 0000	0x0000 2944
ESM4STA	RW	32	0x0000 0000	0x0000 2948
ESM5STA	RW	32	0x0000 0000	0x0000 294C
ESM3STA2ND	RW	32	0x0000 0000	0x0000 2950
ESM4STA2ND	RW	32	0x0000 0000	0x0000 2954
ESM5STA2ND	RW	32	0x0000 0000	0x0000 2958
LCSTA	RW	32	0x0000 0000	0x0000 295C
DRMAST	RW	32	0x0000 0000	0x0000 2960
FLASHMASK	RW	32	0x0000 0001	0x0000 2964
WSOCROM	RW	32	0b0000 0000 0000 0000 0000 0000 0000 000x	0x0000 2968

SOC_AON Instances Register Mapping Summary

SOC_AON Register Descriptions

:SOC_AON Common Register Descriptions

:SOC_AON:M3EVTCTL1

Address offset	0x0000 0000
Description	M3 Event MUXs Selectors. One of three registers that contain selectors to M3 events. There are 10 event MUXs for M3. The selected event goes to ELP module as a wakeup event. INTERNAL NOTES: Event Manager DD - CORE 10 MUXs Selector Table [Confluence][https://confluence.itg.ti.com/display/WNG/Event+Manager+DD#EventManagerDD-CORE10MUXSelectorTable]
Type	RW

Bits	Field Name	Description	Type	Reset
31:30	Reserved		RO	0x0
29:24	SEL3	M3 Event Select Mux. This field selects 4th MUX output to M3 IRQ trough ELP as a wakeup event.	RW	0x00
23:22	Reserved		RO	0x0
21:16	SEL2	M3 Event Select Mux. This field selects 3rd MUX output to M3 IRQ trough ELP as a wakeup event.	RW	0x00
15:14	Reserved		RO	0x0
13:8	SEL1	M3 Event Select Mux. This field selects 2nd MUX output to M3 IRQ trough ELP as a wakeup event.	RW	0x00
7:6	Reserved		RO	0x0
5:0	SEL0	M3 Event Select Mux. This field selects 1st MUX output to M3 IRQ trough ELP as a wakeup event.	RW	0x00

:SOC_AON:M3IRQCTL2

Address offset	0x0000 0004
Description	M3 Event MUXs Selectors. One of three registers that contain selectors to M3 events. There are 10 event MUXs for M3. The selected event goes to ELP module as a wakeup event. INTERNAL NOTES: Event Manager DD - CORE 10 MUXs Selector Table [Confluence][https://confluence.itg.ti.com/display/WNG/Event+Manager+DD#EventManagerDD-CORE10MUXSelectorTable]
Type	RW

Bits	Field Name	Description	Type	Reset
31:30	Reserved		RO	0x0
29:24	SEL7	M3 Event Select Mux. This field selects 8th MUX output to M3 IRQ trough ELP as a wakeup event.	RW	0x00
23:22	Reserved		RO	0x0
21:16	SEL6	M3 Event Select Mux. This field selects 7th MUX output to M3 IRQ trough ELP as a wakeup event.	RW	0x00
15:14	Reserved		RO	0x0
13:8	SEL5	M3 Event Select Mux. This field selects 6th MUX output to M3 IRQ trough ELP as a wakeup event.	RW	0x00
7:6	Reserved		RO	0x0
5:0	SEL4	M3 Event Select Mux. This field selects 5th MUX output to M3 IRQ trough ELP as a wakeup event.	RW	0x00

:SOC_AON:M3EVTCTL3

Address offset	0x0000 0008
Description	M3 Event MUXs Selectors. One of three registers that contain selectors to M3 events. There are 10 event MUXs for M3. The selected event goes to ELP module as a wakeup event. INTERNAL NOTES: Event Manager DD - CORE 10 MUXs Selector Table [Confluence][https://confluence.itg.ti.com/display/WNG/Event+Manager+DD#EventManagerDD-CORE10MUXSelectorTable]
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:8	SEL9	M3 Event Select Mux. This field selects 10th MUX output to M3 IRQ trough ELP as a wakeup event.	RW	0x00
7:6	Reserved		RO	0x0
5:0	SEL8	M3 Event Select Mux. This field selects 9th MUX output to M3 IRQ trough ELP as a wakeup event.	RW	0x00

:SOC_AON:SPEVTCTL

Address offset	0x0000 000C
Description	Shared Peripherals Event MUXs Selectors. This register selects events to ADC, I2S and PDM. INTERNAL NOTE: Shared Peripherals selector table- [Confluence][https://confluence.itg.ti.com/display/WNG/Event+Manager+DD#EventManagerDD-SharedPeripheralsMUXSelectorTable]
Type	RW

Bits	Field Name	Description	Type	Reset
31:23	Reserved		RO	0x000
22:16	PDM	PDM Event Selector. This field selects event to PDM. INTERNAL NOTE: PDM event selector table: [Confluence][https://confluence.itg.ti.com/display/WNG/Event+Manager+DD#EventManagerDD-PDMEventSelectorTable]	RW	0x00
15	Reserved		RO	0
14:8	I2S	I2S Event Selector. This field selects event to I2S. INTERNAL NOTE: I2S event selector table: [Confluence][https://confluence.itg.ti.com/display/WNG/Event+Manager+DD#EventManagerDD-I2SEventSelectorTable]	RW	0x00
7:6	Reserved		RO	0x0
5:0	ADC	ADC Event Selector. This field selects event to ADC. INTERNAL NOTE: ADC event selector table: [Confluence][https://confluence.itg.ti.com/display/WNG/Event+Manager+DD#EventManagerDD-ADCEventSelectorTable]	RW	0x00

:SOC_AON:TMEVTCTL

Address offset	0x0000 0010
Description	Timers Event MUXs Selectors. This register selects events to SYSTIMER and RTC. There are two MUXs of SYSTIMER and one for RTC.
Type	RW

Bits	Field Name	Description	Type	Reset
31:23	Reserved		RO	0x000
22:16	RTC	RTC Event Selector. This field selects event to RTC. INTERNAL NOTE: RTC event selector table: [Confluence][https://confluence.itg.ti.com/display/WNG/Event+Manager+DD#EventManagerDD-RTCEventSelectorTable]	RW	0x00
15:14	Reserved		RO	0x0
13:8	SYSTM1	SYSTIMER Event 2nd Selector. This field selects event to SYSTIMER. INTERNAL NOTE: SYSTIMER event selector table: [Confluence][https://confluence.itg.ti.com/display/WNG/Event+Manager+DD#EventManagerDD-SysTimerEventSelectorTable]	RW	0x00
7:6	Reserved		RO	0x0
5:0	SYSTM0	SYSTIMER Event 1st Selector. This field selects event to SYSTIMER. INTERNAL NOTE: SYSTIMER event selector table: [Confluence][https://confluence.itg.ti.com/display/WNG/Event+Manager+DD#EventManagerDD-SysTimerEventSelectorTable]	RW	0x00

:SOC_AON:GPT0EVTCTL0

Address offset	0x0000 0014
Description	GPTIMER0 Channels Event MUXs Selectors. This register selects events to GPTIMER0. There are 4 event MUXs for GPTIMER Channels. INTERNAL NOTE: GPTIMER0 selector table- [Confluence][https://confluence.itg.ti.com/display/WNG/Event+Manager+DD#EventManagerDD-GPTIMER0EventSelectorTable]
Type	RW

Bits	Field Name	Description	Type	Reset
31:28	Reserved		RO	0x0
27:21	CH3SEL	This field selects MUX output to CH3 of GPTIMER0 IRQ.	RW	0x00
20:14	CH2SEL	This field selects MUX output to CH2 of GPTIMER0 IRQ.	RW	0x00
13:7	CH1SEL	This field selects MUX output to CH1 of GPTIMER0 IRQ.	RW	0x00
6:0	CH0SEL	This field selects MUX output to CH0 of GPTIMER0 IRQ.	RW	0x00

:SOC_AON:GPT1EVTCTL0

Address offset	0x0000 0018
Description	GPTIMER1 Event MUXs Selectors. This register selects events to GPTIMER1. There are 4 event MUXs for GPTIMER Channels. INTERNAL NOTE: GPTIMER1 selector table- [Confluence][https://confluence.itg.ti.com/display/WNG/Event+Manager+DD#EventManagerDD-GPTIMER1EventSelectorTable]
Type	RW

Bits	Field Name	Description	Type	Reset
31:28	Reserved		RO	0x0
27:21	CH3SEL	This field selects MUX output to CH3 of GPTIMER1 IRQ.	RW	0x00
20:14	CH2SEL	This field selects MUX output to CH2 of GPTIMER1 IRQ.	RW	0x00
13:7	CH1SEL	This field selects MUX output to CH1 of GPTIMER1 IRQ.	RW	0x00
6:0	CH0SEL	This field selects MUX output to CH0 of GPTIMER1 IRQ.	RW	0x00

:SOC_AON:DB0M33CLR

Address offset	0x0000 001C
Description	Doorbell 0 M33 Clear Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	CLR	M33 to clear the IRQ after handled the massage from M3. type : Write-Clear	WO	0

:SOC_AON:DB0M33SET

Address offset	0x0000 0020
Description	Doorbell 0 M33 Set Register.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	SET	M33 to generate IRQ towards M3 after writing the message. type: Write-Clear	WO	0

:SOC_AON:DB0M33LOCK

Address offset	0x0000 0024
Description	Doorbell 0 M33 Lock Bit.
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1:0	LOCKBIT	Lock Bit. S/w attempt to lock upon read. if lock obtained, value set to 2 by h/w. M33 always looses to M3 Reading value: 0. not taken 1. taken by M3 2. taken by M33 (should wr IRQ afterwards) 3. invalid. generating the IRQ towards M3 clears the lock. Writing '00' also release the lock. '01' means lock obtained by receiver side Type: Write-Read-Clear	RW	0x0

:SOC_AON:DB1M33CLR

Address offset	0x0000 0028
Description	Doorbell 1 M33 Clear Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	CLR	M33 to clear the IRQ after handled the massage from M3. type : Write-Clear	WO	0

:SOC_AON:DB1M33SET

Address offset	0x0000 002C
Description	Doorbell 1 M33 Set Register.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	SET	M33 to generate IRQ towards M3 after writing the message. type: Write-Clear	WO	0

:SOC_AON:DB1M33LOCK

Address offset	0x0000 0030
Description	Doorbell 1 M33 Lock Bit.
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1:0	LOCKBIT	Lock Bit. S/w attempt to lock upon read. if lock obtained, value set to 2 by h/w. M33 always looses to M3 Reading value: 0. not taken 1. taken by M3 2. taken by M33 (should wr IRQ afterwards) 3. invalid. generating the IRQ towards M3 clears the lock. Writing '00' also release the lock. '01' means lock obtained by receiver side Type: Write-Read-Clear	RW	0x0

:SOC_AON:DB4M33CLR

Address offset	0x0000 0034
Description	Doorbell 4 M33 Clear Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	CLR	M33 to clear the IRQ after handled the massage from M3. type : Write-Clear	WO	0

:SOC_AON:DB4M33SET

Address offset	0x0000 0038
Description	Doorbell 4 M33 Set Register.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	SET	M33 to generate IRQ towards M3 after writing the message. type: Write-Clear	WO	0

:SOC_AON:DB4M33LOCK

Address offset	0x0000 003C
Description	Doorbell 4 M33 Lock Bit.
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1:0	LOCKBIT	Lock Bit. S/w attempt to lock upon read. if lock obtained, value set to 2 by h/w. M33 always looses to M3 Reading value: 0. not taken 1. taken by M3 2. taken by M33 (should wr IRQ afterwards) 3. invalid. generating the IRQ towards M3 clears the lock. Writing '00' also release the lock. '01' means lock obtained by receiver side Type: Write-Read-Clear	RW	0x0

:SOC_AON:DB5M33CLR

Address offset	0x0000 0040
Description	Doorbell 5 M33 Clear Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	CLR	M33 to clear the IRQ after handled the massage from M3. type : Write-Clear	WO	0

:SOC_AON:DB5M33SET

Address offset	0x0000 0044
Description	Doorbell 5 M33 Set Register.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	SET	M33 to generate IRQ towards M3 after writing the message. type: Write-Clear	WO	0

:SOC_AON:DB5M33LOCK

Address offset	0x0000 0048
Description	Doorbell 5 M33 Lock Bit.
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1:0	LOCKBIT	Lock Bit. S/w attempt to lock upon read. if lock obtained, value set to 2 by h/w. M33 always looses to M3 Reading value: 0. not taken 1. taken by M3 2. taken by M33 (should wr IRQ afterwards) 3. invalid. generating the IRQ towards M3 clears the lock. Writing '00' also release the lock. '01' means lock obtained by receiver side Type: Write-Read-Clear	RW	0x0

:SOC_AON:CMEMSTART

Address offset	0x0000 004C
Description	CODE Memory MEMSS Start Address. CMEM Start Address-also define S/NS region split. split is in 1k resolution
Type	RW

Bits	Field Name	Description	Type	Reset
31:12	ADDR	CMEM Start Address-also define S/NS region split. split is in 1k resolution	RW	0x0 8000
11:0	Reserved		RO	0x000

:SOC_AON:CMEMEND

Address offset	0x0000 0050
Description	CODE Memory MEMSS End Address. CMEM end Address-also define S/NS region split
Type	RW

Bits	Field Name	Description	Type	Reset
31:12	ADDR	CMEM end Address-also define S/NS region split	RW	0x0 FFFF
11:0	Reserved		RO	0xFFF

:SOC_AON:DMEMSTART

Address offset	0x0000 0054
Description	DATA Memory MEMSS Start Address. DMEM Start Address-also define S/NS region split
Type	RW

Bits	Field Name	Description	Type	Reset
31:12	ADDR	DMEM Start Address-also define S/NS region split	RW	0x2 8000
11:0	Reserved		RO	0x000

:SOC_AON:DMEMEND

Address offset	0x0000 0058
Description	DATA Memory MEMSS End Address. DMEM end Address-also define S/NS region split
Type	RW

Bits	Field Name	Description	Type	Reset
31:12	ADDR	DMEM end Address-also define S/NS region split	RW	0x2 FFFF
11:0	Reserved		RO	0xFFF

:SOC_AON:TCMSTART

Address offset	0x0000 0064
Description	TCM DATA Memory MEMSS Start Address. TCM data Start Address-also define S/NS region split
Type	RW

Bits	Field Name	Description	Type	Reset
31:10	ADDR	TCM data Start Address-also define S/NS region split	RW	0x08 0000
9:0	Reserved		RO	0x000

:SOC_AON:TCMEND

Address offset	0x0000 0068
Description	TCM DATA Memory MEMSS End Address. TCM data end Address-also define S/NS region split
Type	RW

Bits	Field Name	Description	Type	Reset
31:10	ADDR	TCM data end Address-also define S/NS region split	RW	0x09 FFFF
9:0	Reserved		RO	0x3FF

:SOC_AON:GPIOEVTS0

Address offset	0x0000 007C
Description	Secured GPIO Event Status, 1st Register. 45 bits status over two registers.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	STA31TO0	Secured event status , first 32 bits. ([31:0])			RO	0x0000 0000

:SOC_AON:GPIOEVTS1

Address offset	0x0000 0080
Description	Secured GPIO Event Status, 2nd Register. 45 bits status over two registers.
Type	RW

Bits	Field Name	Description	Type	Reset
31:13	Reserved		RO	0x0 0000
12:0	STA44TO32	Secured event status , 13 MSBs. ([44:32])	RO	0x0000

:SOC_AON:MEMSSCTL0

Address offset	0x0000 0084
Description	MEMSS General Control Register. This register controls starvation mechanism counter value and MEMSS bus fault mask.
Type	RW

Bits	Field Name	Description	Type	Reset
31:7	Reserved		RO	0x000 0000
6:4	BFLTMSTA	Bus Fault Masked Status. Out of Memory Index: 0. No error 1. M33 Code 2. M33 Data #1 + #2 3. M3 Code 4. M3 Data 5. M3 PRAM 6. BLE Code 7. Global OCP	RO	0x0
3	BFLTMASK	MEMSS Bus Fault Mask 1. Mask 0. Do not mask	RW	0
2:0	STRVCNTV	Starvation Counter Value Configuration. That value reflect how long writing to mailbox can be delayed.	RW	0x0

:SOC_AON:MEMSSCTL1

Address offset	0x0000 0088
Description	MEMSS General Control Register. This is a status register for bus fault raw status.
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2:0	BFLTRWSTA	Bus Fault Raw Status. Error indication from memss. Out of Memory Index: 0. No error 1. M33 Code 2. M33 Data #1 + #2 3. M3 Code 4. M3 Data 5. M3 PRAM 6. BLE Code 7. Global OCP Type: Read-Clear	RO	0x0

:SOC_AON:SPARE0

Address offset	0x0000 0090
Description	Spare Register. This is a spare register in M33S aperture.
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:0	MEM_SPARE0_AON	Spare Field. Non-locked , M33S aperture.	RW	0x0

:SOC_AON:VTORS

Address offset	0x0000 009C
Description	M33 Secure Vector Table Base Address.
Type	RW

Bits	Field Name	Description	Type	Reset
31:7	ADDR	init VTOR Secured Address.	RW	0x000 0000
6:0	Reserved		RO	0x00

:SOC_AON:VTORNS

Address offset	0x0000 00A0
Description	M33 Non-Secure Vector Table Base Address.
Type	RW

Bits	Field Name	Description	Type	Reset
31:7	ADDR	init VTOR non Secured address	RW	0x000 0000
6:0	Reserved		RO	0x00

:SOC_AON:CPULOCKS

Address offset	0x0000 00A8
Description	CPU Locks. This register contain 5 locks. Issued to M33 Cortex and used to lock internal cortex registers. LOCKSVTAIRCR, LOCKNSVTOR, LOCKSMPU, LOCKNSMPU, LOCKSAU.
Type	RW

Bits	Field Name	Description	Type	Reset
31:5	Reserved	Reserved	RO	0x000 0000
4	SAU	Locking this Cortex internal configuration	RW	0
3	NSPMU	Locking this Cortex internal configuration	RW	0
2	SMPU	Locking this Cortex internal configuration	RW	0
1	NSVTOR	Locking this Cortex internal configuration	RW	0
0	SVTAIRCR	Locking this Cortex internal configuration	RW	0

:SOC_AON:HOSTLOCKS

Address offset	0x0000 00AC
Description	Host Lock Signals. lock once. Do Not lock until written. When written Locked immediately, cleared only at soc aon reset or por reset. These are host security lock configurations (some can be also locked by TI)
Type	RW

Bits	Field Name	Description	Type	Reset
31:7	Reserved	Reserved	RO	0x000 0000
6	PERIPHEVT	Locking the firewall configurations of: HIF, CORE, CORE AON, HSM, shared Periphs	WOnce	0
5	M3EVT	Locking the configurations of M3 Events	WOnce	0
4	FLASH	Locking the configurations of On The Fly Enc/Decryption Module Region Related Registers (four registers per region, four regions)	WOnce	0
3	DMA	Locking the configurations of System DMA	WOnce	0
2	MEMSSANDFW	Locking the configurations of Memory Sub System	WOnce	0
1	M33	Locking the configurations of Host MCU, both Secured and non Secured	WOnce	0
0	CACHE	Locking the configurations of ICACHE	WOnce	0

:SOC_AON:HOSTBOOT

Address offset	0x0000 00B0
Description	Host Boot Done 1 lock. Write once. Asserted by FW by the end of soc boot done Or in elevated mode By either by TI of by the host and indicates device exit from secure boot mode. this signal also locks host security configurations , Locked immediately , cleared only at soc aon reset or por reset
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved	Reserved	RO	0x0000 0000
0	HOSTBOOT_WROPT	Locking host security configurations	WOnce	0

:SOC_AON:SECCFG

Address offset	0x0000 00B4
Description	Security Configurations.
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	BLKSBSWR	BLOCK SBUS WRITE LOCK Enable this field to block sbus write transactions	RW	0
1	SELNSIRQ	This field determine whether the 4 SW interrupts MSbits will be owned by secured/non secured. 0. Non-Secured 1. Secured	RW	0
0	MEM_BLOCK_UDMA_TO_CMEM	This Field blocks the uDMA transactions to CMEM. 0. un-Block 1. Block	RW	0

:SOC_AON:DBSIMASK

Address offset	0x0000 00B8
Description	Doorbell M33 Secured IMASK. Mask Event. 0. CLR - Clear Interrupt Mask 1. SET - Set Interrupt Mask
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:0	IMASK	Bits division to events: bit [3] - doorbell 5 M3 IRQ bit [2] - doorbell 4 M3 IRQ bit [1] - doorbell 1 M3 IRQ bit [0] - doorbell 0 M3 IRQ	RW	0x0

:SOC_AON:DBSISET

Address offset	0x0000 00BC
Description	Doorbell M33 Secured ISET. Sets event in RIS Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - SET - Sets interrupt
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:0	ISET	Bits division to events: bit [3] - doorbell 5 M3 IRQ bit [2] - doorbell 4 M3 IRQ bit [1] - doorbell 1 M3 IRQ bit [0] - doorbell 0 M3 IRQ Type: Write-Clear	WO	0x0

:SOC_AON:DBSICLR

Address offset	0x0000 00C0
Description	Doorbell M33 Secured ICLR. Clears event in RIS Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - CLR - Clears the Event
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:0	ICLR	Bits division to events: bit [3] - doorbell 5 M3 IRQ bit [2] - doorbell 4 M3 IRQ bit [1] - doorbell 1 M3 IRQ bit [0] - doorbell 0 M3 IRQ Type: Write-Clear	WO	0x0

:SOC_AON:DBSIMSET

Address offset	0x0000 00C4
Description	Doorbell M33 Secured IMSET. Sets Event Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - SET - Set interrupt mask
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:0	IMSET	Bits division to events: bit [3] - doorbell 5 M3 IRQ bit [2] - doorbell 4 M3 IRQ bit [1] - doorbell 1 M3 IRQ bit [0] - doorbell 0 M3 IRQ Type: Write-Clear	WO	0x0

:SOC_AON:DBSIMCLR

Address offset	0x0000 00C8
Description	Doorbell M33 Secured IMCLR. Clears Event Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - CLR - Clear interrupt mask
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:0	IMCLR	Bits division to events: bit [3] - doorbell 5 M3 IRQ bit [2] - doorbell 4 M3 IRQ bit [1] - doorbell 1 M3 IRQ bit [0] - doorbell 0 M3 IRQ Type: Write-Clear	WO	0x0

:SOC_AON:DBSRIS

Address offset	0x0000 00CC
Description	Doorbell M33 Secured RIS. Raw interrupt status for event. This bit is set to 1 when an event is received. when the corresponding bit in ICLR is set to 1, this bit will be cleared. Read 0 - CLR - Interrupt did not occur Read 1 - SET - Interrupt occurred
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:0	RIS	Bits division to events: bit [3] - doorbell 5 M3 IRQ bit [2] - doorbell 4 M3 IRQ bit [1] - doorbell 1 M3 IRQ bit [0] - doorbell 0 M3 IRQ	RO	0x0

:SOC_AON:DBSMIS

Address offset	0x0000 00D0
Description	Doorbell M33 Secured MIS. Mask interrupt status for event Read 0 - CLR - Interrupt did not occur Read 1 - SET - Interrupt occurred
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:0	MIS	Bits division to events: bit [3] - doorbell 5 M3 IRQ bit [2] - doorbell 4 M3 IRQ bit [1] - doorbell 1 M3 IRQ bit [0] - doorbell 0 M3 IRQ	RO	0x0

:SOC_AON:ERRSIMASK

Address offset	0x0000 00D4
Description	M33 Secured Error IMASK. Mask Event. '0' - CLR - Clear Interrupt Mask '1' - SET - Set Interrupt Mask
Type	RW

Bits	Field Name	Description	Type	Reset
31:9	Reserved		RO	0x00 0000
8:0	IMASK	Bits division to events: bit[8] - UDMA ERR IRQ bit[7] - CORE ELP WATCHDOG Timer bit[6] - SOC IC IRQs - Address Watch bit[5] - SOC IC IRQs - IC Timeout bit[4] - SOC IC IRQs - serror bit[3] - CORE to SDIO WATCHDOG bit[2] - PLL Unlock bit[1] - MEMss bus fault bit[0] - HSM fatal error	RW	0x000

:SOC_AON:ERRSISET

Address offset	0x0000 00D8
Description	M33 Secured Error ISET. Sets event in RIS Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - SET - Sets interrupt
Type	RW

Bits	Field Name	Description	Type	Reset
31:9	Reserved		RO	0x00 0000
8:0	ISET	Bits division to events: bit[8] - UDMA ERR IRQ bit[7] - CORE ELP WATCHDOG Timer bit[6] - SOC IC IRQs - Address Watch bit[5] - SOC IC IRQs - IC Timeout bit[4] - SOC IC IRQs - serror bit[3] - CORE to SDIO WATCHDOG bit[2] - PLL Unlock bit[1] - MEMss bus fault bit[0] - HSM fatal error Type: Write-Clear	WO	0x000

:SOC_AON:ERRSICLR

Address offset	0x0000 00DC
Description	M33 Secured Error ICLR. Clears event in RIS Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - CLR - Clears the Event
Type	RW

Bits	Field Name	Description	Type	Reset
31:9	Reserved		RO	0x00 0000
8:0	ICLR	Bits division to events: bit[8] - UDMA ERR IRQ bit[7] - CORE ELP WATCHDOG Timer bit[6] - SOC IC IRQs - Address Watch bit[5] - SOC IC IRQs - IC Timeout bit[4] - SOC IC IRQs - serror bit[3] - CORE to SDIO WATCHDOG bit[2] - PLL Unlock bit[1] - MEMss bus fault bit[0] - HSM fatal error Type: Write-Clear	WO	0x000

:SOC_AON:ERRSIMSET

Address offset	0x0000 00E0
Description	M33 Secured Error IMSET. Sets Event Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - SET - Set interrupt mask
Type	RW

Bits	Field Name	Description	Type	Reset
31:9	Reserved		RO	0x00 0000
8:0	IMSET	Bits division to events: bit[8] - UDMA ERR IRQ bit[7] - CORE ELP WATCHDOG Timer bit[6] - SOC IC IRQs - Address Watch bit[5] - SOC IC IRQs - IC Timeout bit[4] - SOC IC IRQs - serror bit[3] - CORE to SDIO WATCHDOG bit[2] - PLL Unlock bit[1] - MEMss bus fault bit[0] - HSM fatal error Type: Write-Clear	WO	0x000

:SOC_AON:ERRSIMCLR

Address offset	0x0000 00E4
Description	M33 Secured Error IMCLR. Clears Event Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - CLR - Clear interrupt mask
Type	RW

Bits	Field Name	Description	Type	Reset
31:9	Reserved		RO	0x00 0000
8:0	IMCLR	Bits division to events: bit[8] - UDMA ERR IRQ bit[7] - CORE ELP WATCHDOG Timer bit[6] - SOC IC IRQs - Address Watch bit[5] - SOC IC IRQs - IC Timeout bit[4] - SOC IC IRQs - serror bit[3] - CORE to SDIO WATCHDOG bit[2] - PLL Unlock bit[1] - MEMss bus fault bit[0] - HSM fatal error Type: Write-Clear	WO	0x000

:SOC_AON:ERRSRIS

Address offset	0x0000 00E8
Description	M33 Secured Error RIS. Raw interrupt status for event. This bit is set to 1 when an event is received. when the corresponding bit in ICLR is set to 1, this bit will be cleared. Read 0 - CLR - Interrupt did not occur Read 1 - SET - Interrupt occurred
Type	RW

Bits	Field Name	Description	Type	Reset
31:9	Reserved		RO	0x00 0000
8:0	RIS	Bits division to events: bit[8] - UDMA ERR IRQ bit[7] - CORE ELP WATCHDOG Timer bit[6] - SOC IC IRQs - Address Watch bit[5] - SOC IC IRQs - IC Timeout bit[4] - SOC IC IRQs - serror bit[3] - CORE to SDIO WATCHDOG bit[2] - PLL Unlock bit[1] - MEMss bus fault bit[0] - HSM fatal error	RO	0x000

:SOC_AON:ERRSMIS

Address offset	0x0000 00EC
Description	M33 Secured Error MIS. Mask interrupt status for event Read 0 - CLR - Interrupt did not occur Read 1 - SET - Interrupt occurred
Type	RW

Bits	Field Name	Description	Type	Reset
31:9	Reserved		RO	0x00 0000
8:0	MIS	Bits division to events: bit[8] - UDMA ERR IRQ bit[7] - CORE ELP WATCHDOG Timer bit[6] - SOC IC IRQs - Address Watch bit[5] - SOC IC IRQs - IC Timeout bit[4] - SOC IC IRQs - serror bit[3] - CORE to SDIO WATCHDOG bit[2] - PLL Unlock bit[1] - MEMss bus fault bit[0] - HSM fatal error	RO	0x000

:SOC_AON:GPT0EVTCTL1

Address offset	0x0000 00F0
Description	GPTIMER0 Sync, Tick Enable and Fault Event MUXs Selectors. This register selects events to GPTIMER0. INTERNAL NOTE: GPTIMER0 selector table- [Confluence][https://confluence.itg.ti.com/display/WNG/Event+Manager+DD#EventManagerDD]
Type	RW

Bits	Field Name	Description	Type	Reset
31:23	Reserved		RO	0x000
22:16	FAULT	Selects fault MUX output to GPTIMER0 IRQ	RW	0x00
15	Reserved		RO	0
14:8	TICKEN	Selects tick enable MUX output to GPTIMER0 IRQ	RW	0x00
7	Reserved		RO	0
6:0	SYNC	Selects sync MUX output to GPTIMER0 IRQ	RW	0x00

:SOC_AON:GPT1EVTCTL1

Address offset	0x0000 00F4
Description	GPTIMER1 Sync, Tick Enable and Fault Event MUXs Selectors. This register selects events to GPTIMER1. INTERNAL NOTE: GPTIMER0 selector table- [Confluence][https://confluence.itg.ti.com/display/WNG/Event+Manager+DD#EventManagerDD]
Type	RW

Bits	Field Name	Description	Type	Reset
31:23	Reserved		RO	0x000
22:16	FAULT	Selects fault MUX output to GPTIMER0 IRQ	RW	0x00
15	Reserved		RO	0
14:8	TICKEN	Selects tick enable MUX output to GPTIMER0 IRQ	RW	0x00
7	Reserved		RO	0
6:0	SYNC	Selects sync MUX output to GPTIMER0 IRQ	RW	0x00

:SOC_AON:ESMSTACST

Address offset	0x0000 0104
Description	Customer ESMs Status. status register , for each of the ESM (enable sequence monitor) what is the status (Done, violated, or None) Final ESM status for the entire ESM - ESM machine + magic value comparators
Type	RW

Bits	Field Name	Description	Type	Reset
31:10	Reserved		RO	0x00 0000
9	ESM2VIO	This field indicates that ESM1 is violated.	RO	0
8	ESM2DONE	This field indicates that ESM2 is done.	RO	0
7:2	Reserved		RO	0x00
1	ESM1VIO	This field indicates that ESM1 is violated.	RO	0
0	ESM1DONE	This field indicates that ESM1 is done.	RO	0

:SOC_AON:MEMSSCFG

Address offset	0x0000 010C
Description	MEMSS Configurations. Supported Memory configurations: Functional Modes: 0x0. Baseline 0x1. Extended M3 0x2. Extended throughput 0x3. Extended throughput + WIFI features 0x4. Extended Host Execution 0x5. Extended M33 Data Debug Modes (OCLA Memory): 0x6. Core debug (0x7. Core debug Extended throughput (0x8. Core debug PHY only (0x9. Host debug (0xA. Host debug extended Host Execution 0xB. Host debug extended M33 Data
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:0	MODE	MEMSS mode of bank ownership	RW	0x0

:SOC_AON:GPIOMIS0S

Address offset	0x0000 0138
Description	Secured Gpio MIS.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	31TO0	32 LSBs of MIS. (45 Total)			RO	0x0000 0000

:SOC_AON:GPIOMIS1S

Address offset	0x0000 013C
Description	Secured Gpio MIS.
Type	RW

Bits	Field Name	Description	Type	Reset
31:13	Reserved		RO	0x0 0000
12:0	44TO32	13 MSBs of MIS. (45 Total)	RO	0x0000

:SOC_AON:GPIOFNC0S

Address offset	0x0000 0140
Description	Secured GPIO Functional Mask. 0. Mask 1. Un-Mask
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	MASK31TO0	32 LSBs of MASK. (45 Total)			RW	0x0000 0000

:SOC_AON:GPIOFNC1S

Address offset	0x0000 0144
Description	Secured GPIO Functional Mask. 0. Mask 1. Un-Mask
Type	RW

Bits	Field Name	Description	Type	Reset
31:13	Reserved		RO	0x0 0000
12:0	MASK44TO32	13 MSBs of MASK. (45 Total)	RW	0x0000

:SOC_AON:SPARE10

Address offset	0x0000 0148
Description	Spare Reg, M33S Aperture. non-locked.
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:0	MEM_SPARE10	M33S spare register. not locked.	RW	0x0

:SOC_AON:ESM1VAL2ND

Address offset	0x0000 014C
Description	ESM1 2nd Magic Value. This value is compared to hard coded value and unmask ESM only when value is matched. This additional compare allow additional protection on ESM and also allow vendor to unmask ESM only at the end of vendor secure boot (SBL) is completed
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	Reserved		RO	0x00 0000
7:0	MGCVAL	ESM 2nd magic value	RW	0x00

:SOC_AON:ESM2VAL2ND

Address offset	0x0000 0150
Description	ESM2 2nd Magic Value. This value is compared to hard coded value and unmask ESM only when value is matched. This additional compare allow additional protection on ESM and also allow vendor to unmask ESM only at the end of vendor secure boot (SBL) is completed
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	Reserved		RO	0x00 0000
7:0	MGCVAL	ESM 2nd magic value	RW	0x00

:SOC_AON:ESM1STA2ND

Address offset	0x0000 0154
Description	ESM1 2nd Magic Value Status. ESM magic value match indication.
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1	FAULT	ESM 2nd magic val fault ( note: indicates fault before a write to the magic val register)	RO	0
0	DONE	ESM 2nd magic val match	RO	0

:SOC_AON:ESM2STA2ND

Address offset	0x0000 0158
Description	ESM2 2nd Magic Value. ESM magic value match indication.
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1	FAULT	ESM 2nd magic val fault ( note: indicates fault before a write to the magic val register)	RO	0
0	DONE	ESM 2nd magic val match	RO	0

:SOC_AON:FWCFGHOST

Address offset	0x0000 015C
Description	HOST FW Bypass.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	BYPASS	bypass the following module's firewall configuration: IOMUX_COMMON_SEL PRCM_AON_HOST PRCM_AON_COMMON SCRATCHPAD PLLSHARING SOC_IC SOC_AON_M33_S SOC_AON_M33_NS SOC_AAON_M33_S SOC_AAON_M33_NS RTC XIP_OSPI XIP_OSPI_INDAC XIP_GENERAL XIP_UDMA_SEC XIP_UDMA_NON_SEC OTFDE_REGION0-3 HOST_DMA_GENERAL_CFG	RW	1

:SOC_AON:FWCFGDMA

Address offset	0x0000 0160
Description	DMA FW BYPASS
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	BYPASS	Bypass the firewall configuration for HOST_DMA module	RW	1

:SOC_AON:FWCFGFPRPH

Address offset	0x0000 0164
Description	Peripheral Firewall Bypass.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	BYPASS	bypass the following module's firewall configuration: HIF HSM CORE_AON I2C0/1 SPI0/1 UART0/1 GPTIMER0/1 I2S PDM CAN ADC SDMMC SDIO	RW	1

:SOC_AON:FWCFGM33

Address offset	0x0000 0168
Description	HOST MCU Firewall Bypass
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	BYPASS	bypass the firewall configuration for HOST MCU module.	RW	1

:SOC_AON:FWCFGMEMSS

Address offset	0x0000 016C
Description	MEMSS Firewall Bypass
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	BYPASS	bypass the Firewall configuration for MEMSS module.	RW	1

:SOC_AON:FWIOGENSEL

Address offset	0x0000 0170
Description	IOMUX General firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWPRCMHOST

Address offset	0x0000 0174
Description	PRCM_HOST firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0
1	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWPRCMSPAD

Address offset	0x0000 0178
Description	M33 SCRATCHPAD firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWPRCMCMN

Address offset	0x0000 017C
Description	PRCM_COMMON firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:6	Reserved		RO	0x000 0000
5	CORENSRD	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
4	CORENSWR	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
3	M33NSRD	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0
2	M33NSWR	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33SRD	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33SWR	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWCKM

Address offset	0x0000 0180
Description	CKM firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWSOCIC

Address offset	0x0000 0184
Description	SOC_IC firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:6	Reserved		RO	0x000 0000
5	CORENSRD	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
4	CORENSWR	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
3	M33SRD	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
2	M33SWR	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33NSRD	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NSWR	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWAONM33S

Address offset	0x0000 0188
Description	AON_M33_S firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWAONM33NS

Address offset	0x0000 018C
Description	AON_M33_NS firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWAAONM33S

Address offset	0x0000 0190
Description	AAON_M33_S firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWAAONM33NS

Address offset	0x0000 0194
Description	AAON_M33_NS firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWCMNRTC

Address offset	0x0000 0198
Description	RTC firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:6	Reserved		RO	0x000 0000
5	CORENSRD	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
4	CORENSWR	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
3	M33SRD	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
2	M33SWR	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33NSRD	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NSWR	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWMEMSS0

Address offset	0x0000 019C
Description	MEMSS region 0 firewall access permission for 3 controller id : 0 - M33 Non Secured (valid only in privilege mode) 1 - M33 Secured (valid only in privilege mode) 2 - Core (Non Secure) MEMSS address space: 0x41C00000 - 0x41CCFFFF for Memss the base address for security firewalls is 0x41c40000 ( M33 Data Ram from global port access) max window size is 256Kb (M33D banks) + 10*32K (Flex) = 576Kb
Type	RW

Bits	Field Name	Description	Type	Reset
31:26	Reserved		RO	0x00
25:16	BASE_LEN	address base with 1K granularity : address base len for firewall is the offset from the region's base address indicated in the same region field describing the end of a firewall window that has a certain access rules (R/W Permission) for each controller-id MEMSS address space: 0x41C00000 - 0x41CCFFFF for Memss the base address for security firewalls is 0x41c40000 ( M33 Data Ram from global port access) max window size is 576Kb example: worker base address: 0x41C40000 current address to access: 0x41C41514 region_base_address: 0x4 region_base_address_len: 0x2 --> (region_base_address + region_base_address_len) --> 0x4+0x2 -->0x6 0x41C41514 --> ((0x41C41514 - 0x41C40000) >> 10) -->0x5 0x4 <= 0x5 < 0x6 that address falls on the region window and therefor obeys to that region set of access rules	RW	0x000
15:14	Reserved		RO	0x0
13:4	BASE	address base with 1K granularity : address base for firewall is the the offset start address from a worker base address describing the beginning of a firewall window that has a certain access rules (R/W Permission) for each controller-id MEMSS address space: 0x41C00000 - 0x41CCFFFF for Memss the base address for security firewalls is 0x41c40000 ( M33 Data Ram from global port access) max base value is 0x23F max window size is 576Kb example: worker base address: 0x41C40000 current address to access: 0x41C40504 region_base_address: 0x1 region_base_address_len: 0x1 0x41C40504 --> ((0x41C40504 - 0x41C40000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules	RW	0x000
3	Reserved		RO	0
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: (valid only in privilege mode) '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: (valid only in privilege mode) '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWMEMSS1

Address offset	0x0000 01A0
Description	MEMSS region 1 firewall access permission for 3 controller id : 0 - M33 Non Secured (valid only in privilege mode) 1 - M33 Secured (valid only in privilege mode) 2 - Core (Non Secure) MEMSS address space: 0x41C00000 - 0x41CCFFFF for Memss the base address for security firewalls is 0x41c40000 ( M33 Data Ram from global port access) max window size is 256Kb (M33D banks) + 10*32K (Flex) = 576Kb
Type	RW

Bits	Field Name	Description	Type	Reset
31:26	Reserved		RO	0x00
25:16	BASE_LEN	address base with 1K granularity : address base len for firewall is the offset from the region's base address indicated in the same region field describing the end of a firewall window that has a certain access rules (R/W Permission) for each controller-id MEMSS address space: 0x41C00000 - 0x41CCFFFF for Memss the base address for security firewalls is 0x41c40000 ( M33 Data Ram from global port access) max window size is 576Kb example: worker base address: 0x41C40000 current address to access: 0x41C41514 region_base_address: 0x4 region_base_address_len: 0x2 --> (region_base_address + region_base_address_len) --> 0x4+0x2 -->0x6 0x41C41514 --> ((0x41C41514 - 0x41C40000) >> 10) -->0x5 0x4 <= 0x5 < 0x6 that address falls on the region window and therefor obeys to that region set of access rules	RW	0x000
15:14	Reserved		RO	0x0
13:4	BASE	address base with 1K granularity : address base for firewall is the the offset start address from a worker base address describing the beginning of a firewall window that has a certain access rules (R/W Permission) for each controller-id MEMSS address space: 0x41C00000 - 0x41DFFFFF for Memss the base address for security firewalls is 0x41c40000 ( M33 Data Ram from global port access) max base value is 0x23F max window size is 576Kb example: worker base address: 0x41C40000 current address to access: 0x41C40504 region_base_address: 0x1 region_base_address_len: 0x1 0x41C40504 --> ((0x41C40504 - 0x41C40000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules	RW	0x000
3	Reserved		RO	0
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: (valid only in privilege mode) '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: (valid only in privilege mode) '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWMEMSS2

Address offset	0x0000 01A4
Description	MEMSS region 2 firewall access permission for 3 controller id : 0 - M33 Non Secured (valid only in privilege mode) 1 - M33 Secured (valid only in privilege mode) 2 - Core (Non Secure) MEMSS address space: 0x41C00000 - 0x41CCFFFF for Memss the base address for security firewalls is 0x41c40000 ( M33 Data Ram from global port access) max window size is 256Kb (M33D banks) + 10*32K (Flex) = 576Kb
Type	RW

Bits	Field Name	Description	Type	Reset
31:26	Reserved		RO	0x00
25:16	BASE_LEN	address base with 1K granularity : address base len for firewall is the offset from the region's base address indicated in the same region field describing the end of a firewall window that has a certain access rules (R/W Permission) for each controller-id MEMSS address space: 0x41C00000 - 0x41CCFFFF for Memss the base address for security firewalls is 0x41c40000 ( M33 Data Ram from global port access) max window size is 576Kb example: worker base address: 0x41C40000 current address to access: 0x41C41514 region_base_address: 0x4 region_base_address_len: 0x2 --> (region_base_address + region_base_address_len) --> 0x4+0x2 -->0x6 0x41C41514 --> ((0x41C41514 - 0x41C40000) >> 10) -->0x5 0x4 <= 0x5 < 0x6 that address falls on the region window and therefor obeys to that region set of access rules	RW	0x000
15:14	Reserved		RO	0x0
13:4	BASE	address base with 1K granularity : address base for firewall is the the offset start address from a worker base address describing the beginning of a firewall window that has a certain access rules (R/W Permission) for each controller-id MEMSS address space: 0x41C00000 - 0x41DFFFFF for Memss the base address for security firewalls is 0x41c40000 ( M33 Data Ram from global port access) max base value is 0x23F max window size is 576Kb example: worker base address: 0x41C40000 current address to access: 0x41C40504 region_base_address: 0x1 region_base_address_len: 0x1 0x41C40504 --> ((0x41C40504 - 0x41C40000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules	RW	0x000
3	Reserved		RO	0
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: (valid only in privilege mode) '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 non Secured: (valid only in privilege mode) '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWHOSTAON

Address offset	0x0000 01A8
Description	HOST_AON_SLV firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWHIF

Address offset	0x0000 01B0
Description	HIF firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure) - Not in use , core always has access.
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWHOST0

Address offset	0x0000 01B4
Description	HOST MCU region 0 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:26	Reserved		RO	0x00
25:16	BASE_LEN	address base with 1K granularity : address base len for firewall is the offset from the region's base address indicated in the same region field describing the end of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU_REGION_0 address space: 0x20000000 - 0x2FFFFFFF HOST_MCU_REGION_0 base_len can range from: ##register base_len value## 0x0 - 0x7F for HOST_MCU_REGION_0 the base address for security firewalls is 0x23F80000 ( HOST_MCU_REGION_0 ) max window size is 128Kb example: worker base address: 0x23F80000 current address to access: 0x23F81504 region_base_address: 0x4 region_base_address_len: 0x2 --> (region_base_address + region_base_address_len) --> 0x4+0x2 -->0x6 0x23F81504 --> ((0x23F81504 - 0x23F80000) >> 10) -->0x4 0x4 <= 0x5 < 0x6 that address falls on the region window and therefor obeys to that region set of access rules	RW	0x000
15	Reserved		RO	0
14:4	BASE	address base with 1K granularity : address base for firewall is the the offset start address from a worker base address describing the beginning of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU address space: 0x00000000 - 0x2FFFFFFF / 0x41900000 - 0x4190FFFF HOST_MCU_REGION_0 is assigned to TCM DATA RAM HOST_MCU_REGION_0 base address can range from: ##register base value## 0x0 - 0x27F ##absolute equivalent value## 0x23F800000 - 0x2401FC00 for HOST_MCU_REGION_0 the base address for security firewalls is 0x23F80000 ( M33 TCM Data RAM ) max window size is 128Kb example: worker base address: 0x23F80000 current address to access: 0x23F80504 region_base_address: 0x1 region_base_address_len: 0x1 0x23F80504 --> ((0x23F80504 - 0x23F800000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules	RW	0x000
3	Reserved		RO	0
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWHOST1

Address offset	0x0000 01B8
Description	HOST MCU region 1 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:26	Reserved		RO	0x00
25:16	BASE_LEN	address base with 1K granularity : address base len for firewall is the offset from the region's base address indicated in the same region field describing the end of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU_REGION_0 address space: 0x20000000 - 0x2FFFFFFF HOST_MCU_REGION_0 base_len can range from: ##register base_len value## 0x0 - 0x7F for HOST_MCU_REGION_0 the base address for security firewalls is 0x23F80000 ( HOST_MCU_REGION_1 ) max window size is 128Kb example: worker base address: 0x23F80000 current address to access: 0x23F81504 region_base_address: 0x4 region_base_address_len: 0x2 --> (region_base_address + region_base_address_len) --> 0x4+0x2 -->0x6 0x23F81504 --> ((0x23F81504 - 0x23F80000) >> 10) -->0x4 0x4 <= 0x5 < 0x6 that address falls on the region window and therefor obeys to that region set of access rules	RW	0x000
15	Reserved		RO	0
14:4	BASE	address base with 1K granularity : address base for firewall is the the offset start address from a worker base address describing the beginning of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU address space: 0x00000000 - 0x2FFFFFFF / 0x41900000 - 0x4190FFFF HOST_MCU_REGION_1 is assigned to TCM DATA RAM HOST_MCU_REGION_1 base address can range from: ##register base value## 0x0 - 0x27F ##absolute equivalent value## 0x23F800000 - 0x2401FC00 for HOST_MCU_REGION_0 the base address for security firewalls is 0x23F80000 ( M33 TCM Data RAM ) max window size is 128Kb example: worker base address: 0x23F80000 current address to access: 0x23F80504 region_base_address: 0x1 region_base_address_len: 0x1 0x23F80504 --> ((0x23F80504 - 0x23F800000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules	RW	0x000
3	Reserved		RO	0
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWHOST2

Address offset	0x0000 01BC
Description	HOST MCU region 2 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:26	Reserved		RO	0x00
25:16	BASE_LEN	address base with 1K granularity : address base len for firewall is the offset from the region's base address indicated in the same region field describing the end of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU_REGION_2 address space: 0x20000000 - 0x2FFFFFFF HOST_MCU_REGION_2 base_len can range from: ##register base_len value## 0x0 - 0x240 for HOST_MCU_REGION_0 the base address for security firewalls is 0x2BF00000 ( HOST_MCU_REGION_2 ) max window size is 576Kb example: worker base address: 0x2BF00000 current address to access: 0x2BF01504 region_base_address: 0x4 region_base_address_len: 0x2 --> (region_base_address + region_base_address_len) --> 0x4+0x2 -->0x6 0x2BF01504 --> ((0x2BF01504 - 0x2BF00000) >> 10) -->0x4 0x4 <= 0x5 < 0x6 that address falls on the region window and therefor obeys to that region set of access rules	RW	0x000
15	Reserved		RO	0
14:4	BASE	address base with 1K granularity : address base for firewall is the the offset start address from a worker base address describing the beginning of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU address space: 0x00000000 - 0x2FFFFFFF / 0x41900000 - 0x4190FFFF HOST_MCU_REGION_2 is assigned to M33 DATA RAM HOST_MCU_REGION_2 base address can range from: ##register base value## 0x0 - 0x63F ##absolute equivalent value## 0x2BF00000 - 0x2C08FC00 for HOST_MCU_REGION_2 the base address for security firewalls is 0x2BF00000 ( M33 Data RAM ) max window size is 576Kb (depending on the MEMSS mode) example: worker base address: 0x2BF000000 current address to access: 0x2BF00504 region_base_address: 0x1 region_base_address_len: 0x1 0x2BF00504 --> ((0x2BF00504 - 0x2BF000000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules	RW	0x000
3	Reserved		RO	0
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWHOST3

Address offset	0x0000 01C0
Description	HOST MCU region 3 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:26	Reserved		RO	0x00
25:16	BASE_LEN	address base with 1K granularity : address base len for firewall is the offset from the region's base address indicated in the same region field describing the end of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU_REGION_2 address space: 0x20000000 - 0x2FFFFFFF HOST_MCU_REGION_2 base_len can range from: ##register base_len value## 0x0 - 0x240 for HOST_MCU_REGION_0 the base address for security firewalls is 0x2BF00000 ( HOST_MCU_REGION_2 ) max window size is 576Kb example: worker base address: 0x2BF00000 current address to access: 0x2BF01504 region_base_address: 0x4 region_base_address_len: 0x2 --> (region_base_address + region_base_address_len) --> 0x4+0x2 -->0x6 0x2BF01504 --> ((0x2BF01504 - 0x2BF00000) >> 10) -->0x4 0x4 <= 0x5 < 0x6 that address falls on the region window and therefor obeys to that region set of access rules	RW	0x000
15	Reserved		RO	0
14:4	BASE	address base with 1K granularity : address base for firewall is the the offset start address from a worker base address describing the beginning of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU address space: 0x00000000 - 0x2FFFFFFF / 0x41900000 - 0x4190FFFF HOST_MCU_REGION_3 is assigned to M33 DATA RAM HOST_MCU_REGION_3 base address can range from: ##register base value## 0x0 - 0x63F ##absolute equivalent value## 0x2BF00000 - 0x2C08FC00 for HOST_MCU_REGION_2 the base address for security firewalls is 0x2BF00000 ( M33 Data RAM ) max window size is 576Kb (depending on the MEMSS mode) example: worker base address: 0x2BF000000 current address to access: 0x2BF00504 region_base_address: 0x1 region_base_address_len: 0x1 0x2BF00504 --> ((0x2BF00504 - 0x2BF000000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules	RW	0x000
3	Reserved		RO	0
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWHOST4

Address offset	0x0000 01C4
Description	access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:27	Reserved		RO	0x00
26	BASESEL	Base select for Reserved region defaulted to M33 TCM Data RAM (base_sel = 0): this select bit will assign this region to either TCM Data (base_sel = 0) ##register base value## 0x0 - 0x80 ##absolute equivalent value## 0x200000000 - 0x20001FFFF or Data RAM (base_sel = 1) ##register base value## 0x0 - 0x63F ##absolute equivalent value## 0x2BF00000 - 0x2C08FC00 for HOST_MCU_REGION_4 with base_sel = 0 the base address for security firewalls is 0x23F80000 ( M33 TCM Data RAM ) max window size is 128Kb (depending on the MEMSS mode) for HOST_MCU_REGION_4 with base_sel = 1 the base address for security firewalls is 0x2BF00000 ( M33 Data RAM ) max window size is 576Kb (depending on the MEMSS mode) example: worker base address: 0x2BF00000 current address to access: 0x2BF00504 region_base_address: 0x1 region_base_address_len: 0x1 0x2BF00504 --> ((0x2BF00504 - 0x2BF00000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules	RW	0
25:16	BASE_LEN	address base len for firewall is the offset from the region's base address indicated in the same region field describing the end of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU_REGION_4 address space: 0x20000000 - 0x2FFFFFFF HOST_MCU_REGION_4 base_len can range from: base_sel = 0 ##register base_len value## 0x0 - 0x7F base_sel = 0 --> HOST_MCU_REGION_4 the base address for security firewalls is 0x23F80000 ( TCM M33 Data RAM ) max window size is 128Kb ################# base_sel = 1 ##register base_len value## 0x0 - 0x240 base_sel = 1 --> HOST_MCU_REGION_4 the base address for security firewalls is 0x2BF00000 (M33 Data RAM ) max window size is 576Kb ################# example: worker base address: 0x23F80000 current address to access: 0x23F81504 region_base_address: 0x4 region_base_address_len: 0x2 --> (region_base_address + region_base_address_len) --> 0x4+0x2 -->0x6 0x23F81504 --> ((0x23F81504 - 0x23F80000) >> 10) -->0x4 0x4 <= 0x5 < 0x6 that address falls on the region window and therefor obeys to that region set of access rules	RW	0x000
15	Reserved		RO	0
14:4	BASE	address base with 1K granularity : address base for firewall is the the offset start address from a worker base address describing the beginning of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU address space: 0x00000000 - 0x2FFFFFFF / 0x41900000 - 0x4190FFFF HOST_MCU_REGION_4 is assigned to TCM DATA RAM (base_sel = 0) or M33 Data Ram (base_sel = 1) HOST_MCU_REGION_4 base address can range from: (base_sel = 0) ##register base value## 0x0 - 0x27F ##absolute equivalent value## 0x23F80000 - 0x2401FC00 for HOST_MCU_REGION_4 the base address for security firewalls is 0x23F80000 ( TCM Data RAM ) max window size is 128Kb ################## (base_sel = 1) ##register base value## 0x0 - 0x63F ##absolute equivalent value## 0x2BF000000 - 0x2C08FC00 for HOST_MCU_REGION_4 the base address for security firewalls is 0x2BF00000 ( M33 Data RAM ) max window size is 576Kb (depending on the MEMSS mode) example: worker base address: 0x2BF000000 current address to access: 0x2BF00504 region_base_address: 0x1 region_base_address_len: 0x1 0x2BF00504 --> ((0x2BF00504 - 0x2BF00000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules	RW	0x000
3	Reserved		RO	0
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWHOST5

Address offset	0x0000 01C8
Description	HOST MCU region 5 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:27	Reserved		RO	0x00
26	BASESEL	Base select for Reserved region defaulted to M33 TCM Data RAM (base_sel = 0): this select bit will assign this region to either TCM Data (base_sel = 0) ##register base value## 0x0 - 0x80 ##absolute equivalent value## 0x200000000 - 0x20001FFFF or Data RAM (base_sel = 1) ##register base value## 0x0 - 0x63F ##absolute equivalent value## 0x2BF00000 - 0x2C08FC00 for HOST_MCU_REGION_4 with base_sel = 0 the base address for security firewalls is 0x23F80000 ( M33 TCM Data RAM ) max window size is 128Kb (depending on the MEMSS mode) for HOST_MCU_REGION_4 with base_sel = 1 the base address for security firewalls is 0x2BF00000 ( M33 Data RAM ) max window size is 576Kb (depending on the MEMSS mode) example: worker base address: 0x2BF00000 current address to access: 0x2BF00504 region_base_address: 0x1 region_base_address_len: 0x1 0x2BF00504 --> ((0x2BF00504 - 0x2BF00000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules	RW	0
25:16	BASE_LEN	address base len for firewall is the offset from the region's base address indicated in the same region field describing the end of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU_REGION_4 address space: 0x20000000 - 0x2FFFFFFF HOST_MCU_REGION_4 base_len can range from: base_sel = 0 ##register base_len value## 0x0 - 0x7F base_sel = 0 --> HOST_MCU_REGION_4 the base address for security firewalls is 0x23F80000 ( TCM M33 Data RAM ) max window size is 128Kb ################# base_sel = 1 ##register base_len value## 0x0 - 0x240 base_sel = 1 --> HOST_MCU_REGION_4 the base address for security firewalls is 0x2BF00000 (M33 Data RAM ) max window size is 576Kb ################# example: worker base address: 0x23F80000 current address to access: 0x23F81504 region_base_address: 0x4 region_base_address_len: 0x2 --> (region_base_address + region_base_address_len) --> 0x4+0x2 -->0x6 0x23F81504 --> ((0x23F81504 - 0x23F80000) >> 10) -->0x4 0x4 <= 0x5 < 0x6 that address falls on the region window and therefor obeys to that region set of access rules	RW	0x000
15	Reserved		RO	0
14:4	BASE	address base with 1K granularity : address base for firewall is the the offset start address from a worker base address describing the beginning of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU address space: 0x00000000 - 0x2FFFFFFF / 0x41900000 - 0x4190FFFF HOST_MCU_REGION_4 is assigned to TCM DATA RAM (base_sel = 0) or M33 Data Ram (base_sel = 1) HOST_MCU_REGION_4 base address can range from: (base_sel = 0) ##register base value## 0x0 - 0x27F ##absolute equivalent value## 0x23F80000 - 0x2401FC00 for HOST_MCU_REGION_4 the base address for security firewalls is 0x23F80000 ( TCM Data RAM ) max window size is 128Kb ################## (base_sel = 1) ##register base value## 0x0 - 0x63F ##absolute equivalent value## 0x2BF000000 - 0x2C08FC00 for HOST_MCU_REGION_4 the base address for security firewalls is 0x2BF00000 ( M33 Data RAM ) max window size is 576Kb (depending on the MEMSS mode) example: worker base address: 0x2BF000000 current address to access: 0x2BF00504 region_base_address: 0x1 region_base_address_len: 0x1 0x2BF00504 --> ((0x2BF00504 - 0x2BF00000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules	RW	0x000
3	Reserved		RO	0
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWHOST6

Address offset	0x0000 01CC
Description	HOST MCU region 6 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:27	Reserved		RO	0x00
26	BASESEL	Base select for Reserved region defaulted to M33 TCM Data RAM (base_sel = 0): this select bit will assign this region to either TCM Data (base_sel = 0) ##register base value## 0x0 - 0x80 ##absolute equivalent value## 0x200000000 - 0x20001FFFF or Data RAM (base_sel = 1) ##register base value## 0x0 - 0x63F ##absolute equivalent value## 0x2BF00000 - 0x2C08FC00 for HOST_MCU_REGION_4 with base_sel = 0 the base address for security firewalls is 0x23F80000 ( M33 TCM Data RAM ) max window size is 128Kb (depending on the MEMSS mode) for HOST_MCU_REGION_4 with base_sel = 1 the base address for security firewalls is 0x2BF00000 ( M33 Data RAM ) max window size is 576Kb (depending on the MEMSS mode) example: worker base address: 0x2BF00000 current address to access: 0x2BF00504 region_base_address: 0x1 region_base_address_len: 0x1 0x2BF00504 --> ((0x2BF00504 - 0x2BF00000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules	RW	1
25:16	BASE_LEN	address base len for firewall is the offset from the region's base address indicated in the same region field describing the end of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU_REGION_4 address space: 0x20000000 - 0x2FFFFFFF HOST_MCU_REGION_4 base_len can range from: base_sel = 0 ##register base_len value## 0x0 - 0x7F base_sel = 0 --> HOST_MCU_REGION_4 the base address for security firewalls is 0x23F80000 ( TCM M33 Data RAM ) max window size is 128Kb ################# base_sel = 1 ##register base_len value## 0x0 - 0x240 base_sel = 1 --> HOST_MCU_REGION_4 the base address for security firewalls is 0x2BF00000 (M33 Data RAM ) max window size is 576Kb ################# example: worker base address: 0x23F80000 current address to access: 0x23F81504 region_base_address: 0x4 region_base_address_len: 0x2 --> (region_base_address + region_base_address_len) --> 0x4+0x2 -->0x6 0x23F81504 --> ((0x23F81504 - 0x23F80000) >> 10) -->0x4 0x4 <= 0x5 < 0x6 that address falls on the region window and therefor obeys to that region set of access rules	RW	0x000
15	Reserved		RO	0
14:4	BASE	address base with 1K granularity : address base for firewall is the the offset start address from a worker base address describing the beginning of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU address space: 0x00000000 - 0x2FFFFFFF / 0x41900000 - 0x4190FFFF HOST_MCU_REGION_4 is assigned to TCM DATA RAM (base_sel = 0) or M33 Data Ram (base_sel = 1) HOST_MCU_REGION_4 base address can range from: (base_sel = 0) ##register base value## 0x0 - 0x27F ##absolute equivalent value## 0x23F80000 - 0x2401FC00 for HOST_MCU_REGION_4 the base address for security firewalls is 0x23F80000 ( TCM Data RAM ) max window size is 128Kb ################## (base_sel = 1) ##register base value## 0x0 - 0x63F ##absolute equivalent value## 0x2BF000000 - 0x2C08FC00 for HOST_MCU_REGION_4 the base address for security firewalls is 0x2BF00000 ( M33 Data RAM ) max window size is 576Kb (depending on the MEMSS mode) example: worker base address: 0x2BF000000 current address to access: 0x2BF00504 region_base_address: 0x1 region_base_address_len: 0x1 0x2BF00504 --> ((0x2BF00504 - 0x2BF00000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules	RW	0x000
3	Reserved		RO	0
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWHOST7

Address offset	0x0000 01D0
Description	HOST MCU region 7 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:27	Reserved		RO	0x00
26	BASESEL	Base select for Reserved region defaulted to M33 TCM Data RAM (base_sel = 0): this select bit will assign this region to either TCM Data (base_sel = 0) ##register base value## 0x0 - 0x80 ##absolute equivalent value## 0x200000000 - 0x20001FFFF or Data RAM (base_sel = 1) ##register base value## 0x0 - 0x63F ##absolute equivalent value## 0x2BF00000 - 0x2C08FC00 for HOST_MCU_REGION_4 with base_sel = 0 the base address for security firewalls is 0x23F80000 ( M33 TCM Data RAM ) max window size is 128Kb (depending on the MEMSS mode) for HOST_MCU_REGION_4 with base_sel = 1 the base address for security firewalls is 0x2BF00000 ( M33 Data RAM ) max window size is 576Kb (depending on the MEMSS mode) example: worker base address: 0x2BF00000 current address to access: 0x2BF00504 region_base_address: 0x1 region_base_address_len: 0x1 0x2BF00504 --> ((0x2BF00504 - 0x2BF00000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules	RW	1
25:16	BASE_LEN	address base len for firewall is the offset from the region's base address indicated in the same region field describing the end of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU_REGION_4 address space: 0x20000000 - 0x2FFFFFFF HOST_MCU_REGION_4 base_len can range from: base_sel = 0 ##register base_len value## 0x0 - 0x7F base_sel = 0 --> HOST_MCU_REGION_4 the base address for security firewalls is 0x23F80000 ( TCM M33 Data RAM ) max window size is 128Kb ################# base_sel = 1 ##register base_len value## 0x0 - 0x240 base_sel = 1 --> HOST_MCU_REGION_4 the base address for security firewalls is 0x2BF00000 (M33 Data RAM ) max window size is 576Kb ################# example: worker base address: 0x23F80000 current address to access: 0x23F81504 region_base_address: 0x4 region_base_address_len: 0x2 --> (region_base_address + region_base_address_len) --> 0x4+0x2 -->0x6 0x23F81504 --> ((0x23F81504 - 0x23F80000) >> 10) -->0x4 0x4 <= 0x5 < 0x6 that address falls on the region window and therefor obeys to that region set of access rules	RW	0x000
15	Reserved		RO	0
14:4	BASE	address base with 1K granularity : address base for firewall is the the offset start address from a worker base address describing the beginning of a firewall window that has a certain access rules (R/W Permission) for each controller-id HOST_MCU address space: 0x00000000 - 0x2FFFFFFF / 0x41900000 - 0x4190FFFF HOST_MCU_REGION_4 is assigned to TCM DATA RAM (base_sel = 0) or M33 Data Ram (base_sel = 1) HOST_MCU_REGION_4 base address can range from: (base_sel = 0) ##register base value## 0x0 - 0x27F ##absolute equivalent value## 0x23F80000 - 0x2401FC00 for HOST_MCU_REGION_4 the base address for security firewalls is 0x23F80000 ( TCM Data RAM ) max window size is 128Kb ################## (base_sel = 1) ##register base value## 0x0 - 0x63F ##absolute equivalent value## 0x2BF000000 - 0x2C08FC00 for HOST_MCU_REGION_4 the base address for security firewalls is 0x2BF00000 ( M33 Data RAM ) max window size is 576Kb (depending on the MEMSS mode) example: worker base address: 0x2BF000000 current address to access: 0x2BF00504 region_base_address: 0x1 region_base_address_len: 0x1 0x2BF00504 --> ((0x2BF00504 - 0x2BF00000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules	RW	0x000
3	Reserved		RO	0
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWHOST8

Address offset	0x0000 01D4
Description	HOST MCU region 8 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWHOST9

Address offset	0x0000 01D8
Description	HOST MCU region 9 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWHOST10

Address offset	0x0000 01DC
Description	HOST MCU region 10 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWHOST11

Address offset	0x0000 01E0
Description	HOST MCU region 11 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWXIPOSPI

Address offset	0x0000 01E4
Description	XIP_OSPI firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWXIPINDAC

Address offset	0x0000 01E8
Description	OSPI_INDAC firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWXIPGEN

Address offset	0x0000 01EC
Description	XIP_GEN firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWXIPUDMAS

Address offset	0x0000 01F0
Description	XIP_UDMA_SEC firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWXIPUDMANS

Address offset	0x0000 01F4
Description	UDMA_NONSEC firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWOTFDE0

Address offset	0x0000 01F8
Description	OTFDE_REGION0 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWOTFDE1

Address offset	0x0000 01FC
Description	OTFDE_REGION1 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWOTFDE2

Address offset	0x0000 0200
Description	OTFDE_REGION2 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWOTFDE3

Address offset	0x0000 0204
Description	OTFDE_REGION3 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWDMAGEN

Address offset	0x0000 0208
Description	DMA_GEN firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWDMA0

Address offset	0x0000 020C
Description	DMA_CH_0 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWDMA1

Address offset	0x0000 0210
Description	DMA_CH_1 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWDMA2

Address offset	0x0000 0214
Description	DMA_CH_2 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWDMA3

Address offset	0x0000 0218
Description	DMA_CH_3 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWDMA4

Address offset	0x0000 021C
Description	DMA_CH_4 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWDMA5

Address offset	0x0000 0220
Description	DMA_CH_5 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWDMA6

Address offset	0x0000 0224
Description	DMA_CH_6 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWDMA7

Address offset	0x0000 0228
Description	DMA_CH_7 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWDMA8

Address offset	0x0000 022C
Description	DMA_CH_8 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWDMA9

Address offset	0x0000 0230
Description	DMA_CH_9 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWDMA10

Address offset	0x0000 0234
Description	DMA_CH_10 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWDMA11

Address offset	0x0000 0238
Description	DMA_CH_11 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWHSMEIPNS

Address offset	0x0000 023C
Description	HSM EIP NONSEC firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:21	Reserved		RO	0x000
20:16	LEN	address base with 1K granularity : address base len for firewall is the offset from the region's base address indicated in the same region field describing the end of a firewall window that has a certain access rules (R/W Permission) for each controller-id HSM address space: 0x41B00000 - 0x41B3FFFF HSM_EIP_REGS base_len can range from: ##register base_len value## 0x0 - 0xF for HSM the base address for security firewalls is 0x41B00000 ( HSM_EIP_REGS ) max window size is 16Kb example: worker base address: 0x41B00000 current address to access: 0x41B01504 region_base_address: 0x4 region_base_address_len: 0x2 --> (region_base_address + region_base_address_len) --> 0x4+0x2 -->0x6 0x41B01504 --> ((0x41B01504 - 0x41B00000) >> 10) -->0x4 0x4 <= 0x5 < 0x6 that address falls on the region window and therefor obeys to that region set of access rules	RW	0x00
15:9	Reserved		RO	0x00
8:4	BASE	address base with 1K granularity : address base for firewall is the the offset start address from a worker base address describing the beginning of a firewall window that has a certain access rules (R/W Permission) for each controller-id HSM address space: 0x41B00000 - 0x41B3FFFF HSM_EIP_REGS base address can range from: ##register base value## 0x0 - 0xF ##absolute equivalent value## 0x41B00000 - 0x41B03FFF for HSM the base address for security firewalls is 0x41B00000 ( HSM_EIP_REGS ) max window size is 16Kb example: worker base address: 0x41B00000 current address to access: 0x41B00504 region_base_address: 0x1 region_base_address_len: 0x1 0x41B00504 --> ((0x41B00504 - 0x41B00000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules	RW	0x00
3	Reserved		RO	0
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWHSMEIPS

Address offset	0x0000 0240
Description	HSM EIP SEC firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:21	Reserved		RO	0x000
20:16	BASE_LEN	address base with 1K granularity : address base len for firewall is the offset from the region's base address indicated in the same region field describing the end of a firewall window that has a certain access rules (R/W Permission) for each controller-id HSM address space: 0x41B00000 - 0x41B3FFFF HSM_EIP_REGS base_len can range from: ##register base_len value## 0x0 - 0xF for HSM the base address for security firewalls is 0x41B00000 ( HSM_EIP_REGS ) max window size is 16Kb example: worker base address: 0x41B00000 current address to access: 0x41B01504 region_base_address: 0x4 region_base_address_len: 0x2 --> (region_base_address + region_base_address_len) --> 0x4+0x2 -->0x6 0x41B01504 --> ((0x41B01504 - 0x41B00000) >> 10) -->0x4 0x4 <= 0x5 < 0x6 that address falls on the region window and therefor obeys to that region set of access rules	RW	0x00
15:9	Reserved		RO	0x00
8:4	BASE	address base with 1K granularity : address base for firewall is the the offset start address from a worker base address describing the beginning of a firewall window that has a certain access rules (R/W Permission) for each controller-id HSM address space: 0x41B00000 - 0x41B3FFFF HSM_EIP_REGS base address can range from: ##register base value## 0x0 - ##absolute equivalent value## 0x41B00000 - 0x41B03FFF for HSM the base address for security firewalls is 0x41B00000 ( HSM_EIP_REGS ) max window size is 16Kb example: worker base address: 0x41B00000 current address to access: 0x41B00504 region_base_address: 0x1 region_base_address_len: 0x1 0x41B00504 --> ((0x41B00504 - 0x41B00000) >> 10) --> 0x1 0x1(base) <= 0x1(current) < 0x1(base)+0x1(len) that address falls on the region window and therefor obeys to that region set of access rules	RW	0x00
3	Reserved		RO	0
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWHSMWRAPNS

Address offset	0x0000 0244
Description	HSM Wrapper NONSEC firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWHSMWRAPS

Address offset	0x0000 0248
Description	HSM Wrapper SEC firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWHSMDBG

Address offset	0x0000 024C
Description	HSM DEBUG firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWI2C0

Address offset	0x0000 0250
Description	I2C0 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWI2C1

Address offset	0x0000 0254
Description	I2C1 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWSPSPI0

Address offset	0x0000 0258
Description	SPI0 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWSPSPI1

Address offset	0x0000 025C
Description	SPI1 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWSPUART0

Address offset	0x0000 0260
Description	UART0 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWSPUART1

Address offset	0x0000 0264
Description	UART1 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWSPGPT0

Address offset	0x0000 0268
Description	GPTIMER0 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWSPGPT1

Address offset	0x0000 026C
Description	GPTIMER1 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWSPI2S

Address offset	0x0000 0270
Description	I2S firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWPDM

Address offset	0x0000 0274
Description	PDM firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWSPCAN

Address offset	0x0000 0278
Description	CAN firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWSPADC

Address offset	0x0000 027C
Description	ADC firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWSPSDMMC

Address offset	0x0000 0280
Description	SDMMC firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWSPSDIO

Address offset	0x0000 0284
Description	SDIO firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWSPUART2

Address offset	0x0000 0288
Description	UART2 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:UDMANSCTL

Address offset	0x0000 028C
Description	uDMA Non-secured Channel Control.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	ACCPER	Access Permission. Define uDMA non-sec channel access permission to secured flash address: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD0

Address offset	0x0000 0290
Description	IOMUX_PAD_0 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD1

Address offset	0x0000 0294
Description	IOMUX_PAD_1 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD2

Address offset	0x0000 0298
Description	IOMUX_PAD_2 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD3

Address offset	0x0000 029C
Description	IOMUX_PAD_3 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD4

Address offset	0x0000 02A0
Description	IOMUX_PAD_4 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD5

Address offset	0x0000 02A4
Description	IOMUX_PAD_5 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD6

Address offset	0x0000 02A8
Description	IOMUX_PAD_6 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD7

Address offset	0x0000 02AC
Description	IOMUX_PAD_7 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD8

Address offset	0x0000 02B0
Description	IOMUX_PAD_8 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD9

Address offset	0x0000 02B4
Description	IOMUX_PAD_9 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD10

Address offset	0x0000 02B8
Description	IOMUX_PAD_10 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD11

Address offset	0x0000 02BC
Description	IOMUX_PAD_11 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD12

Address offset	0x0000 02C0
Description	IOMUX_PAD_12 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD13

Address offset	0x0000 02C4
Description	IOMUX_PAD_13 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD14

Address offset	0x0000 02C8
Description	IOMUX_PAD_14 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD15

Address offset	0x0000 02CC
Description	IOMUX_PAD_15 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD16

Address offset	0x0000 02D0
Description	IOMUX_PAD_16 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD17

Address offset	0x0000 02D4
Description	IOMUX_PAD_17 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD18

Address offset	0x0000 02D8
Description	IOMUX_PAD_18 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD19

Address offset	0x0000 02DC
Description	IOMUX_PAD_19 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD20

Address offset	0x0000 02E0
Description	IOMUX_PAD_20 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD21

Address offset	0x0000 02E4
Description	IOMUX_PAD_21 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD22

Address offset	0x0000 02E8
Description	IOMUX_PAD_22 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD23

Address offset	0x0000 02EC
Description	IOMUX_PAD_23 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD24

Address offset	0x0000 02F0
Description	IOMUX_PAD_24 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD25

Address offset	0x0000 02F4
Description	IOMUX_PAD_25 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD26

Address offset	0x0000 02F8
Description	IOMUX_PAD_26 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD27

Address offset	0x0000 02FC
Description	IOMUX_PAD_27 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD28

Address offset	0x0000 0300
Description	IOMUX_PAD_28 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD29

Address offset	0x0000 0304
Description	IOMUX_PAD_29 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD30

Address offset	0x0000 0308
Description	IOMUX_PAD_30 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD31

Address offset	0x0000 030C
Description	IOMUX_PAD_31 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD32

Address offset	0x0000 0310
Description	IOMUX_PAD_32 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD33

Address offset	0x0000 0314
Description	IOMUX_PAD_33 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD34

Address offset	0x0000 0318
Description	IOMUX_PAD_34 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD35

Address offset	0x0000 031C
Description	IOMUX_PAD_35 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD36

Address offset	0x0000 0320
Description	IOMUX_PAD_36 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD37

Address offset	0x0000 0324
Description	IOMUX_PAD_37 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD38

Address offset	0x0000 0328
Description	IOMUX_PAD_38 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD39

Address offset	0x0000 032C
Description	IOMUX_PAD_39 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD40

Address offset	0x0000 0330
Description	IOMUX_PAD_40 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD41

Address offset	0x0000 0334
Description	IOMUX_PAD_41 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD42

Address offset	0x0000 0338
Description	IOMUX_PAD_42 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD43

Address offset	0x0000 033C
Description	IOMUX_PAD_43 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD44

Address offset	0x0000 0340
Description	IOMUX_PAD_44 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD45

Address offset	0x0000 0344
Description	IOMUX_PAD_45 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD46

Address offset	0x0000 0348
Description	IOMUX_PAD_46 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD47

Address offset	0x0000 034C
Description	IOMUX_PAD_47 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWIOPAD48

Address offset	0x0000 0350
Description	IOMUX_PAD_48 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWDMA12

Address offset	0x0000 0354
Description	DMA_CH_12 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWDMA13

Address offset	0x0000 0358
Description	DMA_CH_13 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:SECGK_FIREWALL_CONFIG_SPARE0_0

Address offset	0x0000 035C
Description	Spare firewall access register. locked by HOST BOOT DONE (secgk) 3 access bits - {M33NS , M33S , M3} .
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	MEM_SPARE0_0_ACCESS_REG_CORE_NS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	MEM_SPARE0_0_ACCESS_REG_M33_S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	MEM_SPARE0_0_ACCESS_REG_M33_NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:USECSTB

Address offset	0x0000 1000
Description	Micro Second STB
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:8	16US	Set how many micro second strobes are in 16 micro seconds, minus 1. Default: 16-1 =15.	RW	0x0F
7:0	MEM_USECSTB	Set how many soc clk are in one micro second, minus 1. for 40mhz : should be 39. for 80mhz : should be 79. (Soc clock default is 80MHz)	RW	0x4F

:SOC_AON:DB2M33CLR

Address offset	0x0000 1004
Description	Doorbell 2 M33 Clear Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	CLR	M33 to clear the IRQ when handled the massage from M3 Type: Write-Clear	WO	0

:SOC_AON:DB2M33SET

Address offset	0x0000 1008
Description	Doorbell 2 M33 Set Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	SET	M33 to generate IRQ towards M3 after writing the message Type: Write-Clear	WO	0

:SOC_AON:DB2M33LOCK

Address offset	0x0000 100C
Description	Doorbell 2 M33 Lockbit Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1:0	LOCKBIT	Lock Bit. S/w attempt to lock upon read. if lock obtained, value set to 2 by h/w. M33 always looses to M3 Reading value: 00: not taken 01: taken by M3 10: taken by M33 (should wr IRQ afterwards) 11: invalid. generating the IRQ towards M1 clears the lock. Writing '00' also release the lock. 2'b01 means lock obtained by receiver side Type: Write-Read-Clear	RW	0x0

:SOC_AON:DB3M33CLR

Address offset	0x0000 1010
Description	Doorbell 3 M33 Clear Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	CLR	M33 to clear the IRQ when handled the massage from M3 Type: Write-Clear	WO	0

:SOC_AON:DB3M33SET

Address offset	0x0000 1014
Description	Doorbell 3 M33 Set Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	SET	M33 to generate IRQ towards M3 after writing the message Type: Write-Clear	WO	0

:SOC_AON:DB3M33LOCK

Address offset	0x0000 1018
Description	Doorbell 3 M33 Lockbit Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1:0	LOCKBIT	Lock Bit. S/w attempt to lock upon read. if lock obtained, value set to 2 by h/w. M33 always looses to M3 Reading value: 00: not taken 01: taken by M3 10: taken by M33 (should wr IRQ afterwards) 11: invalid. generating the IRQ towards M1 clears the lock. Writing '00' also release the lock. 2'b01 means lock obtained by receiver side Type: Write-Read-Clear	RW	0x0

:SOC_AON:DB6M33CLR

Address offset	0x0000 101C
Description	Doorbell 6 M33 Clear Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	CLR	M33 to clear the IRQ when handled the massage from M3 Type: Write-Clear	WO	0

:SOC_AON:DB6M33SET

Address offset	0x0000 1020
Description	Doorbell 6 M33 Set Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	SET	M33 to generate IRQ towards M3 after writing the message Type: Write-Clear	WO	0

:SOC_AON:DB6M33LOCK

Address offset	0x0000 1024
Description	Doorbell 6 M33 Lockbit Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1:0	LOCKBIT	Lock Bit. S/w attempt to lock upon read. if lock obtained, value set to 2 by h/w. M33 always looses to M3 Reading value: 00: not taken 01: taken by M3 10: taken by M33 (should wr IRQ afterwards) 11: invalid. generating the IRQ towards M1 clears the lock. Writing '00' also release the lock. 2'b01 means lock obtained by receiver side Type: Write-Read-Clear	RW	0x0

:SOC_AON:DB7M33CLR

Address offset	0x0000 1028
Description	Doorbell 7 M33 Clear Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	CLR	M33 to clear the IRQ when handled the massage from M3 Type: Write-Clear	WO	0

:SOC_AON:DB7M33SET

Address offset	0x0000 102C
Description	Doorbell 7 M33 Set Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	SET	M33 to generate IRQ towards M3 after writing the message Type: Write-Clear	WO	0

:SOC_AON:DB7M33LOCK

Address offset	0x0000 1030
Description	Doorbell 7 M33 Lockbit Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1:0	LOCKBIT	Lock Bit. S/w attempt to lock upon read. if lock obtained, value set to 2 by h/w. M33 always looses to M3 Reading value: 00: not taken 01: taken by M3 10: taken by M33 (should wr IRQ afterwards) 11: invalid. generating the IRQ towards M1 clears the lock. Writing '00' also release the lock. 2'b01 means lock obtained by receiver side Type: Write-Read-Clear	RW	0x0

:SOC_AON:NON_GPIOEVTS0

Address offset	0x0000 1044
Description	Non-Secured GPIO Event Status, 1st Register. 45 bits status over two registers.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	NON_STA31TO0	Non-Secured event status , first 32 bits. ([31:0])			RO	0x0000 0000

:SOC_AON:NON_GPIOEVTS1

Address offset	0x0000 1048
Description	Non-Secured GPIO Event Status, 2nd Register. 45 bits status over two registers.
Type	RW

Bits	Field Name	Description	Type	Reset
31:13	Reserved		RO	0x0 0000
12:0	NON_STA44TO32	Non-Secured event status , 13 MSBs. ([44:32])	RO	0x0000

:SOC_AON:DBM33NS0

Address offset	0x0000 1054
Description	M33 Non-Secured Doorbell IMASK. Mask Event. '0' - CLR - Clear Interrupt Mask '1' - SET - Set Interrupt Mask
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:0	IMASK	bit3 - doorbell 7 M3 IRQ bit2 - doorbell 6 M3 IRQ bit1 - doorbell 3 M3 IRQ bit0 - doorbell 2 M3 IRQ	RW	0x0

:SOC_AON:DBNSISET

Address offset	0x0000 1058
Description	M33 Non-Secured Doorbells ISET. Sets event in RIS Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - SET - Sets interrupt
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:0	ISET	bit3 - doorbell 7 M3 IRQ bit2 - doorbell 6 M3 IRQ bit1 - doorbell 3 M3 IRQ bit0 - doorbell 2 M3 IRQ Type: Write-Clear	WO	0x0

:SOC_AON:DBNSICLR

Address offset	0x0000 105C
Description	M33 Non-Secured Doorbell ICLR. Clears event in RIS Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - CLR - Clears the Event
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:0	ICLR	bit3 - doorbell 7 M3 IRQ bit2 - doorbell 6 M3 IRQ bit1 - doorbell 3 M3 IRQ bit0 - doorbell 2 M3 IRQ Type: Write-Clear	WO	0x0

:SOC_AON:DBNSIMSET

Address offset	0x0000 1060
Description	M33 Non-Secured Doorbell IMSET. Sets Event Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - SET - Set interrupt mask
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:0	IMSET	bit3 - doorbell 7 M3 IRQ bit2 - doorbell 6 M3 IRQ bit1 - doorbell 3 M3 IRQ bit0 - doorbell 2 M3 IRQ Type: Write-Clear	WO	0x0

:SOC_AON:DBNSIMCLR

Address offset	0x0000 1064
Description	M33 Non-Secured Doorbell IMCLR, Clears Event Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - CLR - Clear interrupt mask
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:0	IMCLR	bit3 - doorbell 7 M3 IRQ bit2 - doorbell 6 M3 IRQ bit1 - doorbell 3 M3 IRQ bit0 - doorbell 2 M3 IRQ Type: Write-Clear	WO	0x0

:SOC_AON:DBNSRIS

Address offset	0x0000 1068
Description	M33 Non-Secured Doorbell RIS. Raw interrupt status for event. This bit is set to 1 when an event is received. when the corresponding bit in ICLR is set to 1, this bit will be cleared. Read 0 - CLR - Interrupt did not occur Read 1 - SET - Interrupt occurred
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:0	RIS	bit3 - doorbell 7 M3 IRQ bit2 - doorbell 6 M3 IRQ bit1 - doorbell 3 M3 IRQ bit0 - doorbell 2 M3 IRQ	RO	0x0

:SOC_AON:DBNSMIS

Address offset	0x0000 106C
Description	M33 Non-Secured Doorbell MIS. Mask interrupt status for event Read 0 - CLR - Interrupt did not occur Read 1 - SET - Interrupt occurred
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:0	MIS	bit3 - doorbell 7 M3 IRQ bit2 - doorbell 6 M3 IRQ bit1 - doorbell 3 M3 IRQ bit0 - doorbell 2 M3 IRQ	RO	0x0

:SOC_AON:NON_GPIOMIS0S

Address offset	0x0000 1070
Description	Non Secured GPIO MIS. 31-0
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	NON_31TO0	32 LSBs of GPIO MIS			RO	0x0000 0000

:SOC_AON:NON_GPIOMIS1S

Address offset	0x0000 1074
Description	Non Secure GPIO MIS. 44-32
Type	RW

Bits	Field Name	Description	Type	Reset
31:13	Reserved		RO	0x0 0000
12:0	NON_44TO32	13 MSBs of GPIO MIS. 44-32	RO	0x0000

:SOC_AON:NON_GPIOFNC0S

Address offset	0x0000 1078
Description	Non Secured GPIO Functional Mask. 31-0 0. Mask 1. Un-Mask
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	MASK31TO0	32 LSBs of non-secured functional mask for GPIO.			RW	0x0000 0000

:SOC_AON:NON_GPIOFNC1S

Address offset	0x0000 107C
Description	non secured gpio functional mask
Type	RW

Bits	Field Name	Description	Type	Reset
31:13	Reserved		RO	0x0 0000
12:0	MASK44TO32	13 MSBs of non-secured functional mask for GPIO. 44-32	RW	0x0000

:SOC_AON:SPARE20

Address offset	0x0000 1080
Description	Spare Register for M22 Secured Aperture. not locked.
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:0	MEM_SPARE20	M33NS spare register. not locked.	RW	0x0

:SOC_AON:FUSE

Address offset	0x0000 2004
Description	Selected Security Fuse Lines. This register contain selected fields reflects Security from Fuse lines.
Type	RW

Bits	Field Name	Description	Type	Reset
31:24	Reserved		RO	0x00
23:21	MEMSTCK	Enable watchdog timer for protecting boot: (This enable M33 watchdog second threshold to reset device when asserted). 0 - Disable Boot Watchdog 1 - Enable Boot Watchdog	RO	0x0
20:18	PRIVDBGREQ	Enforce TI privilege Debug Request (Relevant in AT TEST privilege only used by SW) 0 - Disable other (1-7) - Enable (When SW check these bits: if equal to '0' bypass otherwise check.)	RO	0x0
17:16	LDAUTHEN	RAM Bootloader authentication enable: 00 - Disable Other- Enable	RO	0x0
15	RESBOOTEXE	Resume boot in non-normal boot flows where the boot cannot progress (e.g. when assets are hidden). For example, in forced supply in operational or deployed life cycles, 1st bday/at test (normal) life cycles, etc. 0 - Halt boot execution as early as possible 1 - Resume/Continue boot execution This bit is ignored when the device can run the boot flow normally (e.g. deployed life cycle with default SOP).	RO	0
14	DISVERB	Disable Verbose Mode 0 - Verbose Mode (Enable) - Full Logger 1 - Normal Mode (Disable)	RO	0
13	RANDDLYEN	Random Delay Enable: 0 - Disable 1 - Enable	RO	0
12	ENBOOTWDT	Enable watchdog timer for protecting boot: (This enable M33 watchdog second threshold to reset device when asserted). 0 - Disable Boot Watchdog 1 - Enable Boot Watchdog	RO	0
11	DISCANFD	Disable CAN FD - to eliminate the need to pay royalties 0 - Enable 1 - Disable (In probe we can program '0' (which practically means not programming) to achieve continuous programming it of all shifted rows) HCANEN (Enable/Disable the CAN IP) - Determined according to paper spin HCANRAMEN(Enable disable access to CAN memory) - Determined according to paper spin. HCANFDEN - Disable/Enable CAN. Determined according to eFuse bit (this bit)	RO	0
10:9	TEMP	Supported Temperature 00 - 85degC 01 - 105degC 10 - 125degC 11 - Reserved	RO	0x0
8	DISM33	Disable M33 0 - Enable 1 - Disable (In probe we can program '0' (which practically means not programming) to achieve continuous programming it of all shifted rows)	RO	0
7	DISBLE_M0PLUS	Disable BLE M0+ (RFC_CPE_CLKEN ) 0 - Enable 1 - Disable (In probe we can program '0' (which practically means not programming) to achieve continuous programming it of all shifted rows)	RO	0
6	DISBLE	Disable BLE (RFC_MDM_CLKEN) 0 - Enable 1 - Disable (In probe we can program '0' (which practically means not programming) to achieve continuous programming it of all shifted rows)	RO	0
5	DIS6GHZ	Disable 6GHz 0 - Enable 1 - Disable (In probe we can program '0' (which practically means not programming) to achieve continuous programming it of all shifted rows)	RO	0
4	DIS5GHZ	Disable 5GHz 0 - Enable 1 - Disable (In probe we can program '0' (which practically means not programming) to achieve continuous programming it of all shifted rows)	RO	0
3:0	BOOTLVL	Determine which part of the boot ROM bypass options for risk mitigation Level0 - Do not bypass anything Level1- Ignore Error Level2 - TI ROM bypass Level3 - Minimize access to HW. Do min mandatory. 0b0110 - Level3 0b1010 - Level 2 0b0101 - Level 1 All the rest - Level 0	RO	0x0

:SOC_AON:ESM1CFG

Address offset	0x0000 2048
Description	ESM1 Configuration- Customer Debug M33 Non Secure Enable Sequence Monitor. Enable timeout mechanism and timeout counter value.
Type	RW

Bits	Field Name	Description	Type	Reset
31:12	Reserved		RO	0x0 0000
11:8	TIMEOUTCNT	This field sets the timeout value. time resolution equals to 16us. while: value 0 representing 16us value 1 - 216us value 2 - 316us and so on. value 15 is not supported.	RW	0x1
7:1	Reserved		RO	0x00
0	ENTIMEOUT	This field enables timeout mechanism for ESM.	RW	1

:SOC_AON:ESM1EN1

Address offset	0x0000 204C
Description	ESM1 Enable Number 1.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	EN1	This field is the 1st enable for the ESM. Type: Write-Clear	WO	0

:SOC_AON:ESM1EN2

Address offset	0x0000 2050
Description	ESM1 Enable Number 2.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	EN2	This field is the 2nd enable for the ESM. Type: Write-Clear	WO	0

:SOC_AON:ESM1EN3

Address offset	0x0000 2054
Description	ESM1 Enable Number 3.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	EN3	This field is the 3rd enable for the ESM. Type: Write-Clear	WO	0

:SOC_AON:ESM1EN4

Address offset	0x0000 2058
Description	ESM1 Enable Number 4.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	EN4	This field is the 4th enable for the ESM. Type: Write-Clear	WO	0

:SOC_AON:ESM1EN5

Address offset	0x0000 205C
Description	ESM1 Enable Number 5.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	EN5	This field is the 5th enable for the ESM. Type: Write-Clear	WO	0

:SOC_AON:ESM2EN1

Address offset	0x0000 2060
Description	ESM2 Enable Number 1.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	EN1	This field is the 1st enable for the ESM. Type: Write-Clear	WO	0

:SOC_AON:ESM2EN2

Address offset	0x0000 2064
Description	ESM2 Enable Number 2.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	EN2	This field is the 2nd enable for the ESM. Type: Write-Clear	WO	0

:SOC_AON:ESM2EN3

Address offset	0x0000 2068
Description	ESM2 Enable Number 3.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	EN3	This field is the 3rd enable for the ESM. Type: Write-Clear	WO	0

:SOC_AON:ESM2EN4

Address offset	0x0000 206C
Description	ESM2 Enable Number 4.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	EN4	This field is the 4th enable for the ESM. Type: Write-Clear	WO	0

:SOC_AON:ESM2EN5

Address offset	0x0000 2070
Description	ESM2 Enable Number 5.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	EN5	This field is the 5th enable for the ESM. Type: Write-Clear	WO	0

:SOC_AON:ESM2CFG

Address offset	0x0000 2074
Description	ESM2 Configuration- Customer Debug M33 Secure Enable Sequence Monitor. Enable timeout mechanism and timeout counter value.
Type	RW

Bits	Field Name	Description	Type	Reset
31:12	Reserved		RO	0x0 0000
11:8	TIMEOUTCNT	This field sets the timeout value. time resolution equals to 16us. while: value 0 representing 16us value 1 - 216us value 2 - 316us and so on. value 15 is not supported.	RW	0x1
7:1	Reserved		RO	0x00
0	ENTIMEOUT	This field enables timeout mechanism for ESM.	RW	1

:SOC_AON:DBGSSDSSM

Address offset	0x0000 20A4
Description	This register allow indication of debug port is present: ble, wlphy, wsoccpu, app cpu
Type	RW

Bits	Field Name	Description	Type	Reset
31:20	Reserved		RO	0x000
19	APPSCPU	HOST M33 MCU , debug port present (enable), locked on boot done applicable only for MDB	RW	0
18	BLE	BLE MCU , debug port present (enable), locked on boot done	RW	1
17	WLPHYCPU	WLPHY MCU , debug port present (enable), locked on boot done	RW	1
16	WSOCCPU	WSOC MCU , debug port present (enable), locked on boot done	RW	1
15:13	Reserved		RO	0x0
12:9	SWJINSTID	Single wire Jtag, these field set the instance ID for multi probe SWJDP configuration, going to debugss and locked on boot done	RW	0x0
8:1	Reserved		RO	0x00
0	MBOXRSTEN	If this signal is set, debug request command sent to DSSM TX DAT register shall assert "Mailbox_reset_req" signal above, otherwise the debug request command is ignored.	RW	1

:SOC_AON:ESM3CFG

Address offset	0x0000 20B4
Description	ESM3 Configuration- TI Debug Enable Sequence Monitor. Enable timeout mechanism and timeout counter value.
Type	RW

Bits	Field Name	Description	Type	Reset
31:17	Reserved		RO	0x0000
16	BACK2IDLE	1 - Allow ESM3 to be restarted (IDLE) when entering Elevated mode 0 - Keep ESM3 state (not restarted) when entering Elevated mode	RW	0
15:12	Reserved		RO	0x0
11:8	TIMEOUTCNT	This field sets the timeout value. time resolution equals to 16us. while: value 0 representing 16us value 1 - 216us value 2 - 316us and so on. value 15 is not supported.	RW	0x1
7:1	Reserved		RO	0x00
0	ENTIMEOUT	This field enables timeout mechanism for ESM.	RW	1

:SOC_AON:ESM3EN1

Address offset	0x0000 20B8
Description	ESM3 Enable Number 1.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	EN1	This field is the 1st enable for the ESM. Type: Write-Clear	WO	0

:SOC_AON:ESM3EN2

Address offset	0x0000 20BC
Description	ESM3 Enable Number 2.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	EN2	This field is the 2nd enable for the ESM. Type: Write-Clear	WO	0

:SOC_AON:ESM3EN3

Address offset	0x0000 20C0
Description	ESM3 Enable Number 3.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	EN3	This field is the 3rd enable for the ESM. Type: Write-Clear	WO	0

:SOC_AON:ESM3EN4

Address offset	0x0000 20C4
Description	ESM3 Enable Number 4.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	EN4	This field is the 4th enable for the ESM. Type: Write-Clear	WO	0

:SOC_AON:ESM3EN5

Address offset	0x0000 20C8
Description	ESM3 Enable Number 5.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	EN5	This field is the 5th enable for the ESM. Type: Write-Clear	WO	0

:SOC_AON:SOC_AON_FUSE_LINE0

Address offset	0x0000 20CC
Description	Fuse Line 0. Actual fuse line is 32
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	DEVLCSPAT	Device Life Cycle Operational (Strong Pattern) 24'hca5b3a Device Life Cycle AT TEST Privilege (Strong Pattern) Allows unhide the assets in device AT TEST for TI debug/development. 24'h484a28 (This number allows moving to operational assuming no HW CRC is disabled)	RO	0x00 0000
7:4	DEVLCSW	Device Life Cycle (SW Managed)	RO	0x0
3:0	DEVLCHW	Device Life Cycle (HW Managed) - Programmed on Package 0 - 1st Birthday 1 - ATTEST (For Development) 3 - Operational (For Customer) 7 - Reserved	RO	0x0

:SOC_AON:SOC_AON_FUSE_LINE1

Address offset	0x0000 20D0
Description	Fuse Line 1. Actual fuse line is 33.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	UNQ31TO0	Unique Device Identification [31:0]			RO	0x0000 0000

:SOC_AON:SOC_AON_FUSE_LINE2

Address offset	0x0000 20D4
Description	Fuse Line 2. Actual fuse line is 34.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	UNQ63TO32	Unique Device Identification [63:32]			RO	0x0000 0000

:SOC_AON:SECGV_SOC_AON_FUSE_LINE3

Address offset	0x0000 20D8
Description	Fuse Line 3. Actual fuse line is 35.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	UNQS31TO0	Unique Device Secret [31:0]			RO	0x0000 0000

:SOC_AON:SECGV_SOC_AON_FUSE_LINE4

Address offset	0x0000 20DC
Description	Fuse Line 4. Actual fuse line is 36.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	UNQS63TO32	Unique Device Secret [63:32]			RO	0x0000 0000

:SOC_AON:SECGV_SOC_AON_FUSE_LINE5

Address offset	0x0000 20E0
Description	Fuse Line 5. Actual fuse line is 37.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	UNQS95TO64	Unique Device Secret [95:64]			RO	0x0000 0000

:SOC_AON:SECGV_SOC_AON_FUSE_LINE6

Address offset	0x0000 20E4
Description	Fuse Line 6. Actual fuse line is 38.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	UNQS127TO96	Unique Device Secret [127:96]			RO	0x0000 0000

:SOC_AON:SOC_AON_FUSE_LINE7

Address offset	0x0000 20E8
Description	Fuse Line 7. Actual fuse line is 39.
Type	RW

Bits	Field Name	Description	Type	Reset
31:29	FUSE_DATA_39_PRIVDBGREQ	Enforce TI privilege Debug Request (Relevant in AT TEST privilege only used by SW) 0 - Disable other (1-7) - Enable (When SW check these bits: if equal to '0' bypass otherwise check.)	RO	0x0
28:27	FUSE_DATA_39_LDAUTHEN	RAM Bootloader authentication enable: 00 - Disable Other- Enable	RO	0x0
26	FUSE_DATA_39_RESBOOTEXE	Resume boot in non-normal boot flows where the boot cannot progress (e.g. when assets are hidden). For example, in forced supply in operational or deployed life cycles, 1st bday/at test (normal) life cycles, etc. 0 - Halt boot execution as early as possible 1 - Resume/Continue boot execution This bit is ignored when the device can run the boot flow normally (e.g. deployed life cycle with default SOP).	RO	0
25	FUSE_DATA_39_DISVERB	Disable Verbose Mode 0 - Verbose Mode (Enable) - Full Logger 1 - Normal Mode (Disable)	RO	0
24	FUSE_DATA_39_RANDDLYEN	Random Delay Enable: 0 - Disable 1 - Enable	RO	0
23	FUSE_DATA_39_ENBOOTWDT	Enable watchdog timer for protecting boot: (This enable M33 watchdog second threshold to reset device when asserted). 0 - Disable Boot Watchdog 1 - Enable Boot Watchdog	RO	0
22:20	FUSE_DATA_39_MEMSTCK	Enable watchdog timer for protecting boot: (This enable M33 watchdog second threshold to reset device when asserted). 0 - Disable Boot Watchdog 1 - Enable Boot Watchdog	RO	0x0
19	FUSE_DATA_39_DISCANFD	Disable CAN FD - to eliminate the need to pay royalties 0 - Enable 1 - Disable (In probe we can program '0' (which practically means not programming) to achieve continuous programming it of all shifted rows) HCANEN (Enable/Disable the CAN IP) - Determined according to paper spin HCANRAMEN(Enable disable access to CAN memory) - Determined according to paper spin. HCANFDEN - Disable/Enable CAN. Determined according to eFuse bit (this bit)	RO	0
18:17	FUSE_DATA_39_TEMP	Supported Temperature 00 - 85degC 01 - 105degC 10 - 125degC 11 - Reserved	RO	0x0
16	FUSE_DATA_39_DISM33	Disable M33 0 - Enable 1 - Disable (In probe we can program '0' (which practically means not programming) to achieve continuous programming it of all shifted rows)	RO	0
15	FUSE_DATA_39_DISBLE_M0PLUS	Disable BLE M0+ (RFC_CPE_CLKEN ) 0 - Enable 1 - Disable (In probe we can program '0' (which practically means not programming) to achieve continuous programming it of all shifted rows)	RO	0
14	FUSE_DATA_39_DISBLE	Disable BLE (RFC_MDM_CLKEN) 0 - Enable 1 - Disable (In probe we can program '0' (which practically means not programming) to achieve continuous programming it of all shifted rows)	RO	0
13	FUSE_DATA_39_DIS6GHZ	Disable 6GHz 0 - Enable 1 - Disable (In probe we can program '0' (which practically means not programming) to achieve continuous programming it of all shifted rows)	RO	0
12	FUSE_DATA_39_DIS5GHZ	Disable 5GHz 0 - Enable 1 - Disable (In probe we can program '0' (which practically means not programming) to achieve continuous programming it of all shifted rows)	RO	0
11:10	Reserved		RO	0x0
9:6	FUSE_DATA_39_BOOTLVL	Determine which part of the boot ROM bypass options for risk mitigation Level0 - Do not bypass anything Level1- Ignore Error Level2 - TI ROM bypass Level3 - Minimize access to HW. Do min mandatory. 0b0110 - Level3 0b1010 - Level 2 0b0101 - Level 1 All the rest - Level 0	RO	0x0
5:3	SWCRCEN	SW CRC check Enable/Disable: 0 - Disable Other (1-7) - Enable (When SW check these bits: if equal to '0' do not check otherwise check.)	RO	0x0
2:0	HWCRCEN	HW CRC check Enable/Disable: 0 - Disable other (1-7) - Enable (When HW check these bits: if equal to '0' do not check otherwise check.)	RO	0x0

:SOC_AON:SOC_AON_FUSE_LINE8

Address offset	0x0000 20EC
Description	Fuse Line 8. Actual fuse line is 40.
Type	RO

Bits	Field Name	Description			Type	Reset
31:0	HWCRCVAL	HW CRC Check for all shifted rows. XORs operation with 0x04C11DB7 CRC32 polynomial engine. Init value = 0			RO	0x0000 0000

:SOC_AON:FUSECTL

Address offset	0x0000 2100
Description	Fuse Access Control. disconnect fuse from OCP access. locked with fuse_ocp_disable_lock.
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1	OCPEN	OTP FROM , when jtag is 1 the i/f is jtag regardless of ocp_en to enable OCP need to write this bit to 1 and jtag to 0 '1' by default. optional - write once to '0'.	RW	1
0	OCPDIS	Disconnect FUSE FARM and OTP OCP access, should be configured once as locked on boot done	RW	0

:SOC_AON:COREMEMCTL

Address offset	0x0000 2104
Description	CORE Memory Access Control CORE CPU: Allow M3 Fetch From non-owned memory Allow WiFi M0+ Fetch From non-owned memory Allow BLE M0+ Fetch From non-owned memory
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	BLEFETCH	Allow BLE M0+ Fetch From non-owned memory	RW	0
1	WSOCMCUFET	Allow M3 Fetch From non-owned memory	RW	0
0	WLPHYFETCH	Allow WiFi M0+ Fetch From non-owned memory	RW	0

:SOC_AON:COREGPCTL

Address offset	0x0000 2108
Description	Access Control - Core Global Port Enable
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	ALLOW	Allow CORE global port. when enabled allow access to core (based on firewall configuration), must stay enabled to allow host access to Nub (sdio) and locked on soc_boot_done	RW	1

:SOC_AON:MEMSSGPCTL

Address offset	0x0000 210C
Description	MEMSS Global Port Access Control. Allow access to entire memss through memss global port. Default: Access is disabled
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	ALLOW	Access is allowed to both M33 & M3 during privilege boot and changed to M3 only (fixed firewall) after boot (controlled by soc_boot_done)	RW	0

:SOC_AON:BLEFUSECTL

Address offset	0x0000 2110
Description	BLE Fuse Access Control. Disable BLE modem and CPE clock - based on indication bits on fuse
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1	MDMOFF	Disable the BLE MDM clock , should be configured based on fuse pare spin	RW	0
0	CPEOFF	This control disable the clk to the CPE clk gate. should be disabled in WIFI only paper spin (based on fuse)	RW	0

:SOC_AON:SPARE4

Address offset	0x0000 2118
Description	not in use. can be use as spare
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	BIT	spare bit	RW	0

:SOC_AON:ESM4CFG

Address offset	0x0000 211C
Description	ESM4 Configuration- TI DFT Enable Sequence Monitor. Enable timeout mechanism and timeout counter value.
Type	RW

Bits	Field Name	Description	Type	Reset
31:12	Reserved		RO	0x0 0000
11:8	TIMEOUTCNT	This field sets the timeout value. time resolution equals to 16us. while: value 0 representing 16us value 1 - 216us value 2 - 316us and so on. value 15 is not supported.	RW	0x1
7:1	Reserved		RO	0x00
0	ENTIMEOUT	This field enables timeout mechanism for ESM.	RW	1

:SOC_AON:ESM4EN1

Address offset	0x0000 2120
Description	ESM4 Enable Number 1.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	EN1	This field is the 1st enable for the ESM. Type: Write-Clear	WO	0

:SOC_AON:ESM4EN2

Address offset	0x0000 2124
Description	ESM4 Enable Number 2.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	EN2	This field is the 2nd enable for the ESM. Type: Write-Clear	WO	0

:SOC_AON:ESM4EN3

Address offset	0x0000 2128
Description	ESM4 Enable Number 3.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	EN4	This field is the 3rd enable for the ESM. Type: Write-Clear	WO	0

:SOC_AON:ESM4EN4

Address offset	0x0000 212C
Description	ESM4 Enable Number 4.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	EN4	This field is the 4th enable for the ESM. Type: Write-Clear	WO	0

:SOC_AON:ESM4EN5

Address offset	0x0000 2130
Description	ESM4 Enable Number 5.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	EN5	This field is the 5th enable for the ESM. Type: Write-Clear	WO	0

:SOC_AON:MEMPROT

Address offset	0x0000 2140
Description	This register is locking the CORE related security bits , should be written in boot and on elevated mode exit: [COREMEMCTL], [CRAMPROT1.FETCHTH], [DRAMPROT1.FETCHTH], [MEMPROT.MEMLOCK], [ROMJUMPCTL.DIS], [DRAMCTL.ERASEASST], [VTORCFG.INIT], [CPEPROT1.RFCOVR], [CPEPROT1.RFCMODE], [CPEPROT1.FETCHTH], [PHYPROT1.FETCHTH]
Type	RW

Bits	Field Name	Description	Type	Reset
31:17	Reserved	Reserved	RO	0x0000
16	MEMLOCK	Locking the configurations on mem prot	WOnce	0
15:0	Reserved	Reserved	RO	0x0000

:SOC_AON:VTORCFG

Address offset	0x0000 2144
Description	WSOC MCU VTOR CONFIGURATION. this is the jump address during boot (default is 0 - Rom) and after boot done - as POR this should be configured to CRAM start during boot of ROM. in boot done command the MCU will jump to this address
Type	RW

Bits	Field Name	Description	Type	Reset
31:7	INIT	VTOR Init register	RW	0x000 0000
6:0	Reserved	Reserved	RO	0x00

:SOC_AON:ROMJUMPCTL

Address offset	0x0000 2148
Description	MCU ROM Jump Disable. Prevents the use of the VTOR function , by default it is off.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	DIS	0 - CTX icode bus jumps from 0x0/0x04 to vtor/vtor+4. 1 - Do not jump.	RW	0

:SOC_AON:CRAMPROT1

Address offset	0x0000 214C
Description	Execution RAM (CRAM) - Threshold register
Type	RW

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:7	WRTH	Below this CRAM Threshold register - Fetch/read only after 'mem_cram_write_disable_pulse'. Write is allowed above this threshold regardless to S/W setting the [CRAMPROT0.WRDIS]. Resolution is 1KB: (1- 1KB, 2 - 2KB, ..., 511 - 511KB). Effectively we have 76+398KB of Code-RAM	RW	0x000
6:0	Reserved		RO	0x00

:SOC_AON:CRAMPROT0

Address offset	0x0000 2150
Description	Execution RAM (CRAM) - Protect from write
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved	Reserved	RO	0x0000 0000
0	WRDIS	Write Once MMR protection - Do not allow writing to CRAM (below a threshold) after this MMR is set. Before this MMR is set - write is allowed , fetch is not allowed. (for all the memory) S/W pulse (WRCL) that sets an H/W F.F - cannot be cleared by S/W.	WO	0

:SOC_AON:DRAMPROT1

Address offset	0x0000 2154
Description	Data RAM (DRAM) - Threshold register
Type	RW

Bits	Field Name	Description	Type	Reset
31:15	Reserved		RO	0x0 0000
14:7	FETCHTH	Below this DRAM Threshold register - read/write only (never-execute-region) after 'mem_dram_fetch_disable_pulse'. Fetch is allowed above this threshold regardless to S/W setting the [DRAMPROT0.FETCHDIS]. Resolution is 1KB: (1- 1KB, 2 - 2KB, ..., 255 - 255KB). Effectively we have 144KB of Data-RAM. [Cortex fetch from 61xx_xxxx (executable region) instead of 45xx_xxxx and the address is automatically (MCUSS H/W) remapped to 45xx_xxxx]	RW	0x00
6:0	Reserved		RO	0x00

:SOC_AON:DRAMPROT0

Address offset	0x0000 2158
Description	Data RAM (DRAM) - Protect from fetch
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved	Reserved	RO	0x0000 0080
0	FETCHDIS	Write Once MMR protection - Do not allow fetching from DRAM (below a threshold) after this MMR is set. Before this MMR is set - write is allowed , fetch is not allowed. (for all the memory) S/W pulse (WRCL) that sets an H/W F.F - cannot be cleared by S/W.	WO	0

:SOC_AON:PRAMPROT0

Address offset	0x0000 215C
Description	Packet RAM (PRAM) - Protect from fetch
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved	Reserved	RO	0x0000 0080
0	FETCHDIS	Write Once MMR protection - Do not allow fetching from PRAM after this MMR is set. Before this MMR is set - write is allowed , fetch is not allowed. S/W pulse (WRCL) that sets an H/W F.F - cannot be cleared by S/W.	WO	0

:SOC_AON:STRONGPAT

Address offset	0x0000 2160
Description	Security Strong Pattern. the 24 bit pattern that is burn on the fuse to qualify the fuse data against possible attack
Type	RW

Bits	Field Name	Description	Type	Reset
31:24	Reserved	Reserved	RO	0x00
23:0	PAT	24 bit pattern from fuse	RO	0x00 0000

:SOC_AON:UDS0

Address offset	0x0000 2164
Description	Unique Device Secret. 31-0
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	31TO0	bits 31-0			RO	0x0000 0000

:SOC_AON:UDS1

Address offset	0x0000 2168
Description	Unique Device Secret. 63-32
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	63TO32	Bits 63-32			RO	0x0000 0000

:SOC_AON:UDS2

Address offset	0x0000 216C
Description	Unique Device Secret. 95-64
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	95TO64	Bits 95-64			RO	0x0000 0000

:SOC_AON:UDS3

Address offset	0x0000 2170
Description	Unique Device Secret. 127-96
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	127TO96	Bits 127-96			RO	0x0000 0000

:SOC_AON:DBGBUS

Address offset	0x0000 2174
Description	SOC_AON Debug Bus. This register sets the debug over sleep and IOMUX debug bus selection
Type	RW

Bits	Field Name	Description	Type	Reset
31:19	Reserved		RO	0x0000
18:17	SECSEL	Security Debug Selector. selects soc aon debug bus	RW	0x0
16:15	MUXPSEL	Debug Mux Port Selector. Chooses debug mux port '00' - prcm/elp '01' - soc aod '10' - ocla	RW	0x0
14:12	AODPSEL	SOC AOD Port Selector. Chooses soc aod port '000' - host_aon_tp1 '001' - host_aon_tp2 '010' - io mux tp1 '011' - io mux tp2 '100' - debug aon tp1 '101' - debug aon tp2 '110' - soc aon tp1 '111' - rtc_tp1	RW	0x0
11	AODSEL	SOC AOD Upper/Lower Selector. selects upper or lower 16 bits out of the soc aod bus of 32 '1' - 16 MSBs '0' - 16 LSBs	RW	0
10:9	ELPUPPSEL	PRCM ELP Upper Port Selector. Chooses upper byte port '00' - prcm tp1 '01' - prcm tp2 '10' - elp tp1 '11' - elp tp2	RW	0x0
8:7	ELPLOPSEL	PRCM ELP Lower Port Selector. Chooses lower byte port '00' - prcm tp1 '01' - prcm tp2 '10' - elp tp1 '11' - elp tp2	RW	0x0
6:5	ELPLOSEL	PRCM ELP Lower Byte Selector. Chooses lower byte out of prcm elp 32 bit '00' - [7:0] '01' - [15:8] '10' - [23:16] '11' - [31:24]	RW	0x0
4:3	ELPUPSEL	PRCM ELP Upper Byte Selector. Chooses upper byte out of prcm elp 32 bit '00' - [7:0] '01' - [15:8] '10' - [23:16] '11' - [31:24]	RW	0x1
2	OCLASEL	OCLA bus upper/lower selector. selects upper or lower 16 bits out of the ocla bus of 32 '1' - 16 MSBs '0' - 16 LSBs	RW	0
1:0	IOCLKSEL	selects the clock source for iomux debug clk 0 :SCLK 1: SOC CLK (40) 2: CORE M3 CLK (80)	RW	0x0

:SOC_AON:DEBUGSS

Address offset	0x0000 217C
Description	DEBUGSS JTAG User Code. This 32 bit register can be read through JTAG , and reflected on CFG-AP
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	JTAGUSER	This 32 bit register can be read through JTAG , and reflected on CFG-AP			RW	0x0000 0000

:SOC_AON:CPEPROT1

Address offset	0x0000 2180
Description	Execution RAM (CRAM) - Threshold register
Type	RW

Bits	Field Name	Description	Type	Reset
31:24	Reserved		RO	0x00
23:20	HIACCESS	Define the CPE (BLE CM0+) most high address space access allowed (should be configured according to MEM-SS mode). Value granularity is 16K, So for the default allocation of 64k it set to 3. (value 0 is for the lower 16k, value 15 is for 256k)	RW	0x3
19	Reserved		RO	0
18:15	GENERAL	Bit 0 is force clk en for all BLE sub clocks . this is enabled on default for safety reasons on boot. this bit should be cleared by SW during boot and then internal IP clock manager takes control	RW	0x3
14:7	FETCHTH	Above this BLE CPE Threshold register - read/write only (never-execute-region) after 'mem_dram_fetch_disable_pulse'. Fetch is allowed below this threshold regardless to S/W setting the [CPEPROT0.FETCHDIS]. Resolution is 1KB: (1- 1KB, 2 - 2KB, ..., 255 - 255KB). MSBit not in use (MSBit is reserved bit).	RW	0x00
6:4	Reserved		RO	0x0
3:1	RFCMODE	RFC Confidential Mode.	RW	0x0
0	RFCOVR	RFC Confidential Over.	RW	1

:SOC_AON:CPEPROT0

Address offset	0x0000 2184
Description	CPE Data RAM (DRAM) - Protect from fetch
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved	Reserved	RO	0x0000 0080
0	FETCHDIS	Write Once MMR protection - Do not allow fetching from DRAM (above a threshold) after this MMR is set. S/W pulse (WRCL) that sets an H/W F.F - cannot be cleared by S/W.	WO	0

:SOC_AON:FUSESHIFT

Address offset	0x0000 2188
Description	Security Fuse Shift CRC Calc result on fuse chain
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	CRCCALC	Calc CRC result of fuse chain - this include the CRC result crunching a s well, so expected / correct result would be 0.			RO	0x0000 0000

:SOC_AON:SECROM

Address offset	0x0000 218C
Description	Security Hide Rom Assets. SW control to hide ROM assets, written once
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1	UNHIDE	ROM assets is Hidden in case ATTEST or Error or if SOP=FS. during either Operational or ATTEST Privilege: 1. ROM assets is Hidden by default 2. Unhide ROM assets by setting [UNHIDE] bitfield. 3. After unhide ROM it could be Hidden by setting [HIDEASSETS] bitfield. 4. ROM will be Hidden when privilege/elevated mode done without dependancy of [HIDEASSETS] field. Type: Write-Clear.	WO	0
0	HIDEASSETS	ROM assets is Hidden in case ATTEST or Error or if SOP=FS. during either Operational or ATTEST Privilege: 1. ROM assets is Hidden by default 2. Unhide ROM assets by setting [UNHIDE] bitfield. 3. After unhide ROM it could be Hidden by setting [HIDEASSETS] bitfield. 4. ROM will be Hidden when privilege/elevated mode done without dependancy of [HIDEASSETS] field. Type: Write-Clear.	WO	0

:SOC_AON:SECUDS

Address offset	0x0000 2190
Description	Security Hide UDS Assets. SW control to hide UDS assets, written once
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	HIDEASSETS	UDS is Hidden in case ATTEST or Error or.. during ATTEST-Privilege or Operational-and-not-in-force-supply-SOPs (except during soc privilege in which this MMR applies the hide) Type: Write-Clear.	WO	0

:SOC_AON:PHYPROT1

Address offset	0x0000 2198
Description	WLPHY RAM memory protection - Threshold register
Type	RW

Bits	Field Name	Description	Type	Reset
31:15	Reserved		RO	0x0 0000
14:7	FETCHTH	Above this WLPHY Threshold register - read/write only (never-execute-region) after 'mem_wlphy_fetch_disable_pulse'. Fetch is allowed below this threshold regardless to S/W setting the [PHYPROT0.FETCHDIS]. Resolution is 1KB: (1- 1KB, 2 - 2KB, ..., 255 - 255KB). MSBit not in use. (MSBit is reserved bit)	RW	0x00
6:0	Reserved		RO	0x00

:SOC_AON:PHYPROT0

Address offset	0x0000 219C
Description	WLPHY RAM - Protect from fetch
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved	Reserved	RO	0x0000 0080
0	FETCHDIS	Write Once MMR protection - Do not allow fetching from WLPHY RAM (above a threshold) after this MMR is set. S/W pulse (WRCL) that sets an H/W F.F - cannot be cleared by S/W.	WO	0

:SOC_AON:ESMDIS

Address offset	0x0000 21A0
Description	ESMs Graceful Disable. Setting this bit - moving all ESM's from IDLE state to disabled state and cannot be configured until the next AON reset. notice this can be set only in IDLE mode - prior to other ESM configurations (i,e if ESM state is VIOLATED or DONE it will remain there)
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved	Reserved	RO	0x0000 0080
0	DIS	Setting this bit - moving all ESM's from IDLE state to disabled state and cannot be configured until the next AON reset. notice this can be set only in IDLE mode - prior to other ESM configurations (i,e if ESM state is VIOLATED or DONE it will remain there)	WO	0

:SOC_AON:SPARE50

Address offset	0x0000 21A4
Description	Spare bits , locked on boot
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved	Reserved	RO	0x0000 0000
2	BF02	Spare2 locked on boot done	RW	0
1	BF01	Spare1 locked on boot done	RW	0
0	BF00	Spare0 locked on boot done	RW	0

:SOC_AON:TOPDBG

Address offset	0x0000 21A8
Description	Top Debug Selectors. This register selects debug ports from Top debug to OCLA. INTERNAL NOTE: [Confluence][https://confluence.itg.ti.com/display/WNG/Osprey+MDB+PG1.0+-+OCLA+integration+Spec] [LINUX- OSPREYMDB - MDBPG10C3V2 Branch][toplevel/wsoc/doc/wsoc.xls]
Type	RW

Bits	Field Name	Description	Type	Reset
31	TPSEL	TP1/TP2 Selector. This field is used for Peripheral TP that have two 32bits TP (mode #3) e.g. SDIO_PHY, SDIO_FN1 In this case TP include 64 bits but we can expose only 32bits So we need this MMR field to select either TP1 or TP2 In this case this 16LSB(15:0) bit are connected to TP1 and 16MSB(31:16) to TP2 0 - Select IP TP1 1 - Select IP TP2 Example: TP1 = mem_ocla_tp1_tp2_sel ? IP_TP2[15: 0] : IP_TP1[15: 0] ; TP2 = mem_ocla_tp1_tp2_sel ? IP_TP2[31:16] : IP_TP1[31:16] ;	RW	0
30:29	Reserved		RO	0x0
28:24	P1SEL	Port Set 1 - IP Selector. Selects the IP. INTERNAL NOTE- 2.2.4 SOC (TOP) [Confluence][https://confluence.itg.ti.com/display/WNG/Osprey+MDB+PG1.0+-+OCLA+integration+Spec]	RW	0x00
23:21	Reserved		RO	0x0
20:16	P2SEL	Port Set 2 - IP Selector. Selects the IP. INTERNAL NOTE- 2.2.4 SOC (TOP) [Confluence][https://confluence.itg.ti.com/display/WNG/Osprey+MDB+PG1.0+-+OCLA+integration+Spec]	RW	0x00
15:13	Reserved		RO	0x0
12:8	P1SUB	Port Set 1 - Submodule Selector. Selects the Submodule from the IP. INTERNAL NOTE- [LINUX- OSPREYMDB - MDBPG10C3V2 Branch][toplevel/wsoc/doc/wsoc.xls]	RW	0x00
7:5	Reserved		RO	0x0
4:0	P2SUB	Port Set 2 - Submodule Selector. Selects the Submodule from the IP. INTERNAL NOTE- [LINUX- OSPREYMDB - MDBPG10C3V2 Branch][toplevel/wsoc/doc/wsoc.xls]	RW	0x00

:SOC_AON:DB0M3CLR

Address offset	0x0000 2370
Description	Doorbell 0 M3 Clear Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	CLR	M3 to clear the IRQ after handled the massage from M33. type : Write-Clear	WO	0

:SOC_AON:DB0M3SET

Address offset	0x0000 2374
Description	Doorbell 0 M3 Set Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	IRQ	M3 to generate IRQ towards M33 after writing the message. type: Write-Clear	WO	0

:SOC_AON:DB0M3LOCK

Address offset	0x0000 2378
Description	Doorbell 0 M3 Lock Bit
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1:0	LOCKBIT	Lock Bit. S/w attempt to lock upon read. if lock obtained, value set to 1 by h/w. M33 always looses to M3 Reading value: 00: not taken 01: taken by M3 (should wr IRQ afterwards) 10: taken by M33 11: invalid. generating the IRQ towards M33 clears the lock. Writing '00' also release the lock. 2'b10 means lock obtained by receiver side Type: Write-Read-Clear.	RW	0x0

:SOC_AON:DB1M3CLR

Address offset	0x0000 237C
Description	Doorbell 1 M3 Clear Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	CLR	M3 to clear the IRQ after handled the massage from M33. type : Write-Clear	WO	0

:SOC_AON:DB1M3SET

Address offset	0x0000 2380
Description	Doorbell 1 M3 Set Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	SET	M3 to generate IRQ towards M33 after writing the message. type: Write-Clear	WO	0

:SOC_AON:DB1M3LOCK

Address offset	0x0000 2384
Description	Doorbell 1 M3 Lock Bit
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1:0	LOCKBIT	Lock Bit. S/w attempt to lock upon read. if lock obtained, value set to 1 by h/w. M33 always looses to M3 Reading value: 00: not taken 01: taken by M3 (should wr IRQ afterwards) 10: taken by M33 11: invalid. generating the IRQ towards M33 clears the lock. Writing '00' also release the lock. 2'b10 means lock obtained by receiver side Type: Write-Read-Clear.	RW	0x0

:SOC_AON:DB2M3CLR

Address offset	0x0000 2388
Description	Doorbell 2 M3 Clear Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	CLR	M3 to clear the IRQ after handled the massage from M33. type : Write-Clear	WO	0

:SOC_AON:DB2M3SET

Address offset	0x0000 238C
Description	Doorbell 2 M3 Set Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	SET	M3 to generate IRQ towards M33 after writing the message. type: Write-Clear	WO	0

:SOC_AON:DB2M3LOCK

Address offset	0x0000 2390
Description	Doorbell 2 M3 Lock Bit
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1:0	LOCKBIT	Lock Bit. S/w attempt to lock upon read. if lock obtained, value set to 1 by h/w. M33 always looses to M3 Reading value: 00: not taken 01: taken by M3 (should wr IRQ afterwards) 10: taken by M33 11: invalid. generating the IRQ towards M33 clears the lock. Writing '00' also release the lock. 2'b10 means lock obtained by receiver side Type: Write-Read-Clear.	RW	0x0

:SOC_AON:DB3M3CLR

Address offset	0x0000 2394
Description	Doorbell 3 M3 Clear Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	CLR	M3 to clear the IRQ after handled the massage from M33. type : Write-Clear	WO	0

:SOC_AON:DB3M3SET

Address offset	0x0000 2398
Description	Doorbell 3 M3 Set Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	SET	M3 to generate IRQ towards M33 after writing the message. type: Write-Clear	WO	0

:SOC_AON:DB3M3LOCK

Address offset	0x0000 239C
Description	Doorbell 3 M3 Lock Bit
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1:0	LOCKBIT	Lock Bit. S/w attempt to lock upon read. if lock obtained, value set to 1 by h/w. M33 always looses to M3 Reading value: 00: not taken 01: taken by M3 (should wr IRQ afterwards) 10: taken by M33 11: invalid. generating the IRQ towards M33 clears the lock. Writing '00' also release the lock. 2'b10 means lock obtained by receiver side Type: Write-Read-Clear.	RW	0x0

:SOC_AON:DB4M3CLR

Address offset	0x0000 23A0
Description	Doorbell 4 M3 Clear Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	CLR	M3 to clear the IRQ after handled the massage from M33. type : Write-Clear	WO	0

:SOC_AON:DB4M3SET

Address offset	0x0000 23A4
Description	Doorbell 4 M3 Set Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	SET	M3 to generate IRQ towards M33 after writing the message. type: Write-Clear	WO	0

:SOC_AON:DB4M3LOCK

Address offset	0x0000 23A8
Description	Doorbell 4 M3 Lock Bit
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1:0	LOCKBIT	Lock Bit. S/w attempt to lock upon read. if lock obtained, value set to 1 by h/w. M33 always looses to M3 Reading value: 00: not taken 01: taken by M3 (should wr IRQ afterwards) 10: taken by M33 11: invalid. generating the IRQ towards M33 clears the lock. Writing '00' also release the lock. 2'b10 means lock obtained by receiver side Type: Write-Read-Clear.	RW	0x0

:SOC_AON:DB5M3CLR

Address offset	0x0000 23AC
Description	Doorbell 5 M3 Clear Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	CLR	M3 to clear the IRQ after handled the massage from M33. type : Write-Clear	WO	0

:SOC_AON:DB5M3SET

Address offset	0x0000 23B0
Description	Doorbell 5 M3 Set Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	SET	M3 to generate IRQ towards M33 after writing the message. type: Write-Clear	WO	0

:SOC_AON:DB5M3LOCK

Address offset	0x0000 23B4
Description	Doorbell 5 M3 Lock Bit
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1:0	LOCKBIT	Lock Bit. S/w attempt to lock upon read. if lock obtained, value set to 1 by h/w. M33 always looses to M3 Reading value: 00: not taken 01: taken by M3 (should wr IRQ afterwards) 10: taken by M33 11: invalid. generating the IRQ towards M33 clears the lock. Writing '00' also release the lock. 2'b10 means lock obtained by receiver side Type: Write-Read-Clear.	RW	0x0

:SOC_AON:DB6M3CLR

Address offset	0x0000 23B8
Description	Doorbell 6 M3 Clear Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	CLR	M3 to clear the IRQ after handled the massage from M33. type : Write-Clear	WO	0

:SOC_AON:DB6M3SET

Address offset	0x0000 23BC
Description	Doorbell 6 M3 Set Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	SET	M3 to generate IRQ towards M33 after writing the message. type: Write-Clear	WO	0

:SOC_AON:DB6M3LOCK

Address offset	0x0000 23C0
Description	Doorbell 6 M3 Lock Bit
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1:0	LOCKBIT	Lock Bit. S/w attempt to lock upon read. if lock obtained, value set to 1 by h/w. M33 always looses to M3 Reading value: 00: not taken 01: taken by M3 (should wr IRQ afterwards) 10: taken by M33 11: invalid. generating the IRQ towards M33 clears the lock. Writing '00' also release the lock. 2'b10 means lock obtained by receiver side Type: Write-Read-Clear.	RW	0x0

:SOC_AON:DB7M3CLR

Address offset	0x0000 23C4
Description	Doorbell 7 M3 Clear Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	CLR	M3 to clear the IRQ after handled the massage from M33. type : Write-Clear	WO	0

:SOC_AON:DB7M3SET

Address offset	0x0000 23C8
Description	Doorbell 7 M3 Set Register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	SET	M3 to generate IRQ towards M33 after writing the message. type: Write-Clear	WO	0

:SOC_AON:DB7M3LOCK

Address offset	0x0000 23CC
Description	Doorbell 7 M3 Lock Bit
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1:0	LOCKBIT	Lock Bit. S/w attempt to lock upon read. if lock obtained, value set to 1 by h/w. M33 always looses to M3 Reading value: 00: not taken 01: taken by M3 (should wr IRQ afterwards) 10: taken by M33 11: invalid. generating the IRQ towards M33 clears the lock. Writing '00' also release the lock. 2'b10 means lock obtained by receiver side Type: Write-Read-Clear.	RW	0x0

:SOC_AON:M3GPIOEVT0

Address offset	0x0000 23D0
Description	M3 GPIO Event Status. 32 LSBs
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	STA31TO0	32 LSBs			RO	0x0000 0000

:SOC_AON:M3GPIOEVT1

Address offset	0x0000 23D4
Description	M3 GPIO Event Status. 13 MSBs
Type	RW

Bits	Field Name	Description	Type	Reset
31:13	Reserved		RO	0x0 0000
12:0	STA44TO32	13 MSBs (44-32)	RO	0x0000

:SOC_AON:FUSELOCK

Address offset	0x0000 23E8
Description	Fuse Lock. 1 lock. Write once. Issued to Fusefram Reg file and used to lock fusefarm OCP Disable indication (MMR), Locked immediately , cleared by core disable (or at soc aon reset or por reset)
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved	Reserved	RO	0x0000 0000
0	OCPDIS	Locking the FUSE FARM OCP Reg File	WOnce	0

:SOC_AON:ROMBOOT

Address offset	0x0000 23EC
Description	ROM Boot Done. 1 lock. Write once. Asserted by FW at the end of ROM boot. Used to implement the ROM Hide, Locked immediately , cleared by core disable (or at soc aon reset or por reset)
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved	Reserved	RO	0x0000 0000
0	DONE	Hiding the ROM at ROM Boot	WOnce	0

:SOC_AON:SOCBOOT

Address offset	0x0000 23FC
Description	SOC Boot Done. 1 lock. Write once. Asserted by FW at the end of TI secure boot, Used to lock the access to SOC security configurations , Locked immediately, cleared only at soc aon reset or por reset
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved	Reserved	RO	0x0000 0000
0	MEM_SOCBOOT_WROPT	locking the access to SOC security configurations	RW	0

:SOC_AON:ELEVATED

Address offset	0x0000 2400
Description	Elevated Mode Done. 1 lock. Write once. Asserted by FW at the end of elevated mode and indicates the end of elevated mode, Locked immediately , cleared by core disable (or at soc aon reset or por reset)
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved	Reserved	RO	0x0000 0000
0	MEM_ELEVATED_WROPT	nd of elevated mode (M3 Boot ROM + M3 Core Boot)	WOnce	0

:SOC_AON:M3TCM

Address offset	0x0000 2408
Description	M3 TCM Access. TCM access between M3 to M33
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	ACCESSDIS	M3 TCM Access Disable. Control the mux which select TCM access between M3 to M33 0. M3 1. M33	RW	0

:SOC_AON:HSMCFG

Address offset	0x0000 240C
Description	HSM Configurations. Fips Support, HSM_Configs, HSM_assets_hide, hsm_controller_host_mode (or firewall_mode).
Type	RW

Bits	Field Name	Description	Type	Reset
31:6	Reserved		RO	0x000 0000
5	HIDEASSETS	HSM Assets Hide. Change the control on HSM assets from OCP to HSM. Controlling this value is allowed during boot (before soc_boot_done) is enabled	RW	0
4	FIREWALL	HSM Firewall Mode. Select the controller id to hsm cpu_id transaction mode: 0-M3_MST_ID is translated to hsm cpu id 0 (controller host), this mode is used during boot (default=0) 1-M33_MST_ID (secure and non secure) are translated to hsm cpu id 0 (controller host), operational mode	RW	0
3	DMAGATEWAY	DMA Gateway Mode. Define the ids to be used on hsm dma access to OCP: 0-M33 using HSM, use M33S and M33NS Mater IDs 1-M33+M3 are using the HSM, use M33S and M3 Mater IDs	RW	0
2	WMSELFDIS	HSM Warmboot Post Disable. Disable self test & crc check on hsm reset exit, possible only is fips not supported: warmboot_post_disable: 0-enable self test on sleep exit, 1-disable self test on sleep exit (default=1)	RW	1
1	SELFDIS	Disable self test & crc check on hsm reset exit, possible only is fips not supported: post_disable: 0-enable self test on reset exit, 1-disable self test on reset exit (default=1)	RW	1
0	FIPS	Indication if hsm FIPS support: 1- HSM run in fips compliant mode 0- HSM doesn't run in fips compliant mode	RW	0

:SOC_AON:ESM5CFG

Address offset	0x0000 2410
Description	ESM4 Configuration- Customer HSM Debug Enable Sequence Monitor. Enable timeout mechanism and timeout counter value.
Type	RW

Bits	Field Name	Description	Type	Reset
31:12	Reserved		RO	0x0 0000
11:8	TIMEOUTCNT	This field sets the timeout value. time resolution equals to 16us. while: value 0 representing 16us value 1 - 216us value 2 - 316us and so on. value 15 is not supported.	RW	0x1
7:1	Reserved		RO	0x00
0	ENTIMEOUT	This field enables timeout mechanism for ESM.	RW	1

:SOC_AON:ESM5EN1

Address offset	0x0000 2414
Description	ESM5 Enable Number 1.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	EN1	This field is the 1st enable for the ESM. Type: Write-Clear	WO	0

:SOC_AON:ESM5EN2

Address offset	0x0000 2418
Description	ESM5 Enable Number 2.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	EN2	This field is the 2nd enable for the ESM. Type: Write-Clear	WO	0

:SOC_AON:ESM5EN3

Address offset	0x0000 241C
Description	ESM5 Enable Number 3.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	EN3	This field is the 3rd enable for the ESM. Type: Write-Clear	WO	0

:SOC_AON:ESM5EN4

Address offset	0x0000 2420
Description	ESM5 Enable Number 4.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	EN1	This field is the 4th enable for the ESM. Type: Write-Clear	WO	0

:SOC_AON:ESM5EN5

Address offset	0x0000 2424
Description	ESM5 Enable Number 5.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	EN5	This field is the 5th enable for the ESM. Type: Write-Clear	WO	0

:SOC_AON:ESM1VAL1ST

Address offset	0x0000 2428
Description	ESM1 1st Magic Value. This value is compared to hard coded value and unmask ESM only when value is matched. This additional compare allow ESM protection against fault injection
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	Reserved		RO	0x00 0000
7:0	MGCVAL	ESM 1st magic value	RW	0x00

:SOC_AON:ESM2VAL1ST

Address offset	0x0000 242C
Description	ESM2 1st Magic Value. This value is compared to hard coded value and unmask ESM only when value is matched. This additional compare allow ESM protection against fault injection
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	Reserved		RO	0x00 0000
7:0	MGCVAL	ESM 1st magic value	RW	0x00

:SOC_AON:ESM3VAL1ST

Address offset	0x0000 2430
Description	ESM3 1st Magic Value. This value is compared to hard coded value and unmask ESM only when value is matched. This additional compare allow ESM protection against fault injection
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	Reserved		RO	0x00 0000
7:0	MGCVAL	ESM 1st magic value	RW	0x00

:SOC_AON:ESM4VAL1ST

Address offset	0x0000 2434
Description	ESM4 1st Magic Value. This value is compared to hard coded value and unmask ESM only when value is matched. This additional compare allow ESM protection against fault injection
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	Reserved		RO	0x00 0000
7:0	MGCVAL	ESM 1st magic value	RW	0x00

:SOC_AON:ESM5VAL1ST

Address offset	0x0000 2438
Description	ESM5 1st Magic Value. This value is compared to hard coded value and unmask ESM only when value is matched. This additional compare allow ESM protection against fault injection
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	Reserved		RO	0x00 0000
7:0	MGCVAL	ESM 1st magic value	RW	0x00

:SOC_AON:DBM3IMASK

Address offset	0x0000 2450
Description	M3 Doorbell IMASK. Mask Event. '0' - CLR - Clear Interrupt Mask '1' - SET - Set Interrupt Mask
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	Reserved		RO	0x00 0000
7:0	IMASK	bit7 - doorbell 7 M3 IRQ bit6 - doorbell6 M3 IRQ bit5 - doorbell 5 M3 IRQ bit4 - doorbell 4 M3 IRQ bit3 - doorbell 3 M3 IRQ bit2 - doorbell 2 M3 IRQ bit1 - doorbell 1 M3 IRQ bit0 - doorbell 0 M3 IRQ	RW	0x00

:SOC_AON:DBM3ISET

Address offset	0x0000 2454
Description	M3 Doorbell ISET. Sets event in RIS Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - SET - Sets interrupt
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	Reserved		RO	0x00 0000
7:0	ISET	bit7 - doorbell 7 M3 IRQ bit6 - doorbell6 M3 IRQ bit5 - doorbell 5 M3 IRQ bit4 - doorbell 4 M3 IRQ bit3 - doorbell 3 M3 IRQ bit2 - doorbell 2 M3 IRQ bit1 - doorbell 1 M3 IRQ bit0 - doorbell 0 M3 IRQ	WO	0x00

:SOC_AON:DBM3ICLR

Address offset	0x0000 2458
Description	M3 Doorbell ICLR. Clears event in RIS Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - CLR - Clears the Event
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	Reserved		RO	0x00 0000
7:0	ICLR	bit7 - doorbell 7 M3 IRQ bit6 - doorbell6 M3 IRQ bit5 - doorbell 5 M3 IRQ bit4 - doorbell 4 M3 IRQ bit3 - doorbell 3 M3 IRQ bit2 - doorbell 2 M3 IRQ bit1 - doorbell 1 M3 IRQ bit0 - doorbell 0 M3 IRQ	WO	0x00

:SOC_AON:DBM3IMSET

Address offset	0x0000 245C
Description	M3 Doorbell IMSET. Sets Event Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - SET - Set interrupt mask
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	Reserved		RO	0x00 0000
7:0	IMSET	bit7 - doorbell 7 M3 IRQ bit6 - doorbell6 M3 IRQ bit5 - doorbell 5 M3 IRQ bit4 - doorbell 4 M3 IRQ bit3 - doorbell 3 M3 IRQ bit2 - doorbell 2 M3 IRQ bit1 - doorbell 1 M3 IRQ bit0 - doorbell 0 M3 IRQ	WO	0x00

:SOC_AON:DBM3IMCLR

Address offset	0x0000 2460
Description	M3 Doorbell IMCLR. Clears Event Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - CLR - Clear interrupt mask
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	Reserved		RO	0x00 0000
7:0	IMCLR	bit7 - doorbell 7 M3 IRQ bit6 - doorbell6 M3 IRQ bit5 - doorbell 5 M3 IRQ bit4 - doorbell 4 M3 IRQ bit3 - doorbell 3 M3 IRQ bit2 - doorbell 2 M3 IRQ bit1 - doorbell 1 M3 IRQ bit0 - doorbell 0 M3 IRQ	WO	0x00

:SOC_AON:DBM3RIS

Address offset	0x0000 2464
Description	M3 Doorbell RIS. Raw interrupt status for event. This bit is set to 1 when an event is received. when the corresponding bit in ICLR is set to 1, this bit will be cleared. Read 0 - CLR - Interrupt did not occur Read 1 - SET - Interrupt occurred
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	Reserved		RO	0x00 0000
7:0	RIS	bit7 - doorbell 7 M3 IRQ bit6 - doorbell6 M3 IRQ bit5 - doorbell 5 M3 IRQ bit4 - doorbell 4 M3 IRQ bit3 - doorbell 3 M3 IRQ bit2 - doorbell 2 M3 IRQ bit1 - doorbell 1 M3 IRQ bit0 - doorbell 0 M3 IRQ	RO	0x00

:SOC_AON:DBM3MIS

Address offset	0x0000 2468
Description	M3 Doorbell MIS. Mask interrupt status for event Read 0 - CLR - Interrupt did not occur Read 1 - SET - Interrupt occurred
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	Reserved		RO	0x00 0000
7:0	MIS	bit7 - doorbell 7 M3 IRQ bit6 - doorbell6 M3 IRQ bit5 - doorbell 5 M3 IRQ bit4 - doorbell 4 M3 IRQ bit3 - doorbell 3 M3 IRQ bit2 - doorbell 2 M3 IRQ bit1 - doorbell 1 M3 IRQ bit0 - doorbell 0 M3 IRQ	RO	0x00

:SOC_AON:HOSTCRTX

Address offset	0x0000 2680
Description	M33 cortex system reset request
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved	Reserved	RO	0x0000 0000
0	SYSRSTREQ	M33 cortex system reset request. Level register. 1 - request for reset 0- lower reset request User should set and clear this register (two writes)	RW	0

:SOC_AON:FWCFGSOC

Address offset	0x0000 2684
Description	SOC Firewall Bypass
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	BYPASS	SOC Firewall Bypass	RW	1

:SOC_AON:FWCOEX

Address offset	0x0000 2688
Description	COEX firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWPRCM

Address offset	0x0000 268C
Description	PRCM CORE + M3 Scratchpad firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWFUSE

Address offset	0x0000 2690
Description	FUSE FARM firewall access permission for 3 controller id : 0 - M33 Non Secured (valid only in privilege mode) 1 - M33 Secured (valid only in privilege mode) 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWGPADC

Address offset	0x0000 2694
Description	GPADC firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWDBGSS

Address offset	0x0000 2698
Description	DEBUGSS firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWAONM3

Address offset	0x0000 269C
Description	SOC_AON_M3 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWOCLA

Address offset	0x0000 26A0
Description	OCLA firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWCORE

Address offset	0x0000 26A4
Description	WSOC_IC firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWAAONM3

Address offset	0x0000 26A8
Description	SOC_AAON_M3 firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWXIPCFG

Address offset	0x0000 26AC
Description	XIP_CFG firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWOTFLCK

Address offset	0x0000 26B0
Description	OTFE_BOOT_LOCK firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWOTFNLCK

Address offset	0x0000 26B4
Description	OTFDE_NON_LOCK firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:FWCOREAON

Address offset	0x0000 2808
Description	CORE_AON firewall access permission for 3 controller id : 0 - M33 Non Secured 1 - M33 Secured 2 - Core (Non Secure)
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	CORENS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	M33S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	M33NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:SECGA_FIREWALL_CONFIG_SPARE0_1

Address offset	0x0000 287C
Description	Spare firewall access register. locked by SOC BOOT DONE (secgk) 3 access bits - {M33NS , M33S , M3} .
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	MEM_SPARE0_1_ACCESS_REG_CORE_NS	Controller Core Non Secured: '0' - access not allowed '1' - access allowed	RW	0
1	MEM_SPARE0_1_ACCESS_REG_M33_S	Controller M33 Secured: '0' - access not allowed '1' - access allowed	RW	0
0	MEM_SPARE0_1_ACCESS_REG_M33_NS	Controller M33 None Secured: '0' - access not allowed '1' - access allowed	RW	0

:SOC_AON:SOCSTA

Address offset	0x0000 2898
Description	Boot Status. Report boot status which reflected on Config AP on DebugSS and can be read by JTAG (tools), these configuration will be used by both privilege and elevated boot code The Boot status reveal is controlled by FW - status will be updated using authenticated request.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	BOOTSTA	Boot Status.			RW	0x0000 0000

:SOC_AON:LCCFG

Address offset	0x0000 289C
Description	LifeCycle Config. Report device parameters to config - AP.
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	DEVPARAMS	Bits 7:0 - Fixed lifecycle taken from HW (SW_LIFECYCLE, HW_LIFECYCLE) Bits 31:8 - device parameters (fuse/SW)	RW	0x00 0000
7:0	Reserved	Reserved	RO	0x00

:SOC_AON:ESM1STA

Address offset	0x0000 28A0
Description	status register , for each of the ESM (enable sequence monitor) what is the current state of esm.
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:0	ESM1STA	5 states: 0000 - READY 0001 - ENABLED (not guarenteed that magic values match) 0010 - PENDING TO NEXT WRITE 0100 - GRACFULLY LOCKED 1000 - FAULT	RO	0x0

:SOC_AON:ESM2STA

Address offset	0x0000 28A4
Description	status register , for each of the ESM (enable sequence monitor) what is the current state of esm.
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:0	ESM2STA	5 states: 0000 - READY 0001 - ENABLED (not guarenteed that magic values match) 0010 - PENDING TO NEXT WRITE 0100 - GRACFULLY LOCKED 1000 - FAULT	RO	0x0

:SOC_AON:ESM1STA1ST

Address offset	0x0000 28A8
Description	ESM1 1st magic value match indication.
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1	MGCVFLT	ESM 1st magic val fault ( note: indicates fault before a write to the magic val register)	RO	0
0	MGCVDONE	ESM 1st magic val match	RO	0

:SOC_AON:ESM2STA1ST

Address offset	0x0000 28AC
Description	ESM2 1st magic value match indication.
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1	MGCVFLT	ESM 1st magic val fault ( note: indicates fault before a write to the magic val register)	RO	0
0	MGCVDONE	ESM 1st magic val match	RO	0

:SOC_AON:ESM3STA1ST

Address offset	0x0000 28B0
Description	ESM3 1st magic value match indication.
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1	MGCVFLT	ESM 1st magic val fault ( note: indicates fault before a write to the magic val register)	RO	0
0	MGCVDONE	ESM 1st magic val match	RO	0

:SOC_AON:ESM4STA1ST

Address offset	0x0000 28B4
Description	ESM4 1st magic value match indication.
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1	MGCVFAULT	ESM 1st magic val fault ( note: indicates fault before a write to the magic val register)	RO	0
0	MGCVDONE	ESM 1st magic val match	RO	0

:SOC_AON:ESM5STA1ST

Address offset	0x0000 28B8
Description	ESM5 1st magic value match indication.
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1	MGCVFLT	ESM 1st magic val fault ( note: indicates fault before a write to the magic val register)	RO	0
0	MGCVDONE	ESM 1st magic val match	RO	0

:SOC_AON:SECGSERR

Address offset	0x0000 2908
Description	Enable Security Group SERROR. Enable SERROR when trying to access locked register in SOC AON , HOSTXIP and WSOCCOMMONS regfiles
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	MEM_SECGSERR	Enable secgroup serror.	RW	0

:SOC_AON:DRAMCTL

Address offset	0x0000 290C
Description	Erase Assets DRAM.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved	Reserved	RO	0x0000 0080
0	ERASEASST	Enable the automatic erase of the assets area of DRAM (8K) upon core reset exit. This action erase 8k in 25.6us	RW	0

:SOC_AON:CONNSTPCTL

Address offset	0x0000 2910
Description	Conn Stop Control By M33. '1' - Switch control of con_stop from HW (default con start) to M33 (default con stop)
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved	Reserved	RO	0x0000 0080
0	MEM_CONNSTPCTL_WROPT	'1' - Switch control of con_stop from HW (default con start) to M33 (default con stop)	WOnce	0

:SOC_AON:ESMSTATI

Address offset	0x0000 2914
Description	TI ESMs STATUS (3,4,5) status register , for each of the ESM (enable sequence monitor) what is the status (Done, violated, or None). Final ESM status for the entire ESM - ESM machine + magic value comparators
Type	RW

Bits	Field Name	Description	Type	Reset
31:18	Reserved		RO	0x0000
17	ESM5VIO	ESM 5 Violated.	RO	0
16	ESM5DONE	ESM 5Done.	RO	0
15:10	Reserved		RO	0x00
9	ESM4VIO	ESM 4 Violated.	RO	0
8	ESM4DONE	ESM 4 Done.	RO	0
7:2	Reserved		RO	0x00
1	ESM3VIO	ESM 3 Violated.	RO	0
0	ESM3DONE	ESM 3 Done.	RO	0

:SOC_AON:M3GPIOMIS0

Address offset	0x0000 2918
Description	M3 GPIO Functional MIS. 32 LSBs
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	31TO0	M3 GPIO Functional MIS. 32 LSBs			RO	0x0000 0000

:SOC_AON:M3GPIOMIS1

Address offset	0x0000 291C
Description	M3 GPIO Functional MIS. 13 MSBs (44-32)
Type	RW

Bits	Field Name	Description	Type	Reset
31:13	Reserved		RO	0x0 0000
12:0	44TO32	M3 GPIO Functional MIS. 13 MSBs (44-32)	RO	0x0000

:SOC_AON:M3GPIOFNC0

Address offset	0x0000 2920
Description	M3 GPIO Functional Mask
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	MASK31TO0	M3 GPIO Functional Mask. 32 LSBs 0. Mask 1. Un-Mask			RW	0x0000 0000

:SOC_AON:M3GPIOFNC1

Address offset	0x0000 2924
Description	M3 GPIO Functional Mask
Type	RW

Bits	Field Name	Description	Type	Reset
31:13	Reserved		RO	0x0 0000
12:0	MASK44TO32	M3 GPIO Functional Mask. 13 MSBs (44-32) 0. Mask 1. Un-Mask	RW	0x0000

:SOC_AON:DBGBUS_OUT_SEL

Address offset	0x0000 2928
Description	Debug Bus Out Select. This register sets the debug over sleep and IOMUX debug bus selection
Type	RW

Bits	Field Name	Description	Type	Reset
31:12	Reserved		RO	0x0 0000
11:9	AODTP2SEL	AOD to OCLA TP2 Select. Chooses debug mux port to ocla '000' - prcm tp2 '001' - elp tp2 '010' - rtc tp2 '011' - iomux tp2 '100' - debug aon tp2 '101' - soc aon tp1 '110' - host aon tp2	RW	0x0
8:6	AODTP1SEL	AOD to OCLA TP1 select. Chooses debug mux port to ocla '000' - prcm tp1 '001' - elp tp1 '010' - rtc tp1 '011' - iomux tp1 '100' - debug aon tp1 '101' - soc aon tp1 '110' - host aon tp1	RW	0x0
5:3	MUXPSEL_MSB	Debug mux port select MSB: Chooses debug mux port to iomux '000' - prcm/elp debug mux [7:0] '001' - prcm/elp debug mux [15:8] '010' - soc aod debug mux [7:0] '011' - soc aod debug mux [15:8] '100' - ocla debug mux [7:0] '101' - ocla debug mux [15:8]	RW	0x1
2:0	MUXPSEL_LSB	Debug mux port select LSB: Chooses debug mux port to iomux '000' - prcm/elp debug mux [7:0] '001' - prcm/elp debug mux [15:8] '010' - soc aod debug mux [7:0] '011' - soc aod debug mux [15:8] '100' - ocla debug mux [7:0] '101' - ocla debug mux [15:8]	RW	0x0

:SOC_AON:CPUWAIT

Address offset	0x0000 292C
Description	M33 CPUWAIT. lock once. Do Not lock until written. When written Locked immediately, cleared only at soc aon reset or por reset. These are host security lock configurations
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved	Reserved	RO	0x0000 0000
0	EXIT	locking HOSTMCU CPUWAIT '1' - use FSM value '0' - CPUWAIT	WOnce	0

:SOC_AON:SPARE60

Address offset	0x0000 2930
Description	spare reg for m3 aperture. not locked.
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:0	MEM_SPARE60	M3 spare register	RW	0x0

:SOC_AON:SECSTA

Address offset	0x0000 2934
Description	Security AON Status.
Type	RW

Bits	Field Name	Description	Type	Reset
31:26	Reserved		RO	0x00
25	ELEVMODE	Device Elevated Mode.	RO	0
24	ROMASSETS	Hide Rom Assets, 0 - OPEN 1- HIDE This bit is the status of ROM hide H/W indication. 1 - ROM Assets (2KB in M3 BOOT ROM is hidden); 0 - ROM Assets (2KB in M3 BOOT ROM) is NOT hidden. NOTE: same as [HIDEASSETS]	RO	0
23	BOOTROM	Hide Boot ROM. This bit is the status of ROM hide H/W indication. 1 - entire Boot ROM is hidden; 0 - Boot ROM is NOT hidden.	RO	0
22	LCSTRONG	Device LifeCycle Strong Pattern Valid. 0 - FAIL 1- PASS This bit indicates the fuse shift is done without EFC error	RO	0
21	CRCIGNORE	PRCM Ignore Fuse CRC Check. 0 - NO 1 - YES This bit indicates the Device System PRCM module sets the CRC check ignored bit	RO	0
20	CRCPASSED	Fuse CRC Check Passed. 0 - NO 1- YES This bit indicates the Device h/w fuse shift has passed without CRC error, or that fuse shift is done with the CRC check being ignored by System PRCM module	RO	0
19	LCPATMATCH	Pattern Match LyfeCycle. 0 - NO_MATCH 1 - MATCH This bit indicates the Device h/w fuse shift has done and that the Lifecycle matches the strong pattern. Meaning pattern equal to 0 in LC equal to 0 or 1; pattern equal to LC of ATTST PRIVILEGE; pattern equal to LC of Operational; NOTE: No validity Check is conditioning this indication. Specifically no EFC or CRC check masks this indication.	RO	0
18	COREEN	Core Enable, 0 - NO 1 - YES This bit indicates the Device Application CPU requested the Network CPU to power off ("Connectivity Stop" a.k.a "SL STOP" in former device family). When This bit is set the Network Core CPU registers will be automatically cleared. The device is now ready to be reloaded in "elevated mode" namely Secondary Boot.	RO	0
17	LCVALID	Device LifeCycle Valid. 0 - FAIL 1 - PASS This bit indicates the Device h/w fuse shift has pass without EFC or CRC errors and that the Lifecycle matches the strong pattern. Meaning pattern equal to 0 in LC equal to 0 or 1; pattern equal to LC of ATTST PRIVILEGE; pattern equal to LC of Operational;	RO	0
16	EFCLDDONE	EFC Autoload Done. 0 - FAIL 1 - PASS This bit indicates the Device h/w fuse shit progress has been done.	RO	0
15:11	EFCERR	EFC Error. This field reflects the Device fuse shift EFC error 5 bits. All zeros means no error.	RO	0x00
10	Reserved		RO	0
9:8	PRCMSOP	PRCM SOP: 0- DEBUG 1- DEFAULT 2- FSPKG 3- FSPRB This field reflects the Device Sense on Power (SOP): OSPREY_DEV_SOP_SOC_DEBUG 2'h0 OSPREY_DEV_SOP_DEFAULT 2'h1 OSPREY_DEV_SOP_FORCE_SUPPLY_PKG 2'h2 OSPREY_DEV_SOP_FORCE_SUPPLY 2'h3	RO	0x0
7:5	HWCRCEN	HW CRC Enable. This field reflects the Device fuse shift field HWCRCEN (3b) in case that EFC check has passed. Otherwise, it reflects "000"	RO	0x0
4	SECBYPASS	Security Bypass. 0 - FALSE 1 - TRUE This bit indicates the Device is in ATTEST (or First Birthday). Specifically, the Fuse pass without EFC or CRC errors, the Lifecycle is either 0 or 1 and strong pattern is all zeros. NOTE: same as [DEVATTEST]	RO	0
3	Reserved		RO	0
2	DEVATTEST	Device At test. 0 - FALSE 1 - TRUE This bit indicates the Device is in ATTEST (or First Birthday). Specifically, the Fuse pass without EFC or CRC errors, the Lifecycle is either 0 or 1 and strong pattern is all zeros. NOTE: same as [SECBYPASS]	RO	0
1	UDSRDEN	UDS Read Enable. 0 - HIDE 1- OPEN This bit is the status of UDS hide H/W indication. 1 - UDS is readable; 0 - UDS is hidden. The Status Registers [UDS0.], [UDS1.], [UDS2.], [UDS3.] and [FUSELINE3.], [FUSELINE4.], [FUSELINE5.], [FUSELINE6.] will be read as 0	RO	0
0	HIDEASST	Hide assets. 0. OPEN 1. HIDE This bit is the status of ROM hide H/W indication. 1 - ROM Assets (2KB in M3 BOOT ROM is hidden); 0 - ROM Assets (2KB in M3 BOOT ROM) is NOT hidden. NOTE: same as [ROMASSETS]	RO	0

:SOC_AON:ESM3VAL2ND

Address offset	0x0000 2938
Description	ESM3 2nd Magic Value. This value is compared to hard coded value and unmask ESM only when value is matched. This additional compare allow additional protection on ESM and also allow vendor to unmask ESM only at the end of vendor secure boot (SBL) is completed
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	Reserved		RO	0x00 0000
7:0	MGCVAL	ESM 2nd magic value	RW	0x00

:SOC_AON:ESM4VAL2ND

Address offset	0x0000 293C
Description	ESM4 2nd Magic Value. This value is compared to hard coded value and unmask ESM only when value is matched. This additional compare allow additional protection on ESM and also allow vendor to unmask ESM only at the end of vendor secure boot (SBL) is completed
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	Reserved		RO	0x00 0000
7:0	MGCVAL	ESM 2nd magic value	RW	0x00

:SOC_AON:ESM5VAL2ND

Address offset	0x0000 2940
Description	ESM5 2nd Magic Value. This value is compared to hard coded value and unmask ESM only when value is matched. This additional compare allow additional protection on ESM and also allow vendor to unmask ESM only at the end of vendor secure boot (SBL) is completed
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	Reserved		RO	0x00 0000
7:0	MGCVAL	ESM 2nd magic value	RW	0x00

:SOC_AON:ESM3STA

Address offset	0x0000 2944
Description	ESM3 Status. status register , for each of the ESM (enable sequence monitor) what is the current state of esm.
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:0	ESM3STA	5 states: 0000 - READY 0001 - ENABLED (not guarenteed that magic values match) 0010 - PENDING TO NEXT WRITE 0100 - GRACFULLY LOCKED 1000 - FAULT	RO	0x0

:SOC_AON:ESM4STA

Address offset	0x0000 2948
Description	ESM4 Status. status register , for each of the ESM (enable sequence monitor) what is the current state of esm.
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:0	ESM4STA	5 states: 0000 - READY 0001 - ENABLED (not guarenteed that magic values match) 0010 - PENDING TO NEXT WRITE 0100 - GRACFULLY LOCKED 1000 - FAULT	RO	0x0

:SOC_AON:ESM5STA

Address offset	0x0000 294C
Description	ESM5 Status. status register , for each of the ESM (enable sequence monitor) what is the current state of esm.
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:0	ESM5STA	5 states: 0000 - READY 0001 - ENABLED (not guarenteed that magic values match) 0010 - PENDING TO NEXT WRITE 0100 - GRACFULLY LOCKED 1000 - FAULT	RO	0x0

:SOC_AON:ESM3STA2ND

Address offset	0x0000 2950
Description	ESM3 2nd magic value match indication.
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1	MGCVFLT	ESM 2nd magic val fault ( note: indicates fault before a write to the magic val register)	RO	0
0	MGCVDONE	ESM 2nd magic val match	RO	0

:SOC_AON:ESM4STA2ND

Address offset	0x0000 2954
Description	ESM4 2nd magic value match indication.
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1	MGCVFLT	ESM 2nd magic val fault ( note: indicates fault before a write to the magic val register)	RO	0
0	MGCVDONE	ESM 2nd magic val match	RO	0

:SOC_AON:ESM5STA2ND

Address offset	0x0000 2958
Description	ESM5 2nd magic value match indication.
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1	MGCVFLT	ESM 2nd magic val fault ( note: indicates fault before a write to the magic val register)	RO	0
0	MGCVDONE	ESM 2nd magic val match	RO	0

:SOC_AON:LCSTA

Address offset	0x0000 295C
Description	This register contains information on Device Life Cycles ad follow: 1. [11:8] Device Life Cycle SW Managed - as exist at [FUSELINE0.DEVLCSW] 2. [3:0] Device Life Cycle - based on Device Life Cycle HW Managed as exist at [FUSELINE0.DEVLCHW] but with following decoding and validation logic: if fuse data is valid- no crc/no efc ready /pattern error the Decoded value is: 0 - 1st Birthday 1 - AT TEST 2 - AT TEST Privilege 3 - Operational otherwise, the value is 4 - fault mode -fault occurred on life cycle read
Type	RW

Bits	Field Name	Description	Type	Reset
31:12	Reserved		RO	0x0 0000
11:8	LIFECYCLE_SW_MANAGED	OSPREY SW device lifecycle	RO	0x0
7:4	Reserved		RO	0x0
3:0	LIFECYCLE	OSPREY device lifecycle	RO	0x0

:SOC_AON:DRMAST

Address offset	0x0000 2960
Description	DRMAST
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	ERASE_DRMAST_DONE	ERASE_DRMAST_DONE 1: erase done 0: erase in progress	RO	0

:SOC_AON:FLASHMASK

Address offset	0x0000 2964
Description	FLASH MASK
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	FLASHMASKOV	FLASH_MASK_OVERRIDE Override flash data output masking logic ( done using flash cs ) to allow working on external flash on stacked PSRAM devices 1: unmask flash lines, data visible on external pins 0: flash lines are masked according to flash_cs	RW	1

:SOC_AON:WSOCROM

Address offset	0x0000 2968
Description	WSOC ROM Unhide. 1 lock. Write once. Asserted by FW at the end of ROM boot. Locked immediately , cleared by core disable (or at soc aon reset or por reset)
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved	Reserved	RO	0x0000 0000
0	UNHIDE	Hiding the ROM	WOnce	X