SOC_AAON

This section provides information on the SOC_AAON Module Instance within this product. Each of the registers within the Module Instance is described separately below.

SOC_AAON Registers Mapping Summary

:SOC_AAON Common Register Mapping Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset
DMASIMASK	RW	32	0x0000 0000	0x0000 0000
DMASISET	RW	32	0x0000 0000	0x0000 0004
DMASICLR	RW	32	0x0000 0000	0x0000 0008
DMASIMSET	RW	32	0x0000 0000	0x0000 000C
DMASIMCLR	RW	32	0x0000 0000	0x0000 0010
DMASRIS	RW	32	0x0000 0000	0x0000 0014
DMASMIS	RW	32	0x0000 0000	0x0000 0018
DMANSIMASK	RW	32	0x0000 0000	0x0000 1000
DMANSISET	RW	32	0x0000 0000	0x0000 1004
DMANSICLR	RW	32	0x0000 0000	0x0000 1008
DMANSIMSET	RW	32	0x0000 0000	0x0000 100C
DMANSIMCLR	RW	32	0x0000 0000	0x0000 1010
DMANSRIS	RW	32	0x0000 0000	0x0000 1014
DMANSMIS	RW	32	0x0000 0000	0x0000 1018
DMAM3IMASK	RW	32	0x0000 0000	0x0000 2000
DMAM3ISET	RW	32	0x0000 0000	0x0000 2004
DMAM3ICLR	RW	32	0x0000 0000	0x0000 2008
DMAM3IMSET	RW	32	0x0000 0000	0x0000 200C
DMAM3IMCLR	RW	32	0x0000 0000	0x0000 2010
DMAM3RIS	RW	32	0x0000 0000	0x0000 2014
DMAM3MIS	RW	32	0x0000 0000	0x0000 2018

SOC_AAON Instances Register Mapping Summary

SOC_AAON Register Descriptions

:SOC_AAON Common Register Descriptions

:SOC_AAON:DMASIMASK

Address offset	0x0000 0000
Description	DMA M33 Secure Event IMASK. Mask Event. '0' - CLR - Clear Interrupt Mask '1' - SET - Set Interrupt Mask
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:0	IMASK	'0' - CLR - Clear Interrupt Mask '1' - SET - Set Interrupt Mask	RW	0x0000

:SOC_AAON:DMASISET

Address offset	0x0000 0004
Description	DMA M33 Secure Event ISET. Sets event in RIS Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - SET - Sets interrupt
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:0	ISET	Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - SET - Sets interrupt Type: Write-Clear.	WO	0x0000

:SOC_AAON:DMASICLR

Address offset	0x0000 0008
Description	DMA M33 Secure Event ICLR. Clears event in RIS Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - CLR - Clears the Event
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:0	ICLR	Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - CLR - Clears the Event Type: Write-Clear.	WO	0x0000

:SOC_AAON:DMASIMSET

Address offset	0x0000 000C
Description	DMA M33 Secure Event IMSET. Sets Event Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - SET - Set interrupt mask
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:0	IMSET	Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - SET - Set interrupt mask Type: Write-Clear	WO	0x0000

:SOC_AAON:DMASIMCLR

Address offset	0x0000 0010
Description	DMA M33 Secure Event IMCLR. Clears Event Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - CLR - Clear interrupt mask
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:0	IMCLR	Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - CLR - Clear interrupt mask Type: Write-Clear.	WO	0x0000

:SOC_AAON:DMASRIS

Address offset	0x0000 0014
Description	DMA M33 Secure Event RIS. Raw interrupt status for event. This bit is set to 1 when an event is received. when the corresponding bit in ICLR is set to 1, this bit will be cleared. Read 0 - CLR - Interrupt did not occur Read 1 - SET - Interrupt occurred
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:0	RIS	Read 0 - CLR - Interrupt did not occur Read 1 - SET - Interrupt occurred	RO	0x0000

:SOC_AAON:DMASMIS

Address offset	0x0000 0018
Description	DMA M33 Secure Event MIS. Mask interrupt status for event Read 0 - CLR - Interrupt did not occur Read 1 - SET - Interrupt occurred
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:0	MIS	Read 0 - CLR - Interrupt did not occur Read 1 - SET - Interrupt occurred	RO	0x0000

:SOC_AAON:DMANSIMASK

Address offset	0x0000 1000
Description	DMA M33 Non-Secured IMASK. Mask Event. '0' - CLR - Clear Interrupt Mask '1' - SET - Set Interrupt Mask
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:0	IMASK	'0' - CLR - Clear Interrupt Mask '1' - SET - Set Interrupt Mask	RW	0x0000

:SOC_AAON:DMANSISET

Address offset	0x0000 1004
Description	DMA M33 Non-Secured ISET. Sets event in RIS Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - SET - Sets interrupt
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:0	ISET	Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - SET - Sets interrupt Type: Write-Clear.	WO	0x0000

:SOC_AAON:DMANSICLR

Address offset	0x0000 1008
Description	DMA M33 Non-Secured ICLR. Clears event in RIS Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - CLR - Clears the Event
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:0	ICLR	Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - CLR - Clears the Event Type: Write-Clear.	WO	0x0000

:SOC_AAON:DMANSIMSET

Address offset	0x0000 100C
Description	DMA M33 Non-Secured IMSET. Sets Event Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - SET - Set interrupt mask
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:0	IMSET	Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - SET - Set interrupt mask Type: Write-Clear	WO	0x0000

:SOC_AAON:DMANSIMCLR

Address offset	0x0000 1010
Description	DMA M33 Non-Secured IMCLR. Clears Event Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - CLR - Clear interrupt mask
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:0	IMCLR	Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - CLR - Clear interrupt mask Type: Write-Clear.	WO	0x0000

:SOC_AAON:DMANSRIS

Address offset	0x0000 1014
Description	DMA M33 Non-Secured RIS. Raw interrupt status for event. This bit is set to 1 when an event is received. when the corresponding bit in ICLR is set to 1, this bit will be cleared. Read 0 - CLR - Interrupt did not occur Read 1 - SET - Interrupt occurred
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:0	RIS	Read 0 - CLR - Interrupt did not occur Read 1 - SET - Interrupt occurred	RO	0x0000

:SOC_AAON:DMANSMIS

Address offset	0x0000 1018
Description	DMA M33 Non-Secured MIS. Mask interrupt status for event Read 0 - CLR - Interrupt did not occur Read 1 - SET - Interrupt occurred
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:0	MIS	Read 0 - CLR - Interrupt did not occur Read 1 - SET - Interrupt occurred	RO	0x0000

:SOC_AAON:DMAM3IMASK

Address offset	0x0000 2000
Description	DMA M3 Event IMASK. Mask Event. '0' - CLR - Clear Interrupt Mask '1' - SET - Set Interrupt Mask
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:0	IMASK	'0' - CLR - Clear Interrupt Mask '1' - SET - Set Interrupt Mask	RW	0x0000

:SOC_AAON:DMAM3ISET

Address offset	0x0000 2004
Description	DMA M3 Event ISET. Sets event in RIS Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - SET - Sets interrupt
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:0	ISET	Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - SET - Sets interrupt Type: Write-Clear.	WO	0x0000

:SOC_AAON:DMAM3ICLR

Address offset	0x0000 2008
Description	DMA M3 Event ICLR. Clears event in RIS Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - CLR - Clears the Event
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:0	ICLR	Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - CLR - Clears the Event Type: Write-Clear.	WO	0x0000

:SOC_AAON:DMAM3IMSET

Address offset	0x0000 200C
Description	DMA M3 Event IMSET. Sets Event Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - SET - Set interrupt mask
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:0	IMSET	Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - SET - Set interrupt mask Type: Write-Clear	WO	0x0000

:SOC_AAON:DMAM3IMCLR

Address offset	0x0000 2010
Description	DMA M3 Event IMCLR. Clears Event Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - CLR - Clear interrupt mask
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:0	IMCLR	Write 0 - NO_EFFECT - Writing 0 has no effect Write 1 - CLR - Clear interrupt mask Type: Write-Clear.	WO	0x0000

:SOC_AAON:DMAM3RIS

Address offset	0x0000 2014
Description	DMA M3 Event RIS. This bit is set to 1 when an event is received. when the corresponding bit in ICLR is set to 1, this bit will be cleared. Read 0 - CLR - Interrupt did not occur Read 1 - SET - Interrupt occurred
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:0	RIS	Read 0 - CLR - Interrupt did not occur Read 1 - SET - Interrupt occurred	RO	0x0000

:SOC_AAON:DMAM3MIS

Address offset	0x0000 2018
Description	DMA M3 Event MIS. Mask interrupt status for event Read 0 - CLR - Interrupt did not occur Read 1 - SET - Interrupt occurred
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:0	MIS	Read 0 - CLR - Interrupt did not occur Read 1 - SET - Interrupt occured	RO	0x0000