PRCM_SCRATCHPAD

PRCM_SCRATCHPAD

This section provides information on the PRCM_SCRATCHPAD Module Instance within this product. Each of the registers within the Module Instance is described separately below.

SCRATCHPAD CONTROL REGISTERS

PRCM_SCRATCHPAD Registers Mapping Summary

:PRCM_SCRATCHPAD Common Register Mapping Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset
LINE1	RW	32	0x0000 0000	0x0000 0000
RSTCAUS	RW	32	0x0000 0000	0x0000 0004
LINE0	RW	32	0x0000 0000	0x0000 0008
LOCK	RW	32	0x0000 0000	0x0000 000C
LINE2	RW	32	0x0000 0000	0x0000 1000

PRCM_SCRATCHPAD Instances Register Mapping Summary

PRCM_SCRATCHPAD Register Descriptions

:PRCM_SCRATCHPAD Common Register Descriptions

:PRCM_SCRATCHPAD:LINE1

Address offset	0x0000 0000
Description	PRCM SCRATCHPAD m3 messages which should survive AON Reset and provide additional info on reset cause: Critical error types + indication if reset applied for this error- number of bits? Max number of failures for reset apply - one common value for all errors with reset apply set Counter
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	VALUE LINE 1 Scratch pad line 1			RW	0x0000 0000

:PRCM_SCRATCHPAD:RSTCAUS

Address offset	0x0000 0004
Description	RESET CAUSE OSPREY PRCM AON scratch pad, this register bank is not deleted in SOC AON RESET and kept through reset/low power and brownout events
Type	RW

Bits	Field Name	Description			Type	Reset
31:17	RESERVED	spare			RW	0x0000
16	RSTCAUS_CLR_WRCL	CLEAR write clear Reset cause clear on write - first initiate relevant source reset clear RVM - RVMTRIMCTL.RVMRSTCAUSCLR BOD - BODCTL.RSTCAUSECLR DEBUGSS - PMURSTCLR.DBGSSCAUS WDT - PMURSTCLR.WDTCAUS			WO	0
15:12	RESERVED_2_2	spare			RO	0x0
11	M3WD	M3 Watch Dog			RO	0
10	M33CRSLSTA	M33 CORE SL START Core CONN STOP (M33 driven)			RO	0
9	OOFSLP	OUT OF SLEEP Exit sleep on wakeup event only			RO	0
8	SOCAON_BY_HOST	SOC AON by HOST			RO	0
7	M33WD	M33 WATCH DOG			RO	0
6	DBGSS	DEBUGSS REQUEST Debug req reset			RO	0
5	SOCAON	SOC AON Device self reset (SOC AON by CORE )			RO	0
4	BOD	BOD; applicable only when protection BOD is disabled			RO	0
3	RVMH	RVM high detect of fault injection ; applicable only when protection RVMH is disabled			RO	0
2	RVML	RVM low detect of fault injection ; applicable only when protection RVML is disabled			RO	0
1	POR	POR			RO	0
0	RSTLINE	Reset line			RO	0

:PRCM_SCRATCHPAD:LINE0

Address offset	0x0000 0008
Description	OSPREY PRCM AON scratch pad, this register bank is not deleted in SOC AON RESET and kept through reset/low power and brownout events keep approved authenticated debug requests locked to allow OTA debug allow write only during M3 boot - M3 Privilege mode (before soc_boot_done) Allow read by M3/M33 according to configuration/firewall
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	VALUE LINE 0 Scratch pad line 0			RW	0x0000 0000

:PRCM_SCRATCHPAD:LOCK

Address offset	0x0000 000C
Description	OSPREY PRCM AON scratch pad, this register bank is not deleted in SOC AON RESET and kept through reset/low power and brownout events Lock is released on power on reset allow write only during M3 boot - M3 Privilege mode (before soc_boot_done)
Type	RW

Bits	Field Name	Description			Type	Reset
31:1	Reserved	spare			RW	0x0000 0000
0	SPLOCK	SCRATCHPAD LOCK			RW	0

:PRCM_SCRATCHPAD:LINE2

Address offset	0x0000 1000
Description	PRCM SCRATCHPAD 2 m33 messages which should survive AON Reset: OTA info -number of bits? Critical error types + indication if reset applied for this error- number of bits?
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	VALUE LINE 2 Scratch pad line 2			RW	0x0000 0000