PRCM_AON

This section provides information on the PRCM_AON Module Instance within this product. Each of the registers within the Module Instance is described separately below.

PRCM - POWER, RESET, CLK, MANAGEMENT INTERNAL NOTE: [confluence][https://confluence.itg.ti.com/display/WNG/PRCM+TOP+-+PRCM]

PRCM_AON Registers Mapping Summary

:PRCM_AON Common Register Mapping Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset
HFLXGRP	RW	32	0x000F FFFF	0x0000 1034
HFLXGRPIND	RW	32	0x0000 0000	0x0000 1038
REFCTL	RW	32	0x0001 0000	0x0000 1048
REFCTL_DONE	RW	32	0x0000 0001	0x0000 104C
HSTATICGRP	RW	32	0x0BEE FFFF	0x0000 1054
HSTATICGRPIND	RW	32	0x0000 0000	0x0000 1058
LOGHMEMSTA	RW	32	0x0000 0000	0x0000 105C
CONNSTP	RW	32	0x0000 0001	0x0000 1060
HRSTOV	RW	32	0x0000 0000	0x0000 1064
SLPDEEP	RW	32	0x0000 0000	0x0000 1068
SHPRECISE	RW	32	0x0000 0000	0x0000 2000
LFXTCTL	RW	32	0x0000 0000	0x0000 2008
LFXTSPARE	RW	32	0x0000 0000	0x0000 200C
LFOSCEN	RO	32	0x0000 0000	0x0000 2010
FUSEDATA5	RO	32	0x0000 0000	0x0000 2014
FUSEDATA6	RO	32	0x0000 0000	0x0000 2018
FUSEDATA7	RO	32	0x0000 0000	0x0000 201C
FUSEDATA8	RO	32	0x0000 0000	0x0000 2020
FUSEDATA9	RO	32	0x0000 0000	0x0000 2024
FUSEDATA10	RO	32	0x0000 0000	0x0000 2028
FUSEDATA11	RO	32	0x0000 0000	0x0000 202C
FUSEDATA12	RO	32	0x0000 0000	0x0000 2030
FUSEDATA13	RO	32	0x0000 0000	0x0000 2034
FUSEDATA14	RO	32	0x0000 0000	0x0000 2038
PRCMRAWFS0	RO	32	0x0000 0000	0x0000 203C
PRCMRAWFS1	RO	32	0x0000 0000	0x0000 2040
PRCMRAWFS2	RO	32	0x0000 0000	0x0000 2044
PRCMRAWFS3	RO	32	0x0000 0000	0x0000 2048
PRCMRAWFS4	RO	32	0x0000 0000	0x0000 204C
PRCMRAWFS5	RO	32	0x0000 0000	0x0000 2050
PRCMRAWFS6	RO	32	0x0000 0000	0x0000 2054
PRCMRAWFS7	RO	32	0x0000 0000	0x0000 2058
PRCMRAWFS8	RO	32	0x0000 0000	0x0000 205C
PRCMRAWFS9	RO	32	0x0000 0000	0x0000 2060
PRCMRAWFS10	RO	32	0x0000 0000	0x0000 2064
FCLKDET	RW	32	0x0000 0000	0x0000 2068
PLOCKLOSCFG	RW	32	0x0000 0000	0x0000 206C
PLOCKLOSSTA	RO	32	0x0000 0000	0x0000 2070
RTCCTL	RW	32	0x0000 0002	0x0000 2074
LFINCCTL	RW	32	0x8000 0014	0x0000 2078
LFCLKSTA	RO	32	0x0000 0000	0x0000 207C
LFINCOVR	RW	32	0x0000 0000	0x0000 2080
LFQUALCTL	RW	32	0x0000 2064	0x0000 2084
LFINCCTLI	RW	32	0x001E 8480	0x0000 2088
SCLKCNT	RW	32	0x0000 0000	0x0000 208C
SCLKCNT_CTRL	RW	32	0x0000 000C	0x0000 2090
SCLKCNT_START	RW	32	0x0000 0000	0x0000 2094
SCLKCTL	RW	32	0x0000 0000	0x0000 2098
STA	RW	32	0x0000 0000	0x0000 209C
INTERUPT	RW	32	0x0000 0000	0x0000 20A0
HPRCMSHAR	RW	32	0x0000 0000	0x0000 20A4
CRSLPIND	RW	32	0x0000 0000	0x0000 20A8
HSLPIND	RW	32	0x0000 0000	0x0000 20AC
FNCLKMUXCTL	RW	32	0x0000 0000	0x0000 20B0
RSTCTL	RW	32	0x0000 0000	0x0000 20B4
LFOSC	RW	32	0x0000 0000	0x0000 20B8
FSCFG	RW	32	0x0000 0002	0x0000 7000
PMCIO	RO	32	0x0000 0000	0x0000 7004
BOD	RW	32	0x0400 0003	0x0000 700C
RVMH	RW	32	0x0000 0003	0x0000 7010
RVML	RW	32	0x0000 0003	0x0000 7014
PSCON	RW	32	0x0000 1108	0x0000 7018
DBGAPEN	RW	32	0x0000 0003	0x0000 701C
OVDBGAP1	RW	32	0x0000 0000	0x0000 7020
OVDBGAP2	RW	32	0x0000 0000	0x0000 7024
SLPREF	RW	32	0x0000 0360	0x0000 7028
DBGGM	RW	32	0x0007 0040	0x0000 702C
PMURTRIM	RW	32	0x0000 0000	0x0000 7030
VNWACTL	RW	32	0x0000 0000	0x0000 7034
SRAMKATRIM	RW	32	0x0000 12C0	0x0000 7038
VAL	RW	32	0x0000 0000	0x0000 7040
SRAMKAEN	RW	32	0x0000 0002	0x0000 7044
DLDOEN	RW	32	0x0000 0003	0x0000 7048
DLDOVTRIM	RW	32	0x0000 0007	0x0000 704C
DKAEN	RW	32	0x0000 0000	0x0000 7050
DKATRIM	RW	32	0x0000 0019	0x0000 7054
DLDOLPMOD	RW	32	0x0000 0000	0x0000 7058
DLDOCFG	RW	32	0x0000 023E	0x0000 705C
RVMTRIMCTL	RW	32	0x0000 0000	0x0000 7060
RVMTRIMPMUSTA	RW	32	0x0000 0000	0x0000 7064
RVMLTRIMCTL	RW	32	0x0000 0000	0x0000 7068
I2VCIRCUIT_CTRL	RW	32	0x0000 0200	0x0000 706C
PMBISTCTL	RW	32	0x0000 0000	0x0000 7070
PMUCOMP	RW	32	0x0000 0000	0x0000 7074
ABGRTRIM	RW	32	0x0000 0000	0x0000 7078
ABGTRIMTMP	RW	32	0x0000 0000	0x0000 707C
CKMSPARE	RW	32	0x0000 0000	0x0000 7080
ABGPEN	RW	32	0x0000 8601	0x0000 7084
ABGPTRIMMAG	RW	32	0x0000 0000	0x0000 7088
FCLKREQABGPDLY	RW	32	0x0000 0000	0x0000 708C
FCLKLDODLY	RW	32	0x0001 000E	0x0000 7090
FCBGSETDLY	RW	32	0x0000 0007	0x0000 7094
FCLKABGPFCDLY	RW	32	0x0000 0013	0x0000 7098
ABGPDISDLY	RW	32	0x0000 0008	0x0000 709C
ABGPTSTMOD	RW	32	0x0000 0000	0x0000 70A0
PRIMSLDOILOD	RW	32	0x0000 0000	0x0000 70A4
PRIMSLIC	RW	32	0x0000 0801	0x0000 70A8
FCLKDISHFXTDLY	RW	32	0x0000 0008	0x0000 70AC
CLKSLIEN	RW	32	0x0000 0001	0x0000 70B0
CLKSLIITRIM	RW	32	0x0000 0000	0x0000 70B4
PRIMSLIRTRIM	RW	32	0x0000 0000	0x0000 70B8
PRIMOSC	RW	32	0x0000 0000	0x0000 70BC
OSCEN	RW	32	0x0000 0010	0x0000 70C0
OSCITRIM	RW	32	0x0000 2F00	0x0000 70C4
OSCBSTDLY	RW	32	0x0000 00F0	0x0000 70C8
OSCNORMDLY	RW	32	0x0000 0078	0x0000 70CC
CRDIGBUFCTRL	RW	32	0x0000 0024	0x0000 70D0
OSCDLY	RW	32	0x0000 0005	0x0000 70D4
STRUCMLDOCTL	RW	32	0x0000 0004	0x0000 70D8
SHDOWFCLKCTL	RW	32	0x0000 0033	0x0000 70DC
SLIBIBYPCTL	RW	32	0x0000 0000	0x0000 70E0
ECLKREQDLY	RW	32	0x0000 0108	0x0000 70E4
OSCGN	RW	32	0x0000 066F	0x0000 70E8
PRIMENTMUX	RW	32	0x0000 0000	0x0000 70EC
PRIMEN	RW	32	0x0000 0000	0x0000 70F0
PUSHPULEN	RW	32	0x0000 0000	0x0000 70F4
FCLKDISCODLY	RW	32	0x0000 0008	0x0000 70F8
FCLKVLDEXNDLY	RW	32	0x0000 0000	0x0000 70FC
PRIMEXITSLPDLY	RW	32	0x0000 0000	0x0000 7100
FCLK	RW	32	0x0000 0840	0x0000 7108
FCLKDURDLY	RW	32	0x0000 0001	0x0000 710C
FREFDET	RW	32	0x0000 0002	0x0000 7110
FCLKFSMSOPOV	RW	32	0x0000 0000	0x0000 7114
PMSRNWCAL	RW	32	0x0000 0000	0x0000 7118
PMSTEST	RW	32	0x0000 0000	0x0000 711C
PMSTMUXCTL	RW	32	0x0000 0000	0x0000 7120
PMSSPAR0	RW	32	0x0000 0000	0x0000 7124
PMSSPAR1	RW	32	0x0000 00C0	0x0000 7128
PMSSPAR2	RW	32	0x0000 7E00	0x0000 712C
PMSCTLSTA	RW	32	0x0000 0036	0x0000 7130
PMSSPARIN	RW	32	0x0000 0000	0x0000 7134
PMSPORTSTCTL	RW	32	0x0000 0000	0x0000 7138
PMSSPAR3	RW	32	0x01F2 F200	0x0000 7140
PMSSPAR4	RW	32	0x0000 7E00	0x0000 7144
PMSDLY	RW	32	0x0015 5000	0x0000 7148
BGDISBGENDLY	RW	32	0x0000 0005	0x0000 714C
SWENSWDISDLY	RW	32	0x0000 0003	0x0000 7150
BGENSWENDLY	RW	32	0x0000 0001	0x0000 7154
SWDISBGDISDLY	RW	32	0x0000 0001	0x0000 7158
ICG CTL	RW	32	0x0000 000F	0x0000 715C
HALT	RW	32	0x0000 0000	0x0000 7160
LOGICCA	RW	32	0x0000 000A	0x0000 716C
LOGICMEMSTA	RW	32	0x1300 0000	0x0000 7170
HOL	RW	32	0x0000 0000	0x0000 7174
PSCONHGEN	RW	32	0x0000 0004	0x0000 7178
IOPROCSBIT	RW	32	0x0000 0000	0x0000 717C
SCLKCNT_CTRL_CORE	RW	32	0x0000 000C	0x0000 7180
STA_CORE	RW	32	0x0000 0000	0x0000 7184
AAONLOGCAPT	RW	32	0x0000 000A	0x0000 718C
HWDT	RW	32	0x0000 0000	0x0000 7190
SCLKCNT_CORE	RW	32	0x0000 0000	0x0000 7194
SRAMLDO	RW	32	0x0000 0002	0x0000 7198
DBG	RW	32	0x0000 0000	0x0000 719C
RSTOVCTL	RW	32	0x0000 0000	0x0000 71A0
PMURSTCLR	RW	32	0x0000 0000	0x0000 71A4
MEMGCTLCRSTAT1	RW	32	0xFFFF FFFF	0x0000 71A8
MEMGCTLCRFLEX	RW	32	0x000F FFFF	0x0000 71AC
CRSH	RW	32	0x0000 0000	0x0000 71B0

PRCM_AON Instances Register Mapping Summary

PRCM_AON Register Descriptions

:PRCM_AON Common Register Descriptions

:PRCM_AON:HFLXGRP

Address offset	0x0000 1034
Description	PSCON Memory Groups Control Host Flex. Applicable only if MODE selected flex as HOST memory. Bank power State When owner IP Active/Sleep (power domain is ON/OFF) 0 - OFF/OFF 1 - Reserved 2 - ON/OFF 3 - ON/RET
Type	RW

Bits	Field Name	Description	Type	Reset
31:20	Reserved		RO	0x000
19:18	PWRSTATE10	POWER STATE 10 Group 10	RW	0x3
17:16	PWRSTATE9	POWER STATE 9 Group 9	RW	0x3
15:14	PWRSTATE8	POWER STATE 8 Group 8	RW	0x3
13:12	PWRSTATE7	POWER STATE 7 Group 7	RW	0x3
11:10	PWRSTATE6	POWER STATE 6 Group 6	RW	0x3
9:8	PWRSTATE5	POWER STATE 5 Group 5	RW	0x3
7:6	PWRSTATE4	POWER STATE 4 Group 4	RW	0x3
5:4	PWRSTATE3	POWER STATE 3 Group 3	RW	0x3
3:2	PWRSTATE2	POWER STATE 2 Group 2	RW	0x3
1:0	PWRSTATE1	POWER STATE 1 Group 1	RW	0x3

:PRCM_AON:HFLXGRPIND

Address offset	0x0000 1038
Description	PSCON Memory Groups Indication Host Flex Applicable only if MODE selected flex as HOST memory. Memory bank from this group is shared 1 - Shared 0 - Not Shared
Type	RW

Bits	Field Name	Description	Type	Reset
31:10	Reserved		RO	0x00 0000
9	ISSHARED10	IS SHARED 10 Group 10	RW	0
8	ISSHARED9	IS SHARED 9 Group 9	RW	0
7	ISSHARED8	IS SHARED 8 Group 8	RW	0
6	ISSHARED7	IS SHARED 7 Group 7	RW	0
5	ISSHARED6	IS SHARED 6 Group 6	RW	0
4	ISSHARED5	IS SHARED 5 Group 5	RW	0
3	ISSHARED4	IS SHARED 4 Group 4	RW	0
2	ISSHARED3	IS SHARED 3 Group 3	RW	0
1	ISSHARED2	IS SHARED 2 Group 2	RW	0
0	ISSHARED1	IS SHARED 1 Group 1	RW	0

:PRCM_AON:REFCTL

Address offset	0x0000 1048
Description	PSCON Memory Status Refresh
Type	RW

Bits	Field Name	Description	Type	Reset
31:17	Reserved		RO	0x0000
16	ENISO	Enable ISO During Refresh '1' - set ISO during refresh '0' - don't set ISO	RW	1
15:1	Reserved		RO	0x0000
0	SETKICK	Memory Host Set Refresh write clear triggers the refresh cycle. first set all memories to desired status, then fire the "refresh" pulse	WO	0

:PRCM_AON:REFCTL_DONE

Address offset	0x0000 104C
Description	Memory Refresh Status
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	REFCTL_DONE	memories status refresh is done	RO	1

:PRCM_AON:HSTATICGRP

Address offset	0x0000 1054
Description	PSCON Memory Groups Control Host Static. Bank power State When owner IP Active/Sleep (power domain is ON/OFF) 0 - OFF/OFF 1 - Reserved 2 - ON/OFF 3 - ON/RET
Type	RW

Bits	Field Name	Description	Type	Reset
31:28	Reserved		RO	0x0
27:26	PWRSTAT14	POWER STATE 14 Group 36	RW	0x2
25:24	PWRSTAT13	POWER STATE 13 Group 35	RW	0x3
23:22	PWRSTAT12	POWER STATE 12 HIF Group 34 - being used as shared memory	RW	0x3
21:20	PWRSTAT11	POWER STATE 11 Group 33	RW	0x2
19:18	PWRSTAT10	POWER STATE 10 Group 32	RW	0x3
17:16	PWRSTAT9	POWER STATE 9 Group 31	RW	0x2
15:14	PWRSTAT8	POWER STATE 8 Group 30	RW	0x3
13:12	PWRSTAT7	POWER STATE 7 Group 29	RW	0x3
11:10	PWRSTAT6	POWER STATE 6 Group 28	RW	0x3
9:8	PWRSTAT5	POWER STATE 5 Group 27	RW	0x3
7:6	PWRSTAT4	POWER STATE 4 Group 26	RW	0x3
5:4	PWRSTAT3	POWER STATE 3 Group 25	RW	0x3
3:2	PWRSTAT2	POWER STATE 2 Group 24	RW	0x3
1:0	PWRSTAT1	POWER STATE 1 Group 23	RW	0x3

:PRCM_AON:HSTATICGRPIND

Address offset	0x0000 1058
Description	Memory bank from this group is shared 1 - Shared 0 - Not Shared
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3	ISSHARED4	IS SHARED 4 Group 26	RW	0
2	ISSHARED3	IS SHARED 3 Group 25	RW	0
1	ISSHARED2	IS SHARED 2 Group 24	RW	0
0	ISSHARED1	IS SHARED 1 Group 23	RW	0

:PRCM_AON:LOGHMEMSTA

Address offset	0x0000 105C
Description	Logic Host Memory Status
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:0	AONIN	Host Memory AONIN indication	RO	0x0000

:PRCM_AON:CONNSTP

Address offset	0x0000 1060
Description	Connectivity Stop
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	SET	'1' - Connectivity Stop '0' - Connectivity Start	RW	1

:PRCM_AON:HRSTOV

Address offset	0x0000 1064
Description	HOST RESET OV CONTROL reset override control register, active low polarity: '0' - override reset (force reset line to 0, reset asserted, active low) '1' - don't override reset
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	PULSE	PULSE write clear	WO	0

:PRCM_AON:SLPDEEP

Address offset	0x0000 1068
Description	The register holds sleepdeep command for the host_mcu for debugging
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	MEM_SLPDEEP_WROPT	Set this field to force HOST deepsleep. It will cleared by HW when [HSLPIND] is '1'.	RW	0

:PRCM_AON:SHPRECISE

Address offset	0x0000 2000
Description	SHARED PRECISE override values for PRCM SHARED Modules
Type	RW

Bits	Field Name	Description	Type	Reset
31:23	Reserved		RO	0x000
22:16	HOSTPDU	HOST POWER DOMAIN UP SET precise duration for HOST Power Domain UP - factor 4 slow CLK resolution 0 - 1 Slow CLKs 1 - 5 Slow CLKs 2 - 9 Slow CLKs 3 - 13 Slow CLKs ... 127 - 509 Slow CLKs	RW	0x00
15	Reserved		RO	0
14:8	COREPDU	CORE POWER DOMAIN UP SET precise duration for CORE Power Domain UP - factor 4 slow CLK resolution 0 - 1 Slow CLKs 1 - 5 Slow CLKs 2 - 9 Slow CLKs 3 - 13 Slow CLKs ... 127 - 509 Slow CLKs	RW	0x00
7	Reserved		RO	0
6:0	PMSFREFPU	PMS FREF PLL UP SET precise duration for CORE PRCM Shared UP - factor 4 slow CLK resolution 0 - 1 Slow CLKs 1 - 5 Slow CLKs 2 - 9 Slow CLKs 3 - 13 Slow CLKs ... 127 - 509 Slow CLKs	RW	0x00

:PRCM_AON:LFXTCTL

Address offset	0x0000 2008
Description	LFXT CONTROL
Type	RW

Bits	Field Name	Description	Type	Reset
31:27	Reserved		RO	0x00
26:22	AMPREGITRIM	AMPLITUDE REGULATION CURRENT TRIM Amplitude regulation current trim	RW	0x00
21:17	IBIASRTRIM	IBIAS RTRIM Constant gm bias resistor ladder trim	RW	0x00
16:12	AMPREGRTRIM	AMPLITUDE REGULATION RESISTOR TRIM Amplitude regulation resistor ladder trim	RW	0x00
11:7	IBIASITRIM	IBIAS ITRIM Constant gm bias current trim	RW	0x00
6	AMPREGEN	AMPLITUDE REGULATION ENABLE Enable amplitude regulation	RW	0
5	BOOSTMODE	BOOST MODE Start-up pulse for bias current generation	RW	0
4	BYPASS	Bypass LFXT	RW	0
3	CPEN	Comparator (slicer) enable	RW	0
2	CPHPMODEN	COMP HP MODE EN Comparator high current mode	RW	0
1	IBIASEN	Enable constant-gm bias	RW	0
0	OSCEN	Oscillator core enable	RW	0

:PRCM_AON:LFXTSPARE

Address offset	0x0000 200C
Description	LFXT SPARE
Type	RW

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	MEM_LFXTSPARE	CTL lfxt spare reg	RW	0x0000

:PRCM_AON:LFOSCEN

Address offset	0x0000 2010
Description	LFOSC ENABLE
Type	RO

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	GOOD	CLK GOOD LFOSC clock good indication based on clock qualification logic	RO	0

:PRCM_AON:FUSEDATA5

Address offset	0x0000 2014
Description	FUSE DATA 5
Type	RO

Bits	Field Name	Description	Type	Reset
31:30	Reserved		RO	0x0
29:24	FUSEDATA5_DEVWAF	DEVWAF	RO	0x00
23:12	FUSEDATA5_DEVY	DEVY	RO	0x000
11:0	FUSEDATA5_DEVX	DEVX	RO	0x000

:PRCM_AON:FUSEDATA6

Address offset	0x0000 2018
Description	FUSE DATA 6
Type	RO

Bits	Field Name	Description	Type	Reset
31:29	FUSEDATA6_DEVFABBE	DEVFABBE	RO	0x0
28:24	FUSEDATA6_DEVFAB	DEVFAB	RO	0x00
23:0	FUSEDATA6_DEVLOT	DEVLOT	RO	0x00 0000

:PRCM_AON:FUSEDATA7

Address offset	0x0000 201C
Description	FUSE DATA 7
Type	RO

Bits	Field Name	Description	Type	Reset
31:25	FUSEDATA7_PMCTEMPSNS1	PMCIO TEMP SENSOR 1ST INSERTION For the first insertion.	RO	0x00
24:20	FUSEDATA7_DIGBGGMI1	DIGBG GMI 1ST INSERTION For the first insertion. This field is used for trimming at boot after shift done.	RO	0x00
19:15	FUSEDATA7_DIGBGRTRIM1	DIGBG RTRIM 1ST INSERTION For the first insertion. This field is used for trimming at boot after shift done.	RO	0x00
14:7	FUSEDATA7_DIGBGMAG1	DIGBG MAG 1ST INSERTION For the first insertion. This field is used for trimming at boot after shift done.	RO	0x00
6:0	FUSEDATA7_DIGBGCURVE1	DIGBG CURVE 1St INSERTION For the first insertion. This field is used for trimming at boot after shift done.	RO	0x00

:PRCM_AON:FUSEDATA8

Address offset	0x0000 2020
Description	FUSE DATA 8
Type	RO

Bits	Field Name	Description	Type	Reset
31	Reserved		RO	0
30:17	FUSEDATA8_CHECKSUM	Checksum_TI_ DIEID_FUSEDATA5_6_8	RO	0x0000
16:6	FUSEDATA8_MKDASHDEFINED	Make-defined	RO	0x000
5	FUSEDATA8_MEMREPAIR	memrepair	RO	0
4:0	FUSEDATA8_DEVDESREV	DEVDesREV	RO	0x00

:PRCM_AON:FUSEDATA9

Address offset	0x0000 2024
Description	FUSE DATA 9
Type	RO

Bits	Field Name	Description	Type	Reset
31:25	FUSEDATA9_PMCTMPSNS2	PMCIO TEMP SENSOR 2ND INSERTION For the second insertion. This field is used by SW only.	RO	0x00
24:20	FUSEDATA9_DIGBGGMI2	DIGBG GMI 2ND INSERTION For the second insertion. This field is used by SW only.	RO	0x00
19:15	FUSEDATA9_DIGBGRTRIM2	DIGBG RTRIM 2ND INSERTION For the second insertion. This field is used by SW only.	RO	0x00
14:7	FUSEDATA9_DIGBGMAG2	DIGBG MAG 2ND INSERTION For the second insertion. This field is used by SW only.	RO	0x00
6:0	FUSEDATA9_DIGBGCUR2	DIGBG CURVE 2ND INSERTION For the second insertion. This field is used by SW only.	RO	0x00

:PRCM_AON:FUSEDATA10

Address offset	0x0000 2028
Description	FUSE DATA 10
Type	RO

Bits	Field Name	Description	Type	Reset
31:26	FUSEDATA10_BROWNOUTTRIM	Brownout Trims	RO	0x00
25:19	FUSEDATA10_I2VCIRCUIT	I2V Circuit (Measure Current using GPADC)	RO	0x00
18:16	FUSEDATA10_ENHIRVMPROT	Enable High RVM protection (Specify whether to use the indication from RVM to reset the device). The RVM Enable can be override by SW (Boot RAM/Privilege mode). 0 - Disable (Ignore indication from RVM) Other (1-7) - Enable (Do not ignore indication from RVM) Consider Splitting the enables (including CRC)	RO	0x0
15:13	FUSEDATA10_ENLOWRVMPROT	Enable Low RVM protection (Specify whether to use the indication from RVM to reset the device). The RVM Enable can be override by SW (Boot RAM/Privilege mode). 0 - Disable (Ignore indication from RVM) Other (1-7) - Enable (Do not ignore indication from RVM)	RO	0x0
12:7	FUSEDATA10_HIRVMTRIM	High Digital Supply RVM Trimming	RO	0x00
6:0	FUSEDATA10_LOWRVMTRIM	Low Digital Supply RVM Trimming	RO	0x00

:PRCM_AON:FUSEDATA11

Address offset	0x0000 202C
Description	FUSE DATA 11
Type	RO

Bits	Field Name	Description	Type	Reset
31	Reserved		RO	0
30:26	FUSEDATA11_RFNWELL	RF NWELL Will be used to calculate during production the PMREF_V2I_RTRIM - Reference current to the RFCIO RX/TX modules (Can be part of OCP\, Not used in cold boot)	RO	0x00
25:22	FUSEDATA11_ANABGRTRIM	ANA BG RTRIM This field is calculated bases on the 'RF_NWELL_Efuse' trimming results ANABG RTRIM (REFSYS_REG0<9:6>)	RO	0x0
21:17	FUSEDATA11_ABGAPMAG2	ANA BGAP MAG 2ND INSERTION For the second insertion. This field is used by SW only.	RO	0x00
16	Reserved		RO	0
15:11	FUSEDATA11_ABGAPTMP2	ANABGAP TEMP 2ND INSERTION Trimming. For the second insertion. This field is used by SW only.	RO	0x00
10:6	FUSEDATA11_ABGAPMAG1	ANA BGAP MAG 1St INSERTION For the first insertion. This field is used for trimming at boot after shift done.	RO	0x00
5	Reserved		RO	0
4:0	FUSEDATA11_ABGAPTMP1	ANABGAP TEMP 1ST INSERTION Trimming. For the first insertion. This field is used for trimming at boot after shift done.	RO	0x00

:PRCM_AON:FUSEDATA12

Address offset	0x0000 2030
Description	FUSE DATA 12
Type	RO

Bits	Field Name	Description	Type	Reset
31:29	FUSEDATA12_IONMOS	IO NMOS	RO	0x0
28:26	FUSEDATA12_IOPMOS	IO PMOS	RO	0x0
25:20	Reserved		RO	0x00
19:17	FUSEDATA12_BROWNOUTEN	Brownout Enable/Disable: 0 - Disable Other (1-7) - Enable (When HW check these bits: if equal to '0' disable otherwise enable)	RO	0x0
16:15	FUSEDATA12_LFOSCFSEL	LFOSC Frequency Trimming	RO	0x0
14:8	FUSEDATA12_LFORESTRIM	LFOSC Resistor Trimming	RO	0x00
7:0	FUSEDATA12_DELTATMP12	DELTA TEMP 1ST 2ND INSERTIONS Defines the delta temperature between the 1st and 2nd insertion in degC	RO	0x00

:PRCM_AON:FUSEDATA13

Address offset	0x0000 2034
Description	FUSE DATA 13
Type	RO

Bits	Field Name	Description	Type	Reset
31:25	FUSEDATA13_GPADCOFFSET	GPADC OFFSET Capture the offset error of the GPADC	RO	0x00
24:22	FUSEDATA13_BYPASSPLL	Bypass SoC PLL Other (0-6) - Do not bypass SoC PLL 7 - Bypass SoC PLL	RO	0x0
21:19	FUSEDATA13_CORENMOS	CORE NMOS SOC ODP	RO	0x0
18:16	FUSEDATA13_COREPMOS	CORE PMOS SOC ODP	RO	0x0
15:12	FUSEDATA13_AFPMOSRFCODP	AF PMOS RFCIO ODP	RO	0x0
11:8	FUSEDATA13_CRPMOSRFCODP	CORE PMOS RFCIO ODP	RO	0x0
7:4	FUSEDATA13_AFNMOSRFCODP	AF NMOS RFCIO ODP	RO	0x0
3:0	FUSEDATA13_CRNMOSRFCODP	CORE NMOS RFCIO ODP	RO	0x0

:PRCM_AON:FUSEDATA14

Address offset	0x0000 2038
Description	FUSE DATA 14
Type	RO

Bits	Field Name	Description	Type	Reset
31:21	Reserved		RO	0x000
20:19	FUSEDATA14_SOCPROCES	SOC PROCESS The value is calculated based on Core PMOS/NMOS (SoC ODP) 2b'00 - Nominal 2b'01 - Weak 2b'10 - Strong	RO	0x0
18:14	FUSEDATA14_PALDOINMON	PA LDO IN MONITOR PA LDO In ('Battery') Sensor Trimming for 3V	RO	0x00
13:11	FUSEDATA14_SLITRIMCTRL	Slicer ITRIM Control (CKM_SLICER_REG0<7:5>)	RO	0x0
10:5	FUSEDATA14_XTITRIMCTRL	XTAL ITRIM control (CKM_OSC_REG0<6:1>)	RO	0x00
4:0	FUSEDATA14_CMRTRIM	CLKM RTRIM This field is calculated base on the 'RF_NWELL_Efuse ' trimming results (CKM_SLICER_REG0<4:0>)	RO	0x00

:PRCM_AON:PRCMRAWFS0

Address offset	0x0000 203C
Description	PRCM RAW FUSE 0 fuse line 5
Type	RO

Bits	Field Name	Description	Type	Reset
31:30	Reserved		RO	0x0
29:24	DEVWAF	DEVWAF	RO	0x00
23:12	DEVY	DEVY	RO	0x000
11:0	DEVX	DEVX	RO	0x000

:PRCM_AON:PRCMRAWFS1

Address offset	0x0000 2040
Description	PRCM RAW FUSE 1 fuse line 6
Type	RO

Bits	Field Name	Description	Type	Reset
31:29	DEVFABBE	DEVFABBE	RO	0x0
28:24	DEVFAB	DEVFAB	RO	0x00
23:0	DEVLOT	DEVLOT	RO	0x00 0000

:PRCM_AON:PRCMRAWFS2

Address offset	0x0000 2044
Description	PRCM RAW FUSE 2 fuse line 7
Type	RO

Bits	Field Name	Description	Type	Reset
31:25	PMCTEMPSNS1	PMCIO TEMP SENSOR 1ST INSERTION For the first insertion.	RO	0x00
24:20	DIGBGGMI1	DIGBG GMI 1ST INSERTION For the first insertion. This field is used for trimming at boot after shift done.	RO	0x00
19:15	DIGBGRTRIM1	DIGBG RTRIM 1ST INSERTION For the first insertion. This field is used for trimming at boot after shift done.	RO	0x00
14:7	DIGBGMAG1	DIGBG MAG 1ST INSERTION For the first insertion. This field is used for trimming at boot after shift done.	RO	0x00
6:0	DIGBGCURVE1	DIGBG CURVE 1ST INSERTION For the first insertion. This field is used for trimming at boot after shift done.	RO	0x00

:PRCM_AON:PRCMRAWFS3

Address offset	0x0000 2048
Description	PRCM RAW FUSE 3 fuse line 8
Type	RO

Bits	Field Name	Description	Type	Reset
31	Reserved		RO	0
30:17	CHECKSUM	Checksum_TI_ DIEID_FUSEDATA5_6_8	RO	0x0000
16:6	MKDASHDEFINED	Make-defined	RO	0x000
5	MEMREPAIR	memrepair	RO	0
4:0	DEVDESREV	DEVDesREV	RO	0x00

:PRCM_AON:PRCMRAWFS4

Address offset	0x0000 204C
Description	PRCM RAW FUSE 4 fuse line 9
Type	RO

Bits	Field Name	Description	Type	Reset
31:25	PMCTMPSNS2	PMCIO TEMP SENSOR 2ND INSERTION For the second insertion. This field is used by SW only.	RO	0x00
24:20	DIGBGGMI2	DIGBG GMI 2ND INSERTION For the second insertion. This field is used by SW only.	RO	0x00
19:15	DIGBGRTRIM2	DIGBG RTRIM 2ND INSERTION For the second insertion. This field is used by SW only.	RO	0x00
14:7	DIGBGMAG2	DIGBG MAG 2ND INSERTION For the second insertion. This field is used by SW only.	RO	0x00
6:0	DIGBGCUR2	DIGBG CURVE 2ND INSERTION For the second insertion. This field is used by SW only.	RO	0x00

:PRCM_AON:PRCMRAWFS5

Address offset	0x0000 2050
Description	PRCM RAW FUSE 5 fuse line 10
Type	RO

Bits	Field Name	Description	Type	Reset
31:26	BROWNOUTTRIM	Brownout Trims	RO	0x00
25:19	I2VCIRCUIT	I2V Circuit (Measure Current using GPADC)	RO	0x00
18:16	ENHIRVMPROT	Enable High RVM protection (Specify whether to use the indication from RVM to reset the device). The RVM Enable can be override by SW (Boot RAM/Privilege mode). 0 - Disable (Ignore indication from RVM) Other (1-7) - Enable (Do not ignore indication from RVM) Consider Splitting the enables (including CRC)	RO	0x0
15:13	ENLOWRVMPROT	Enable Low RVM protection (Specify whether to use the indication from RVM to reset the device). The RVM Enable can be override by SW (Boot RAM/Privilege mode). 0 - Disable (Ignore indication from RVM) Other (1-7) - Enable (Do not ignore indication from RVM)	RO	0x0
12:7	HIRVMTRIM	High Digital Supply RVM Trimming	RO	0x00
6:0	LOWRVMTRIM	Low Digital Supply RVM Trimming	RO	0x00

:PRCM_AON:PRCMRAWFS6

Address offset	0x0000 2054
Description	PRCM RAW FUSE 6 fuse line 11
Type	RO

Bits	Field Name	Description	Type	Reset
31	Reserved		RO	0
30:26	RFNWELL	RF NWELL EFUSE Will be used to calculate during production the PMREF_V2I_RTRIM - Reference current to the RFCIO RX/TX modules (Can be part of OCP\, Not used in cold boot)	RO	0x00
25:22	ANABGRTRIM	ANA BG RTRIM This field is calculated bases on the 'RF_NWELL_Efuse' trimming results ANABG RTRIM (REFSYS_REG0<9:6>)	RO	0x0
21:17	ABGAPMAG2	ANA BGAP MAG 2ND INSERTION For the second insertion. This field is used by SW only.	RO	0x00
16	Reserved		RO	0
15:11	ABGAPTMP2	ANABGAP TEMP 2ND INSERTION Trimming. For the second insertion. This field is used by SW only.	RO	0x00
10:6	ABGAPMAG1	ANA BGAP MAG 1ST INSERTION For the first insertion. This field is used for trimming at boot after shift done.	RO	0x00
5	Reserved		RO	0
4:0	ABGAPTMP1	ANABGAP TEMP 1ST INSERTION Trimming. For the first insertion. This field is used for trimming at boot after shift done.	RO	0x00

:PRCM_AON:PRCMRAWFS7

Address offset	0x0000 2058
Description	PRCM RAW FUSE 7 fuse line 12
Type	RO

Bits	Field Name	Description	Type	Reset
31:29	IONMOS	IO NMOS	RO	0x0
28:26	IOPMOS	IO PMOS	RO	0x0
25:20	Reserved		RO	0x00
19:17	BROWNOUTEN	Brownout Enable/Disable: 0 - Disable Other (1-7) - Enable (When HW check these bits: if equal to '0' disable otherwise enable)	RO	0x0
16:15	LFOSCFSEL	LFOSC Frequency Trimming	RO	0x0
14:8	LFORESTRIM	LFOSC Resistor Trimming	RO	0x00
7:0	DELTATMP12	DELTA TEMPERATURE 1ST 2ND INSERTIONS Defines the delta temperature between the 1st and 2nd insertion in degC	RO	0x00

:PRCM_AON:PRCMRAWFS8

Address offset	0x0000 205C
Description	PRCM RAW FUSE 8 fuse line 13
Type	RO

Bits	Field Name	Description	Type	Reset
31:25	GPADCOFFSET	GPADC OFFSET Capture the offset error of the GPADC	RO	0x00
24:22	BYPASSPLL	Bypass SoC PLL Other (0-6) - Do not bypass SoC PLL 7 - Bypass SoC PLL	RO	0x0
21:19	CORENMOS	CORE NMOS SOC ODP	RO	0x0
18:16	COREPMOS	CORE PMOS SOC ODP	RO	0x0
15:12	AFPMOSRFCODP	AF PMOS RFCIO ODP	RO	0x0
11:8	CRPMOSRFCODP	CORE PMOS RFCIO ODP	RO	0x0
7:4	AFNMOSRFCODP	AF NMOS RFCIO ODP	RO	0x0
3:0	CRNMOSRFCODP	CORE NMOS RFCIO ODP	RO	0x0

:PRCM_AON:PRCMRAWFS9

Address offset	0x0000 2060
Description	PRCM RAW FUSE 9 fuse line 14
Type	RO

Bits	Field Name	Description	Type	Reset
31:21	Reserved		RO	0x000
20:19	SOCPROCES	SOC PROCESS The value is calculated based on Core PMOS/NMOS (SoC ODP) 2b'00 - Nominal 2b'01 - Weak 2b'10 - Strong	RO	0x0
18:14	PALDOINMON	PA LDO IN MONITOR PA LDO In ('Battery') Sensor Trimming for 3V	RO	0x00
13:11	SLITRIMCTRL	Slicer ITRIM Control (CKM_SLICER_REG0<7:5>)	RO	0x0
10:5	XTITRIMCTRL	XTAL ITRIM control (CKM_OSC_REG0<6:1>)	RO	0x00
4:0	CMRTRIM	CLKM RTRIM This field is calculated base on the 'RF_NWELL_Efuse ' trimming results (CKM_SLICER_REG0<4:0>)	RO	0x00

:PRCM_AON:PRCMRAWFS10

Address offset	0x0000 2064
Description	PRCM RAW FUSE 10 fuse line 15
Type	RO

Bits	Field Name	Description			Type	Reset
31:0	Reserved				RO	0x0000 0000

:PRCM_AON:FCLKDET

Address offset	0x0000 2068
Description	FAST CLK DETECTION primary clock detection result
Type	RW

Bits	Field Name	Description	Type	Reset
31:6	Reserved		RO	0x000 0000
5	OVERLAP	Not in use. '1' - if FREF value is overlapping at 40/48MHz or 48/52MHz	RO	0
4	FAILED	fast clock detection FSM failed counter was no in any FREQ boundaries '1' - failed '0' - OK	RO	0
3	Reserved		RO	0
2:0	FREQVAL	FAST CLK FREQUENCY DETECTION VALUE fast clock detection value : 0: 10MHz 1: 26MHz 2: 40MHz 3: 52MHz	RO	0x0

:PRCM_AON:PLOCKLOSCFG

Address offset	0x0000 206C
Description	SOC PLL LOCK LOSS CONFIG
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	CLR	CLEAR write clear Clear Lock Loss Status.	WO	0

:PRCM_AON:PLOCKLOSSTA

Address offset	0x0000 2070
Description	SOC PLL LOCK LOSS STATUS
Type	RO

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	STA	STATUS Lock Loss Status. Set when SOC PLL is low during active (PD Core ON). This indication is latch asynchronously since lock low implies no SOC PLL clock is available. In PLL Bypass mode (e.g. SOP = DoA) this indication is ignored. (Yet, in SOP = DoA , when SOP bypass is applied, and SOC PLL is no more bypassed, this indication is valid)	RO	0

:PRCM_AON:RTCCTL

Address offset	0x0000 2074
Description	RTC CONTROL
Type	RW

Bits	Field Name	Description	Type	Reset
31:12	Reserved		RO	0x0 0000
11:8	LFTICKSTA	LFTICK STATE '1101' - Real LFTICK '1100' - Gate RTC CLK '1110' - Force LFTICK high '1010' - Switch RTC CLK low '0010' - Standby '0000' - Force LFTICK low '0100' - switch RTC CLK high '0101' - Ungate RTC CLK	RO	0x0
7:2	Reserved		RO	0x00
1	DISIMMINENT	NOT USED - DO NOT CHANGE VALUE '1' - disables imminent option towards SYSTIMER '0' - enables imminent	RW	1
0	LFTICKSEL	LFTICK SELECT '1' - use real LFTICK '0' - use fake LFTICK	RW	0

:PRCM_AON:LFINCCTL

Address offset	0x0000 2078
Description	LFINC CONTROL Low frequency time increment control
Type	RW

Bits	Field Name	Description		Type	Reset
31	PREVSTBY	PREVENT STANDBY Controls if the LFINC filter prevents STANDBY entry until settled.		RW	1
		0	OFF Disable. Do not prevent STANDBY entry.
		1	ON Enable. Prevent STANDBY entry.
30:10	Reserved			RO	0x00 0000
9:8	FKLFTICKSEL	FAKE LFTICK SELECTOR '00' - default - LOKI + corner case scenario '01' - first integration '10' - LOKI '11' - always enable		RW	0x0
		0x0	LARGE Restart gearing on large error. Fewer false restarts, slower response on small frequency shifts.
		0x1	MIDLARGE Middle value towards LARGE.
		0x2	MIDSMALL Middle value towards SMALL.
		0x3	SMALL Restart gearing on small error. Potentially more false restarts, faster response on small frequency shifts.
7	STOPGEAR	STOP GEAR Controls the final gear of the LFINC filter.		RW	0
		0	LOW Lowest final gear. Best settling, but less dynamic frequency tracking.
		1	HIGH Highest final gear. Best dynamic frequency tracking, but higher variation in filter value.
6:5	ERRTHR	ERROR THRESHOLD Controls the threshold for gearing restart of the LFINC filter. Only effective if [GEARRSTRT] is not ONETHR or TWOTHR.		RW	0x0
		0x0	LARGE Restart gearing on large error. Fewer false restarts, slower response on small frequency shifts.
		0x1	MIDLARGE Middle value towards LARGE.
		0x2	MIDSMALL Middle value towards SMALL.
		0x3	SMALL Restart gearing on small error. Potentially more false restarts, faster response on small frequency shifts.
4:3	GEARRSTRT	GEAR RESTART Controls gearing restart of the LFINC filter.		RW	0x2
		0x0	NEVER Never restart gearing. Very stable filter value, but very slow response on frequency changes.
		0x1	ONETHR Restart gearing when the error accumulator crosses the threshold once.
		0x2	TWOTHR Restart gearing when the error accumulator crosses the threshold twice in a row.
2	SOFTRSTRT	SOFT RESTART Use a higher gear after re-enabling / wake-up. The filter will require 16-24 LFCLK periods to settle (depending on [STOPGEAR]), but may respond faster to frequency changes during STANDBY.		RW	1
		0	OFF Don't use soft gearing restarts
		1	ON Use soft gearing restarts
1:0	Reserved			RO	0x0

:PRCM_AON:LFCLKSTA

Address offset	0x0000 207C
Description	LFCLK STATUS Low-frequency clock status
Type	RO

Bits	Field Name	Description		Type	Reset
31	LFCLKSTA_GOOD	Low frequency clock good Note: This is only a coarse frequency check based on [LFQUALCTL.*]. The clock may not be accurate enough for timing purposes.		RO	0
30:26	Reserved			RO	0x00
25	LFCLKSTA_FLTSETTLED	FILTER SETTLED LFINC filter is running and settled.		RO	0
24	LFCLKSTA_LFTICKSRC	Source of LFTICK.		RO	0
		Read 0	LFCLK LFTICK generated from the selected LFCLK
		Read 1	FAKE LFTICK generated from CLKULL (LFCLK not available)
23:22	LFCLKSTA_LFINCSRC	Source of LFINC used by the RTC. This value depends on [LFINCOVR.OVERRIDE], LF clock availability, HF tracking loop status and the device state (ACTIVE/STANDBY).		RO	0x0
		Read 0x0	MEAS Using measured value. This value is updated by hardware and can be read from [LFINC].
		Read 0x1	AVG Using filtered / average value. This value is updated by hardware and can be read and updated in [LFINCCTL.INT].
		Read 0x2	OVERRIDE Using override value from [LFINCOVR.LFINC]
		Read 0x3	FAKE Using FAKE LFTICKs with corresponding LFINC value.
21:0	LFCLKSTA_LFINC	Measured value of LFCLKSTA_LFINC. Given in microseconds with 16 fractional bits. This value is calculated by Hardware. It is the LFCLK period according to CLKULL cycles.		RO	0x00 0000

:PRCM_AON:LFINCOVR

Address offset	0x0000 2080
Description	LFINC OVERRIDE Low frequency time increment override control
Type	RW

Bits	Field Name	Description	Type	Reset
31	OV	Override LF increment Use the value provided in [LFINC] instead of the value calculated by Hardware.	RW	0
30:22	Reserved		RO	0x000
21:0	LFINC	LF increment value This value is used when [OVERRIDE] is set to 1. Otherwise the value is calculated automatically.	RW	0x00 0000

:PRCM_AON:LFQUALCTL

Address offset	0x0000 2084
Description	Low frequency clock qualification control
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:8	MAXERR	Maximum LFCLK period error. Value given in microseconds, 3 integer bits + 3 fractional bits.	RW	0x20
7:0	CONSEC	Number of consecutive times the LFCLK period error has to be smaller than [MAXERR] to be considered "good". Setting this value to 0 will bypass clock qualification, and the "good" indicator will always be 1.	RW	0x64

:PRCM_AON:LFINCCTLI

Address offset	0x0000 2088
Description	Low frequency time increment value
Type	RW

Bits	Field Name	Description	Type	Reset
31:22	Reserved		RO	0x000
21:0	LFINCCTLI_WROPT	Increment override value write opt SW and HW can write this value Integral part of the LFINC filter. This value is updated by Hardware to reflect the current state of the filter. It can also be written to change the current state.	RW	0x1E 8480

:PRCM_AON:SCLKCNT

Address offset	0x0000 208C
Description	SLOW CLK COUNT
Type	RW

Bits	Field Name	Description	Type	Reset
31:23	Reserved		RO	0x000
22:16	PERVAL	PERIOD VALUE slow CLK current value. bounds are 0 to slow_clk_counter_period	RO	0x00
15	Reserved		RO	0
14:0	DET	FAST CLK DETECTION COUNTER VALUE Counter results for 4 slow clock freq lower upper (MHz) (dec) (dec) 10 1190 1503 26 3094 3908 40 4760 6012 52 6188 7815	RO	0x0000

:PRCM_AON:SCLKCNT_CTRL

Address offset	0x0000 2090
Description	SLOW CLOCK COUNTER CONTROL
Type	RW

Bits	Field Name	Description	Type	Reset
31:25	Reserved		RO	0x00
24	RESULT_VALID_RDCLP	RESULT VALID read clear pulse Determine whether the measurement is in progress or done: 0x0 - In progress (Relevant in one shot only) 0x1 - Done (when finish measurement and result ready)	RO	0
23:9	RESULT	RESULT Slow Clock counter result	RO	0x0000
8:2	PER	PERIOD Determine the Slow clock counter period (Slow Clock cycles), 1 - 128. '0' - 1 CLK cycle '1' - 2 CLK cycles '2' - 3 CLK cycles ... '127' - 128 CLK cycles	RW	0x03
1:0	MODE	MODE Determine the Slow clock counter mode- 0x3 - Reserved 0x2 - Periodic 0x1 - One Shot 0x0 - Disable	RW	0x0

:PRCM_AON:SCLKCNT_START

Address offset	0x0000 2094
Description	SLOW CLK COUNT START KICK
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	EN	ENABLE write clear start the FREQUENCY DETECTION. MEM_SLOW_CLK_COUNTER_MODE should be set prior to the start indication	WO	0

:PRCM_AON:SCLKCTL

Address offset	0x0000 2098
Description	SLOW CLK CONTROL
Type	RW

Bits	Field Name	Description	Type	Reset
31:5	Reserved		RO	0x000 0000
4	DETGOOD	DETECTION GOOD '1' - means 5 edges detected of LFXT/EXT/XTAL	RO	0
3	GOOD	'1' - set LFXT CLK good	RW	0
2	P32CLKSEL	PLL CLOCK SELECTOR '0' - LFCLK (real tick should be selected) '1' - PLL32 CLK (fake tick should be selected)	RW	0
1	SDIVCLKSEL	SLOW CLOCK DIVISION SELECTOR 1 - select LFXT/EXT/XTAL CLK DIV 8 0 - select LFXT/EXT/XTAL CLK	RW	0
0	LFOSCSEL	LFOSC SELECTOR 0 - select RCOSC 1 - select LFXT/EXT/XTAL	RW	0

:PRCM_AON:STA

Address offset	0x0000 209C
Description	PRCM STATUS
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1	XTALMOD	XTAL MODE '1' - XTAL mode '0' - TCXO External mode	RO	0
0	FAILED_STATUS	FAST CLK DETECTIOn FAILED '1' - FREF detection failed	RO	0

:PRCM_AON:INTERUPT

Address offset	0x0000 20A0
Description	[0]- indication at slow CLK calibration for one shot mode. [1] - lfinc_updated [2] - lfinc_gearing_restart [3] - lfclk_oor [4] - lfclk_loss [5] - NU [6] - NU [7] - NU
Type	RW

Bits	Field Name	Description	Type	Reset
31:24	Reserved		RO	0x00
23:16	IRQSTABM	IRQs indication after Mask	RO	0x00
15:8	IRQBM	PRCM IRQ mask option	RW	0x00
7:0	IRQSTARAW	PRCM IRQ Clear indication and raw status read clear	RO	0x00

:PRCM_AON:HPRCMSHAR

Address offset	0x0000 20A4
Description	HOST PRCM SHARED override values for PRCM SHARED Modules
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	PSHREQOV	PLL REQUEST OVERRIDE '1' - keeps awake at sleep state '0' - regular operation note: in order to set this field as '1', FREF OV and PMS OV must be set as well.	RW	0
1	FREFREQOV	FREF REQUEST OVERRIDE '1' - keeps awake at sleep state '0' - regular operation note: in order to set this field as '1', PMS OV must be set as well.	RW	0
0	PMSREQOV	PMS REQUEST OVERRIDE '1' - keeps awake at sleep state '0' - regular operation	RW	0

:PRCM_AON:CRSLPIND

Address offset	0x0000 20A8
Description	CORE SLEEP INDICATION
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	CTLSTAT	CONTROL STATE '1' - CORE is SLEEP '0' - CORE is in ACTIVE or gets into ACTIVE	RO	0

:PRCM_AON:HSLPIND

Address offset	0x0000 20AC
Description	HOST SLEEP INDICATION
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	CTLSTAT	CONTROL STATE '1' - HOST is SLEEP '0' - HOST is in ACTIVE or gets into ACTIVE	RO	0

:PRCM_AON:FNCLKMUXCTL

Address offset	0x0000 20B0
Description	PRCM functional selection towards FAST CLK DETECTION '00000' - prcm_fast_clock 'xxx01' - ospr_hsm_tst_fro_clk_out 'xxx10' - clk_gpadc_clk 'xxx11' - fref_2m_socpll_1p8v 'xx100' - rf_pll_divided_clk '01000' - src_clk_40 '10000' - lfxt / xtal / ext '11000' - rcosc
Type	RW

Bits	Field Name	Description	Type	Reset
31:5	Reserved		RO	0x000 0000
4:3	SEL	Fast CLK detection selector MEM_DBGCLKSEL should be set 3'b0 for this reg to take place '00' - prcm_fast_clock. '01' - src_clk_40 '10' - lfxt / xtal / ext '11' - rcosc	RW	0x0
2:0	DBGCLKSEL	Debug and Fast CLK detection selector 'x00' - prcm_fast_clock. 'x01' - ospr_hsm_tst_fro_clk_out 'x10' - clk_gpadc_clk 'x11' - fref_2m_socpll_1p8v '100' - rf_pll_divided_clk	RO	0x0

:PRCM_AON:RSTCTL

Address offset	0x0000 20B4
Description	RESET CONTROL
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	SOCAON	SOC AON write clear '1' - set reset	WO	0

:PRCM_AON:LFOSC

Address offset	0x0000 20B8
Description	LFOSC OVERRIDE STATUS
Type	RW

Bits	Field Name	Description	Type	Reset
31:23	Reserved		RO	0x000
22	OVOSCSTOPEN	OVERRIDE OSC STOP EN LFOSC STOP enable override value	RW	0
21	OVOSCEN	OVERRIDE OSC EN LFOSC enable override value	RW	0
20	SELOVOSCEN	SELECTOR OVERRIDE OSC ENABLE LFOSC enable override select	RW	0
19:13	OVRESTRIMVAL	OVERRIDE RESISTOR SELECTOR VALUE LFOSC RES trim override value	RW	0x00
12	SELOVRESTRIM	SELECTOR OVERRIDE RESISTOR TRIM LFOSC RES trim override select	RW	0
11:5	FSRESTRIM	FUSE RESISTOR TRIM Analog band gap rtrimfuse value for LFOSC rtrim	RO	0x00
4:3	OVFSELVAL	OVERRIDE FSEL SELECTOR VALUE LFOSC frequency trim override value	RW	0x0
2	SELOVFSEL	SELECT OVERRIDE FSEL LFOSC frequency trim override select	RW	0
1:0	FSFSEL	LFOSC frequency trim value	RO	0x0

:PRCM_AON:FSCFG

Address offset	0x0000 7000
Description	FUSE CONFIG config efc ready
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1	OVEFCRDY	OVERRIDE EFC READY VALUE	RW	1
0	SELOVEFCRDY	SELECT OVERRIDE EFC READY '1' selects ov_efc_ready reg	RW	0

:PRCM_AON:PMCIO

Address offset	0x0000 7004
Description	PMCIO
Type	RO

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1:0	SOPSTA	SOP status output from POL sequencer	RO	0x0

:PRCM_AON:BOD

Address offset	0x0000 700C
Description	BODCTL
Type	RW

Bits	Field Name	Description	Type	Reset
31	RSTCAUSECLR	BOD reset cause clear value Set '1' to this field will automated a pulse to pmu. clear this field to '0' after use.	RW	0
30:27	Reserved		RO	0x0
26	BTFDBACKEN	boot feedback for bod enable status	RO	1
25:23	FSENPROT	bod protection enable fuse value	RO	0x0
22	OVENPROT	override value for BOD protection enable	RW	0
21	SELOVENPROT	select BOD protection enable '1' - select override '0' - select fuse	RW	0
20:19	HYSTCTL	BOD hysteresis control	RW	0x0
18:13	OVTRIM	BOD trim override value	RW	0x00
12	SELOVTRIM	BOD trim override select	RW	0
11:6	FSTRIM	BOD fuse trim value	RO	0x00
5	FSMLOIQ	FSM bod low IQ status	RO	0
4	OVLOIQ	OVERRIDE LOW IQ BOD Comparator low IQ power mode override value	RW	0
3	SELOVLOIQ	SELECTOR OVERRIDE BOD LOW IQ BOD Comparator low IQ power mode override select	RW	0
2	Reserved		RO	0
1	IPEN	IP ENABLE BOD Comparator input Enable value	RW	1
0	COMPEN	BOD COMPARATOR ENABLE Enable value	RW	1

:PRCM_AON:RVMH

Address offset	0x0000 7010
Description	RVM HIGH CONTROL
Type	RW

Bits	Field Name	Description	Type	Reset
31:12	Reserved		RO	0x0 0000
11:10	HYSTCTL	RVMH hysteresis control	RW	0x0
9	FSMLOIQ	FSM rvml lo IQ status	RO	0
8	OVLOIQ	RVMH Comparator low IQ power mode override value	RW	0
7	SELOVLOIQ	RVMH Comparator low IQ power mode override select	RW	0
6	OVENPROT	RVMH Comparator En protection mode override value (Override the fuse value) 1 - RVM Hi violation will NOT be detected by device (PMU.POL) 1 - RVM Hi violation will be detected by device (PMU.POL)	RW	0
5	SELOVENPROT	RVMH Comparator En protection power mode override select (override fuse value)	RW	0
4:2	FSENPROT	RVMH Comparator En protection fuse data	RO	0x0
1	IPEN	RVMH Comparator input Enable	RW	1
0	COMPEN	RVMH COMPARATOR Enable	RW	1

:PRCM_AON:RVML

Address offset	0x0000 7014
Description	RVM LOW CONTROL
Type	RW

Bits	Field Name	Description	Type	Reset
31:12	Reserved		RO	0x0 0000
11:10	HYSTCTL	RVMH hysteresis control	RW	0x0
9	FSMLOIQ	FSM rvml lo IQ status	RO	0
8	OVLOIQ	RVML Comparator low IQ power mode override value	RW	0
7	SELOVLOIQ	RVML Comparator low IQ power mode override select	RW	0
6	OVENPROT	RVML Comparator En protection mode override value (Override the fuse value) 1 - RVM Low violation will NOT be detected by device (PMU.POL) 1 - RVM Low violation will be detected by device (PMU.POL)	RW	0
5	SELOVENPROT	RVML Comparator En protection power mode override select (override fuse value)	RW	0
4:2	FSENPROT	RVML Comparator En protection fuse data	RO	0x0
1	IPEN	RVML Comparator input Enable override value	RW	1
0	COMPEN	RVML Enable override value	RW	1

:PRCM_AON:PSCON

Address offset	0x0000 7018
Description	PSCON MEMORY DELAY CONTROL
Type	RW

Bits	Field Name	Description	Type	Reset
31:18	Reserved		RO	0x0000
17:13	DLYPGOODRETUP	DELAY BETWEEN PGOOD to RET UP 0000:0.8us; 0001:1.6us; 0010:2.4us; 0011:3.2us;...;1001:8us;1111:12.8us	RW	0x00
12:9	DLYRTAONGOOD	DELAY BETWEEn RTAOn to RTAGOOD 0000:0.8us; 0001:1.6us; 0010:3us; 0011:3.2us;...;1001:8us;1111:12.8us	RW	0x8
8:5	DLYAONAGOOD	DELAY BETWEEN AON to AGOOD 0000:0.8us; 0001:1.6us; 0010:2.4us; 0011:3.2us;...;1001:8us;1111:12.8us	RW	0x8
4:0	DLYPONPGOOD	DELAY BETWEEN PON to PGOOD 0000:0.8us; 0001:1.6us; 0010:2.4us; 0011:3.2us;...;1001:8us;1111:12.8us	RW	0x08

:PRCM_AON:DBGAPEN

Address offset	0x0000 701C
Description	digital bandgap enable register
Type	RW

Bits	Field Name	Description	Type	Reset
31:5	Reserved		RO	0x000 0000
4	ISCONST0	IS CONSTANT 0 1: keep the DBGAP off during sleep BG disable and SW disable 0: allow hibernate	RW	0
3	ISCONST1	IS CONSTANT 1 1: keep the DBGAP on during sleep BG enable and SW enable 0: allow hibernate	RW	0
2	MEM_SEL_OV_DBGAPEN	SELECT OVERRIDE ENABLE 1: select override value for DBGAP enable : 0: DBGAP enable according to FSM	RW	0
1	MEM_OV_DBGAPEN	override value for DBGAP enable	RW	1
0	FSMEN	FSM DIGBG enable status	RO	1

:PRCM_AON:OVDBGAP1

Address offset	0x0000 7020
Description	DBGAP override register
Type	RW

Bits	Field Name	Description	Type	Reset
31:22	Reserved		RO	0x000
21:15	FSCURVTRIM1	FS 1st insertion curve	RO	0x00
14:8	FSCURVTRIM2	FS 2nd insertion curve	RO	0x00
7	SELOVCURVTRIM	SELECT OVERRIDE CURVE VTRIM 1: select override for curve trim : 0: select curve trim from fuse	RW	0
6:0	OVCURVTRIM	override value for DBGAP curve trim : used until fuse chain or when selected	RW	0x00

:PRCM_AON:OVDBGAP2

Address offset	0x0000 7024
Description	DBGAP override register
Type	RW

Bits	Field Name	Description	Type	Reset
31:25	Reserved		RO	0x00
24:17	FSVMAGTRIM2	fuse value for magnitude 2nd insertion trim	RO	0x00
16:9	FSVMAGTRIM1	fuse value for magnitude 1st insertion trim	RO	0x00
8	SELOVVMAGTRIM	SELECT OVERRIDE MAG TRIM 1: select override for mag trim : 0: select mag trim from fuse	RW	0
7:0	OVVMAGTRIM	override value for DBGAP mag trim : used until fuse chain or when selected	RW	0x00

:PRCM_AON:SLPREF

Address offset	0x0000 7028
Description	SLEEP REFERENCE
Type	RW

Bits	Field Name	Description	Type	Reset
31:10	Reserved		RO	0x00 0000
9	FSMEN_CAP_SW	FSM digital bad gap enable cap status	RO	1
8	OVLKSWON	override value for DBGAP switch en	RW	1
7	SELOVLKSWON	SELECT OVERRIDE LEAKAGE SWITCH ON 1: select override value for the DBGAP switch on : 0: prcm_leakage_sw_on controlled by FSM	RW	0
6	FSMDIGBGIREFEN	FSM digital band gap iref enable status	RO	1
5	OVDBGIREFEN	OVERRIDE DBGAP IREF EN	RW	1
4	SELOVDBGIREFEN	SELECT OVERRIDE DBGAP IREF ENABLE	RW	0
3:0	Reserved		RO	0x0

:PRCM_AON:DBGGM

Address offset	0x0000 702C
Description	Digital Band Gap GM GMBIAS config register
Type	RW

Bits	Field Name	Description	Type	Reset
31:19	Reserved		RO	0x0000
18	MEM_PRCM_DBGAPEN_GMBIAS_TRIM	ENABLE BIAS TRIM Enable Trim to GMBIAS module	RW	1
17	MEM_PRCM_DBGAPEN_GMBIAS_STARTUP	ENABLE BOAS STARTUP Startup control from PRCM to power-up GMBIAS.	RW	1
16	MEM_PRCM_DBGAPEN_GMBIAS	dedicated enable for GMBIAS module	RW	1
15:11	FS_DBGGMI_TRIM_2ND_INSERTION	fuse value for gmi 2nd insertion trim	RO	0x00
10:6	FS_DBGGMI_TRIM_1ST_INSERTION	fuse value for gmi 1st insertion trim Trim for GMBIAS IREF current	RO	0x01
5	MEM_SEL_OV_PRCM_DBGGMI_TRIM	SELECT OVERRIDE GMI TRIM 1: select override value for dbgap_gmi_trim : 0: fuse value	RW	0
4:0	MEM_OV_PRCM_DBGGMI_TRIM	override value for dbgap_gmi_trim	RW	0x00

:PRCM_AON:PMURTRIM

Address offset	0x0000 7030
Description	PMU RTRIM
Type	RW

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:11	FSDBGAP2	fuse value for resistor trim 2st insertion	RO	0x00
10:6	FSDBGAP1	fuse value for resistor trim 1st insertion	RO	0x00
5	MEM_SEL_OV_PRCM_PMURTRIM	SELECT OVERRIDE	RW	0
4:0	MEM_OV_PRCM_PMURTRIM	OVERRIDE value for PMU RTRIM	RW	0x00

:PRCM_AON:VNWACTL

Address offset	0x0000 7034
Description	VNWA CONTROL
Type	RW

Bits	Field Name	Description	Type	Reset
31:5	Reserved		RO	0x000 0000
4	OVSRENSCRNMOD	OVERRIDE SRAM ENABLE SCREEN MODE	RW	0
3	SELOVSRENSCNMOD	SELECT OVERRIDE SRAM ENABLE SCREEN MODE	RW	0
2	OVVDDSEN	OVERRIDE VDD ENABLE	RW	0
1	OVTOPEN	OVERRIDE TOP ENABLE	RW	0
0	SELOVTPEN	SELECT OVERRIDE TOP ENABLE	RW	0

:PRCM_AON:SRAMKATRIM

Address offset	0x0000 7038
Description	SRAM KA trim register
Type	RW

Bits	Field Name	Description	Type	Reset
31:13	Reserved		RO	0x0 0000
12	SLPNORTAMOD	SLEEP NO RTA MODE when '1' chooses the no rta mode trim value	RW	1
11:6	MEM_SRAMKATRIM_NO_RTA	SRAM KA trim value in NON RTA mode 0.6v : FSM can move memories to NON RTA mode when feature is enabled and WLAN in OFF : When WLAN is ON the BRG HP memories don't support such low array value	RW	0x0B
5:0	MEM_SRAMKATRIM_RTA	SRAM KA trim value in RTA mode - default mode	RW	0x00

:PRCM_AON:VAL

Address offset	0x0000 7040
Description	VALUE
Type	RW

Bits	Field Name	Description	Type	Reset
31:7	Reserved	bit [7]- prcm_sramldo_en_inrush_limit_lowv	RO	0x000 0000
6:0	MEM_VAL	SPARE REG for SRAM LDO	RW	0x00

:PRCM_AON:SRAMKAEN

Address offset	0x0000 7044
Description	SRAM KA ENABLE
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3	TLOAD	Enable test load for SRAM keep alive	RW	0
2	MEM_SEL_OV_SRAMKAEN	SELECT OVERRIDE 1: select override value for SRAM KA enable : 0: SRAM KA enable from FSM	RW	0
1	MEM_OV_SRAMKAEN	override value for SRAM KA	RW	1
0	FSM	status of final SRAM KA enable	RO	0

:PRCM_AON:DLDOEN

Address offset	0x0000 7048
Description	DIG LDO ENABLE
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	MEM_SEL_OV_DLDOEN	1: select override value for DIG LDO enable : 0: DIG LDO enable from FSM	RW	0
1	MEM_OV_DLDOEN	override value for DIG LDO	RW	1
0	FSM	status of FSM DIG LDO enable	RO	1

:PRCM_AON:DLDOVTRIM

Address offset	0x0000 704C
Description	override register for DIG LDO TRIM
Type	RW

Bits	Field Name	Description	Type	Reset
31:6	Reserved		RO	0x000 0000
5:0	OPP1	digital ldo vtrim value 1.1V	RW	0x07

:PRCM_AON:DKAEN

Address offset	0x0000 7050
Description	DIG KA ENABLE
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3	TLOAD	Enable test load for DIG keep alive	RW	0
2	MEM_SEL_OV_DKAEN	1: select override value for DIG KA enable : 0: DIG KA enable from FSM	RW	0
1	MEM_OV_DKAEN	override value for DIG KA	RW	0
0	FSM	status of FSM DIG KA enable	RO	0

:PRCM_AON:DKATRIM

Address offset	0x0000 7054
Description	DIG KA trim register
Type	RW

Bits	Field Name	Description	Type	Reset
31:6	Reserved		RO	0x000 0000
5:0	VAL	DIGITAL KEEP ALIVE VTRIM VALUE	RW	0x19

:PRCM_AON:DLDOLPMOD

Address offset	0x0000 7058
Description	DIGITAL LDO LOW POWER MODE Enable Low Power Mode for DIGLDO register
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	MEM_PRCM_DLDOLPMOD_EN	set DIG LDO LDO mode	RW	0

:PRCM_AON:DLDOCFG

Address offset	0x0000 705C
Description	DIGITAL LDO CONFIG
Type	RW

Bits	Field Name	Description	Type	Reset
31:11	Reserved		RO	0x00 0000
10:9	IQTRIM_INRUSH	IQ TRIM INRUSH Value of IQ TRIM selected Dynamically by H/W on exit sleep. Default = 0x1	RW	0x1
8	SUBREGEN	SUB REGULATION ENABLE Sub Regulation switch from RBYR TO LDO	RW	0
7	MEM_SEL_PRCM_DLDOEN_INRUSH_LIMIT	Select for S/W Enabling the Inrush Current Limit Mask	RW	0
6	MEM_PRCM_DLDOEN_INRUSH_LIMIT	Enable Inrush Current Limit Mask	RW	0
5:4	IQTRIM	Quiescent current trim bits for DIG LDO	RW	0x3
3:2	SCITRIM	Short circuit current trim bits for DIG LDO	RW	0x3
1	SCPROTEN	SHORT CIRCUIT PROTECT ENABLE Enable short circuit protection for DIG LDO	RW	1
0	TLOADEN	TEST LOAD ENABLE Enable test load for DIG LDO	RW	0

:PRCM_AON:RVMTRIMCTL

Address offset	0x0000 7060
Description	RVM TRIM CONTROL
Type	RW

Bits	Field Name	Description	Type	Reset
31	RVMRSTCAUSCLR	RVM RESET CAUSE CLEAR Set '1' to this field will automated a pulse to pmu. clear this field to '0' after use.	RW	0
30:11	Reserved		RO	0x0 0000
10	SELOVRVMLTRIM	SELECT OVERRIDE RVML TRIM '1' uses ov input '0' uses fs input	RW	0
9:8	OVFSM	OVERRIDE FSM defines override value for rvml fsm	RW	0x0
7	SELOVFSM	SELECT OVERRIDE FSM '1' uses ov input '0' uses fsm input	RW	0
6:1	OV	defines override value for rvmh fuse	RW	0x00
0	SELOVRVMHTRIM	SELECT OVERRIDE RVMH TRIM '1' uses ov input '0' uses fs input	RW	0

:PRCM_AON:RVMTRIMPMUSTA

Address offset	0x0000 7064
Description	RVM TRIM PMU STATUS
Type	RW

Bits	Field Name	Description	Type	Reset
31:28	Reserved		RO	0x0
27:26	FSMRVML	status of FSM RVML TRIM value	RO	0x0
25:19	FSRVML	RVML fuse trim value	RO	0x00
18:12	RVML	RVML trim status value to pmu	RO	0x00
11:6	FSRVMH	RVMH fuse trim value	RO	0x00
5:0	RVMH	RVMH trim status value to pmu	RO	0x00

:PRCM_AON:RVMLTRIMCTL

Address offset	0x0000 7068
Description	RVML TRIM CONTROL
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:7	OVSLP	OVERRIDE SLEEP defines trim sleep value	RW	0x00
6:0	OVOPP1	OVERRIDE OPP1 defines trim opp1 value	RW	0x00

:PRCM_AON:I2VCIRCUIT_CTRL

Address offset	0x0000 706C
Description	I2V CIRCUIT CONTROL
Type	RW

Bits	Field Name	Description	Type	Reset
31:15	Reserved		RO	0x0 0000
14:8	MEM_OV_I2VCIRCUIT	I2V circuit trim override value	RW	0x02
7	MEM_SEL_OV_I2VCIRCUIT	SELECT OVERRIDE I2V circuit trim override select	RW	0
6:0	FS_I2VCIRCUIT	fuse value of I2V circuit	RO	0x00

:PRCM_AON:PMBISTCTL

Address offset	0x0000 7070
Description	PMBIST CONTROL
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	Reserved		RO	0x00 0000
7	VTDETCMPBMEN	VT DETECTOR COMPARATOR BIT MASK ENABLE '1' - enable propagation of VTDET Comparator output '0' - disable Comparator	RW	0
6	PORCMPBMEN	POR COMP BIT MASK ENABLE '1' - enable propagation of POR Comparator output '0' - disable Comparator	RW	0
5	EN	'1' - enable PMBIST module	RW	0
4	BM	BIT MASK '1' - mask bit 0	RW	0
3:0	VAL	one hot bit decoder 4 to 16	RW	0x0

:PRCM_AON:PMUCOMP

Address offset	0x0000 7074
Description	PMU COMPARATOR
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	RVMH	RVMH	RO	0
1	RVML	RVML	RO	0
0	BOD	BOD	RO	0

:PRCM_AON:ABGRTRIM

Address offset	0x0000 7078
Description	Analog band gap rtrim
Type	RW

Bits	Field Name	Description	Type	Reset
31:12	Reserved		RO	0x0 0000
11:8	FS_ABGRTRIM	fuse value for abgap rtrim	RO	0x0
7:6	Reserved		RO	0x0
5	MEM_SEL_OV_ABGRTRIM	1: select override option over the use value : 0: fuse value	RW	0
4	Reserved		RO	0
3:0	MEM_OV_ABGRTRIM	override value for abgap rtrim	RW	0x0

:PRCM_AON:ABGTRIMTMP

Address offset	0x0000 707C
Description	ABGAP TRIM TEMP override option over the fuse value for abgap trimcurve
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:9	FS_ABGTRIMTMP	fuse value for abgap trim temp To adjust output of amp to 1.224V Nom = 0,0,0,0,0,1 or 1,0,0,0,0,1 Strong = 0,1,1,1,0,0 or 1,1,1,1,0,0 Weak = 0,0,0,1,1,0 or 1,0,0,1,1,0	RO	0x00
8	MEM_SEL_OV_ABGTRIMTMP	1: select the override option : 0: fuse value	RW	0
7:6	Reserved		RO	0x0
5:0	MEM_OV_ABGTRIMTMP	override value for abgap trimcurve	RW	0x00

:PRCM_AON:CKMSPARE

Address offset	0x0000 7080
Description	CKM SPARE HW connected to abgap
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:2	OSCREG0	OSC REGISTER 0	RW	0x0
1:0	LDOREG0	LDO REGISTER 0	RW	0x0

:PRCM_AON:ABGPEN

Address offset	0x0000 7084
Description	ABGAP ENABLE general abgap config
Type	RW

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15	FFSMV2I	FAST FSM V2I FSM status - analog band gap V2I enable	RO	1
14	OVV2I	OVERRIDE V2I Enable BG's internal V2I which supplies LDOs "L" = Disable V2I, "H" = Enable V2I	RW	0
13	SELOVV2I	SELECT OVERRIDE V2I	RW	0
12:9	FILTTRIM	FILT TRIM HW connected to abgap filt trim each bit according to the description below- Control bit for 150k "H" = Bypass resistor , "L" = Enable resistor	RW	0x3
8:6	Reserved		RO	0x0
5	FFSMFC	FAST FSM FAST CHARGE FSM status - analog band gap FC enable	RO	0
4	OVFC	OVERRIDE FAST CHARGE override value for the abgap fast charge Enable Fast Charge "H" = Enable Fast charging, "L" = Disable	RW	0
3	SELOVFC	SELECT OVERRIDE FAST CHARGE 1: select override value for abgap fast charge : 0: use HW FSM for abgap fast charge enable	RW	0
2	MEM_SEL_OV_ABGPEN	1: select override value for abgap enable : 0: use HW FSM for abgap enable : : the override value should be written first and then the sel_ov_; after writing the sel_ov_ the value of the override cannot be changed.	RW	0
1	MEM_OV_ABGPEN	override value for abgap en	RW	0
0	FAST_FSM_ABGPEN	FAST FSM final abgap enable signal to abgap	RO	1

:PRCM_AON:ABGPTRIMMAG

Address offset	0x0000 7088
Description	ABGAP TRIM MAG analog bandgap trimming register
Type	RW

Bits	Field Name	Description	Type	Reset
31:13	Reserved		RO	0x0 0000
12:8	FS_ABGPTRIMMAG	fuse value for abgap trimming To adjust output of BG to 800mV Nom = 0,0,0,0,0 Strong = 0,0,0,0,1 Weak = 0,0,0,0,0	RO	0x00
7	Reserved		RO	0
6	MEM_SEL_OV_ABGPTRIMMAG	SELECT OVERRIDE 1: select override value over the fuse value : 0: use fuse value	RW	0
5	Reserved		RO	0
4:0	MEM_OV_ABGPTRIMMAG	override value for abgap trimming To adjust output of BG to 800mV Nom = 0,0,0,0,0 Strong = 0,0,0,0,1 Weak = 0,0,0,0,0	RW	0x00

:PRCM_AON:FCLKREQABGPDLY

Address offset	0x0000 708C
Description	FAST CLK REQUEST ABGAP DELAY host clock settling time in FSM
Type	RW

Bits	Field Name	Description	Type	Reset
31:11	Reserved		RO	0x00 0000
10:3	MEM_FCLKREQABGPDLY_NSYNC	time (sclk) from primary CLK req until FSM enable abgap resolution 250us (need to add 1 to value in register) 0 - 1 slow CLK cycle delay 1 - 2 * 8 sclk cycle delays 2 - 3 * 8 sclk cycle delay ... write [10:3] as 250us resolution read [10:0] - reflect the multiplication by 8 already	RW	0x00
2:0	Reserved		RO	0x0

:PRCM_AON:FCLKLDODLY

Address offset	0x0000 7090
Description	FAST CLK LDO DELAY primary clock FSM timers
Type	RW

Bits	Field Name	Description	Type	Reset
31:18	Reserved		RO	0x0000
17:16	STRTUP	delay time for LDO STARTUP to slicer enable or osc_sli_bias_startup (need to add 1 to value in register) 0 - 1 cycle delay 1 - 2 cycle delay	RW	0x1
15:4	Reserved		RO	0x000
3:0	SLICER	settling time (sclk) for slicer LDO en. (at least 3-5 slow clks minimum): time from FSM enables the slicer LDO to the time it enables the ldo startup (need to add 1 to value in register) 0 - 1 cycle delay 1 - 2 cycle delay	RW	0xE

:PRCM_AON:FCBGSETDLY

Address offset	0x0000 7094
Description	FAST CLK ABGAP SET DELAY analog bandgap settling time
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:0	VAL	time (sclk) for analog bandgap settling by fast clock FSM. time from enabling the ABGAP to the time enabling the fast slicer LDO enable (need to add 1 to value in register) 0 - skip the ABGAP fast charge altogether and ABGAP will be enabled simultaneously with slicer LDO configurable time (CLK_REQ_ABGAP_DELAY) after the clock request from ELP is issued 1 - 2 cycle delay	RW	0x7

:PRCM_AON:FCLKABGPFCDLY

Address offset	0x0000 7098
Description	FAST CLK ABGAP FAST CHARGE DELAY analog bandgap fast charge settling time
Type	RW

Bits	Field Name	Description	Type	Reset
31:5	Reserved		RO	0x000 0000
4:0	VAL	time (sclk) that the ABGAP will be in fast charge mode after enable (default 6 RTC clocks - confirmed with ABGAP design) (need to add 1 to value in register) 0 - 1 cycle delay 1 - 2 cycle delay	RW	0x13

:PRCM_AON:ABGPDISDLY

Address offset	0x0000 709C
Description	analog bandgap disabling time register Prior initiating SW SOC-AON RST or Debugger SOC-AON RST, this reg should be initialized to it's default value
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:0	MEM_FAST_ABGPDISDLY_NSYNC	delay (sclk) from the time fast clock is no valid to the time the ABGAP enable will fall 0 - no delay 1 - 1 sclk cycle delay = 31.25us 2 - 2 sclk cycle delay = 62.5us 3 - 3 sclk cycle delay = 93.75us ...	RW	0x8

:PRCM_AON:ABGPTSTMOD

Address offset	0x0000 70A0
Description	ABGAP TEST MODE HW connected to analog bandgap testmode input
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1:0	MEM_ABGPTSTMOD	HW connected to analog bandgap testmode input bit[1] - Bring out "BG_PRETRIM_0P8V" through TMUX bit[0] - Bring out "BG_1P2V" through TMUX	RW	0x0

:PRCM_AON:PRIMSLDOILOD

Address offset	0x0000 70A4
Description	PRIMARY SLICER LDO ILOAD primary slicer LDO configurations
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1:0	MEM_PRCM_PRIMSLDOILOD_INT	Slicer LDO internal load test condition	RW	0x0

:PRCM_AON:PRIMSLIC

Address offset	0x0000 70A8
Description	primary slicer LDO configurations
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13	SELOVFCLKMBIEN	SELECT OVERRIDE FAST CLK MODULE BIAS ENABLE 1: select override option for CKM bias en 0:CKM bias en driven by FSM	RW	0
12	OVFCLKMBIEN	OVERRIDE FAST CLK MODULE BIAS ENABLE override value for CKM bias en	RW	0
11	FFSMCMBIEN	FAST FSM CKM BIAS ENABLE final primary slicer ldo signal going to CLKM	RO	1
10	CMLDOSTRTUMOD1	CLK MODULE LDO STARTUP MODE 1 clock module ldo startup mode 1	RW	0
9	CMLDOSTRTUMOD2	CLOCK MODULE LDO STARTUP MODE 2 clock module ldo startup mode 2	RW	0
8	CMLDOPPUDNCTL	CLKM LDO PMOS PULL DOWN EN clock module ldo pmos pull down ctrl '1' - disable '0' - enable	RW	0
7:5	Reserved		RO	0x0
4	BYPASS	HW connected to slicer ldo bypass input in CLKM	RW	0
3	Reserved		RO	0
2	SELOVEN	SELECT OVERRIDE ENABLE 1: select override option for primary slicer ldo : 0:primary slicer driven by FSM	RW	0
1	OVEN	OVERRIDE ENABLE override value for primary slicer	RW	0
0	FSMEN	FSM ENABLE final primary slicer ldo signal going to CLKM	RO	1

:PRCM_AON:FCLKDISHFXTDLY

Address offset	0x0000 70AC
Description	FAST CLK DISABLE HFXT DELAY delay from primary clock valid goes low to buffer and slicer LDO disable Prior initiating SW SOC-AON RST or Debugger SOC-AON RST, this reg should be initialized to it's default value
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:0	VAL	delay from fast clock valid goes low to slicer ldo, ldo startup, osc enable and slicer enable to disable mode. 0 - no delay 1 - 1 sclk cycle delay = 31.25us 2 - 2 sclk cycle delay = 62.5us 3 - 3 sclk cycle delay = 93.75us ...	RW	0x8

:PRCM_AON:CLKSLIEN

Address offset	0x0000 70B0
Description	CLK SLICER ENABLE enable options for primary slicer
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	MEM_SEL_OV_FAST_CLKSLIEN	1: select override value for primary slicer en : 0: primary slicer enable from FSM	RW	0
1	MEM_OV_FAST_CLKSLIEN	override value for primary slicer enable signal	RW	0
0	FSM	final primary slicer enable signal to CLKM	RO	1

:PRCM_AON:CLKSLIITRIM

Address offset	0x0000 70B4
Description	CLK SLICER ITRIM primary slicer trimming register
Type	RW

Bits	Field Name	Description	Type	Reset
31:7	Reserved		RO	0x000 0000
6:4	FS	final primary slicer trimming value to CLKM : max hold mechanism of IPs requests	RO	0x0
3	SELOV	1: select override value for primary slicer trimming over max hold logic : 0: select max hold logic : : the override value should be written first and then the sel_ov_; after writing the sel_ov_ the value of the override cannot be changed.	RW	0
2:0	OV	primary slicer trimming override value	RW	0x0

:PRCM_AON:PRIMSLIRTRIM

Address offset	0x0000 70B8
Description	primary clock rtrim cfg register
Type	RW

Bits	Field Name	Description	Type	Reset
31:11	Reserved		RO	0x00 0000
10:6	FS_CMRTRIM	final fast clock rtrim value to CLKM I/F	RO	0x00
5	MEM_SEL_OV_CMRTRIM	1: select override option over the fuse value : 0: select override value until efuse shift done and then fuse value	RW	0
4:0	MEM_OV_CMRTRIM_NSYNC	override value for clock module rtrim	RW	0x00

:PRCM_AON:PRIMOSC

Address offset	0x0000 70BC
Description	PRIMARY OSCILLATOR
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3	CLDOVOSCLEN	CKM LDO VOUT SCL EN Control bit for bringing out LDO_Vout/2 to GPADC	RW	0
2	PRCM_PRIMOSC_BIAS_START	BIAS START Override control Start-up bit for the Osc/Slicer Bias	RO	0
1	MEM_OV_PRCM_PRIMOSC_BIAS_START	OVERRIDE BIAS START Override Start-up bit for the Osc/Slicer Bias	RW	0
0	MEM_SEL_PRCM_PRIMOSC_BIAS_START	SELECT BIAS START Override control Start-up bit for the Osc/Slicer Bias	RW	0

:PRCM_AON:OSCEN

Address offset	0x0000 70C0
Description	OSC ENABLE XTAL cfg register
Type	RW

Bits	Field Name	Description	Type	Reset
31:10	Reserved		RO	0x00 0000
9	PRCM_CM_XTALMOD_SENSE	CM XTAL MODE SENSE Read value of CLK_IN_PRIMARY_M (XTAL_M) input	RO	0
8:5	Reserved		RO	0x0
4	XTSNSPU	XTAL SENSE PULL UP enable for the pull resistor in CLKM that detects XTAL mode	RW	1
3	ISNEEDED	fast clock detection FSM indication that XTAL oscillator was detected	RO	0
2	MEM_SEL_OV_OSCEN	1: select override value for osc enable signal : 0: osc enable comes from FSM	RW	0
1	MEM_OV_OSCEN	override value for osc enable signal	RW	0
0	FAST_FSM_OSCEN	final osc enable signal to CLKM	RO	0

:PRCM_AON:OSCITRIM

Address offset	0x0000 70C4
Description	oscillator itrim cfg register
Type	RW

Bits	Field Name	Description	Type	Reset
31:14	Reserved		RO	0x0 0000
13:8	FSM	final XTAL oscillator trimming value to CLKM	RO	0x2F
7	SELOVOSCGN	1: select override for osc gain values, need to use fast_osc_gain_boost (debug only) 0: Logic select between normal and boost values	RW	0
6:1	FSNORMGN	FUSE normal gain value	RO	0x00
0	MEM_SEL_OSCITRIM	1: select override for osc gain normal values, need to use fast_osc_gain_norm 0: Logic select itrim value	RW	0

:PRCM_AON:OSCBSTDLY

Address offset	0x0000 70C8
Description	OSC BOOST DELAY XTAL OSC boost trim cfg
Type	RW

Bits	Field Name	Description	Type	Reset
31:10	Reserved		RO	0x00 0000
9:3	VAL	time (sclk) while osc itrim gets boost value before moving to normal value in the clock FSM (default 4ms) resolution 250us (need to add 1 to value in register) 0 - 1 slow CLK cycle delay 1 - 2 * 8 sclk cycle delays 2 - 3 * 8 sclk cycle delay ... write [9:3] as 250us resolution read [9:0] - reflect the multiplication by 8 already	RW	0x1E
2:0	Reserved		RO	0x0

:PRCM_AON:OSCNORMDLY

Address offset	0x0000 70CC
Description	OSC NORMAL DELAY XTAL OSC normal trim
Type	RW

Bits	Field Name	Description	Type	Reset
31:9	Reserved		RO	0x00 0000
8:3	VAL	time (sclk) while osc itrim gets normal value before moving to next state of opening the buffer in the clock FSM (need to add 1 to value in register) 0 - 1 slow CLK cycle delay 1 - 2 * 8 sclk cycle delays 2 - 3 * 8 sclk cycle delay ... write [8:3] as 250us resolution read [8:0] - reflect the multiplication by 8 already	RW	0x0F
2:0	Reserved		RO	0x0

:PRCM_AON:CRDIGBUFCTRL

Address offset	0x0000 70D0
Description	core and dig buffer control register
Type	RW

Bits	Field Name	Description	Type	Reset
31:6	Reserved		RO	0x000 0000
5	FSMDBUFEN	FSM DIGITAL BUFFER ENABLE dig buf enable status	RO	1
4	SELOVDBUFEN	SELECT OVERRIDE DIGITAL BUFFER ENABLE select override value or FSM '1' - override '0' - FSM	RW	0
3	OVDBUFEN	override digital buffer enable value	RW	0
2	FSMCRBUFEN	FAST FSM CORE BUFFER ENABLE core buf enable status	RO	1
1	SELOVCRBUFEN	SELECT OVERRIDE CORE BUFFER ENABLE select override value or FSM '1' - override '0' - FSM	RW	0
0	OVCRBUFEN	override core buf enable value	RW	0

:PRCM_AON:OSCDLY

Address offset	0x0000 70D4
Description	OSCILLATOR DELAY XTAL OSC normal trim
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:2	DISSLIBI	DISABLE SLICER BIAS time (sclk) while fast CLK fsm move from normal gain to disabling the osc_and_sli_bias (need to add 1 to value in register) 0 - 1 cycle delay 1 - 2 cycle delay	RW	0x1
1:0	STRTCR	START CORE time (sclk) while fast CLK FSM slicer is enabled and osc_and_sli_bias to boost mode or to disable osc mode (not in xtal) need to add 1 to value in register) 0 - 1 cycle delay 1 - 2 cycle delay	RW	0x1

:PRCM_AON:STRUCMLDOCTL

Address offset	0x0000 70D8
Description	startup clock module ldo control
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	FSM	startup clock module fsm value	RO	1
1	OV	override value for startup clock module LDO	RW	0
0	SELOV	'1' selects FSM '0' selects override	RW	0

:PRCM_AON:SHDOWFCLKCTL

Address offset	0x0000 70DC
Description	SHADOW FAST CLK CONTROL dummy regs control
Type	RW

Bits	Field Name	Description	Type	Reset
31:6	Reserved		RO	0x000 0000
5	HPMODEN	HP MODE ENABLE clock module HP mode enable value to push towards dummy once FSM is SLI_LDO_EN	RW	1
4:0	LDOVOUT	LDO VOUT clock ldo vout value to push towards dummy once FSM is SLI_LDO_EN	RW	0x13

:PRCM_AON:SLIBIBYPCTL

Address offset	0x0000 70E0
Description	slicer bias bypass control reg
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2:0	VAL	'1' - slicer bias bypass	RW	0x0

:PRCM_AON:ECLKREQDLY

Address offset	0x0000 70E4
Description	EXTERNAL CLOCK REQUEST DELAY XTAL OSC normal trim
Type	RW

Bits	Field Name	Description	Type	Reset
31:11	Reserved		RO	0x00 0000
10:3	MEM_ECLKREQDLY_NSYNC	time (sclk) while fast CLK FSM move from ext_CLK_req_wait state to to buffer enable or ip buffer enable resolution 250us (need to add 1 to value in register) 0 - 1 slow CLK cycle delay 1 - 2 * 8 sclk cycle delays 2 - 3 * 8 sclk cycle delay ... write [10:3] as 250us resolution read [10:0] - reflect the multiplication by 8 already	RW	0x21
2:0	Reserved		RO	0x0

:PRCM_AON:OSCGN

Address offset	0x0000 70E8
Description	OSC GAIN XTAL oscillator gain control cfg register
Type	RW

Bits	Field Name	Description	Type	Reset
31:12	Reserved		RO	0x0 0000
11:6	MEM_FAST_OV_OSCGN_NORM_NSYNC	gain for normal mode - when enabling	RW	0x19
5:0	MEM_FAST_OSCGN_BOOST_NSYNC	gain for boost mode - when enabling	RW	0x2F

:PRCM_AON:PRIMENTMUX

Address offset	0x0000 70EC
Description	Primary EN TMUX CFG
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2:0	MEM_PRIMENTMUX	HW connected to CLKM - enables the primary slicer ldo output to test mux	RW	0x0

:PRCM_AON:PRIMEN

Address offset	0x0000 70F0
Description	PRIMARY ENABLE primary top digital clock division
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1	OVDIV2	override divide by 2	RW	0
0	OVDIV4	override divide by 4	RW	0

:PRCM_AON:PUSHPULEN

Address offset	0x0000 70F4
Description	PUSH PULL ENABLE cfg option for the clock to the host
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	MEM_PUSHPULEN_NSYNC	'1' - enables push pull	RW	0

:PRCM_AON:FCLKDISCODLY

Address offset	0x0000 70F8
Description	FAST CLOCK DISABLE CLK OUT DELAY cfg to hold the clock request out high while FSM is turning off Prior initiating SW SOC-AON RST or Debugger SOC-AON RST, this reg should be initialized to it's default value
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:0	VAL	time (sclk) from FSM exit EXTEND state (enter CLK_STOP state) to primary clock request out goes low 0 - no delay 1 - 1 sclk cycle delay = 31.25us 2 - 2 sclk cycle delay = 62.5us 3 - 3 sclk cycle delay = 93.75us ...	RW	0x8

:PRCM_AON:FCLKVLDEXNDLY

Address offset	0x0000 70FC
Description	FAST CLK VALID EXTEND DELAY timers for stopping the primary clock
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2:0	VAL	time (sclk) from primary clock valid goes down to the point when the clock actually stops (need to add 1 to value in register) 0 - 1 cycle delay 1 - 2 cycle delay	RW	0x0

:PRCM_AON:PRIMEXITSLPDLY

Address offset	0x0000 7100
Description	PRIMARY EXIT SLEEP DELAY
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2:0	VAL	time (sclk) from IPs stop asking for primary clock to the time the valid will go down (need to add 1 to value in register) 0 - 1 cycle delay 1 - 2 cycle delay	RW	0x0

:PRCM_AON:FCLK

Address offset	0x0000 7108
Description	fast CLK control over selectors and overrides
Type	RW

Bits	Field Name	Description	Type	Reset
31:12	Reserved		RO	0x0 0000
11	FSMREQIN	primary clock request indication to FSM	RO	1
10	OVREQGZ	fast CLK request gz override Override CLK req to pad (GZ)	RW	0
9	SELOVREQGZ	fast CLK request gz select Override CLK req to pad (GZ)	RW	0
8	OVREQOUT	fast CLK request out override Override CLK req to pad (A)	RW	0
7	SELOVREQOUT	fast CLK request out select Override CLK req to pad (A)	RW	0
6	VAL	primary clock valid indication status	RO	1
5	OVVAL	OVERRIDE VALUE fast CLK valid override Override fref valid	RW	0
4	SELOVVAL	SELECT OVERRIDE VALUE fast CLK valid select Override fref valid	RW	0
3:0	Reserved		RO	0x0

:PRCM_AON:FCLKDURDLY

Address offset	0x0000 710C
Description	Primary TMUX CFG
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1:0	STOP	time (sclk) from end of CLK_STOP state elapse to CLK_OFF '0' - bypass '1' - 1 + 8 sclks delay ~250us '2' - 1 + 16 sclks delay ~500us '3' - 1 + 32 sclks delay ~1ms	RW	0x1

:PRCM_AON:FREFDET

Address offset	0x0000 7110
Description	FREF DETECTION
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3:1	OV	0: 10MHz 1: 26MHz 2: 40MHz 3: 52MHz	RW	0x1
0	SELOV	'1' - fref detection value to pll sharing will be override '0' - fast CLK fsm (fref) value is selected	RW	0

:PRCM_AON:FCLKFSMSOPOV

Address offset	0x0000 7114
Description	this is a SOP OV reg, which is a shadow register. user need to lower ELP CLK req and rise it again in order for the OV reg to take action.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	MEM_SEL_FAST_CLK_SOPSTA	'1' - use sop override for fast CLK fsm '0' - use sop status	RW	0

:PRCM_AON:PMSRNWCAL

Address offset	0x0000 7118
Description	HW connected to PMCIO - To enable the Rnwell calibration
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	MEM_PRCM_PMSRNWCAL_EN	To enable the Rnwell calibration	RW	0

:PRCM_AON:PMSTEST

Address offset	0x0000 711C
Description	PMCIO test configurations
Type	RW

Bits	Field Name	Description	Type	Reset
31:9	Reserved		RO	0x00 0000
8	ENTMUX	HW connected to PMCIO - Enable signal for test mux	RW	0
7:3	Reserved		RO	0x00
2:0	MEM_PMSTEST_LOAD_TRIM	HW connected to PMCIO - Trim bist for LDO test loads	RW	0x0

:PRCM_AON:PMSTMUXCTL

Address offset	0x0000 7120
Description	Test mux control signals. To be decoded one hot
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	MEM_PRCM_PMSTMUXCTL	value switch number Signal 0x00000000 None hi-Z 0x00000001 0 irefn_bg_2u_1p8v[1] 0x00000002 1 irefn_slp_1u_1p8v[1] 0x00000004 2 vref_0p9v_post_filt_pmu 0x00000008 3 vbg_1p22v_lowv 0x00000010 4 sramka_testout_1p8v 0x00000020 5 vdd_sram_sense_lowv 0x00000040 6 no-connect 0x00000080 7 gen_rf_1p8v 0x00000100 8 digka_testout_1p8v 0x00000200 9 mask_digldo_en_1p2_subreg_lowv 0x00000400 10 vcntrl_socpll_1p8v 0x00000800 11 ibias_socpll_1p8v 0x00001000 12 test_comp_out_bod_rvm 0x00002000 13 test_rlad_bod_rvm 0x00004000 14 crude_ref_lowv 0x00008000 15 all_supplies_ok_1p8v 0x00010000 16 vt_det_1p8v 0x00020000 17 test_out_dig_sup_mux 0x00040000 18 iref_bg_test_10u_1p8v 0x00080000 19 irefp_v2i_test_10u_1p8v 0x00100000 20 vdd_core_lowv 0x00200000 21 no-connect 0x00400000 22 no-connect 0x00800000 23 no-connect 0x01000000 24 no-connect 0x02000000 25 no-connect 0x04000000 26 gpadc_input_buf_lowv 0x08000000 27 irefp_v2i_test_10u_1p8v_mirrored 0x10000000 28 don't enable 0x20000000 29 no-connect 0x40000000 30 no-connect 0x80000000 31 no-connect			RW	0x0000 0000

:PRCM_AON:PMSSPAR0

Address offset	0x0000 7124
Description	PMS SPARE REG 0 HW connected to PMCIO
Type	RW

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	DIGLDO	DIGITAL LDO	RW	0x0000

:PRCM_AON:PMSSPAR1

Address offset	0x0000 7128
Description	PMS SPARE REG 1 HW connected to PMCIO
Type	RW

Bits	Field Name	Description	Type	Reset
31:24	DIGKA	DIGITAL KEEP ALIVE SPARE REGISTER	RW	0x00
23:16	Reserved		RO	0x00
15:8	DIGBG	DIGITAL BAND GAP SPARE REGISTER	RW	0x00
7:0	RCOSC	RCOSC SPARE REG	RW	0xC0

:PRCM_AON:PMSSPAR2

Address offset	0x0000 712C
Description	PMS SPARE REG 2 HW connected to PMCIO
Type	RW

Bits	Field Name	Description	Type	Reset
31:16	OUT	VALUE	RO	0x0000
15:0	VAL	VALUE [9:5] - dig ldo test mux control [4:0] - sram test mux control	RW	0x7E00

:PRCM_AON:PMSCTLSTA

Address offset	0x0000 7130
Description	PMS CONTROL STATUS PMS FSM cfg register
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	Reserved		RO	0x00 0000
7:0	STA	PMS STATE Following FSM controls PMU for mode transition from ACTIVE to HIBERNATE/LPDS and vice-versa Power Mode PMU sequence: (Go to sleep sequence example. Wakeup is reversed order) bit[0] - LDOs_KA (enable KA LDO's... - wait 1c) bit[1] - LDO_SRAM (disable SRAM LDO... - wait 1c) bit[2] - LDO_DIG (disable DIG LDO... - wait 1c) bit[3] - RVM_LPM (enable RVM Low Power Mode... - wait 1c) bit[4] - BG_CAP_SW (disable BandGap Cap switch... - wait 1c) bit[5] - BG (disable BandGap - wait 1c) localparam [7:0] PM_ACT = 8'b00_110110 , // ACTIVE - Steady State nr. 1 PM_GTS_LDO_KA_EN = 8'b00_110111 , PM_GTS_LDO_SRAM_DIS = 8'b00_110101 , PM_GTS_LDO_DIG_DIS = 8'b00_110001 , PM_GTS_RVM_LPM_EN = 8'b00_111001 , PM_GTS_BG_CAP_SW_DIS = 8'b00_101001 , PM_GTS_BG_DIS = 8'b00_001001 , PM_SLP = 8'b01_001001 , // SLEEP - Steady State nr. 2 (up to 20ms) PM_SLP_TO_RFRSH = 8'b01_101001 , PM_RFRSH = 8'b01_111001 , // Refresh - Steady State nr. 3 (up to 100us) PM_RFRSH_TO_SLP = 8'b10_101001 , PM_WKU_BG_EN = 8'b11_101001 , PM_WKU_BG_CAP_SW_EN = 8'b11_111001 , PM_WKU_RVM_LPM_DIS = 8'b11_110001 , PM_WKU_LDO_DIG_EN = 8'b11_110101 , PM_WKU_LDO_SRAM_EN = 8'b11_110111 , PM_WKU_LDO_KA_DIS = 8'b11_110110 ;	RO	0x36

:PRCM_AON:PMSSPARIN

Address offset	0x0000 7134
Description	PMS SPARE INPUT HW connected to PMCIO - spare input from PMCIO
Type	RW

Bits	Field Name	Description	Type	Reset
31:27	REG1	SPARE_REG1 bit map [15:11] bit <15>- in PMU: no usage. Should not be used. In PRCM: selects MMR control (S/W) mem_bod_comp_en/mem_rvml_comp_en/mem_rvmh_comp_en over the default control (H/W) for comparators BOD/RVML/RVMH enable respectively	RW	0x00
26	GEBM	SPARE_REG1 bit map [10]: used for VBOXLO test	RW	0
25:16	Reserved	SPARE_REG1 bit map [9:0]: [3:0] - pmcio_spare_bits_buf[3:0], set by writing to GPADC REGS MEM_GPADC_PMCIO_SPARE_RX/TX_1/2 [4] - host_elp_wdt_req, set by HOST ELP WDT elapsed [5] - debugss_debug_req, set by debugss reset request [6] - 1'b0 [7] - set by writing to mem_rst_wdt_cause_clr, clears reset cause [8] - set by writing to mem_rst_debugss_cause_clr, clears reset cause [9] - 1'b0	RO	0x000
15:0	REG0	REGISTER 0 <11> - '1' mask BOD and RVMs for 2 cycles in LPDS entry	RW	0x0000

:PRCM_AON:PMSPORTSTCTL

Address offset	0x0000 7138
Description	PMS POR TEST CONTROL Test Mode control for POR POL block
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	Reserved		RO	0x00 0000
7:0	VAL	HW connected to PMCIO	RW	0x00

:PRCM_AON:PMSSPAR3

Address offset	0x0000 7140
Description	PMS SPARE 3 HW connected to PMCIO
Type	RW

Bits	Field Name	Description	Type	Reset
31:24	Reserved		RO	0x01
23:17	SRAMKA	SRAM KEEP ALIVE	RW	0x79
16:6	Reserved	bit [16] is bit[0] of SRAMKA_SPARE port used as - fsm_prcm_ldo_wku_sram_ka_clamp	RO	0x3C8
5:2	INT	INTERNAL	RW	0x0
1:0	Reserved	bit [0] - por_comp_out_mask_en bit [1] - vtdet_comp_out_mask_en	RO	0x0

:PRCM_AON:PMSSPAR4

Address offset	0x0000 7144
Description	PMS SPARE 4 HW connected to PMCIO
Type	RW

Bits	Field Name	Description	Type	Reset
31:16	Reserved		RO	0x0000
15:0	PMBIST	[5:4] - rfcio test switch [3:2] - adc test switch [1] - vdd main divider enable [0] - i2v divider enable	RW	0x7E00

:PRCM_AON:PMSDLY

Address offset	0x0000 7148
Description	PMS DELAYS HW connected to PMCIO - spare input from PMCIO
Type	RW

Bits	Field Name	Description	Type	Reset
31:24	Reserved		RO	0x00
23:20	WU5	WAKEUP DELAY 5 delay from PM_WKU_LDO_SRAM_EN to PM_WKU_LDO_KA_DIS for additional details please review following page: https://confluence.itg.ti.com/pages/viewpage.action?spaceKey=WNG&title=Osprey+PRCM+-+PMU Also used as LDO inrush Limit timer: 0- inrush limit to LDO's will be set 1 slow clock cycle (32us) after DIG LDO has been set 1- inrush limit to LDO's will be set 2 slow clock cycles (64us) after DIG LDO has been set (default) 2- inrush limit to LDO's will be set 3 slow clock cycles (96us) after DIG LDO has been set ... 15- inrush limit to LDO's will be set 16 slow clock cycles (16*32us) after DIG LDO has been set Note that SRAM LDO is set 1-4 cycles (1 is default) before DIG LDO is set. Inrush Limit covers both.	RW	0x1
19:18	WU4	WAKEUP DELAY 4 delay from PM_WKU_LDO_DIG_EN to PM_WKU_LDO_SRAM_EN for additional details please review following page: https://confluence.itg.ti.com/pages/viewpage.action?spaceKey=WNG&title=Osprey+PRCM+-+PMU	RW	0x1
17:16	WU3	WAKEUP DELAY 3 delay from PM_WKU_RVM_LPM_DIS to PM_WKU_LDO_DIG_EN for additional details please review following page: https://confluence.itg.ti.com/pages/viewpage.action?spaceKey=WNG&title=Osprey+PRCM+-+PMU	RW	0x1
15:14	WU2	WAKEUP DELAY 2 delay from PM_WKU_BG_CAP_SW_EN to PM_WKU_RVM_LPM_DIS for additional details please review following page: https://confluence.itg.ti.com/pages/viewpage.action?spaceKey=WNG&title=Osprey+PRCM+-+PMU	RW	0x1
13:12	WU1	WAKEUP DELAY 1 delay from PM_WKU_BG_EN to PM_WKU_BG_CAP_SW_EN for additional details please review following page: https://confluence.itg.ti.com/pages/viewpage.action?spaceKey=WNG&title=Osprey+PRCM+-+PMU	RW	0x1
11:10	Reserved		RO	0x0
9:8	GTS5	GO TO SLEEP DELAY 5 delay from PM_GTS_BG_CAP_SW_DIS to PM_GTS_BG_DIS for additional details please review following page: https://confluence.itg.ti.com/pages/viewpage.action?spaceKey=WNG&title=Osprey+PRCM+-+PMU	RW	0x0
7:6	GTS4	GO TO SLEEP DELAY 4 delay from PM_GTS_RVM_LPM_EN to PM_GTS_BG_CAP_SW_DIS for additional details please review following page: https://confluence.itg.ti.com/pages/viewpage.action?spaceKey=WNG&title=Osprey+PRCM+-+PMU	RW	0x0
5:4	GTS3	GO TO SLEEP DELAY 3 delay from PM_GTS_LDO_DIG_DIS to PM_GTS_RVM_LPM_EN for additional details please review following page: https://confluence.itg.ti.com/pages/viewpage.action?spaceKey=WNG&title=Osprey+PRCM+-+PMU	RW	0x0
3:2	GTS2	GO TO SLEEP DELAY 2 delay from PM_GTS_LDO_SRAM_DIS to PM_GTS_LDO_DIG_DIS for additional details please review following page: https://confluence.itg.ti.com/pages/viewpage.action?spaceKey=WNG&title=Osprey+PRCM+-+PMU	RW	0x0
1:0	GTS1	GO TO SLEEP DELAY 1 delay from PM_GTS_LDO_KA_EN to PM_GTS_LDO_SRAM_DIS for additional details please review following page: https://confluence.itg.ti.com/pages/viewpage.action?spaceKey=WNG&title=Osprey+PRCM+-+PMU	RW	0x0

:PRCM_AON:BGDISBGENDLY

Address offset	0x0000 714C
Description	DIGITAL BANDGAP DISABLE BANDGAP ENABLE DELAY time (sclk) in DBGAP hibernate mode
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2:0	SLP	SLEEP The sleep duration between refresh intervals - from BG disable (Going to Sleep) to BG enable (waking for refresh). Granularity is 128 clocks (clock period is 31.25us) hence: "000" - N.A "001" - 4ms "010" - 8ms "011" - 12ms "100" - 16ms "101" - 20ms (default) "110" - 24ms "111" - 28ms	RW	0x5

:PRCM_AON:SWENSWDISDLY

Address offset	0x0000 7150
Description	SW ENABLE SW DISABLE DELAY time (sclk) in DBGAP hibernate mode
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2:0	SLP	SLEEP The Refresh duration - from Switch enable (go in refresh) to Switch disable (go out of refresh). Granularity is 1 clock (clock period is 31.25us) hence: "000" - 31.25us "001" - 62.5us "010" - 93.75us "011" - 125us (default) "100" - 156.25us "101" - 187.5us "110" - 218.75us "111" - 250us	RW	0x3

:PRCM_AON:BGENSWENDLY

Address offset	0x0000 7154
Description	BANDGAP ENABLE SW ENABLE SLEEP DELAY time (sclk) in DBGAP hibernate mode
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1:0	MEM_BGENSWENDLY_NSYNC	SLEEP The duration from BG enable to SW enable (transition to refresh). Granularity is 1 clock (clock period is 31.25us) hence: "000" - 31.25us "001" - 62.5us (default) "010" - 93.75us "011" - 125us "100" - 156.25us "101" - 187.5us "110" - 218.75us "111" - 250us	RW	0x1

:PRCM_AON:SWDISBGDISDLY

Address offset	0x0000 7158
Description	SW DISABLE BANDGAP DISABLE DELAY time (sclk) in DBGAP hibernate mode
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1:0	MEM_SWDISBGDISDLY_NSYNC	SLEEP The duration from SW disable to BG disable (transition from refresh). Granularity is 1 clock (clock period is 31.25us) hence: "000" - 31.25us "001" - 62.5us (default) "010" - 93.75us "011" - 125us "100" - 156.25us "101" - 187.5us "110" - 218.75us "111" - 250us	RW	0x1

:PRCM_AON:ICG CTL

Address offset	0x0000 715C
Description	ICG CONTROL
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3	SFSCLKREQ	SLOW FUSE CLK REQ '1' - request CLK for prcm fuse farm. default is '1'. S/W will clr to save power	RW	1
2	DBGSCLKREQ	'1' - request CLK for debugss	RW	1
1	OCLACLKREQ	'1' - request CLK for ocla	RW	1
0	COEXCLKREQ	'1' - request CLK for coex	RW	1

:PRCM_AON:HALT

Address offset	0x0000 7160
Description	HALT
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	DBGSEL	select debug halt source: 0 - M33 Halt 1 - M3 Halt	RW	0

:PRCM_AON:LOGICCA

Address offset	0x0000 716C
Description	LOGIC CAPTURE
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3	PGOOD1	read clear CORE PGOOD indication set	RO	1
2	PGOOD0	read clear CORE PGOOD indication fall	RO	0
1	PON1	read clear CORE PON indication set	RO	1
0	PON0	read clear CORE PON indication fall	RO	0

:PRCM_AON:LOGICMEMSTA

Address offset	0x0000 7170
Description	LOGIC MEMORY STATUS
Type	RW

Bits	Field Name	Description	Type	Reset
31	Reserved		RO	0
30	MEMSPWRUDNE	MEMORIES POWERUP DONE	RO	0
29	AAONISO	AAON ISO	RO	0
28	CRISO	CORE ISO	RO	1
27	AAONPONIN	AAON PONIN	RO	0
26	CRPONIN	CORE PONIN	RO	0
25:16	FLXAONIN	FLEX AONIN	RO	0x300
15:12	Reserved		RO	0x0
11:0	CRAONIN	CORE AONIN	RO	0x000

:PRCM_AON:HOL

Address offset	0x0000 7174
Description	HOLISTIC FSM
Type	RW

Bits	Field Name	Description	Type	Reset
31:5	Reserved		RO	0x000 0000
4:0	STA	STATE HOL_IDLE = 5'b00000 HOL_HW_BOOT1 = 5'b00001 HOL_HW_BOOT2 = 5'b00010 HOL_HW_BOOT3 = 5'b00011 HOL_ACTIVE2 = 5'b00100 (CORE & HOST active) HOL_ACTIVE3 = 5'b00101 (CORE sleep, HOST active) HOL_ACTIVE4 = 5'b00110 (CORE active, HOST sleep) HOL_TRN_TRUE_SLEEP1 = 5'b00111 HOL_TRN_TRUE_SLEEP2 = 5'b01000 HOL_TRN_TRUE_SLEEP3 = 5'b01001 HOL_TRUE_SLEEP = 5'b01010 (CORE & HOST sleep) HOL_PRCM_VLD_ACTIVE3 = 5'b01011 HOL_AAON_ACTIVE3 = 5'b01100 HOL_CORE_SLP_ACTIVE3 = 5'b01101 HOL_CORE_ACT_ACTIVE3 = 5'b01110 HOL_PRCM_VLD_ACTIVE4 = 5'b01111 HOL_AAON_ACTIVE4 = 5'b10000 HOL_HOST_SLP_ACTIVE4 = 5'b10001 HOL_HOST_ACT_ACTIVE4 = 5'b10010	RO	0x00

:PRCM_AON:PSCONHGEN

Address offset	0x0000 7178
Description	PSCON HANDLER GENERAL
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	LOGUGTEBP	LOGIC UNGATE BYPASS '1' - bypass the logic UNGATE request option '0' - logic will generate ungate request	RW	1
1:0	RTABHVEMOD	NU at MDB Determine the RTA behavior in sleep/true sleep: [0] - SLEEP MODE [1] - TRUE SLEEP MODE 0 - OFF/OFF : in case issues with RTA toggling in sleep 1 - OFF/ON : in case no ret in true sleep + in case issues with RTA toggling in sleep 2 - ON/OFF : POR 3 - ON/ON : In case use ret in true sleep	RW	0x0

:PRCM_AON:IOPROCSBIT

Address offset	0x0000 717C
Description	IO PROCESS BITS
Type	RW

Bits	Field Name	Description	Type	Reset
31:15	Reserved		RO	0x0 0000
14:12	FSPROGIOP	FUSE PROGIO P OVERRIDE PROGIO N Bit 2 is inverted between MMR and PAD -> so to configure the values 1,3,6 according to the corner, we need to set the registers to 5,7,2: MAX: MMR --> p=n=2 ; PAD --> p=n=6 NOM: MMR --> p=n=7 ; PAD --> p=n=3 MIN: MMR --> p=n=5 ; PAD --> p=n=1	RO	0x0
11	Reserved		RO	0
10:8	FSPROGION	FUSE PROGIO N OVERRIDE PROGIO N Bit 2 is inverted between MMR and PAD -> so to configure the values 1,3,6 according to the corner, we need to set the registers to 5,7,2: MAX: MMR --> p=n=2 ; PAD --> p=n=6 NOM: MMR --> p=n=7 ; PAD --> p=n=3 MIN: MMR --> p=n=5 ; PAD --> p=n=1	RO	0x0
7	SELOVPROGIOP	SELECT OVERRIDE PROGIO P process bit to io set	RW	0
6:4	OVPROGIOP	OVERRIDE PROGIO P OVERRIDE PROGIO N Bit 2 is inverted between MMR and PAD -> so to configure the values 1,3,6 according to the corner, we need to set the registers to 5,7,2: MAX: MMR --> p=n=2 ; PAD --> p=n=6 NOM: MMR --> p=n=7 ; PAD --> p=n=3 MIN: MMR --> p=n=5 ; PAD --> p=n=1	RW	0x0
3	SELOVPROGION	SELECT OVERRIDE PROIO N process bit to io set	RW	0
2:0	OVPROGION	OVERRIDE PROGIO N Bit 2 is inverted between MMR and PAD -> so to configure the values 1,3,6 according to the corner, we need to set the registers to 5,7,2: MAX: MMR --> p=n=2 ; PAD --> p=n=6 NOM: MMR --> p=n=7 ; PAD --> p=n=3 MIN: MMR --> p=n=5 ; PAD --> p=n=1	RW	0x0

:PRCM_AON:SCLKCNT_CTRL_CORE

Address offset	0x0000 7180
Description	SLOW CLOCK COUNT CONTROL CORE
Type	RW

Bits	Field Name	Description	Type	Reset
31:25	Reserved		RO	0x00
24	RESULT_VALID_CORE	RESULT VALID Determine whether the measurement is in progress or done: 0x0 - In progress (Relevant in one shot only) 0x1 - Done (when finish measurement and result ready)	RO	0
23:9	RESULT_CORE	Slow Clock counter result	RO	0x0000
8:2	PER	Determine the Slow clock counter period (Slow Clock cycles), 1 - 128. '0' - 1 CLK cycle '1' - 2 CLK cycles '2' - 3 CLK cycles ... '127' - 128 CLK cycles	RO	0x03
1:0	MOD	MODE Determine the Slow clock counter mode- 0x3 - Reserved 0x2 - Periodic 0x1 - One Shot 0x0 - Disable	RO	0x0

:PRCM_AON:STA_CORE

Address offset	0x0000 7184
Description	STATUS CORE
Type	RW

Bits	Field Name	Description	Type	Reset
31:7	Reserved		RO	0x000 0000
6	PLOCKMON	PLL SHARING LOCK MONITOR	RO	0
5	PLOCK	'1' - pll sharing pll lock	RO	0
4	RVML_STATUS	'1' - GOOD	RO	0
3	RVMH_STATUS	'1' - GOOD	RO	0
2	BOD_STATUS	'1' - GOOD	RO	0
1:0	FREQVAL_STATUS	fast clock frequency detection value : 0: 10MHz 1: 26MHz 2: 40MHz 3: 52MHz	RO	0x0

:PRCM_AON:AAONLOGCAPT

Address offset	0x0000 718C
Description	AAON LOGIC CAPTURE
Type	RW

Bits	Field Name	Description	Type	Reset
31:4	Reserved		RO	0x000 0000
3	PGOOD1	read clear AAON PGOOD indication set	RO	1
2	PGOOD0	read clear AAON PGOOD indication fall	RO	0
1	PON1	read clear AAON PON indication set	RO	1
0	PON0	read clear AAON PON indication fall	RO	0

:PRCM_AON:HWDT

Address offset	0x0000 7190
Description	HOST WATCH DOG TIMER
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	FSENOV	FUSE ENABLE OVERRIDE '1'- override fuse bit value (regular operation) '0'- use fuse bit value.	RW	0

:PRCM_AON:SCLKCNT_CORE

Address offset	0x0000 7194
Description	SLOW CLK COUNT CORE
Type	RW

Bits	Field Name	Description	Type	Reset
31:23	Reserved		RO	0x000
22:16	PERVAL_CORE	PERIOD VALUE slow CLK current value. bounds are 0 to slow_clk_counter_period	RO	0x00
15	Reserved		RO	0
14:0	DET_CORE	FAST CLK DETECTION COUNTER Counter results for 4 slow clock freq lower upper (MHz) (dec) (dec) 10 1190 1503 26 3094 3908 40 4760 6012 52 6188 7815	RO	0x0000

:PRCM_AON:SRAMLDO

Address offset	0x0000 7198
Description	SRAM LDO gen cfg register
Type	RW

Bits	Field Name	Description	Type	Reset
31:6	Reserved		RO	0x000 0000
5	MEM_SEL_PRCM_SRAMLDO_EN_INRUSH_LIMIT	SELECT ENABLE INRUSH LIMIT Select for S/W Enabling the Inrush Current Limit Mask	RW	0
4	MEM_PRCM_SRAMLDO_EN_INRUSH_LIMIT	Enable Inrush Current Limit Mask	RW	0
3	WKUINRSHLIM	WAKEUP INRUSH LIMIT status of final SRAM LDO enable	RO	0
2	MEM_SEL_OV_SRAMLDO_EN	SELECT OVERRIDE ENABLE 1: select override value for SRAM LDO enable : 0: SRAM LDO enable from FSM	RW	0
1	MEM_OV_SRAMLDO_EN	OVERRIDE ENABLE override value for SRAM LDO	RW	1
0	EN	ENABLE status of final SRAM LDO enable	RO	0

:PRCM_AON:DBG

Address offset	0x0000 719C
Description	DBG
Type	RW

Bits	Field Name	Description	Type	Reset
31:17	Reserved		RO	0x0000
16	SHADWSET	SHADOW SET '1' - override condition to load shadow values at FREF and PLLSH	RW	0
15:3	Reserved		RO	0x0000
2:0	MEM_DBGCLKSEL	CLOCK SELECT Debug and Fast CLK detection selector 'x00' - prcm_fast_clock. 'x01' - ospr_hsm_tst_fro_clk_out 'x10' - clk_gpadc_clk 'x11' - fref_2m_socpll_1p8v '100' - rf_pll_divided_clk	RW	0x0

:PRCM_AON:RSTOVCTL

Address offset	0x0000 71A0
Description	reset override control register, active low polarity: '0' - override reset (force reset line to 0, reset asserted, active low) '1' - don't override reset
Type	RW

Bits	Field Name	Description	Type	Reset
31:17	Reserved		RO	0x0000
16	AAON	AAON write clear '1' - request CLK for sdio AAON	WO	0
15	FREF	FREF write clear '1' - request CLK for FREF	WO	0
14	TSENSE	NOT USED write clear '1' - no reset	WO	0
13	GPADC	GPADC write clear '1' - request CLK for sdio GPADC	WO	0
12	FUSE	FUSE FARM write clear '1' - request CLK for sdio FUSEFARM	WO	0
11	MEMSS	MEMORY SUB SYSTEM write clear	WO	0
10	Reserved		RO	0
9	CRAON	CORE AON write clear '1' - request CLK for sdio CORE AON	WO	0
8	HOSTAON	HOSTAON write clear '1' - request CLK for sdio HOST AON	WO	0
7	TEST	NOT USED write clear	WO	0
6	Reserved		RO	0
5	OV_DBG_SS_RSTN_WRCL	DBGSS write clear '1' - request CLK for sdio DBGSS	WO	0
4	PRCMREGS	NOT USED write clear	WO	0
3	CR	CORE write clear '1' - request CLK for sdio CORE	WO	0
2	PSCON	'1' - request CLK for sdio PSCON write clear	WO	0
1	SDIOAO	NOT USED write clear '1' - request CLK for sdio ao	WO	0
0	SDIO	NOT USED write clear '1' - request CLK for sdio sw	WO	0

:PRCM_AON:PMURSTCLR

Address offset	0x0000 71A4
Description	PMU RESET CLEAR Level registers- need to set high and low to clear WDT or DBGSS indications. Set '1' to those fields will automated a pulse to pmu. clear this field to '0' after use.
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved	SPARE_REG1 bit map [9:0]: [3:0] - pmcio_spare_bits_buf[3:0], set by writing to GPADC REGS MEM_GPADC_PMCIO_SPARE_RX/TX_1/2 [4] - host_elp_wdt_req, set by HOST ELP WDT elapsed [5] - debugss_debug_req, set by debugss reset request [6] - 1'b0 [7] - set by writing to mem_rst_wdt_cause_clr, clears reset cause [8] - set by writing to mem_rst_debugss_cause_clr, clears reset cause [9] - 1'b0	RO	0x0000 0000
1	MEM_RST_DBGSS_CAUSE_CLR	PRCM SPARE REG 1 [8] - mem_rst_debugss_cause_clr '1' - clear debugss reset cause	RW	0
0	WDTCAUS	PRCM SPARE REG 1 [7] - mem_rst_wdt_cause_clr '1' - clear wdt reset cause	RW	0

:PRCM_AON:MEMGCTLCRSTAT1

Address offset	0x0000 71A8
Description	MEMORY GROUP CONTROL CORE STATIC 1 Bank power State When owner IP Active/Sleep (power domain is ON/OFF) 0 - OFF/OFF 1 - Reserved 2 - ON/OFF 3 - ON/RET
Type	RW

Bits	Field Name	Description	Type	Reset
31:24	Reserved		RO	0xFF
23:22	PWRSTA12	POWER STATE 12 Group 22	RW	0x3
21:20	PWRSTA11	POWER STATE 11 Group 21	RW	0x3
19:18	PWRSTA10	POWER STATE 10 Group 20	RW	0x3
17:16	PWRSTA9	POWER STATE 9 Group 19	RW	0x3
15:14	PWRSTA8	POWER STATE 8 Group 18	RW	0x3
13:12	PWRSTA7	POWER STATE 7 Group 17	RW	0x3
11:10	PWRSTA6	POWER STATE 6 Group 16	RW	0x3
9:8	PWRSTA5	POWER STATE 5 Group 15	RW	0x3
7:6	PWRSTA4	POWER STATE 4 Group 14	RW	0x3
5:4	PWRSTA3	POWER STATE 3 Group 13	RW	0x3
3:2	PWRSTA2	POWER STATE 2 Group 12	RW	0x3
1:0	PWRSTA1	POWER STATE 1 Group 11	RW	0x3

:PRCM_AON:MEMGCTLCRFLEX

Address offset	0x0000 71AC
Description	MEMORY GROUP CONTROL CORE FLEX Applicable only if MODE selected flex as CORE memory. Bank power State When owner IP Active/Sleep (power domain is ON/OFF) 0 - OFF/OFF 1 - Reserved 2 - ON/OFF 3 - ON/RET
Type	RW

Bits	Field Name	Description	Type	Reset
31:20	Reserved		RO	0x000
19:18	PWRSTA10	POWER STATE 10 Group 10	RW	0x3
17:16	PWRSTA9	POWER STATE 9 Group 9	RW	0x3
15:14	PWRSTA8	POWER STATE 8 Group 8	RW	0x3
13:12	PWRSTA7	POWER STATE 7 Group 7	RW	0x3
11:10	PWRSTA6	POWER STATE 6 Group 6	RW	0x3
9:8	PWRSTA5	POWER STATE 5 Group 5	RW	0x3
7:6	PWRSTA4	POWER STATE 4 Group 4	RW	0x3
5:4	PWRSTA3	POWER STATE 3 Group 3	RW	0x3
3:2	PWRSTA2	POWER STATE 2 Group 2	RW	0x3
1:0	PWRSTA1	POWER STATE 1 Group 1	RW	0x3

:PRCM_AON:CRSH

Address offset	0x0000 71B0
Description	CORE SHARED override values for PRCM SHARED Modules
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved		RO	0x0000 0000
2	PLLSHREQOV	PLL SHAREING REQUEST OVERRIDE '1' - keeps awake at sleep state '0' - regular operation note: in order to set this field as '1', FREF OV and PMS OV must be set as well.	RW	0
1	FREFREQOV	FREF REQUEST OVERRIDE '1' - keeps awake at sleep state '0' - regular operation note: in order to set this field as '1', PMS OV must be set as well.	RW	0
0	PMSREQOV	PMS REQUEST OVERRIDE '1' - keeps awake at sleep state '0' - regular operation	RW	0