HSM_NON

HSM_NON_SEC

This section provides information on the HSM_NON_SEC Module Instance within this product. Each of the registers within the Module Instance is described separately below.

HSM_NON_SEC Registers Mapping Summary

:HSM_NON_SEC Common Register Mapping Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset
CLK_MEM_CTRL	RW	32	0x0000 0000	0x0000 0000
PKA_ABORT_CTRL	RW	32	0x0000 0000	0x0000 0004
HSM_STA_REG	RO	32 (access width : 32 )	0x0000 0000	0x0000 0008
RAM_CLR_STA	RO	32 (access width : 32 )	0x0000 0000	0x0000 000C

HSM_NON_SEC Instances Register Mapping Summary

HSM_NON_SEC Register Descriptions

:HSM_NON_SEC Common Register Descriptions

:HSM_NON_SEC:CLK_MEM_CTRL

Address offset	0x0000 0000
Description	This register is used for enabling clock to the module
Type	RW

Bits	Field Name	Description		Type	Reset
31:9	Reserved	Reads to this field return zero, writes to this field are ignored.		RO	0x00 0000
8	CTR_CLK_BUSY	When 1b, indicates that the counter clock domain is active. This signal is always asserted (set to '1'), except when the counter module is in reset (ctr_reset_n set to '0').		RO	0
7	SLV_CLK_BUSY	When 1b indicates the Host interface is active and busy with Host bus transfers.		RO	0
6	CLK_BUSY	when 1b, indicates that the module is active and busy with processing data and tokens.		RO	0
5	MEM_CTR_CLK_GO_M3	Write this bit to enable counter clock		RW	0
		0	DIS Write 0b to disable clock
		1	EN Write 1b to enable clock
4	MEM_SLV_CLK_GO_M3	Write this bit to enable host interface clock		RW	0
		0	DIS Write 0b to disable clock
		1	EN Write 1b to enable clock
3	MEM_CLK_GO_M3	M3 writes this bit to enable clock to the module		RW	0
		0	DIS Write 0b to disable clock
		1	EN Write 1b to enable clock
2	MEM_CTR_CLK_GO	Write this bit to enable counter clock		RW	0
		0	DIS Write 0b to disable clock
		1	EN Write 1b to enable clock
1	MEM_SLV_CLK_GO	Write this bit to enable host interface clock		RW	0
		0	DIS Write 0b to disable clock
		1	EN Write 1b to enable clock
0	MEM_CLK_GO	Write this bit to enable clock to the module		RW	0
		0	DIS Write 0b to disable clock
		1	EN Write 1b to enable clock

:HSM_NON_SEC:PKA_ABORT_CTRL

Address offset	0x0000 0004
Description	This register is used for aborting PKA operation.
Type	RW

Bits	Field Name	Description		Type	Reset
31:1	Reserved	Reads to this field return zero, writes to this field are ignored.		RO	0x0000 0000
0	MEM_PKA_ABORT_NS	Write 1 to this bit to abort PKA operation		RW	0
		1	ABORT Set to 1, to abort PKA operation

:HSM_NON_SEC:HSM_STA_REG

Address offset	0x0000 0008
Description	This register provides EIP130 status
Type	RO

Bits	Field Name	Description	Type	Reset
31:4	Reserved	Reads to this field return zero, writes to this field are ignored.	RO	0x000 0000
3	POWER_MODE	Power mode value 1'b1 indicates hsm is in sleep and value 1'b0 indicates hsm is out of sleep.	RO	0
2	FATAL_ERROR	If active (set to 1b), EIP130 detected a fatal error and stops operation. fatal error can happen when CRC on firmware ROM fails or selftest fails.	RO	0
1	NON_FIPS_MODE	If active (set to 1b), EIP130 is in NON-FIPS mode	RO	0
0	FIPS_MODE	If active (set to 1b), EIP130 is in FIPS mode	RO	0

:HSM_NON_SEC:RAM_CLR_STA

Address offset	0x0000 000C
Description	This register stores status of asset clear indication.
Type	RO

Bits	Field Name	Description	Type	Reset
31:2	Reserved	Reads to this field return zero, writes to this field are ignored.	RO	0x0000 0000
1	DATARAM_CLR_DONE	If active (set to 1b), it indicates that auto clear of Dataram on reset release has been completed.	RO	0
0	OTP_CLR_DONE	If active (set to 1b), it indicates that auto clear of OTP on reset release has been completed.	RO	0