31:2

Reserved

RO

0x0000 0000

1

WRRCFG

WRR ARB POLICY RR:
0 - Fixed Priority
1 - Round Robin (Default)

RW

1

0

MEM_ARBCTL

0 - Disabled, use SIE-200 arbitration logic.
1 - Enable, use wrapper arbitration logic.

RW

1

31:2

Reserved

RO

0x0000 0000

1

STS

1: Arbiter curently halted

RO

0

0

EN

EN ARBITER HALT.
0: Arbiter transmiting data/ disable halt
1: Arbiter will stop transmiting data

RW

0

31:29

Reserved

RO

0x0

28:24

TRANSDLY

Number of cycle before starting to serve next agent in line.
Up to 32 cycles.

RW

0x04

23:18

Reserved

RO

0x00

17:16

FIXPRI

For Fixed Priority:
0 - Highest.
1 - Medium.
2 - Lowest (default).

RW

0x1

15:13

Reserved

RO

0x0

12:0

NUMWORDS

Number of words to be served in each arbitration grant.
Up to 8,192 words (32KB).
Value must be > 0.

RW

0x0010

31:29

Reserved

RO

0x0

28:24

TRANSDLY

Number of cycle before starting to serve next agent in line.
Up to 32 cycles.

RW

0x00

23:18

Reserved

RO

0x00

17:16

FIXPRI

For Fixed Priority:
0 - Highest.
1 - Medium (default).
2 - Lowest.

RW

0x2

15:13

Reserved

RO

0x0

12:0

NUMWORDS

Number of words to be served in each arbitration grant.
Up to 8,192 words (32KB).
Value must be atleast 1. 0(Zero) is not allowed.

RW

0x0001

31:29

Reserved

RO

0x0

28:24

TRANSDLY

Number of cycle before starting to serve next agent in line.
Up to 32 cycles.

RW

0x04

23:18

Reserved

RO

0x00

17:16

FIXPRI

For Fixed Priority:
0 - Highest (default).
1 - Medium.
2 - Lowest.

RW

0x0

15:13

Reserved

RO

0x0

12:0

NUMWORDS

Number of words to be served in each arbitration grant.
Up to 8,192 words (32KB).
Value must be > 0.

RW

0x0004

31:2

RESERVED2

RO

0x0000 0000

1:0

DEVSWCHDLY

This field configures the extra delay added before the device switch

RW

0x1

31:3

Reserved

RO

0x0000 0000

2

OSPIREF

OSPI REF CLK SW DISABLE:
1 - Clock is permanent blocked (not depended on clk_req input)
0 - (default) - Clock is not blocked, but gated with clk_req input port

RW

0

1

SOC

SOC CLK SW DISABLE:
1 - Clock is permanent blocked (not depended on clk_req input)
0 - (default) - Clock is not blocked, but gated with clk_req input port

RW

0

0

HOSTXIP

HOST_XIP CLK SW DISABLE:
1 - Clock is permanent blocked (not depended on clk_req input)
0 - (default) - Clock is not blocked, but gated with clk_req input port

RW

0

31:3

Reserved

RO

0x0000 0000

2

OSPIREF

OSPI REF CLK SW FORCE:
1 - Force clk (even if sw_disable_clk is 1 or clk_req is 0)
0 - Clock is not forced, but gated with clk_req input port

RW

0

1

SOC

SOC CLK SW FORCE:
1 - Force clk (even if sw_disable_clk is 1 or clk_req is 0)
0 - Clock is not forced, but gated with clk_req input port

RW

0

0

HOSTXIP

HOST_XIP CLK SW FORCE:
1 - Force clk (even if sw_disable_clk is 1 or clk_req is 0)
0 - Clock is not forced, but gated with clk_req input port

RW

0

31:3

Reserved

RO

0x0000 0000

2

OSPIREF

1 - Force clk (even if sw_disable_clk is 1 or clk_req is 0)
0 - Clock is not forced, but gated with clk_req input port

RO

0

1

SOC

1 - Force clk (even if sw_disable_clk is 1 or clk_req is 0)
0 - Clock is not forced, but gated with clk_req input port

RO

0

0

HOSTXIP

1 - Force clk (even if sw_disable_clk is 1 or clk_req is 0)
0 - Clock is not forced, but gated with clk_req input port

RO

0

31:2

RESERVED2

RO

0x0000 0000

1

GLTFIXEN

Field to enable the *OSPI* glitch fix

RW

1

0

HLDFIXEN

HOLD FIX ENABLE
Field to enable the *OSPI* hold fix

RW

1

31:0

JSRCADDR

DMA SEC JOB SRC ADDR:
Specifies source address for secured read master.
Source address must comply with bit.26 to enable Sec/Non-Sec accesses, otherwise transactions will be blocked.

RW

0x0000 0000

31:0

JDESTADDR

DMA SEC JOB DST ADDR:
Specifies destination address for secured write master.
Destination address must comply with bit.26 to enable Sec/Non-Sec accesses, otherwise transactions will be blocked.

RW

0x0000 0000

31:18

Reserved

RO

0x0000

17:0

JLEN

DMA SEC JOB LENGTH:
Resolution - 32 bits/4 bytes
Maximum configurable job size - 1 Mega byte (256K Words).
(Maximum available size in MEMSS is 1MB).

RW

0x0 0000

31:2

Reserved

RO

0x0000 0000

1

SMODE

Secure channel mode
0: Memory Mode
1: Peripheral Mode

RW

0

0

JDIR

DMA SEC JOB MODE:
0 - Data movement from External memory to Internal memory/Peripheral
1 - Data movement from Internal memory/Peripheral to External memory.

RW

0

31:1

Reserved

RO

0x0000 0000

0

JSTART

DMA SEC JOB START WRCL:
Start command for uDMA to start working on secured configured job.

WO

0

31:1

Reserved

RO

0x0000 0000

0

JCLR

DMA SEC JOB CLEAR WRCL:
Clear command for uDMA to stop working and clear configuration.

WO

0

31:28

RESERVED28

RO

0x0

27:8

RDWRDSLFT

DMA SEC JOB READ WORDS LEFT:
number of read words left in sec job.
Note: This value would be updated on a read to this register. [UDSSTA1.WRWRDSLFT] is updated on a read to this register
This register value shows number of words in 32 bit when field [UDSCFG3.JDIR] is configured '0' else shows number of words in 8/16/32 bit based on the configuration of [UDSCFG3.SMODE] and [UDPERCFG.SWORDSZ] fields

RO

0x0 0000

7:5

Reserved

RO

0x0

4

JINPROG

DMA SEC JOB IN PROGRESS:
1- sec job is currently in progress and being executed by uDMA

RO

0

3:1

Reserved

RO

0x0

0

JSTA

DMA SEC JOB ACTIVE:
Status bit to indicate that DMA is processing a secured job.
When this bit is set, SW has written all the job parameters and also provided a start_pulse to HW,
and cannot change job parameters without clear_pulse.
Job will wait to be executed (indicated by job_in_progress)

RO

0

31:3

Reserved

RO

0x0000 0000

2

JIRQBEDIR

Bus Error direction
0: Source bus
1: Destination bus
Note: Source and destination is determined based on [UDSCFG3.JDIR] configuration

RO

0

1:0

JIRQSTA

Status vector for IRQ indication for secured DMA IRQ:
2'd0 - DMA done.
2'd1 - DMA Internal bus error occurred. check SEC_STATUS in order to recovers

RO

0x0

31:28

RESERVED28

RO

0x0

27:8

WRWRDSLFT

DMA SEC JOB WRITE WORDS LEFT:
Number of write words left in sec job.
Note: This value would be updated only on a read to [UDSSTA] register.
This register value shows number of words in 32 bit when field [UDSCFG3.JDIR] is configured '1' else shows number of words in 8/16/32 bit based on the configuration of [UDSCFG3.SMODE] and [UDPERCFG.SWORDSZ] fields

RO

0x0 0000

7:0

WRDOFST

DMA SEC PERIPH WORD OFFSET:
Number of words left in a peripheral block.
Note: This value would be updated only on a read to [UDSSTA] register.
This register value shows number of words in 8/16/32 bit based on the configuration of [UDSCFG3.SMODE] and [UDPERCFG.SWORDSZ] fields

RO

0x00

31:9

RESERVED9

RO

0x00 0000

8

SENCLRSRT

Enable uDMA to set a rd/wr clear pulse at the beginning of a job

RW

0

7:2

SPERBLKSZ

Secure channel peripheral block size(in 32bits/4bytes)
Multiplication of Word size
Upto 64 words based on the word size selected
Block = block_size * word_size

RW

0x00

1:0

SPERWDSZ

Secure channel peripheral job word size
8/16/32 (Word Size of 1/2/4 bytes)
Sel_0 - 32 bit
Sel_1 - 16 bit
Sel_2 - 8 bit

RW

0x0

31:4

RESERVED4

RO

0x000 0000

3:0

SPERSEL

Select the peripheral to serve job. This field along with [UDMA_SEC_MODE.SMODE] selects the peripheral to the channel
0x0 UART0
0x1 UART1
0x2 SPI0
0x3 SPI1
0x4 I2C0
0x5 I2C1
0x6 SDMMC
0x7 SDIO
0x8 MCAN
0x9 ADC
0xA PDM
0xB HIF

RW

0x0

31:4

RESERVED4

RO

0x000 0000

3:0

NSPERSEL

Select the peripheral to serve job. This field along with [UDMA_NONSEC_MODE.NSMODE] selects the peripheral to the channel
0x0 UART0
0x1 UART1
0x2 SPI0
0x3 SPI1
0x4 I2C0
0x5 I2C1
0x6 SDMMC
0x7 SDIO
0x8 MCAN
0x9 ADC
0xA PDM
0xB HIF

RW

0x0

31:0

JSRCADDR

DMA NONSEC JOB SRC ADDR:
Specifies source address for non-secured read master.
Source address must comply with bit.26 to enable Sec/Non-Sec accesses, otherwise transactions will be blocked.
In case using SAU to define secured memory region 'inside' the non-secured, this channel will allow this.

RW

0x0000 0000

31:0

JDESTADDR

DMA NONSEC JOB DST ADDR:
Specifies destination address for non-secured write master.
Destination address must comply with bit.26 to enable Sec/Non-Sec accesses, otherwise transactions will be blocked.
In case using SAU to define secured memory region 'inside' the non-secured, this channel will allow this.

RW

0x0000 0000

31:18

Reserved

RO

0x0000

17:0

JLEN

DMA NONSEC JOB LENGTH:
Resolution - 32 bits/4bytes
Maximum configurable job size - 1 Mega byte (256K Words).
(Maximum available size in MEMSS is 1MB).

RW

0x0 0000

31:2

Reserved

RO

0x0000 0000

1

NSMODE

Non secure channel mode
0: Memory Mode
1: Peripheral Mode

RW

0

0

JDIR

DMA NONSEC JOB MODE:
0 - Data movement from External memory to Internal memory.
1 - Data movement from Internal memory to External memory.

RW

0

31:1

Reserved

RO

0x0000 0000

0

JSTART

DMA NONSEC JOB START WRCL:
Start command for uDMA to start working on non-secured configured job.

WO

0

31:1

Reserved

RO

0x0000 0000

0

JCLR

DMA NONSEC JOB CLEAR WRCL:
Clear command for uDMA to stop working and clear configuration.

WO

0

31:28

RESERVED28

RO

0x0

27:8

RDWRDSLFT

DMA NONSEC JOB READ WORDS LEFT:
Number of read words left in nonsec job
Note: This value would be updated on a read to this register. [UDNSSTA1.WRWRDSLFT] is updated on a read to this register
This register value shows number of words in 32 bit when field [UDNSCFG3.JDIR] is configured '0' else shows number of words in 8/16/32 bit based on the configuration of [UDNSCFG3.NSMODE] and [UDPERCFG.NSWORDSZ] fields

RO

0x0 0000

7:5

Reserved

RO

0x0

4

JINPROG

DMA NONSEC JOB IN PROGRESS:
1- nonsec job is currently in progress and being executed by uDMA

RO

0

3:1

Reserved

RO

0x0

0

JSTA

DMA NONSEC JOB ACTIVE:
Status bit to indicate that DMA is processing a non-secured job.
When this bit is set, SW has written all the job parameters and also provided a start_pulse to HW,
and cannot change job parameters without clear_pulse.
Job will wait to be executed (indicated by job_in_progress)

RO

0

31:3

Reserved

RO

0x0000 0000

2

JIRQBEDIR

Bus Error direction
0: Source bus
1: Destination bus
Note: Source and destination is determined based on [UDNSCFG3.JDIR] configuration

RO

0

1:0

JIRQSTA

Status vector for IRQ indication for non-secured DMA IRQ:
2'd0 - DMA done.
2'd1 - DMA bus error occurred. check NONSEC_STATUS in order to recovers

RO

0x0

31:7

Reserved

RO

0x000 0001

6:5

BURSTVAL

FIFO WRITE BURST LEN:
After uDMA will reached the threshold, uDMA will sent the data in blocks.
0x0 : block size = 4 word
0x1 : block size = 8 word
0x2 : block size = 16 word
0x3 : block size = 32 word

RW

0x0

4:0

THRVAL

FIFO WRITE THRESHOLD:
In case of write to ext mem, uDMA will reach the threshold and after that will send the data to the ext mem
Note: 0(Zero) is not allowed

RW

0x10

31:28

RESERVED28

RO

0x0

27:8

WRDOFST

DMA NONSEC JOB WRITE WORDS LEFT:
Number of write words left in nonsec job.
Note: This value would be updated only on a read to [UDNSSTA] register.
This register value shows number of words in 32 bit when field [UDNSCFG3.JDIR] is configured '1' else shows number of words in 8/16/32 bit based on the configuration of [UDNSCFG3.NSMODE] and [UDPERCFG.NSWORDSZ] fields

RO

0x0 0000

7:0

WRWRDSLFT

DMA NONSEC PERIPH WORD OFFSET:
Number of words left in a peripheral block.
Note: This value would be updated only on a read to [UDNSSTA] register.
This register value shows number of words in 8/16/32 bit based on the configuration of [UDNSCFG3.NSMODE] and [UDPERCFG.NSWORDSZ] fields

RO

0x00

31:9

RESERVED9

RO

0x00 0000

8

NSENCLRSRT

Enable uDMA to set a rd/wr clear pulse at the beginning of a job

RW

0

7:2

NSPERBLSZ

Non-secure channel peripheral job block size(in 32bits/4bytes)
Multiplication of Word size.
Upto 64 words based on Word size
Block = block_size * word_size

RW

0x00

1:0

NSPERWDSZ

Non-secure channel peripheral job word size
8/16/32 (Word Size of 1/2/4 bytes)
Sel_0 - 32 bit
Sel_1 - 16 bit
Sel_2 - 8 bit

RW

0x0

31:0

OTOSMEM_81FC_WRMEMP

OTFDE CFG OSPI 81FC WR MEM
xSPI config Memory wr/rd access (under OTFDE module)

RW

0x0000 0000

31:18

Reserved

RO

0x0000

17

R3ENCBPASS

OTFDE REGION 3 ENC DEC BYPASS:
Encrypt Decrypt or Bypass transactions for region 3
0- Enable bypass and no enc dec
1- Disable bypass and use enc dec

RW

0

16

R3WRLOCK

OTFDE REGION 3 WRITE LOCK EN:
Locks the ability to write into Region 3 registers
0- Lock Disabled
1- Lock Enabled

RW

0

15:14

Reserved

RO

0x0

13

R2ENCBPASS

OTFDE REGION 2 ENC DEC BYPASS:
Encrypt Decrypt or Bypass transactions for region 2
0- Enable bypass and no enc dec
1- Disable bypass and use enc dec

RW

0

12

R2WRLOCK

OTFDE REGION 2 WRITE LOCK EN:
Locks the ability to write into Region 2 registers
0- Lock Disabled
1- Lock Enabled

RW

0

11:10

Reserved

RO

0x0

9

R1ENCBPASS

OTFDE REGION 1 ENC DEC BYPASS:
Encrypt Decrypt or Bypass transactions for region 1
0- Enable bypass and no enc dec
1- Disable bypass and use enc dec

RW

0

8

R1WRLOCK

OTFDE REGION 1 WRITE LOCK EN:
Locks the ability to write into Region 1 registers
0- Lock Disabled
1- Lock Enabled

RW

0

7:6

Reserved

RO

0x0

5

R0ENCBPASS

OTFDE REGION 0 ENC DEC BYPASS:
Encrypt Decrypt or Bypass transactions for region 0
0- Enable bypass and no enc dec
1- Disable bypass and use enc dec

RW

0

4

R0WRLOCK

OTFDE REGION 0 WRITE LOCK EN:
Locks the ability to write into Region 0 registers
0- Lock Disabled
1- Lock Enabled

RW

0

3:0

INITDLY

OTFDE INITIAL DELAY:
0-15 160MHz cycles of initial delay of the first transaction of a task
must configure value greater than 10 (0xa)

RW

0xA

31:0

KEY0

AES encryption Key LSBs

RW

0x0000 0000

31:0

KEY1

AES encryption Key

RW

0x0000 0000

31:0

KEY2

AES encryption Key

RW

0x0000 0000

31:0

KEY3

AES encryption Key MSBs

RW

0x0000 0000

31:0

NONCE0

Nonce (IV)

RW

0x0000 0000

31:0

NONCE1

Nonce (IV)

RW

0x0000 0000

31:0

KEY0

AES encryption Key LSBs

RW

0x0000 0000

31:0

KEY1

AES encryption Key

RW

0x0000 0000

31:0

KEY2

AES encryption Key

RW

0x0000 0000

31:0

KEY3

AES encryption Key MSBs

RW

0x0000 0000

31:0

NONCE0

Nonce (IV)

RW

0x0000 0000

31:0

NONCE1

Nonce (IV)

RW

0x0000 0000

31:0

KEY0

AES encryption Key LSBs

RW

0x0000 0000

31:0

KEY1

AES encryption Key

RW

0x0000 0000

31:0

KEY2

AES encryption Key

RW

0x0000 0000

31:0

KEY3

AES encryption Key MSBs

RW

0x0000 0000

31:0

NONCE0

Nonce (IV)

RW

0x0000 0000

31:0

NONCE1

Nonce (IV)

RW

0x0000 0000

31:0

KEY0

AES encryption Key LSBs

RW

0x0000 0000

31:0

KEY1

AES encryption Key

RW

0x0000 0000

31:0

KEY2

AES encryption Key

RW

0x0000 0000

31:0

KEY3

AES encryption Key MSBs

RW

0x0000 0000

31:0

NONCE0

Nonce (IV)

RW

0x0000 0000

31:0

NONCE1

Nonce (IV)

RW

0x0000 0000

31:1

Reserved

RO

0x0000 0000

0

ENREQ

OTFDE SW ENABLE REQ WRCL:
Pulse signaled by SW to enable OTFDE and start handling incoming tasks

WO

0

31:1

Reserved

RO

0x0000 0000

0

DISREQ

OTFDE SW DISABLE REQ WRCL:
Pulse signaled by SW to disable OTFDE and stop handling incoming task
and erase all task related data

WO

0

31:1

Reserved

RO

0x0000 0000

0

SUSPENDREQ

OTFDE SW SUSPEND TASK REQ WRCL:
Pulse signaled by SW to suspend OTFDE task and hold task related data

WO

0

31:1

Reserved

RO

0x0000 0000

0

RESUMEREQ

OTFDE SW RESUME TASK REQ WRCL:
Pulse signaled by SW to resume OTFDE suspended task

WO

0

31:1

Reserved

RO

0x0000 0000

0

RSTREQ

OTFDE SW SOFT RESET REQ WRCL:
1- Soft Reset request pulse

WO

0

31:9

Reserved

RO

0x00 0000

8

OTFDENBUSY

OTFDE IS NOT BUSY.
This bit set when OTFDE NOT in the middle of configuration or transmitting data.
OTFDE can be halted only when this bit is set.

RO

1

7:6

ACTIVESTA_TASK_REGION

OTFDE ACTIVE TASK REGION:
0- Region 0 active task
1- Region 1 active task
2- Region 2 active task
3- Region 3 active task
value is valid only if ACTIVESTA or TASKSUS are set

RO

0x0

5

ACTIVESTA_TASK_DEVICE

OTFDE ACTIVE TASK DEVICE:
0- Device 0 active task
1- Device 1 active task
value is valid only if ACTIVESTA or TASKSUS are set

RO

0

4

ACTIVESTA_TASK_TYPE

OTFDE ACTIVE TASK TYPE:
0- Active read task
1- Active write task
value is valid only if ACTIVESTA or TASKSUS are set

RO

0

3

ACTIVESTA_TASK_VALID

OTFDE ACTIVE TASK VALID:
0- No task is being handled,
1- A task is being handled,
note: decide if OTFDE is active or suspended using ACTIVESTA and TASKSUS

RO

0

2

EXTMUX

OTFDE SELECT EXTERNAL MUX:
0- External Muxes bypassing OTFDE allowing System/ SW access to xspi
1- External Muxes are controlled by OTFDE which is Active and has access to xspi

RO

0

1

TASKSUS

OTFDE TASK SUSPENDED
1- OTFDE is in task suspended mode
0- OTFDE is either active or disabled (IF ACTIVESTA is also de-asserted then OTFDE is disabled)

RO

0

0

ACTIVESTA

OTFDE ACTIVE:
0- OTFDE is disabled IF TASKSUS is also de-asserted
1- OTFDE is active

RO

0

31:17

Reserved

RO

0x0000

16

SUSPENDDIS

OTFDE SW SUSPEND REQ WHILE DISABLED RDCL:
0 - Disable
1- Set Indication
indication that SW requested suspend while OTFDE is disabled

RO

0

15

REGDIRERR

OTFDE REGION READ WRITE DEF VIOLATION RDCL:
0 - Disable
1- Set Indication
Indication that a transaction type was not allowed according to region definitions

RO

0

14

BURNOALGN

OTFDE TRANS BURST NOT 32 BIT VIOLATION RDCL:
0 - Disable
1- Set Indication
Indication that a transaction burst was not non-seq

RO

0

13

SIZENOALGN

OTFDE TRANS SIZE NOT 32 BIT VIOLATION RDCL:
0 - Disable
1- Set Indication
Indication that a transaction size was not 32 bit

RO

0

12

ADDRNOALGN

OTFDE TRANS ADDRESS NOT 32 BIT VIOLATION RDCL:
0 - Disable
1- Set Indication
Indication that a transaction address was not 32 bit aligned

RO

0

11

REGMAPERR

OTFDE TRANS MULTIPLE REGIONS MAPPED ERROR RDCL:
0 - Disable
1- Set Indication
Indication that a transaction was mapped into more than one region

RO

0

10

POLLITREXP

OTFDE TRANS XSPI POLLING ITR EXPIRED RDCL:
0 - Disable
1- Set Indication
Polling Request iterations expired

RO

0

9

REGDISERR

OTFDE TRANS REGION DISABLED ERROR RDCL:
0 - Disable
1- Set Indication
indication that the current transaction is into a disabled region

RO

0

8

DEVDISERR

OTFDE TRANS DEVICE DISABLED ERROR RDCL:
0 - Disable
1- Set Indication
indication that the current transaction is into a disabled device

RO

0

7

XSPIINT

OTFDE XSPI SERVICE INTERRUPT INDICATION RDCL:
0 - Disable
1- Set Indication
indication that service interruption criteria was triggered

RO

0

6

XSPICFGERR

OTFDE XSPI CNFG PATH ERROR RDCL:
0 - Disable
1- Set Indication
xSPI error on the config path to OTFDE

RO

0

5

DATPATHERR

OTFDE XSPI DATA PATH ERROR_RDCL:
0 - Disable
1- Set Indication
xSPI error on the data path to OTFDE

RO

0

4

GENERALERR

OTFDE GENERAL ERROR RDCL:
0 - Disable
1- Set Indication
General error event indication

RO

0

3

Reserved

0 - Disable
1- Set Indication
OTFDE entered or exited debug mode

RO

0

2

BYPASSEV

OTFDE BYPASS MODE CHANGE EVENT RDCL:
0 - Disable
1- Set Indication
OTFDE entered or exited bypass mode between suspend and resume states

RO

0

1

SWRSTEV

OTFDE SOFT RESET EVENT RDCL:
0 - Disable
1- Set Indication
OTFDE Soft reset completion event indication

RO

0

0

RSTEV

OTFDE RESET EVENT RDCL:
0 - Disable
1- Set Indication
OTFDE Hard reset or Disable request completion event indication

RO

0

31:17

Reserved

RO

0x0000

16

SUSPENDDIS

OTFDE SUSPEND WHILE DISABLED MASK:
0- Masked
1- Enabled
Enable / Mask SW requested suspend while OTFDE is disabled indication

RW

1

15

REGDIRERR

OTFDE REGION READ WRITE DEF MASK:
0- Masked
1- Enabled
Enable / Mask transaction type was not allowed according to region definitions

RW

1

14

BURNOALGN

OTFDE TRANS BURST NOT 32 BIT MASK:
0- Masked
1- Enabled
Enable / Mask transaction burst was not non-seq indication

RW

1

13

SIZENOALGN

OTFDE TRANS SIZE NOT 32 BIT MASK:
0- Masked
1- Enabled
Enable / Mask transaction size was not 32 bit indication

RW

1

12

ADDRNOALGN

OTFDE TRANS ADDRESS NOT 32 BIT MASK:
0- Masked
1- Enabled
Enable / Mask transaction address was not 32 bit aligned indication

RW

1

11

REGMAPERR

OTFDE TRANS MULTIPLE REGIONS MAPPED MASK:
0- Masked
1- Enabled
Enable / Mask transaction was mapped into more than one region indication

RW

1

10

POLLITREXP

OTFDE XSPI POLLING ITR EXPIRED MASK:
0- Masked
1- Enabled
Polling requests iterations expired

RW

1

9

REGDISERR

OTFDE TRANS REGION DISABLED MASK:
0- Masked
1- Enabled
Enable / Mask transaction into a disabled region event indication

RW

1

8

DEVDISERR

OTFDE TRANS DEVICE DISABLED MASK:
0- Masked
1- Enabled
Enable / Mask transaction into a disabled device event indication

RW

1

7

XSPIINT

OTFDE XSPI SERVICE INTERRUPT MASK:
0- Masked
1- Enabled
Enable / Mask xSPI service interrupt criteria event indication

RW

1

6

XSPICFGERR

0- Masked
1- Enabled
Enable / Mask xSPI config path related errors signaled to OTFDE

RW

1

5

DATPATHERR

OTFDE XSPI DATA PATH MASK:
0- Masked
1- Enabled
Enable / Mask xSPI data path related errors signaled to OTFDE

RW

1

4

GENERALERR

OTFDE GENERAL MASK:
0- Masked
1- Enabled
Enable / Mask general error event

RW

1

3

Reserved

0- Masked
1- Enabled
Enable / Mask debug mode change completion

RO

1

2

BYPASSEV

OTFDE BYPASS MODE CHANGE MASK:
0- Masked
1- Enabled
Enable / Mask bypass mode change between suspend and resume completion event

RW

1

1

SWRSTEV

OTFDE SOFT RESET MASK:
0- Masked
1- Enabled
Enable / Mask soft reset completion event

RW

1

0

RSTEV

OTFDE RESET MASK:
0- Masked
1- Enabled
Enable / Mask hard reset completion event

RW

1

31:17

Reserved

RO

0x0000

16

SUSPENDDIS

OTFDE SUSPEND WHILE DISABLED NS:
0- Disable
1- N/A
Decision of next state for SW requested suspend while OTFDE is disabled

RW

0

15

REGDIRERR

OTFDE REGION READ WRITE VIOLATION NS:
0- Disable
1- Active Idle
Decision of next state for transaction type was not allowed according to region definitions

RW

1

14

BURNOALGN

OTFDE TRANS BURST NOT 32 BIT NS:
0- Disable
1- Active Idle
Decision of next state for transaction burst was not non-seq indication

RW

1

13

SIZENOALGN

OTFDE TRANS SIZE NOT 32 BIT NS:
0- Disable
1- Active Idle
Decision of next state for transaction size was not 32 bit indication

RW

1

12

ADDRNOALGN

OTFDE TRANS ADDRESS NOT 32 BIT NS:
0- Disable
1- Active Idle
Decision of next state for transaction address was not 32 bit aligned indication

RW

1

11

REGMAPERR

OTFDE TRANS MULTIPLE REGIONS MAPPED NS:
0- Disable
1- N/A
Decision of next state for transaction was mapped into more than one region

RW

0

10

Reserved

0- Disable
1- N/A
Decision of next state for General region configuration error event indication

RO

0

9

REGDISERR

OTFDE TRANS REGION DISABLED NS:
0- Disable
1- Active Idle
Decision of next state for transaction into a disabled region event indication

RW

1

8

DEVDISERR

OTFDE TRANS DEVICE DISABLED NS:
0- Disable
1- Active Idle
Decision of next state for transaction into a disabled device event indication

RW

1

7

XSPISERINT

XSPI SERVICE INTERRUPT

RW

1

6

XSPICFGERR

OTFDE XSPI CNFG PATH ERROR NS:
0- Disable
1- Active Idle
Decision of next state for xSPI config path related errors signaled to OTFDE

RW

1

5

DATPATHERR

OTFDE XSPI DATA PATH ERROR NS:
0- Disable
1- Active Idle
Decision of next state for xSPI data path related errors signaled to OTFDE

RW

1

4

GENERALERR

OTFDE GENERAL ERROR NS:
0- Disable
1- Active Idle
Decision of next state for general error event

RW

1

3

Reserved

0- Disable
1- Active Idle
Decision of next state for debug mode change completion

RO

1

2

BYPMDCH

BYPASS MODE CHANGE
Used in ECO for PG1.
Problem Statement
In DDR 80MHz mode RD cmd, Seen in QPI (Octal not yet checked) the xSPI IP stop driving the data to soon violating Ext Mem hold requirement (~0.5ns v. up to ~2-3ns requirement for most vendors)
Suggested Fix
extend IO data drive by additional logic at IP for read commands in the DDR 80MHz mode

RW

0

1

SWRSTEV

OTFDE SOFT RESET NS:
0- Disable
1- Active Idle
Decision of next state for soft reset completion event

RW

1

0

RSTNS

RESET NON SECURED

RW

0

31:16

Reserved

RO

0x0000

15

DEV1JOB7

Used when the access address does not match any region
0- Reject not mapped address access
1- Bypass not mapped address access (address is forwarded as is to xspi)

RW

0

14

DEV1JOB6

Used when the access address does not match any region
0- Reject not mapped address access
1- Bypass not mapped address access (address is forwarded as is to xspi)

RW

0

13

DEV1JOB5

Used when the access address does not match any region
0- Reject not mapped address access
1- Bypass not mapped address access (address is forwarded as is to xspi)

RW

0

12

DEV1JOB4

Used when the access address does not match any region
0- Reject not mapped address access
1- Bypass not mapped address access (address is forwarded as is to xspi)

RW

0

11:9

Reserved

RO

0x0

8

DEV1JOB0

Used when the access address does not match any region
0- Reject not mapped address access
1- Bypass not mapped address access (address is forwarded as is to xspi)

RW

0

7

DEV0JOB7

Used when the access address does not match any region
0- Reject not mapped address access
1- Bypass not mapped address access (address is forwarded as is to xspi)

RW

0

6

DEV0JOB6

Used when the access address does not match any region
0- Reject not mapped address access
1- Bypass not mapped address access (address is forwarded as is to xspi)

RW

0

5

DEV0JOB5

Used when the access address does not match any region
0- Reject not mapped address access
1- Bypass not mapped address access (address is forwarded as is to xspi)

RW

0

4

DEV0JOB4

Used when the access address does not match any region
0- Reject not mapped address access
1- Bypass not mapped address access (address is forwarded as is to xspi)

RW

0

3:1

Reserved

RO

0x0

0

DEV0JOB0

Used when the access address does not match any region
0- Reject not mapped address access
1- Bypass not mapped address access (address is forwarded as is to xspi)

RW

0

31:28

INTCRT

OTFDE DEVICE 0 SERVICE INTERRUPT CRITERIA:
0- No service interruption criteria.
any other value is in 160MHz cycles between two transactions towards xSPI

RW

0x0

27

Reserved

RO

0

26:24

NUMBANKS

OTFDE DEVICE 0 NUMBER OF BANKS:
000 - 1 Bank
001 - 2 Banks
010 - 4 Banks
011 - 8 Banks
100 - 16 Banks

RW

0x0

23

Reserved

RO

0

22:20

DEVICESIZE

OTFDE DEVICE 0 SIZE:
000 - 2 MByte
001 - 4 MByte
010 - 8 MByte
011 - 16 MByte
100 - 32 MByte
101 - 64 MByte

RW

0x5

19:17

Reserved

RO

0x0

16

RWW

OTFDE DEVICE 0 RWW EN:
0- Read while Write is disabled
1- Read while Write is Enabled

RW

0

15:14

Reserved

RO

0x0

13:8

WRBUFTMRNG

OTFDE DEVICE 0 WRITE BUFFER TIMER RANGE:
range is 0 - 63 multiplied by Mode resolution
mode0: timer res is 16usec, timer range is 16-1024usec
mode1: timer res is 32usec, timer range is 32-2048usec
mode2: timer res is 64usec, timer range is 64-4192usec
mode3: timer res is 256usec, timer range is 256-16384usec

RW

0x00

7:6

Reserved

RO

0x0

5:4

WRBUFTMMOD

OTFDE DEVICE 0 WRITE BUFFER TIMER MODE:
00- mode0 is 16usec resolution
01- mode1 is 32usec resolution
10- mode2 is 64usec resolution
11- mode3 is 256usec resolution

RW

0x0

3

POSTWRCMD

OTFDE DEVICE 0 ISSUE POST WRITE CMD:
Issue a Post Write command after the write task ended
0- Do not issue POST WR CMD
1- Issue POST WR CMD after every write task

RW

0

2

PREWRCMD

OTFDE DEVICE 0 ISSUE PRE WRITE CMD:
Issue a Pre Write command before the next write task
0- Do not issue PRE WR CMD
1- Issue PRE WR CMD before every write task

RW

0

1

WRPROTTIME

OTFDE DEVICE 0 WRITE PROTECTION TIMER EN:
Set the write protection timer after a write task
0- Write protection timer is disabled
1- Write protection timer is enabled

RW

0

0

DEVICE

OTFDE DEVICE 0 ENABLED:
Device enabled (and all the device parameters were checked in SW)
0- Device Disabled
1- Device Enabled

RW

1

31:21

Reserved

RO

0x000

20:16

POLLITERA

This value holds the number of additional iterations before polling process is considered complete
range : 0-31 iterations
Translating into total polling request iterations: min 1 and max 32

RW

0x01

15:10

Reserved

RO

0x00

9:0

RESPCNT

This value holds the amount of time in us between each polling iteration sent to xspi control
range : 1us-1023us
value zero is NA

RW

0x3FF

31:5

Reserved

RO

0x000 081F

4:1

MEM_OTD0WRAP_SIZE

Define the wrap size, this field is active only if [EN] is set.
0x0. 8 Bytes
0x1. 16 Bytes
0x2. 32 Bytes
0x3. 64 Bytes
0x4. 128 Bytes
0x5. 256 Bytes
0x6. 512 Bytes
0x7. 1024 Bytes
0x8. 2048 Bytes
0x9. 4096 Bytes

RW

0x0

0

MEM_OTD0WRAP_ENABLE

Enable wrap feature for device 0

RW

0

31:20

Reserved

RO

0x000

19:16

INTCRT

OTFDE DEVICE 1 SERVICE INTERRUPT CRITERIA:
0- No service interruption criteria.
any other value is in 160MHz cycles between two transactions towards xSPI

RW

0x0

15:14

Reserved

RO

0x0

13:8

WRBUFTMRNG

OTFDE DEVICE 1 WRITE BUFFER TIMER RANGE:
range is 0 - 63 multiplied by Mode resolution
mode0: timer res is 16usec, timer range is 16-1024usec
mode1: timer res is 32usec, timer range is 32-2048usec
mode2: timer res is 64usec, timer range is 64-4192usec
mode3: timer res is 256usec, timer range is 256-16384usec

RW

0x00

7:6

Reserved

RO

0x0

5:4

WRBUFTMMOD

OTFDE DEVICE 1 WRITE BUFFER TIMER MODE:
00- mode0 is 16usec resolution
01- mode1 is 32usec resolution
10- mode2 is 64usec resolution
11- mode3 is 256usec resolution

RW

0x0

3

POSTWRCMD

OTFDE DEVICE 1 ISSUE POST WRITE CMD:
Issue a Post Write command after the write task ended
0- Do not issue POST WR CMD
1- Issue POST WR CMD after every write task

RW

0

2

PREWRCMD

OTFDE DEVICE 1 ISSUE PRE WRITE CMD:
Issue a Pre Write command before the next write task
0- Do not issue PRE WR CMD
1- Issue PRE WR CMD before every write task

RW

0

1

WRPROTTIME

OTFDE DEVICE 1 WRITE PROTECTION TIMER EN:
Set the write protection timer after a write task
0- Write protection timer is disabled
1- Write protection timer is enabled

RW

0

0

DEVICE

OTFDE DEVICE 1 ENABLED:
Device enabled (and all the device parameters were checked in SW)
0 - Device Disabled
1- Device Enabled

RW

0

31:5

Reserved

RO

0x000 081F

4:1

MEM_OTD1WRAP_SIZE

Define the wrap size, this field is active only if [EN] is set.
0x0. 8 Bytes
0x1. 16 Bytes
0x2. 32 Bytes
0x3. 64 Bytes
0x4. 128 Bytes
0x5. 256 Bytes
0x6. 512 Bytes
0x7. 1024 Bytes
0x8. 2048 Bytes
0x9. 4096 Bytes

RW

0x0

0

MEM_OTD1WRAP_ENABLE

Enable wrap feature for device 1

RW

0

31:3

Reserved

RO

0x0000 0000

2:0

VAL

Watchdog timer in ms
Timer pops watchdog IRQ in case a process within OTFDE crosses the required time
range 0-7
translated to up to 7ms
value 0 is NA

RW

0x5

31:26

Reserved

RO

0x00

25:20

SECID1

6 MSB bits of ID+COUNTER field (out of 38bits)

RW

0x00

19:18

Reserved

RO

0x0

17:4

OFFSET

Device related address offset

RW

0x0000

3

SPIRD

REGION 0 SPI READ ENABLE:
0- Cannot issue a SPI Read from this region
1- Can issue a SPI Read from this region

RW

1

2

SPIWR

REGION 0 SPI WRITE ENABLE:
0- Cannot issue a SPI Write to this region
1- Can issue a SPI Write to this region

RW

1

1

DEVICE

REGION 0 DEVICE ID:
0- Device_0
1- Device_1

RW

0

0

REGION

REGION 0 ENABLED:
0- Disabled
1- Enabled
Region enabled for incoming transactions

RW

1

31:20

Reserved

RO

0x000

19:0

STARTADDR

System start address

RW

0x1 0000

31:20

Reserved

RO

0x000

19:0

ENDADDR

System end address

RW

0x1 7FFF

31:0

SECID0

32 LSB bits of ID+COUNTER field (out of 38bits)

RW

0x0000 0000

31:26

Reserved

RO

0x00

25:20

SECID1

6 MSB bits of ID+COUNTER field (out of 38bits)

RW

0x00

19:18

Reserved

RO

0x0

17:4

OFFSET

Device related address offset

RW

0x0000

3

SPIRD

REGION 1 SPI READ ENABLE:
0- Cannot issue a SPI Read from this region
1- Can issue a SPI Read from this region

RW

0

2

SPIWR

REGION 1 SPI WRITE ENABLE:
0- Cannot issue a SPI Write to this region
1- Can issue a SPI Write to this region

RW

0

1

DEVICE

REGION 1 DEVICE ID:
0- Device_0
1- Device_1

RW

0

0

REGION

REGION 1 ENABLED:
0- Disabled
1- Enabled
Region enabled for incoming transactions

RW

0

31:20

Reserved

RO

0x000

19:0

STARTADDR

System start address

RW

0x0 0001

31:20

Reserved

RO

0x000

19:0

ENDADDR

System end address

RW

0x0 0000

31:0

SECID0

32 LSB bits of ID+COUNTER field (out of 38bits)

RW

0x0000 0000

31:26

Reserved

RO

0x00

25:20

SECID1