HOST_MCU_SEC

HOST_MCU_SEC

This section provides information on the HOST_MCU_SEC Module Instance within this product. Each of the registers within the Module Instance is described separately below.

HOST_MCU_SEC Registers Mapping Summary

:HOST_MCU_SEC Common Register Mapping Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset
SSWIRQ2NS	RW	32	0x0000 0000	0x0000 0000
SWIRQ2CM3	RW	32	0x0000 0000	0x0000 0004
LCKUP	RW	32	0x0000 0000	0x0000 0008

HOST_MCU_SEC Instances Register Mapping Summary

HOST_MCU_SEC Register Descriptions

:HOST_MCU_SEC Common Register Descriptions

:HOST_MCU_SEC:SSWIRQ2NS

Address offset	0x0000 0000
Description	Secure Software Interrupt
Type	RW

Bits	Field Name	Description			Type	Reset
31:8	RESERVED8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior			RO	0x00 0000
7:0	MEM_SSWIRQ2NS	Secure context of CM33 can use this register to interrupt non secure context of CM33.			RW	0x00

:HOST_MCU_SEC:SWIRQ2CM3

Address offset	0x0000 0004
Description	Software Interrupt to CM3
Type	RW

Bits	Field Name	Description			Type	Reset
31:1	RESERVED8				RO	0x0000 0000
0	MEM_SWIRQ2CM3	Secure context of CM33 can use this register to interrupt CM3.			RW	0

:HOST_MCU_SEC:LCKUP

Address offset	0x0000 0008
Description	Software Interrupt to CM3
Type	RW

Bits	Field Name	Description			Type	Reset
31:1	RESERVED8				RO	0x0000 0000
0	VAL	The processor enters a lockup state if a fault occurs when it cannot be serviced or escalated. When the processor is in lockup state, it does not execute any instructions. The processor remains in lockup state until either: * It is reset. * Preemption by a higher priority exception occurs. * It is halted by a debugger.			RO	0